From: Peng Fan Date: Tue, 20 Aug 2019 01:55:07 +0000 (+0000) Subject: clk: imx: imx8mn: fix audio pll setting X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=760e548e7f885d89bf2dfab4838df9379edd19fc;p=openwrt%2Fstaging%2Fblogic.git clk: imx: imx8mn: fix audio pll setting The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Signed-off-by: Peng Fan Reviewed-by: Shengjiu Wang Signed-off-by: Shawn Guo --- diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index f41116d59749..cc65c1369530 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -53,8 +53,8 @@ static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = { }; static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = { - PLL_1443X_RATE(786432000U, 655, 5, 2, 23593), - PLL_1443X_RATE(722534400U, 301, 5, 1, 3670), + PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), + PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), }; static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {