From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 20 Feb 2010 19:31:34 +0000 (+0000)
Subject: Fix build warnings
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=7524480b8253970fef0a3317bda0887a9fc83bce;p=openwrt%2Fstaging%2Fjow.git

Fix build warnings

SVN-Revision: 19782
---

diff --git a/target/linux/brcm47xx/patches-2.6.30/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.30/700-ssb-gigabit-ethernet-driver.patch
index a524dff5d2..f56ae8e71c 100644
--- a/target/linux/brcm47xx/patches-2.6.30/700-ssb-gigabit-ethernet-driver.patch
+++ b/target/linux/brcm47xx/patches-2.6.30/700-ssb-gigabit-ethernet-driver.patch
@@ -98,7 +98,7 @@
  	/* Workaround for unstable PLL clock */
 -	if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 -	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
-+	if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
++	if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
 +				/* !!! FIXME !!! */
 +	    ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 +	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
@@ -252,14 +252,6 @@
  	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -12063,7 +12133,6 @@ static int __devinit tg3_get_invariants(
- 		tp->write32 = tg3_write_flush_reg32;
- 	}
- 
--
- 	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
- 	    (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
- 		tp->write32_tx_mbox = tg3_write32_tx_mbox;
 @@ -12099,6 +12168,11 @@ static int __devinit tg3_get_invariants(
  	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
diff --git a/target/linux/brcm47xx/patches-2.6.31/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.31/700-ssb-gigabit-ethernet-driver.patch
index 4a47e63a79..0273343885 100644
--- a/target/linux/brcm47xx/patches-2.6.31/700-ssb-gigabit-ethernet-driver.patch
+++ b/target/linux/brcm47xx/patches-2.6.31/700-ssb-gigabit-ethernet-driver.patch
@@ -98,7 +98,7 @@
  	/* Workaround for unstable PLL clock */
 -	if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 -	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
-+	if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
++	if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
 +				/* !!! FIXME !!! */
 +	    ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 +	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
@@ -252,14 +252,6 @@
  	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -12100,7 +12170,6 @@ static int __devinit tg3_get_invariants(
- 		tp->write32 = tg3_write_flush_reg32;
- 	}
- 
--
- 	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
- 	    (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
- 		tp->write32_tx_mbox = tg3_write32_tx_mbox;
 @@ -12136,6 +12205,11 @@ static int __devinit tg3_get_invariants(
  	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
diff --git a/target/linux/brcm47xx/patches-2.6.32/260-ohci-set-dma-mask.patch b/target/linux/brcm47xx/patches-2.6.32/260-ohci-set-dma-mask.patch
index 50dcd5718e..9627798472 100644
--- a/target/linux/brcm47xx/patches-2.6.32/260-ohci-set-dma-mask.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/260-ohci-set-dma-mask.patch
@@ -8,7 +8,7 @@
  	int err = -ENOMEM;
  	u32 tmp, flags = 0;
  
-+	if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
++	if (ssb_dma_set_mask(dev, DMA_BIT_MASK(32)))
 +		return -EOPNOTSUPP;
 +
  	if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
diff --git a/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
index f7deb54e17..de25019506 100644
--- a/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
+++ b/target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
@@ -80,7 +80,7 @@
  	/* Workaround for unstable PLL clock */
 -	if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 -	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
-+	if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
++	if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
 +				/* !!! FIXME !!! */
 +	    ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 +	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {