From: Sibi Sankar <sibis@codeaurora.org>
Date: Thu, 27 Feb 2020 10:56:30 +0000 (+0530)
Subject: arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=74f26599809c870c2d744332591e7622b104de26;p=openwrt%2Fstaging%2Fblogic.git

arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider

Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.

Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200227105632.15041-7-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 3da382b502e9..c7ddf215c57e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3560,6 +3560,16 @@
 			};
 		};
 
+		osm_l3: interconnect@17d41000 {
+			compatible = "qcom,sdm845-osm-l3";
+			reg = <0 0x17d41000 0 0x1400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@17d43000 {
 			compatible = "qcom,cpufreq-hw";
 			reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;