From: Rafał Miłecki Date: Wed, 24 Sep 2014 21:08:17 +0000 (+0000) Subject: bcm53xx: add a patch that fixes booting problems X-Git-Tag: reboot~5866 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=747fd7871ca0115aeebb14d1a8fd77c120b3c543;p=openwrt%2Fstaging%2Fblogic.git bcm53xx: add a patch that fixes booting problems Signed-off-by: Rafał Miłecki SVN-Revision: 42659 --- diff --git a/target/linux/bcm53xx/patches-3.14/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch b/target/linux/bcm53xx/patches-3.14/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch new file mode 100644 index 000000000000..e872e3f9008a --- /dev/null +++ b/target/linux/bcm53xx/patches-3.14/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch @@ -0,0 +1,206 @@ +From 26023cdfacaf116545b1087b9d1fe50dc6fbda10 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 24 Sep 2014 22:14:07 +0200 +Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache for decompression +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Without this fix kernel was randomly hanging in ~25% of tries during +early init. Hangs used to happen at random places in the start_kernel. + +Signed-off-by: Rafał Miłecki +--- + arch/arm/boot/compressed/Makefile | 5 + + arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 +++++++ + arch/arm/boot/compressed/mpcore_cache.S | 118 +++++++++++++++++++++++ + 3 files changed, 160 insertions(+) + create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S + create mode 100644 arch/arm/boot/compressed/mpcore_cache.S + +diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile +index 9312edc..ce7438c 100644 +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -44,6 +44,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y) + OBJS += ll_char_wr.o font.o + endif + ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++OBJS += head-bcm_5301x-mpcore.o ++OBJS += mpcore_cache.o ++endif ++ + ifeq ($(CONFIG_ARCH_SA1100),y) + OBJS += head-sa1100.o + endif +diff --git a/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S +new file mode 100644 +index 0000000..fd076a0 +--- /dev/null ++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S +@@ -0,0 +1,37 @@ ++/* ++ * ++ * Platform specific tweaks. This is merged into head.S by the linker. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++ .section ".start", "ax" ++ ++/* ++ * This code section is spliced into the head code by the linker ++ */ ++ ++__plat_uncompress_start: ++ ++ @ Preserve r8/r7 i.e. kernel entry values ++ mov r12, r8 ++ ++ @ Clear MMU enable and Dcache enable bits ++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR ++ bic r0, #CR_C|CR_M ++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR ++ nop ++ ++ @ Call the cache invalidation routine ++ bl v7_all_dcache_invalidate ++ nop ++ mov r0,#0 ++ ldr r3, =0x19022000 @ L2 cache controller, control reg ++ str r0, [r3, #0x100] @ Disable L2 cache ++ nop ++ ++ @ Restore ++ mov r8, r12 +diff --git a/arch/arm/boot/compressed/mpcore_cache.S b/arch/arm/boot/compressed/mpcore_cache.S +new file mode 100644 +index 0000000..ada734c +--- /dev/null ++++ b/arch/arm/boot/compressed/mpcore_cache.S +@@ -0,0 +1,118 @@ ++/***************************************************************************** ++* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++ ++ __INIT ++ ++/* ++ * v7_l1_cache_invalidate ++ * ++ * Invalidate contents of L1 cache without flushing its contents ++ * into outer cache and memory. This is needed when the contents ++ * of the cache are unpredictable after power-up. ++ * ++ * corrupts r0-r6 ++ */ ++ ++ENTRY(v7_l1_cache_invalidate) ++ mov r0, #0 ++ mcr p15, 2, r0, c0, c0, 0 @ set cache level to 1 ++ mrc p15, 1, r0, c0, c0, 0 @ read CLIDR ++ ++ ldr r1, =0x7fff ++ and r2, r1, r0, lsr #13 @ get max # of index size ++ ++ ldr r1, =0x3ff ++ and r3, r1, r0, lsr #3 @ NumWays - 1 ++ add r2, r2, #1 @ NumSets ++ ++ and r0, r0, #0x7 ++ add r0, r0, #4 @ SetShift ++ ++ clz r1, r3 @ WayShift ++ add r4, r3, #1 @ NumWays ++1: sub r2, r2, #1 @ NumSets-- ++ mov r3, r4 @ Temp = NumWays ++2: subs r3, r3, #1 @ Temp-- ++ mov r5, r3, lsl r1 ++ mov r6, r2, lsl r0 ++ orr r5, r5, r6 @ Reg = (Temp<