From: Felix Fietkau <nbd@nbd.name>
Date: Fri, 17 Feb 2017 10:51:42 +0000 (+0100)
Subject: ar71xx: fix ethernet PLL configuration for QCA956x
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=72327d1757b53d36e97282451d3c4d10d99adfc8;p=openwrt%2Fstaging%2Fblogic.git

ar71xx: fix ethernet PLL configuration for QCA956x

QCA956x is configured like AR934x, not like the older chips.
Should fix ethernet hangs when using the WAN port without SGMII

Signed-off-by: Felix Fietkau <nbd@nbd.name>
---

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 91ff8b2fc904..a8b19b68b2a4 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -1096,7 +1096,7 @@ void __init ath79_register_eth(unsigned int id)
 			if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
 				pdata->set_speed = qca956x_set_speed_sgmii;
 			else
-				pdata->set_speed = ath79_set_speed_ge0;
+				pdata->set_speed = ar934x_set_speed_ge0;
 		} else {
 			pdata->reset_bit = QCA955X_RESET_GE1_MAC |
 					   QCA955X_RESET_GE1_MDIO;