From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 29 Oct 2012 17:24:30 +0000 (+0000)
Subject: ar71xx: fix link speed between AR7242 and AR8327 on the RB750GL/RB751G boards
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=7228a91a3b02cf53d2723629836b0eb26080756f;p=openwrt%2Fstaging%2Fstintel.git

ar71xx: fix link speed between AR7242 and AR8327 on the RB750GL/RB751G boards

The default pll_1000 value had to be changed
in order to make it working.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 33993
---

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c
index bee8bdf9c2..71d48679d2 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c
@@ -186,7 +186,7 @@ static struct ar8327_platform_data rb750gr3_ar8327_data = {
 	.pad0_cfg = &rb750gr3_ar8327_pad0_cfg,
 	.cpuport_cfg = {
 		.force_link = 1,
-		.speed = AR8327_PORT_SPEED_100,
+		.speed = AR8327_PORT_SPEED_1000,
 		.duplex = 1,
 		.txpause = 1,
 		.rxpause = 1,
@@ -261,6 +261,7 @@ static void __init rb750gr3_setup(void)
 	ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 	ath79_eth0_data.phy_mask = BIT(0);
+	ath79_eth0_pll_data.pll_1000 = 0x62000000;
 
 	ath79_register_eth(0);