From: Dimitris Papastamos <dimitris.papastamos@arm.com>
Date: Tue, 27 Feb 2018 10:55:39 +0000 (+0000)
Subject: MISRA fixes for Cortex A75 AMU implementation
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=714b21ffc71170bba343589fc010001645f1db57;p=project%2Fbcm63xx%2Fatf.git

MISRA fixes for Cortex A75 AMU implementation

Change-Id: I61c9fdfda0c0b3c3ec6249519db23602cf4c2100
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
---

diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index a54e0852..20f02518 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -28,9 +28,9 @@
  * CPUAMEVTYPER<n> register and are disabled by default. Platforms may
  * enable this with suitable programming.
  */
-#define CORTEX_A75_AMU_NR_COUNTERS	5
-#define CORTEX_A75_AMU_GROUP0_MASK	0x7
-#define CORTEX_A75_AMU_GROUP1_MASK	(0 << 3)
+#define CORTEX_A75_AMU_NR_COUNTERS	U(5)
+#define CORTEX_A75_AMU_GROUP0_MASK	U(0x7)
+#define CORTEX_A75_AMU_GROUP1_MASK	(U(0) << 3)
 
 #ifndef __ASSEMBLY__
 #include <stdint.h>
diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index 87beca27..16f62f47 100644
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -10,14 +10,14 @@
 
 static void *cortex_a75_context_save(const void *arg)
 {
-	if (midr_match(CORTEX_A75_MIDR))
+	if (midr_match(CORTEX_A75_MIDR) != 0)
 		cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
 	return 0;
 }
 
 static void *cortex_a75_context_restore(const void *arg)
 {
-	if (midr_match(CORTEX_A75_MIDR))
+	if (midr_match(CORTEX_A75_MIDR) != 0)
 		cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
 	return 0;
 }
diff --git a/lib/cpus/aarch64/cpuamu.c b/lib/cpus/aarch64/cpuamu.c
index 38c093ac..b9bad860 100644
--- a/lib/cpus/aarch64/cpuamu.c
+++ b/lib/cpus/aarch64/cpuamu.c
@@ -8,11 +8,11 @@
 #include <platform.h>
 #include <pubsub_events.h>
 
-#define CPUAMU_NR_COUNTERS	5
+#define CPUAMU_NR_COUNTERS	5U
 
 struct amu_ctx {
 	uint64_t cnts[CPUAMU_NR_COUNTERS];
-	uint16_t mask;
+	unsigned int mask;
 };
 
 static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
@@ -21,7 +21,7 @@ int midr_match(unsigned int cpu_midr)
 {
 	unsigned int midr, midr_mask;
 
-	midr = read_midr();
+	midr = (unsigned int)read_midr();
 	midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
 		(MIDR_PN_MASK << MIDR_PN_SHIFT);
 	return ((midr & midr_mask) == (cpu_midr & midr_mask));
@@ -30,7 +30,7 @@ int midr_match(unsigned int cpu_midr)
 void cpuamu_context_save(unsigned int nr_counters)
 {
 	struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
-	int i;
+	unsigned int i;
 
 	assert(nr_counters <= CPUAMU_NR_COUNTERS);
 
@@ -49,7 +49,7 @@ void cpuamu_context_save(unsigned int nr_counters)
 void cpuamu_context_restore(unsigned int nr_counters)
 {
 	struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
-	int i;
+	unsigned int i;
 
 	assert(nr_counters <= CPUAMU_NR_COUNTERS);