From: Alexei Fedorov <Alexei.Fedorov@arm.com>
Date: Mon, 29 Jul 2019 12:34:07 +0000 (+0100)
Subject: AArch64: Align crash reporting output
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=6c6a470fc1c2e1a516214f1f6dbe00ef045d1d0f;p=project%2Fbcm63xx%2Fatf.git

AArch64: Align crash reporting output

This patch modifies crash reporting for AArch64 to provide
aligned output of register dump and GIC registers.

Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
---

diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index 40506785..2c410298 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -28,7 +28,7 @@
 	 */
 .section .rodata.crash_prints, "aS"
 print_spacer:
-	.asciz	" =\t\t0x"
+	.asciz	"             = 0x"
 
 gp_regs:
 	.asciz	"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
@@ -55,11 +55,11 @@ aarch32_regs:
 #endif /* CTX_INCLUDE_AARCH32_REGS */
 
 panic_msg:
-	.asciz "PANIC in EL3 at x30 = 0x"
+	.asciz "PANIC in EL3.\nx30"
 excpt_msg:
-	.asciz "Unhandled Exception in EL3.\nx30 =\t\t0x"
+	.asciz "Unhandled Exception in EL3.\nx30"
 intr_excpt_msg:
-	.asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x"
+	.asciz "Unhandled Interrupt Exception in EL3.\nx30"
 
 	/*
 	 * Helper function to print newline to console.
@@ -94,10 +94,11 @@ test_size_list:
 	mov	x4, x6
 	/* asm_print_str updates x4 to point to next entry in list */
 	bl	asm_print_str
+	/* x0 = number of symbols printed + 1 */
+	sub	x0, x4, x6
 	/* update x6 with the updated list pointer */
 	mov	x6, x4
-	adr	x4, print_spacer
-	bl	asm_print_str
+	bl	print_alignment
 	ldr	x4, [x7], #REGSZ
 	bl	asm_print_hex
 	bl	print_newline
@@ -107,6 +108,20 @@ exit_size_print:
 	ret
 endfunc size_controlled_print
 
+	/* -----------------------------------------------------
+	 * This function calculates and prints required number
+	 * of space characters followed by "= 0x", based on the
+	 * length of ascii register name.
+ 	 * x0: length of ascii register name + 1
+	 * ------------------------------------------------------
+ 	 */
+func print_alignment
+	/* The minimum ascii length is 3, e.g. for "x0" */
+	adr	x4, print_spacer - 3
+	add	x4, x4, x0
+	b	asm_print_str
+endfunc print_alignment
+
 	/*
 	 * Helper function to store x8 - x15 registers to
 	 * the crash buf. The system registers values are
@@ -189,7 +204,7 @@ endfunc report_unhandled_interrupt
 	 * -----------------------------------------------------
 	 */
 func el3_panic
-	msr	spsel, #1
+	msr	spsel, #MODE_SP_ELX
 	prepare_crash_buf_save_x0_x1
 	adr	x0, panic_msg
 	mov	sp, x0
@@ -230,6 +245,9 @@ func do_crash_reporting
 	/* Print the crash message. sp points to the crash message */
 	mov	x4, sp
 	bl	asm_print_str
+	/* Print spaces to align "x30" string */
+	mov	x0, #4
+	bl	print_alignment
 	/* load the crash buf address */
 	mrs	x0, tpidr_el3
 	/* report x30 first from the crash buf */
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index da740ef2..ac47cbe9 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 
 	.globl	asm_print_str
 	.globl	asm_print_hex
+	.globl	asm_print_hex_bits
 	.globl	asm_assert
 	.globl	do_panic
 
@@ -107,8 +108,11 @@ endfunc asm_print_str
  * Clobber: x30, x0 - x3, x5
  */
 func asm_print_hex
-	mov	x3, x30
 	mov	x5, #64  /* No of bits to convert to ascii */
+
+	/* Convert to ascii number of bits in x5 */
+asm_print_hex_bits:
+	mov	x3, x30
 1:
 	sub	x5, x5, #4
 	lsrv	x0, x4, x5
diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S
index 0bd0daf5..d47e4e09 100644
--- a/include/plat/arm/common/aarch64/arm_macros.S
+++ b/include/plat/arm/common/aarch64/arm_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,11 +22,13 @@ icc_regs:
 
 /* Registers common to both GICv2 and GICv3 */
 gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+	.asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n"
 newline:
 	.asciz "\n"
 spacer:
-	.asciz ":\t\t0x"
+	.asciz ":\t\t 0x"
+prefix:
+	.asciz "0x"
 
 	/* ---------------------------------------------
 	 * The below utility macro prints out relevant GIC
@@ -77,7 +79,15 @@ gicd_ispendr_loop:
 	sub	x4, x7, x16
 	cmp	x4, #0x280
 	b.eq	exit_print_gic_regs
-	bl	asm_print_hex
+
+	/* Print "0x" */
+	adr	x4, prefix
+	bl	asm_print_str
+
+	/* Print offset */
+	sub	x4, x7, x16
+	mov	x5, #12
+	bl	asm_print_hex_bits
 
 	adr	x4, spacer
 	bl	asm_print_str