From: Stefano Babic <sbabic@denx.de>
Date: Tue, 2 Aug 2011 12:42:36 +0000 (+0200)
Subject: MX35: MX35PDK: support additional RAM on CSD1
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=6b5acfc12151ac151800375b447938cc4a4e86ff;p=project%2Fbcm63xx%2Fu-boot.git

MX35: MX35PDK: support additional RAM on CSD1

Modules on mx35pdk have additional 128MB
memory connected to CSD1.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---

diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S
index 9b0f1b5259..9fd04cbdb8 100644
--- a/board/freescale/mx35pdk/lowlevel_init.S
+++ b/board/freescale/mx35pdk/lowlevel_init.S
@@ -193,10 +193,11 @@
 	mov r2, #0x00
 	mov r1, #CSD0_BASE_ADDR
 	bl setup_sdram_bank
-	cmp r3, #0x0
-	orreq r5, r5, #1
-	eorne r2, r2, #0x1
-	blne setup_sdram_bank
+
+	mov r5, #0x00
+	mov r2, #0x00
+	mov r1, #CSD1_BASE_ADDR
+	bl setup_sdram_bank
 
 	mov lr, fp
 
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index da926e5781..a6b5a51f45 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -52,12 +52,25 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
-		PHYS_SDRAM_1_SIZE);
+	u32 size1, size2;
+
+	size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	gd->ram_size = size1 + size2;
 
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
 static void setup_iomux_i2c(void)
 {
 	int pad;
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 086355bb67..0d4b7334be 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -173,11 +173,11 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	1
+#define CONFIG_NR_DRAM_BANKS	2
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
-#define iomem_valid_addr(addr, size) \
-	(addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(128 * 1024 * 1024)
 
 #define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)