From: Harry Wentland Date: Fri, 5 May 2017 18:57:12 +0000 (-0400) Subject: drm/amd/display: DCE12 num_timing_generators should be 6 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=6a4c32dac559a90b83c5f268b02c1a94df411159;p=openwrt%2Fstaging%2Fblogic.git drm/amd/display: DCE12 num_timing_generators should be 6 We should also use it to determine pipe count. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b6bdd1d52922..b13abb025e1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -426,7 +426,7 @@ static const struct bios_registers bios_regs = { }; static const struct resource_caps res_cap = { - .num_timing_generator = 3, + .num_timing_generator = 6, .num_audio = 7, .num_stream_encoder = 6, .num_pll = 6, @@ -909,7 +909,7 @@ static bool construct( pool->base.funcs = &dce120_res_pool_funcs; /* TODO: Fill more data from GreenlandAsicCapability.cpp */ - pool->base.pipe_count = 6; + pool->base.pipe_count = res_cap.num_timing_generator; pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; dc->public.caps.max_downscale_ratio = 200;