From: Markus Stockhausen Date: Mon, 9 Sep 2024 06:28:42 +0000 (-0400) Subject: realtek: 6.6: rework patch include-linux-add-phy-hsgmii-mode X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=6a340ded82ff316cc57868e3ce99bb3b51831342;p=openwrt%2Fstaging%2Fblocktrron.git realtek: 6.6: rework patch include-linux-add-phy-hsgmii-mode Take over the new patch locations and add references to the link mode into phylink_sfp_interface_preference[] and phylink_get_capabilities(). Signed-off-by: Markus Stockhausen --- diff --git a/target/linux/realtek/patches-6.6/702-include-linux-add-phy-hsgmii-mode.patch b/target/linux/realtek/patches-6.6/702-include-linux-add-phy-hsgmii-mode.patch index 700ec97be8..a43b49c1ff 100644 --- a/target/linux/realtek/patches-6.6/702-include-linux-add-phy-hsgmii-mode.patch +++ b/target/linux/realtek/patches-6.6/702-include-linux-add-phy-hsgmii-mode.patch @@ -1,21 +1,22 @@ From 9d9bf16aa8d966834ac1280f96c37d22552c33d1 Mon Sep 17 00:00:00 2001 From: Birger Koblitz Date: Wed, 8 Sep 2021 16:13:18 +0200 -Subject: phy: Add PHY hsgmii mode +Subject: realtek phy: Add PHY hsgmii mode This adds RTL93xx-specific MAC configuration routines that allow also configuration -of 10GBit links for phylink. There is support for the Realtek-specific HISGMI +of 10GBit links for phylink. There is support for the Realtek-specific HSGMII protocol. Submitted-by: Birger Koblitz --- - drivers/net/phy/phylink.c | 2 ++ - include/linux/phy.h | 3 +++ - 2 file changed, 5 insertions(+) + drivers/net/phy/phy-core.c | 1 + + drivers/net/phy/phylink.c | 4 ++++ + include/linux/phy.h | 3 +++ + 3 files changed, 8 insertions(+) --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c -@@ -124,6 +124,7 @@ int phy_interface_num_ports(phy_interfac +@@ -126,6 +126,7 @@ int phy_interface_num_ports(phy_interfac case PHY_INTERFACE_MODE_MOCA: case PHY_INTERFACE_MODE_TRGMII: case PHY_INTERFACE_MODE_USXGMII: @@ -25,7 +26,15 @@ Submitted-by: Birger Koblitz case PHY_INTERFACE_MODE_1000BASEX: --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -410,6 +410,7 @@ void phylink_get_linkmodes(unsigned long +@@ -124,6 +124,7 @@ do { \ + static const phy_interface_t phylink_sfp_interface_preference[] = { + PHY_INTERFACE_MODE_25GBASER, + PHY_INTERFACE_MODE_USXGMII, ++ PHY_INTERFACE_MODE_HSGMII, + PHY_INTERFACE_MODE_10GBASER, + PHY_INTERFACE_MODE_5GBASER, + PHY_INTERFACE_MODE_2500BASEX, +@@ -238,6 +239,7 @@ static int phylink_interface_max_speed(p case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_RXAUI: @@ -33,7 +42,15 @@ Submitted-by: Birger Koblitz case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_10GKR: -@@ -665,6 +666,7 @@ static int phylink_parse_mode(struct phy +@@ -547,6 +549,7 @@ unsigned long phylink_get_capabilities(p + break; + + case PHY_INTERFACE_MODE_XGMII: ++ case PHY_INTERFACE_MODE_HSGMII: + case PHY_INTERFACE_MODE_RXAUI: + case PHY_INTERFACE_MODE_XAUI: + case PHY_INTERFACE_MODE_10GBASER: +@@ -957,6 +960,7 @@ static int phylink_parse_mode(struct phy fallthrough; case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GKR: @@ -43,20 +60,20 @@ Submitted-by: Birger Koblitz phylink_set(pl->supported, 10baseT_Full); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -141,6 +141,7 @@ typedef enum { +@@ -148,6 +148,7 @@ typedef enum { PHY_INTERFACE_MODE_XGMII, PHY_INTERFACE_MODE_XLGMII, PHY_INTERFACE_MODE_MOCA, + PHY_INTERFACE_MODE_HSGMII, + PHY_INTERFACE_MODE_PSGMII, PHY_INTERFACE_MODE_QSGMII, PHY_INTERFACE_MODE_TRGMII, - PHY_INTERFACE_MODE_100BASEX, -@@ -248,6 +249,8 @@ static inline const char *phy_modes(phy_ +@@ -256,6 +257,8 @@ static inline const char *phy_modes(phy_ return "xlgmii"; case PHY_INTERFACE_MODE_MOCA: return "moca"; + case PHY_INTERFACE_MODE_HSGMII: + return "hsgmii"; + case PHY_INTERFACE_MODE_PSGMII: + return "psgmii"; case PHY_INTERFACE_MODE_QSGMII: - return "qsgmii"; - case PHY_INTERFACE_MODE_TRGMII: