From: Tomasz Maciej Nowak Date: Wed, 18 Mar 2020 18:04:12 +0000 (+0100) Subject: mvebu: cortexa9: correct cpu subtype X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=67ed408af20c3b24725f051596028345497219d8;p=openwrt%2Fstaging%2Fynezz.git mvebu: cortexa9: correct cpu subtype Armada 370 processors have only 16 double-precision registers. The change introduced by 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for mvebu cortexa9 subtarget to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak (cherry picked from commit 2d61f8821c7cf99354e904139226c132554ba180) --- diff --git a/target/linux/mvebu/cortexa9/target.mk b/target/linux/mvebu/cortexa9/target.mk index 2a75599bc9..cdd4d86e49 100644 --- a/target/linux/mvebu/cortexa9/target.mk +++ b/target/linux/mvebu/cortexa9/target.mk @@ -10,5 +10,5 @@ include $(TOPDIR)/rules.mk ARCH:=arm BOARDNAME:=Marvell Armada 37x/38x/XP CPU_TYPE:=cortex-a9 -CPU_SUBTYPE:=vfpv3 +CPU_SUBTYPE:=vfpv3-d16 KERNELNAME:=zImage dtbs