From: John Crispin <john@openwrt.org>
Date: Tue, 24 Jul 2012 20:37:50 +0000 (+0000)
Subject: uart_clk on Rt3352F is always 40MHz
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=6641024f50b61178a07fc2ac846fb0ce8f53ee6f;p=openwrt%2Fstaging%2Fjow.git

uart_clk on Rt3352F is always 40MHz

Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@allnet.de>

SVN-Revision: 32812
---

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index 4a99cf39e2..958547611b 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
 			break;
 		}
 		rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
-		rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
+		rt305x_uart_clk.rate = 40000000;
 		rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
 	} else {
 		BUG();