From: John Crispin Date: Thu, 17 Dec 2015 09:26:35 +0000 (+0000) Subject: ramips: mt7621: setup memory region for pcie controller memory X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=622e2687104b1c2a844f2dcb2a46b4ad2db1df19;p=openwrt%2Fstaging%2Fkaloz.git ramips: mt7621: setup memory region for pcie controller memory Only compile tested since I do not have any hardware with devices on pcie bus. Signed-off-by: Nikolay Martynov SVN-Revision: 47904 --- diff --git a/target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch b/target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch new file mode 100644 index 0000000000..e6338a9478 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0061-mt7621-set-up-pci-memory-region.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/pci/pci-mt7621.c ++++ b/arch/mips/pci/pci-mt7621.c +@@ -46,6 +46,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -553,6 +554,23 @@ set_phy_for_ssc(void) + #endif + } + ++void setup_cm_memory_region(struct resource *mem_resource) ++{ ++ resource_size_t mask; ++ if (mips_cm_numiocu()) { ++ /* FIXME: hardware doesn't accept mask values with 1s after ++ 0s (e.g. 0xffef), so it would be great to warn if that's ++ about to happen */ ++ mask = ~(mem_resource->end - mem_resource->start); ++ ++ write_gcr_reg1_base(mem_resource->start); ++ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); ++ printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n", ++ read_gcr_reg1_base(), ++ read_gcr_reg1_mask()); ++ } ++} ++ + static int mt7621_pci_probe(struct platform_device *pdev) + { + unsigned long val = 0; +@@ -780,6 +798,7 @@ pcie(2/1/0) link status pcie2_num pcie1_ + } + + pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node); ++ setup_cm_memory_region(mt7621_controller.mem_resource); + register_pci_controller(&mt7621_controller); + return 0; +