From: Christian Marangi Date: Thu, 16 Jun 2022 20:13:02 +0000 (+0200) Subject: ipq806x: 5.15: replace lcc patch with upstream version X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=61a2bedf7902c64a47a42a3d8df3350f1b67ee2f;p=openwrt%2Fstaging%2Fdedeckeh.git ipq806x: 5.15: replace lcc patch with upstream version Replace lcc patch with proposed upstream version. Signed-off-by: Christian Marangi --- diff --git a/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch b/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch deleted file mode 100644 index cd2cb33356..0000000000 --- a/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:00:07 +0100 -Subject: [PATCH 2/4] ipq806x: lcc: add missing reset - -Add missing reset for ipq806x lcc clk - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/lcc-ipq806x.c | 8 ++++++++ - include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 + - 2 files changed, 9 insertions(+) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #include - -@@ -22,6 +23,7 @@ - #include "clk-branch.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "reset.h" - - static struct clk_pll pll4 = { - .l_reg = 0x4, -@@ -39,6 +41,10 @@ static struct clk_pll pll4 = { - }, - }; - -+static const struct qcom_reset_map lcc_ipq806x_resets[] = { -+ [LCC_PCM_RESET] = { 0x54, 13 }, -+}; -+ - static const struct pll_config pll4_config = { - .l = 0xf, - .m = 0x91, -@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq - .config = &lcc_ipq806x_regmap_config, - .clks = lcc_ipq806x_clks, - .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), -+ .resets = lcc_ipq806x_resets, -+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), - }; - - static const struct of_device_id lcc_ipq806x_match_table[] = { ---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h -@@ -19,4 +19,5 @@ - #define SPDIF_CLK 10 - #define AHBIX_CLK 11 - -+#define LCC_PCM_RESET 0 - #endif diff --git a/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch b/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch new file mode 100644 index 0000000000..72e70b613c --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-01-dt-bindings-clock-add-pcm-reset-for-ipq806x-lcc.patch @@ -0,0 +1,29 @@ +From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:13:32 +0200 +Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc + +Add pcm reset define for ipq806x lcc. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +Acked-by: Rob Herring +--- +v3: + - Added review tag + - Added ack tag +v2: + - Fix Sob tag + + include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h +@@ -19,4 +19,6 @@ + #define SPDIF_CLK 10 + #define AHBIX_CLK 11 + ++#define LCC_PCM_RESET 0 ++ + #endif diff --git a/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch b/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch new file mode 100644 index 0000000000..2393651306 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-02-clk-qcom-lcc-ipq806x-add-reset-definition.patch @@ -0,0 +1,48 @@ +From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:19:55 +0200 +Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition + +Add reset definition for lcc-ipq806x. + +Signed-off-by: Christian Marangi +Reviewed-by: Dmitry Baryshkov +--- +v3: + - Added review tag +v2: + - Fix Sob tag + + drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/clk/qcom/lcc-ipq806x.c ++++ b/drivers/clk/qcom/lcc-ipq806x.c +@@ -22,6 +22,7 @@ + #include "clk-branch.h" + #include "clk-regmap-divider.h" + #include "clk-regmap-mux.h" ++#include "reset.h" + + static struct clk_pll pll4 = { + .l_reg = 0x4, +@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl + [AHBIX_CLK] = &ahbix_clk.clkr, + }; + ++static const struct qcom_reset_map lcc_ipq806x_resets[] = { ++ [LCC_PCM_RESET] = { 0x54, 13 }, ++}; ++ + static const struct regmap_config lcc_ipq806x_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq + .config = &lcc_ipq806x_regmap_config, + .clks = lcc_ipq806x_clks, + .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), ++ .resets = lcc_ipq806x_resets, ++ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), + }; + + static const struct of_device_id lcc_ipq806x_match_table[] = { diff --git a/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch b/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch new file mode 100644 index 0000000000..905dc5bf40 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/109-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch @@ -0,0 +1,217 @@ +From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 15 Jun 2022 17:35:13 +0200 +Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data + +Convert lcc-ipq806x driver to parent_data API. + +Signed-off-by: Christian Marangi +--- +v5: +- Fix the same compilation error (don't know what the hell happen + to my buildroot) +v4: +- Fix compilation error +v3: + - Inline pxo pll4 parent + - Change .name from pxo to pxo_board + + drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++---------------- + 1 file changed, 42 insertions(+), 35 deletions(-) + +--- a/drivers/clk/qcom/lcc-ipq806x.c ++++ b/drivers/clk/qcom/lcc-ipq806x.c +@@ -34,7 +34,9 @@ static struct clk_pll pll4 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll4", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = &(const struct clk_parent_data) { ++ .fw_name = "pxo", .name = "pxo_board", ++ }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p + { P_PLL4, 2 } + }; + +-static const char * const lcc_pxo_pll4[] = { +- "pxo", +- "pll4_vote", ++static const struct clk_parent_data lcc_pxo_pll4[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .fw_name = "pll4_vote", .name = "pll4_vote" }, + }; + + static struct freq_tbl clk_tbl_aif_mi2s[] = { +@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_osr_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, + }, + }; + +-static const char * const lcc_mi2s_parents[] = { +- "mi2s_osr_src", +-}; +- + static struct clk_branch mi2s_osr_clk = { + .halt_reg = 0x50, + .halt_bit = 1, +@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_osr_clk", +- .parent_names = lcc_mi2s_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_osr_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mi2s_div_clk", +- .parent_names = lcc_mi2s_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_osr_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "mi2s_bit_div_clk", +- .parent_names = (const char *[]){ "mi2s_div_clk" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &mi2s_div_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl + }, + }; + ++static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { ++ { .hw = &mi2s_bit_div_clk.clkr.hw, }, ++ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" }, ++}; + + static struct clk_regmap_mux mi2s_bit_clk = { + .reg = 0x48, +@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mi2s_bit_clk", +- .parent_names = (const char *[]){ +- "mi2s_bit_div_clk", +- "mi2s_codec_clk", +- }, +- .num_parents = 2, ++ .parent_data = lcc_mi2s_bit_div_codec_clk, ++ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcm_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcm_clk_out", +- .parent_names = (const char *[]){ "pcm_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcm_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { + }, + }; + ++static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { ++ { .hw = &pcm_clk_out.clkr.hw, }, ++ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, ++}; ++ + static struct clk_regmap_mux pcm_clk = { + .reg = 0x54, + .shift = 10, +@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "pcm_clk", +- .parent_names = (const char *[]){ +- "pcm_clk_out", +- "pcm_codec_clk", +- }, +- .num_parents = 2, ++ .parent_data = lcc_pcm_clk_out_codec_clk, ++ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), + .ops = &clk_regmap_mux_closest_ops, + .flags = CLK_SET_RATE_PARENT, + }, +@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "spdif_src", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, + }, + }; + +-static const char * const lcc_spdif_parents[] = { +- "spdif_src", +-}; +- + static struct clk_branch spdif_clk = { + .halt_reg = 0xd4, + .halt_bit = 1, +@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "spdif_clk", +- .parent_names = lcc_spdif_parents, ++ .parent_hws = (const struct clk_hw*[]){ ++ &spdif_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "ahbix", +- .parent_names = lcc_pxo_pll4, +- .num_parents = 2, ++ .parent_data = lcc_pxo_pll4, ++ .num_parents = ARRAY_SIZE(lcc_pxo_pll4), + .ops = &clk_rcg_lcc_ops, + }, + },