From: Luka Perkov Date: Thu, 3 Oct 2013 13:06:42 +0000 (+0000) Subject: imx6: update upstream pcie patches X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=60dd4429b71227cbecf22892b26e125fedd4159d;p=openwrt%2Fstaging%2Fthess.git imx6: update upstream pcie patches Signed-off-by: Luka Perkov SVN-Revision: 38298 --- diff --git a/target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch b/target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch index da46405f73..f8229d06b1 100644 --- a/target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch +++ b/target/linux/imx6/patches-3.10/0001-usb-chipidea-improve-kconfig.patch @@ -1,6 +1,4 @@ -From 20a677fd63c57edd5b0c463baa44f133b2f2d4a0 Mon Sep 17 00:00:00 2001 From: Peter Chen -Date: Thu, 13 Jun 2013 17:59:52 +0300 Subject: [PATCH] usb: chipidea: improve kconfig Randy Dunlap reported this problem diff --git a/target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch b/target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch index b921dfd9e0..e44682c3d7 100644 --- a/target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch +++ b/target/linux/imx6/patches-3.10/0002-usb-chipidea-fix-the-build-error-with-randconfig.patch @@ -1,6 +1,4 @@ -From 972a6c5d56b42d6dd326867d5974ffa58383ec53 Mon Sep 17 00:00:00 2001 From: Peter Chen -Date: Mon, 29 Jul 2013 13:09:57 +0300 Subject: [PATCH] usb: chipidea: fix the build error with randconfig Using below configs, the compile will have error: diff --git a/target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch b/target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch index 40968ab4da..f90e7365ec 100644 --- a/target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch +++ b/target/linux/imx6/patches-3.10/0003-usb-chipidea-improve-kconfig-2.0.patch @@ -1,6 +1,4 @@ -From a0cfdc6bc73bc47b63b05b850cf66cf67f2487bf Mon Sep 17 00:00:00 2001 From: Lothar Waßmann -Date: Wed, 14 Aug 2013 12:43:58 +0300 Subject: [PATCH] usb: chipidea: improve kconfig 2.0 This patch provides a cleaner solution to the problem described in diff --git a/target/linux/imx6/patches-3.10/0004-i2c-imx-retry-on-NAK.patch b/target/linux/imx6/patches-3.10/0004-i2c-imx-retry-on-NAK.patch index aea87eaa5f..e876c6ed49 100644 --- a/target/linux/imx6/patches-3.10/0004-i2c-imx-retry-on-NAK.patch +++ b/target/linux/imx6/patches-3.10/0004-i2c-imx-retry-on-NAK.patch @@ -1,6 +1,4 @@ -From 0d1ee1f265cf9730feb214ddd18bc430c0800e8b Mon Sep 17 00:00:00 2001 From: Tim Harvey -Date: Tue, 10 Sep 2013 21:42:29 +0200 Subject: [PATCH] i2c: imx: retry on NAK In case of busy i2c try again to get ACK. diff --git a/target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch b/target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch index 1adb41d25f..c735517c7a 100644 --- a/target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch +++ b/target/linux/imx6/patches-3.10/0005-ahci_imx-add-ahci-sata-support-on-imx-platforms.patch @@ -1,6 +1,4 @@ -From 9e54eae23bc9cca0d8a955018c35b1250e09a73a Mon Sep 17 00:00:00 2001 From: Richard Zhu -Date: Wed, 24 Jul 2013 14:15:29 +0800 Subject: [PATCH] ahci_imx: add ahci sata support on imx platforms imx6q contains one Synopsys AHCI SATA controller, But it can't share diff --git a/target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch b/target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch index 11ce9ccbc8..646273af0f 100644 --- a/target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch +++ b/target/linux/imx6/patches-3.10/0006-ARM-imx6q-update-the-sata-bits-definitions-of-gpr13.patch @@ -1,6 +1,4 @@ -From 6a6c21ef487be47b300a0b24cd6afeb69d8b9a1a Mon Sep 17 00:00:00 2001 From: Richard Zhu -Date: Wed, 24 Jul 2013 14:15:28 +0800 Subject: [PATCH] ARM: imx6q: update the sata bits definitions of gpr13 Replace the SATA_PHY_# by the more readable definitons. diff --git a/target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch b/target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch index 72d41eeb0b..5371524237 100644 --- a/target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch +++ b/target/linux/imx6/patches-3.10/0007-ARM-dtsi-enable-ahci-sata-on-imx6q-platforms.patch @@ -1,6 +1,4 @@ -From 0fb1f804269e549b556b475c8655bc862c220622 Mon Sep 17 00:00:00 2001 From: Richard Zhu -Date: Tue, 16 Jul 2013 11:28:46 +0800 Subject: [PATCH] ARM: dtsi: enable ahci sata on imx6q platforms Only imx6q has the ahci sata controller, enable diff --git a/target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch b/target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch index 7115a6ce73..86e7d8f0cd 100644 --- a/target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch +++ b/target/linux/imx6/patches-3.10/0008-ahci_imx-depend-on-CONFIG_MFD_SYSCON.patch @@ -1,6 +1,4 @@ -From 867974fc09f93bdd7f98d46ac3733934486bbf4a Mon Sep 17 00:00:00 2001 From: Tejun Heo -Date: Fri, 26 Jul 2013 08:57:56 -0400 Subject: [PATCH] ahci_imx: depend on CONFIG_MFD_SYSCON ahci_imx makes use of regmap but the dependency wasn't specified in diff --git a/target/linux/imx6/patches-3.10/0010-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch b/target/linux/imx6/patches-3.10/0010-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch deleted file mode 100644 index bd86fadc33..0000000000 --- a/target/linux/imx6/patches-3.10/0010-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch +++ /dev/null @@ -1,55 +0,0 @@ -Subject: [v6,1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q -From: Sean Cross - -The i.MX6 has two general-purpose LVDS clocks that can be driven -from a variety of sources. This patch adds a mux and a gate for -both of these clocks. - -Signed-off-by: Sean Cross ---- - arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++- - 2 files changed, 23 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-imx/clk-imx6q.c -+++ b/arch/arm/mach-imx/clk-imx6q.c -@@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a - static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", - "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", - "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; -+static const char *lvds_sels[] = { -+ "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", -+ "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", -+ "pcie_ref", "sata_ref", -+}; - - enum mx6q_clks { - dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, -@@ -238,7 +243,8 @@ enum mx6q_clks { - pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, - sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, -- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max -+ usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, -+ lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max - }; - - static struct clk *clk[clk_max]; -@@ -340,6 +346,18 @@ int __init mx6q_clocks_init(void) - base + 0xe0, 0, 2, 0, clk_enet_ref_table, - &imx_ccm_lock); - -+ clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); -+ clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); -+ -+ /* -+ * lvds1_gate and lvds2_gate are pseudo-gates. Both can be -+ * independently configured as clock inputs or outputs. We treat -+ * the "output_enable" bit as a gate, even though it's really just -+ * enabling clock output. -+ */ -+ clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); -+ clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); -+ - /* name parent_name reg idx */ - clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); - clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); diff --git a/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch new file mode 100644 index 0000000000..19ca079dc9 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch @@ -0,0 +1,37 @@ +From: Sean Cross +Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition + +PCIe requires additional bits be defined for GPR8 and GPR12. + +Signed-off-by: Sean Cross +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Helgaas +--- + include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h ++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +@@ -241,6 +241,12 @@ + + #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) + ++#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) ++#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) ++ + #define IMX6Q_GPR9_TZASC2_BYP BIT(1) + #define IMX6Q_GPR9_TZASC1_BYP BIT(0) + +@@ -273,7 +279,9 @@ + #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) + #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) + #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) ++#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) + #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) ++#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) + + #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) + #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) diff --git a/target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch deleted file mode 100644 index df9d9fa961..0000000000 --- a/target/linux/imx6/patches-3.10/0011-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch +++ /dev/null @@ -1,35 +0,0 @@ -Subject: [v6,2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition -From: Sean Cross - -PCIe requires additional bits be defined for GPR8 and GPR12. - -Signed-off-by: Sean Cross ---- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -241,6 +241,12 @@ - - #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) - -+#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) -+#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) -+ - #define IMX6Q_GPR9_TZASC2_BYP BIT(1) - #define IMX6Q_GPR9_TZASC1_BYP BIT(0) - -@@ -273,7 +279,9 @@ - #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) - #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) - #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) -+#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) - #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) -+#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) - - #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) - #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) diff --git a/target/linux/imx6/patches-3.10/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch b/target/linux/imx6/patches-3.10/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch new file mode 100644 index 0000000000..599cd0e084 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch @@ -0,0 +1,616 @@ +Subject: [PATCH 2/2] PCI: imx6: Add support for i.MX6 PCIe controller +From: Sean Cross + +Add support for the PCIe port present on the i.MX6 family of controllers. +These use the Synopsis Designware core tied to their own PHY. + +Signed-off-by: Sean Cross +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Helgaas +Acked-by: Sascha Hauer +--- + drivers/pci/host/Kconfig | 6 + + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pci-imx6.c | 575 +++++++++++++++++++++ + 4 files changed, 588 insertions(+), 1 deletion(-) + create mode 100644 drivers/pci/host/pci-imx6.c + +--- /dev/null ++++ b/drivers/pci/host/Kconfig +@@ -0,0 +1,13 @@ ++menu "PCI host controller drivers" ++ depends on PCI ++ ++config PCIE_DW ++ bool ++ ++config PCI_IMX6 ++ bool "Freescale i.MX6 PCIe controller" ++ depends on SOC_IMX6Q ++ select PCIEPORTBUS ++ select PCIE_DW ++ ++endmenu +--- /dev/null ++++ b/drivers/pci/host/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_PCIE_DW) += pcie-designware.o ++obj-$(CONFIG_PCI_IMX6) += pci-imx6.o +--- /dev/null ++++ b/drivers/pci/host/pci-imx6.c +@@ -0,0 +1,575 @@ ++/* ++ * PCIe host controller driver for Freescale i.MX6 SoCs ++ * ++ * Copyright (C) 2013 Kosagi ++ * http://www.kosagi.com ++ * ++ * Author: Sean Cross ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) ++ ++struct imx6_pcie { ++ int reset_gpio; ++ int power_on_gpio; ++ int wake_up_gpio; ++ int disable_gpio; ++ struct clk *lvds_gate; ++ struct clk *sata_ref_100m; ++ struct clk *pcie_ref_125m; ++ struct clk *pcie_axi; ++ struct pcie_port pp; ++ struct regmap *iomuxc_gpr; ++ void __iomem *mem_base; ++}; ++ ++/* PCIe Port Logic registers (memory-mapped) */ ++#define PL_OFFSET 0x700 ++#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) ++#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) ++ ++#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) ++#define PCIE_PHY_CTRL_DATA_LOC 0 ++#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 ++#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 ++#define PCIE_PHY_CTRL_WR_LOC 18 ++#define PCIE_PHY_CTRL_RD_LOC 19 ++ ++#define PCIE_PHY_STAT (PL_OFFSET + 0x110) ++#define PCIE_PHY_STAT_ACK_LOC 16 ++ ++/* PHY registers (not memory-mapped) */ ++#define PCIE_PHY_RX_ASIC_OUT 0x100D ++ ++#define PHY_RX_OVRD_IN_LO 0x1005 ++#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) ++#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) ++ ++static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) ++{ ++ u32 val; ++ u32 max_iterations = 10; ++ u32 wait_counter = 0; ++ ++ do { ++ val = readl(dbi_base + PCIE_PHY_STAT); ++ val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; ++ wait_counter++; ++ ++ if (val == exp_val) ++ return 0; ++ ++ udelay(1); ++ } while (wait_counter < max_iterations); ++ ++ return -ETIMEDOUT; ++} ++ ++static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) ++{ ++ u32 val; ++ int ret; ++ ++ val = addr << PCIE_PHY_CTRL_DATA_LOC; ++ writel(val, dbi_base + PCIE_PHY_CTRL); ++ ++ val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); ++ writel(val, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ val = addr << PCIE_PHY_CTRL_DATA_LOC; ++ writel(val, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ ++static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) ++{ ++ u32 val, phy_ctl; ++ int ret; ++ ++ ret = pcie_phy_wait_ack(dbi_base, addr); ++ if (ret) ++ return ret; ++ ++ /* assert Read signal */ ++ phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; ++ writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ val = readl(dbi_base + PCIE_PHY_STAT); ++ *data = val & 0xffff; ++ ++ /* deassert Read signal */ ++ writel(0x00, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) ++{ ++ u32 var; ++ int ret; ++ ++ /* write addr */ ++ /* cap addr */ ++ ret = pcie_phy_wait_ack(dbi_base, addr); ++ if (ret) ++ return ret; ++ ++ var = data << PCIE_PHY_CTRL_DATA_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* capture data */ ++ var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ /* deassert cap data */ ++ var = data << PCIE_PHY_CTRL_DATA_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* wait for ack de-assertion */ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ /* assert wr signal */ ++ var = 0x1 << PCIE_PHY_CTRL_WR_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* wait for ack */ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ /* deassert wr signal */ ++ var = data << PCIE_PHY_CTRL_DATA_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* wait for ack de-assertion */ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ writel(0x0, dbi_base + PCIE_PHY_CTRL); ++ ++ return 0; ++} ++ ++/* Added for PCI abort handling */ ++static int imx6q_pcie_abort_handler(unsigned long addr, ++ unsigned int fsr, struct pt_regs *regs) ++{ ++ /* ++ * If it was an imprecise abort, then we need to correct the ++ * return address to be _after_ the instruction. ++ */ ++ if (fsr & (1 << 10)) ++ regs->ARM_pc += 4; ++ return 0; ++} ++ ++static int imx6_pcie_assert_core_reset(struct pcie_port *pp) ++{ ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); ++ ++ gpio_set_value(imx6_pcie->reset_gpio, 0); ++ msleep(100); ++ gpio_set_value(imx6_pcie->reset_gpio, 1); ++ ++ return 0; ++} ++ ++static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) ++{ ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ int ret; ++ ++ if (gpio_is_valid(imx6_pcie->power_on_gpio)) ++ gpio_set_value(imx6_pcie->power_on_gpio, 1); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); ++ ++ ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable sata_ref_100m\n"); ++ goto err_sata_ref; ++ } ++ ++ ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable pcie_ref_125m\n"); ++ goto err_pcie_ref; ++ } ++ ++ ret = clk_prepare_enable(imx6_pcie->lvds_gate); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable lvds_gate\n"); ++ goto err_lvds_gate; ++ } ++ ++ ret = clk_prepare_enable(imx6_pcie->pcie_axi); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable pcie_axi\n"); ++ goto err_pcie_axi; ++ } ++ ++ /* allow the clocks to stabilize */ ++ usleep_range(200, 500); ++ ++ return 0; ++ ++err_pcie_axi: ++ clk_disable_unprepare(imx6_pcie->lvds_gate); ++err_lvds_gate: ++ clk_disable_unprepare(imx6_pcie->pcie_ref_125m); ++err_pcie_ref: ++ clk_disable_unprepare(imx6_pcie->sata_ref_100m); ++err_sata_ref: ++ return ret; ++ ++} ++ ++static void imx6_pcie_init_phy(struct pcie_port *pp) ++{ ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); ++ ++ /* configure constant input signal to the pcie ctrl and phy */ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_LOS_LEVEL, 9 << 4); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); ++} ++ ++static void imx6_pcie_host_init(struct pcie_port *pp) ++{ ++ int count = 0; ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ ++ imx6_pcie_assert_core_reset(pp); ++ ++ imx6_pcie_init_phy(pp); ++ ++ imx6_pcie_deassert_core_reset(pp); ++ ++ dw_pcie_setup_rc(pp); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); ++ ++ while (!dw_pcie_link_up(pp)) { ++ usleep_range(100, 1000); ++ count++; ++ if (count >= 10) { ++ dev_err(pp->dev, "phy link never came up\n"); ++ dev_dbg(pp->dev, ++ "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", ++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), ++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); ++ break; ++ } ++ } ++ ++ return; ++} ++ ++static int imx6_pcie_link_up(struct pcie_port *pp) ++{ ++ u32 rc, ltssm, rx_valid, temp; ++ ++ /* link is debug bit 36, debug register 1 starts at bit 32 */ ++ rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); ++ if (rc) ++ return -EAGAIN; ++ ++ /* ++ * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. ++ * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). ++ * If (MAC/LTSSM.state == Recovery.RcvrLock) ++ * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition ++ * to gen2 is stuck ++ */ ++ pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); ++ ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; ++ ++ if (rx_valid & 0x01) ++ return 0; ++ ++ if (ltssm != 0x0d) ++ return 0; ++ ++ dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); ++ ++ pcie_phy_read(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, &temp); ++ temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN ++ | PHY_RX_OVRD_IN_LO_RX_PLL_EN); ++ pcie_phy_write(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, temp); ++ ++ usleep_range(2000, 3000); ++ ++ pcie_phy_read(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, &temp); ++ temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN ++ | PHY_RX_OVRD_IN_LO_RX_PLL_EN); ++ pcie_phy_write(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, temp); ++ ++ return 0; ++} ++ ++static struct pcie_host_ops imx6_pcie_host_ops = { ++ .link_up = imx6_pcie_link_up, ++ .host_init = imx6_pcie_host_init, ++}; ++ ++static int imx6_add_pcie_port(struct pcie_port *pp, ++ struct platform_device *pdev) ++{ ++ int ret; ++ ++ pp->irq = platform_get_irq(pdev, 0); ++ if (!pp->irq) { ++ dev_err(&pdev->dev, "failed to get irq\n"); ++ return -ENODEV; ++ } ++ ++ pp->root_bus_nr = -1; ++ pp->ops = &imx6_pcie_host_ops; ++ ++ spin_lock_init(&pp->conf_lock); ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to initialize host\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int __init imx6_pcie_probe(struct platform_device *pdev) ++{ ++ struct imx6_pcie *imx6_pcie; ++ struct pcie_port *pp; ++ struct device_node *np = pdev->dev.of_node; ++ struct resource *dbi_base; ++ int ret; ++ ++ imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); ++ if (!imx6_pcie) ++ return -ENOMEM; ++ ++ pp = &imx6_pcie->pp; ++ pp->dev = &pdev->dev; ++ ++ /* Added for PCI abort handling */ ++ hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, ++ "imprecise external abort"); ++ ++ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!dbi_base) { ++ dev_err(&pdev->dev, "dbi_base memory resource not found\n"); ++ return -ENODEV; ++ } ++ ++ pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); ++ if (IS_ERR(pp->dbi_base)) { ++ dev_err(&pdev->dev, "unable to remap dbi_base\n"); ++ ret = PTR_ERR(pp->dbi_base); ++ goto err; ++ } ++ ++ /* Fetch GPIOs */ ++ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); ++ if (!gpio_is_valid(imx6_pcie->reset_gpio)) { ++ dev_err(&pdev->dev, "no reset-gpio defined\n"); ++ ret = -ENODEV; ++ } ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->reset_gpio, ++ GPIOF_OUT_INIT_LOW, ++ "PCIe reset"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get reset gpio\n"); ++ goto err; ++ } ++ ++ imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0); ++ if (gpio_is_valid(imx6_pcie->power_on_gpio)) { ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->power_on_gpio, ++ GPIOF_OUT_INIT_LOW, ++ "PCIe power enable"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get power-on gpio\n"); ++ goto err; ++ } ++ } ++ ++ imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0); ++ if (gpio_is_valid(imx6_pcie->wake_up_gpio)) { ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->wake_up_gpio, ++ GPIOF_IN, ++ "PCIe wake up"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get wake-up gpio\n"); ++ goto err; ++ } ++ } ++ ++ imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0); ++ if (gpio_is_valid(imx6_pcie->disable_gpio)) { ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->disable_gpio, ++ GPIOF_OUT_INIT_HIGH, ++ "PCIe disable endpoint"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get disable-ep gpio\n"); ++ goto err; ++ } ++ } ++ ++ /* Fetch clocks */ ++ imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate"); ++ if (IS_ERR(imx6_pcie->lvds_gate)) { ++ dev_err(&pdev->dev, ++ "lvds_gate clock select missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->lvds_gate); ++ goto err; ++ } ++ ++ imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m"); ++ if (IS_ERR(imx6_pcie->sata_ref_100m)) { ++ dev_err(&pdev->dev, ++ "sata_ref_100m clock source missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->sata_ref_100m); ++ goto err; ++ } ++ ++ imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m"); ++ if (IS_ERR(imx6_pcie->pcie_ref_125m)) { ++ dev_err(&pdev->dev, ++ "pcie_ref_125m clock source missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->pcie_ref_125m); ++ goto err; ++ } ++ ++ imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi"); ++ if (IS_ERR(imx6_pcie->pcie_axi)) { ++ dev_err(&pdev->dev, ++ "pcie_axi clock source missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->pcie_axi); ++ goto err; ++ } ++ ++ /* Grab GPR config register range */ ++ imx6_pcie->iomuxc_gpr = ++ syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); ++ if (IS_ERR(imx6_pcie->iomuxc_gpr)) { ++ dev_err(&pdev->dev, "unable to find iomuxc registers\n"); ++ ret = PTR_ERR(imx6_pcie->iomuxc_gpr); ++ goto err; ++ } ++ ++ ret = imx6_add_pcie_port(pp, pdev); ++ if (ret < 0) ++ goto err; ++ ++ platform_set_drvdata(pdev, imx6_pcie); ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static const struct of_device_id imx6_pcie_of_match[] = { ++ { .compatible = "fsl,imx6q-pcie", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); ++ ++static struct platform_driver imx6_pcie_driver = { ++ .driver = { ++ .name = "imx6q-pcie", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(imx6_pcie_of_match), ++ }, ++}; ++ ++/* Freescale PCIe driver does not allow module unload */ ++ ++static int __init imx6_pcie_init(void) ++{ ++ return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); ++} ++module_init(imx6_pcie_init); ++ ++MODULE_AUTHOR("Sean Cross "); ++MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/imx6/patches-3.10/0012-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch b/target/linux/imx6/patches-3.10/0012-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch new file mode 100644 index 0000000000..3f1b6ebfde --- /dev/null +++ b/target/linux/imx6/patches-3.10/0012-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch @@ -0,0 +1,70 @@ +From: Sean Cross +Subject: [PATCH 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q + +The i.MX6 has two general-purpose LVDS clocks that can be driven +from a variety of sources. This patch adds a mux and a gate for +both of these clocks. + +Signed-off-by: Sean Cross +Signed-off-by: Shawn Guo +--- + .../devicetree/bindings/clock/imx6q-clock.txt | 4 ++++ + arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++- + 2 files changed, 23 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt ++++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt +@@ -208,6 +208,10 @@ clocks and IDs. + pll4_post_div 193 + pll5_post_div 194 + pll5_video_div 195 ++ lvds1_sel 204 ++ lvds2_sel 205 ++ lvds1_gate 206 ++ lvds2_gate 207 + + Examples: + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -205,6 +205,11 @@ static const char *vpu_axi_sels[] = { "a + static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", + "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", + "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; ++static const char *lvds_sels[] = { ++ "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", ++ "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", ++ "pcie_ref", "sata_ref", ++}; + + enum mx6q_clks { + dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, +@@ -238,7 +243,8 @@ enum mx6q_clks { + pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, +- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max ++ usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, ++ lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max + }; + + static struct clk *clk[clk_max]; +@@ -340,6 +346,18 @@ int __init mx6q_clocks_init(void) + base + 0xe0, 0, 2, 0, clk_enet_ref_table, + &imx_ccm_lock); + ++ clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); ++ clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); ++ ++ /* ++ * lvds1_gate and lvds2_gate are pseudo-gates. Both can be ++ * independently configured as clock inputs or outputs. We treat ++ * the "output_enable" bit as a gate, even though it's really just ++ * enabling clock output. ++ */ ++ clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); ++ clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); ++ + /* name parent_name reg idx */ + clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); + clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); diff --git a/target/linux/imx6/patches-3.10/0012-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch b/target/linux/imx6/patches-3.10/0012-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch deleted file mode 100644 index 37d26eabf1..0000000000 --- a/target/linux/imx6/patches-3.10/0012-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch +++ /dev/null @@ -1,668 +0,0 @@ -Subject: [v6,3/3] PCI: imx6: Add support for i.MX6 PCIe controller -From: Sean Cross - -Add support for the PCIe port present on the i.MX6 family of controllers. -These use the Synopsis Designware core tied to their own PHY. - -Signed-off-by: Sean Cross -Acked-by: Bjorn Helgaas -Acked-by: Sascha Hauer ---- - arch/arm/boot/dts/imx6qdl.dtsi | 16 + - arch/arm/mach-imx/Kconfig | 2 + - arch/arm/mach-imx/clk-imx6q.c | 4 + - drivers/pci/host/Kconfig | 6 + - drivers/pci/host/Makefile | 1 + - drivers/pci/host/pci-imx6.c | 576 ++++++++++++++++++++ - 7 files changed, 611 insertions(+), 1 deletion(-) - create mode 100644 drivers/pci/host/pci-imx6.c - ---- a/arch/arm/boot/dts/imx6qdl.dtsi -+++ b/arch/arm/boot/dts/imx6qdl.dtsi -@@ -108,6 +108,22 @@ - cache-level = <2>; - }; - -+ pcie: pcie@0x01000000 { -+ compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; -+ reg = <0x01ffc000 0x4000>; /* DBI */ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ -+ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ -+ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ -+ num-lanes = <1>; -+ interrupts = <0 123 0x04>; -+ clocks = <&clks 189>, <&clks 187>, <&clks 205>, <&clks 144>; -+ clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; -+ status = "disabled"; -+ }; -+ - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 0x04>; ---- a/arch/arm/mach-imx/Kconfig -+++ b/arch/arm/mach-imx/Kconfig -@@ -806,6 +806,8 @@ config SOC_IMX6Q - select HAVE_IMX_SRC - select HAVE_SMP - select MFD_SYSCON -+ select MIGHT_HAVE_PCI -+ select PCI_DOMAINS if PCI - select PINCTRL - select PINCTRL_IMX6Q - select PL310_ERRATA_588369 if CACHE_PL310 ---- a/arch/arm/mach-imx/clk-imx6q.c -+++ b/arch/arm/mach-imx/clk-imx6q.c -@@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void) - clk_prepare_enable(clk[usbphy2_gate]); - } - -+ /* All existing boards with PCIe use LVDS1 */ -+ if (IS_ENABLED(CONFIG_PCI_IMX6)) -+ clk_set_parent(clk[lvds1_sel], clk[sata_ref]); -+ - /* Set initial power mode */ - imx6q_set_lpm(WAIT_CLOCKED); - ---- /dev/null -+++ b/drivers/pci/host/Kconfig -@@ -0,0 +1,13 @@ -+menu "PCI host controller drivers" -+ depends on PCI -+ -+config PCIE_DW -+ bool -+ -+config PCI_IMX6 -+ bool "Freescale i.MX6 PCIe controller" -+ depends on SOC_IMX6Q -+ select PCIEPORTBUS -+ select PCIE_DW -+ -+endmenu ---- /dev/null -+++ b/drivers/pci/host/Makefile -@@ -0,0 +1,2 @@ -+obj-$(CONFIG_PCIE_DW) += pcie-designware.o -+obj-$(CONFIG_PCI_IMX6) += pci-imx6.o ---- /dev/null -+++ b/drivers/pci/host/pci-imx6.c -@@ -0,0 +1,576 @@ -+/* -+ * PCIe host controller driver for Freescale i.MX6 SoCs -+ * -+ * Copyright (C) 2013 Kosagi -+ * http://www.kosagi.com -+ * -+ * Author: Sean Cross -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-designware.h" -+ -+#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) -+ -+struct imx6_pcie { -+ int reset_gpio; -+ int power_on_gpio; -+ int wake_up_gpio; -+ int disable_gpio; -+ struct clk *lvds_gate; -+ struct clk *sata_ref_100m; -+ struct clk *pcie_ref_125m; -+ struct clk *pcie_axi; -+ struct pcie_port pp; -+ struct regmap *iomuxc_gpr; -+ void __iomem *mem_base; -+}; -+ -+/* PCIe Port Logic registers (memory-mapped) */ -+#define PL_OFFSET 0x700 -+#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) -+#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) -+ -+#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) -+#define PCIE_PHY_CTRL_DATA_LOC 0 -+#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 -+#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 -+#define PCIE_PHY_CTRL_WR_LOC 18 -+#define PCIE_PHY_CTRL_RD_LOC 19 -+ -+#define PCIE_PHY_STAT (PL_OFFSET + 0x110) -+#define PCIE_PHY_STAT_ACK_LOC 16 -+ -+/* PHY registers (not memory-mapped) */ -+#define PCIE_PHY_RX_ASIC_OUT 0x100D -+ -+#define PHY_RX_OVRD_IN_LO 0x1005 -+#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) -+#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) -+ -+static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) -+{ -+ u32 val; -+ u32 max_iterations = 10; -+ u32 wait_counter = 0; -+ -+ do { -+ val = readl(dbi_base + PCIE_PHY_STAT); -+ val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; -+ wait_counter++; -+ -+ if (val == exp_val) -+ return 0; -+ -+ udelay(1); -+ } while ((wait_counter < max_iterations) && (val != exp_val)); -+ -+ return -ETIMEDOUT; -+} -+ -+static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) -+{ -+ u32 val; -+ int ret; -+ -+ val = addr << PCIE_PHY_CTRL_DATA_LOC; -+ writel(val, dbi_base + PCIE_PHY_CTRL); -+ -+ val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); -+ writel(val, dbi_base + PCIE_PHY_CTRL); -+ -+ ret = pcie_phy_poll_ack(dbi_base, 1); -+ if (ret) -+ return ret; -+ -+ val = addr << PCIE_PHY_CTRL_DATA_LOC; -+ writel(val, dbi_base + PCIE_PHY_CTRL); -+ -+ ret = pcie_phy_poll_ack(dbi_base, 0); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ -+static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) -+{ -+ u32 val, phy_ctl; -+ int ret; -+ -+ ret = pcie_phy_wait_ack(dbi_base, addr); -+ if (ret) -+ return ret; -+ -+ /* assert Read signal */ -+ phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; -+ writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); -+ -+ ret = pcie_phy_poll_ack(dbi_base, 1); -+ if (ret) -+ return ret; -+ -+ val = readl(dbi_base + PCIE_PHY_STAT); -+ *data = val & 0xffff; -+ -+ /* deassert Read signal */ -+ writel(0x00, dbi_base + PCIE_PHY_CTRL); -+ -+ ret = pcie_phy_poll_ack(dbi_base, 0); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) -+{ -+ u32 var; -+ int ret; -+ -+ /* write addr */ -+ /* cap addr */ -+ ret = pcie_phy_wait_ack(dbi_base, addr); -+ if (ret) -+ return ret; -+ -+ var = data << PCIE_PHY_CTRL_DATA_LOC; -+ writel(var, dbi_base + PCIE_PHY_CTRL); -+ -+ /* capture data */ -+ var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); -+ writel(var, dbi_base + PCIE_PHY_CTRL); -+ -+ ret = pcie_phy_poll_ack(dbi_base, 1); -+ if (ret) -+ return ret; -+ -+ /* deassert cap data */ -+ var = data << PCIE_PHY_CTRL_DATA_LOC; -+ writel(var, dbi_base + PCIE_PHY_CTRL); -+ -+ /* wait for ack de-assetion */ -+ ret = pcie_phy_poll_ack(dbi_base, 0); -+ if (ret) -+ return ret; -+ -+ /* assert wr signal */ -+ var = 0x1 << PCIE_PHY_CTRL_WR_LOC; -+ writel(var, dbi_base + PCIE_PHY_CTRL); -+ -+ /* wait for ack */ -+ ret = pcie_phy_poll_ack(dbi_base, 1); -+ if (ret) -+ return ret; -+ -+ /* deassert wr signal */ -+ var = data << PCIE_PHY_CTRL_DATA_LOC; -+ writel(var, dbi_base + PCIE_PHY_CTRL); -+ -+ /* wait for ack de-assetion */ -+ ret = pcie_phy_poll_ack(dbi_base, 0); -+ if (ret) -+ return ret; -+ -+ writel(0x0, dbi_base + PCIE_PHY_CTRL); -+ -+ return 0; -+} -+ -+/* Added for PCI abort handling */ -+static int imx6q_pcie_abort_handler(unsigned long addr, -+ unsigned int fsr, struct pt_regs *regs) -+{ -+ /* -+ * If it was an imprecise abort, then we need to correct the -+ * return address to be _after_ the instruction. -+ */ -+ if (fsr & (1 << 10)) -+ regs->ARM_pc += 4; -+ return 0; -+} -+ -+static int imx6_pcie_assert_core_reset(struct pcie_port *pp) -+{ -+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); -+ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, -+ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); -+ -+ gpio_set_value(imx6_pcie->reset_gpio, 0); -+ msleep(100); -+ gpio_set_value(imx6_pcie->reset_gpio, 1); -+ -+ return 0; -+} -+ -+static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) -+{ -+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); -+ int ret; -+ -+ if (gpio_is_valid(imx6_pcie->power_on_gpio)) -+ gpio_set_value(imx6_pcie->power_on_gpio, 1); -+ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); -+ -+ ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); -+ if (ret) { -+ dev_err(pp->dev, "unable to enable sata_ref_100m\n"); -+ goto err_sata_ref; -+ } -+ -+ ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m); -+ if (ret) { -+ dev_err(pp->dev, "unable to enable pcie_ref_125m\n"); -+ goto err_pcie_ref; -+ } -+ -+ ret = clk_prepare_enable(imx6_pcie->lvds_gate); -+ if (ret) { -+ dev_err(pp->dev, "unable to enable lvds_gate\n"); -+ goto err_lvds_gate; -+ } -+ -+ ret = clk_prepare_enable(imx6_pcie->pcie_axi); -+ if (ret) { -+ dev_err(pp->dev, "unable to enable pcie_axi\n"); -+ goto err_pcie_axi; -+ } -+ -+ /* allow the clocks to stabilize */ -+ usleep_range(200, 500); -+ -+ return 0; -+ -+err_pcie_axi: -+ clk_disable_unprepare(imx6_pcie->lvds_gate); -+err_lvds_gate: -+ clk_disable_unprepare(imx6_pcie->pcie_ref_125m); -+err_pcie_ref: -+ clk_disable_unprepare(imx6_pcie->sata_ref_100m); -+err_sata_ref: -+ return ret; -+ -+} -+ -+static void imx6_pcie_init_phy(struct pcie_port *pp) -+{ -+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); -+ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, -+ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); -+ -+ /* configure constant input signal to the pcie ctrl and phy */ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, -+ IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, -+ IMX6Q_GPR12_LOS_LEVEL, 9 << 4); -+ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, -+ IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, -+ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, -+ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, -+ IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, -+ IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); -+} -+ -+static void imx6_pcie_host_init(struct pcie_port *pp) -+{ -+ int count = 0; -+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); -+ -+ imx6_pcie_assert_core_reset(pp); -+ -+ imx6_pcie_init_phy(pp); -+ -+ imx6_pcie_deassert_core_reset(pp); -+ -+ dw_pcie_setup_rc(pp); -+ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, -+ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); -+ -+ while (!dw_pcie_link_up(pp)) { -+ usleep_range(100, 1000); -+ count++; -+ if (count >= 10) { -+ dev_err(pp->dev, "phy link never came up\n"); -+ dev_dbg(pp->dev, -+ "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", -+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), -+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); -+ break; -+ } -+ } -+ -+ return; -+} -+ -+static int imx6_pcie_link_up(struct pcie_port *pp) -+{ -+ u32 rc, ltssm, rx_valid, temp; -+ -+ /* link is debug bit 36, debug register 1 starts at bit 32 */ -+ rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); -+ if (rc) -+ return -EAGAIN; -+ -+ /* -+ * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. -+ * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). -+ * If (MAC/LTSSM.state == Recovery.RcvrLock) -+ * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition -+ * to gen2 is stuck -+ */ -+ pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); -+ ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; -+ -+ if (rx_valid & 0x01) -+ return 0; -+ -+ if (ltssm != 0x0d) -+ return 0; -+ -+ dev_err(pp->dev, -+ "transition to gen2 is stuck, reset PHY!\n"); -+ -+ pcie_phy_read(pp->dbi_base, -+ PHY_RX_OVRD_IN_LO, &temp); -+ temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN -+ | PHY_RX_OVRD_IN_LO_RX_PLL_EN); -+ pcie_phy_write(pp->dbi_base, -+ PHY_RX_OVRD_IN_LO, temp); -+ -+ usleep_range(2000, 3000); -+ -+ pcie_phy_read(pp->dbi_base, -+ PHY_RX_OVRD_IN_LO, &temp); -+ temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN -+ | PHY_RX_OVRD_IN_LO_RX_PLL_EN); -+ pcie_phy_write(pp->dbi_base, -+ PHY_RX_OVRD_IN_LO, temp); -+ -+ return 0; -+} -+ -+static struct pcie_host_ops imx6_pcie_host_ops = { -+ .link_up = imx6_pcie_link_up, -+ .host_init = imx6_pcie_host_init, -+}; -+ -+static int imx6_add_pcie_port(struct pcie_port *pp, -+ struct platform_device *pdev) -+{ -+ int ret; -+ -+ pp->irq = platform_get_irq(pdev, 0); -+ if (!pp->irq) { -+ dev_err(&pdev->dev, "failed to get irq\n"); -+ return -ENODEV; -+ } -+ -+ pp->root_bus_nr = -1; -+ pp->ops = &imx6_pcie_host_ops; -+ -+ spin_lock_init(&pp->conf_lock); -+ ret = dw_pcie_host_init(pp); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to initialize host\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int __init imx6_pcie_probe(struct platform_device *pdev) -+{ -+ struct imx6_pcie *imx6_pcie; -+ struct pcie_port *pp; -+ struct device_node *np = pdev->dev.of_node; -+ struct resource *dbi_base; -+ int ret; -+ -+ imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); -+ if (!imx6_pcie) -+ return -ENOMEM; -+ -+ pp = &imx6_pcie->pp; -+ pp->dev = &pdev->dev; -+ -+ /* Added for PCI abort handling */ -+ hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, -+ "imprecise external abort"); -+ -+ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!dbi_base) { -+ dev_err(&pdev->dev, "dbi_base memory resource not found\n"); -+ return -ENODEV; -+ } -+ -+ pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); -+ if (IS_ERR(pp->dbi_base)) { -+ dev_err(&pdev->dev, "unable to remap dbi_base\n"); -+ ret = PTR_ERR(pp->dbi_base); -+ goto err; -+ } -+ -+ /* Fetch GPIOs */ -+ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); -+ if (!gpio_is_valid(imx6_pcie->reset_gpio)) { -+ dev_err(&pdev->dev, "no reset-gpio defined\n"); -+ ret = -ENODEV; -+ } -+ ret = devm_gpio_request_one(&pdev->dev, -+ imx6_pcie->reset_gpio, -+ GPIOF_OUT_INIT_LOW, -+ "PCIe reset"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to get reset gpio\n"); -+ goto err; -+ } -+ -+ imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0); -+ if (gpio_is_valid(imx6_pcie->power_on_gpio)) { -+ ret = devm_gpio_request_one(&pdev->dev, -+ imx6_pcie->power_on_gpio, -+ GPIOF_OUT_INIT_LOW, -+ "PCIe power enable"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to get power-on gpio\n"); -+ goto err; -+ } -+ } -+ -+ imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0); -+ if (gpio_is_valid(imx6_pcie->wake_up_gpio)) { -+ ret = devm_gpio_request_one(&pdev->dev, -+ imx6_pcie->wake_up_gpio, -+ GPIOF_IN, -+ "PCIe wake up"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to get wake-up gpio\n"); -+ goto err; -+ } -+ } -+ -+ imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0); -+ if (gpio_is_valid(imx6_pcie->disable_gpio)) { -+ ret = devm_gpio_request_one(&pdev->dev, -+ imx6_pcie->disable_gpio, -+ GPIOF_OUT_INIT_HIGH, -+ "PCIe disable endpoint"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to get disable-ep gpio\n"); -+ goto err; -+ } -+ } -+ -+ /* Fetch clocks */ -+ imx6_pcie->lvds_gate = clk_get(&pdev->dev, "lvds_gate"); -+ if (IS_ERR(imx6_pcie->lvds_gate)) { -+ dev_err(&pdev->dev, -+ "lvds_gate clock select missing or invalid\n"); -+ ret = PTR_ERR(imx6_pcie->lvds_gate); -+ goto err; -+ } -+ -+ imx6_pcie->sata_ref_100m = clk_get(&pdev->dev, "sata_ref_100m"); -+ if (IS_ERR(imx6_pcie->sata_ref_100m)) { -+ dev_err(&pdev->dev, -+ "sata_ref_100m clock source missing or invalid\n"); -+ ret = PTR_ERR(imx6_pcie->sata_ref_100m); -+ goto err; -+ } -+ -+ imx6_pcie->pcie_ref_125m = clk_get(&pdev->dev, "pcie_ref_125m"); -+ if (IS_ERR(imx6_pcie->pcie_ref_125m)) { -+ dev_err(&pdev->dev, -+ "pcie_ref_125m clock source missing or invalid\n"); -+ ret = PTR_ERR(imx6_pcie->pcie_ref_125m); -+ goto err; -+ } -+ -+ imx6_pcie->pcie_axi = clk_get(&pdev->dev, "pcie_axi"); -+ if (IS_ERR(imx6_pcie->pcie_axi)) { -+ dev_err(&pdev->dev, -+ "pcie_axi clock source missing or invalid\n"); -+ ret = PTR_ERR(imx6_pcie->pcie_axi); -+ goto err; -+ } -+ -+ /* Grab GPR config register range */ -+ imx6_pcie->iomuxc_gpr = -+ syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); -+ if (IS_ERR(imx6_pcie->iomuxc_gpr)) { -+ dev_err(&pdev->dev, "unable to find iomuxc registers\n"); -+ ret = PTR_ERR(imx6_pcie->iomuxc_gpr); -+ goto err; -+ } -+ -+ ret = imx6_add_pcie_port(pp, pdev); -+ if (ret < 0) -+ goto err; -+ -+ platform_set_drvdata(pdev, imx6_pcie); -+ return 0; -+ -+err: -+ return ret; -+} -+ -+static const struct of_device_id imx6_pcie_of_match[] = { -+ { .compatible = "fsl,imx6q-pcie", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); -+ -+static struct platform_driver imx6_pcie_driver = { -+ .driver = { -+ .name = "imx6q-pcie", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(imx6_pcie_of_match), -+ }, -+}; -+ -+/* Freescale PCIe driver does not allow module unload */ -+ -+static int __init imx6_init(void) -+{ -+ return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); -+} -+module_init(imx6_init); -+ -+MODULE_AUTHOR("Sean Cross "); -+MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/imx6/patches-3.10/0013-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch b/target/linux/imx6/patches-3.10/0013-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch new file mode 100644 index 0000000000..25f207af07 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0013-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch @@ -0,0 +1,38 @@ +From 4f6723e8ff497e35c8f2fb20886fccc533c58cdb Mon Sep 17 00:00:00 2001 +From: Sean Cross +Date: Thu, 26 Sep 2013 10:45:35 +0800 +Subject: [PATCH] ARM: imx6q: clock and Kconfig update for PCIe support + +Update imx6q clock initialization and Kconfig for PCIe support. + +Signed-off-by: Sean Cross +Signed-off-by: Shawn Guo +--- + arch/arm/mach-imx/Kconfig | 2 ++ + arch/arm/mach-imx/clk-imx6q.c | 4 ++++ + 2 files changed, 6 insertions(+) + +--- a/arch/arm/mach-imx/Kconfig ++++ b/arch/arm/mach-imx/Kconfig +@@ -806,6 +806,8 @@ config SOC_IMX6Q + select HAVE_IMX_SRC + select HAVE_SMP + select MFD_SYSCON ++ select MIGHT_HAVE_PCI ++ select PCI_DOMAINS if PCI + select PINCTRL + select PINCTRL_IMX6Q + select PL310_ERRATA_588369 if CACHE_PL310 +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void) + clk_prepare_enable(clk[usbphy2_gate]); + } + ++ /* All existing boards with PCIe use LVDS1 */ ++ if (IS_ENABLED(CONFIG_PCI_IMX6)) ++ clk_set_parent(clk[lvds1_sel], clk[sata_ref]); ++ + /* Set initial power mode */ + imx6q_set_lpm(WAIT_CLOCKED); + diff --git a/target/linux/imx6/patches-3.10/0014-ARM-dts-imx6qdl-add-pcie-device-node.patch b/target/linux/imx6/patches-3.10/0014-ARM-dts-imx6qdl-add-pcie-device-node.patch new file mode 100644 index 0000000000..e78d9ba8b0 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0014-ARM-dts-imx6qdl-add-pcie-device-node.patch @@ -0,0 +1,38 @@ +From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001 +From: Sean Cross +Date: Thu, 26 Sep 2013 10:51:09 +0800 +Subject: [PATCH] ARM: dts: imx6qdl: add pcie device node + +Add pcie device node for imx6qdl. + +Signed-off-by: Sean Cross +Signed-off-by: Shawn Guo +--- + arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -108,6 +108,22 @@ + cache-level = <2>; + }; + ++ pcie: pcie@0x01000000 { ++ compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; ++ reg = <0x01ffc000 0x4000>; /* DBI */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ ++ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ ++ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ ++ num-lanes = <1>; ++ interrupts = <0 123 0x04>; ++ clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; ++ clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; ++ status = "disabled"; ++ }; ++ + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 94 0x04>; diff --git a/target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch b/target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch index bd20d2d25c..0b7ac7d308 100644 --- a/target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch +++ b/target/linux/imx6/patches-3.10/0015-thermal-add-imx-thermal-driver-support.patch @@ -25,9 +25,6 @@ Signed-off-by: Eduardo Valentin create mode 100644 Documentation/devicetree/bindings/thermal/imx-thermal.txt create mode 100644 drivers/thermal/imx_thermal.c -diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt -new file mode 100644 -index 0000000..541c25e --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt @@ -0,0 +1,17 @@ @@ -48,8 +45,6 @@ index 0000000..541c25e + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; +}; -diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index e988c81..69eed55 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -91,6 +91,17 @@ config THERMAL_EMULATION @@ -70,21 +65,16 @@ index e988c81..69eed55 100644 config SPEAR_THERMAL bool "SPEAr thermal sensor driver" depends on PLAT_SPEAR -diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index 67184a2..dff19c6 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_thermal.o +@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_t obj-$(CONFIG_DOVE_THERMAL) += dove_thermal.o obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o +obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o - obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o -diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c -new file mode 100644 -index 0000000..d16c33c + --- /dev/null +++ b/drivers/thermal/imx_thermal.c @@ -0,0 +1,397 @@ @@ -485,6 +475,3 @@ index 0000000..d16c33c +MODULE_DESCRIPTION("Thermal driver for Freescale i.MX SoCs"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:imx-thermal"); --- -1.8.4 - diff --git a/target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch b/target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch index aef6b05f48..2aea7084c7 100644 --- a/target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch +++ b/target/linux/imx6/patches-3.10/010-pcie-backport-fixes.patch @@ -1,3 +1,14 @@ +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -119,7 +119,7 @@ + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <0 123 0x04>; +- clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; ++ clocks = <&clks 189>, <&clks 187>, <&clks 198>, <&clks 144>; + clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + status = "disabled"; + }; --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -125,3 +125,5 @@ config PCI_IOAPIC diff --git a/target/linux/imx6/patches-3.10/011-pci-tweaks.patch b/target/linux/imx6/patches-3.10/011-pci-tweaks.patch index 08a08fb43f..eda007eb6d 100644 --- a/target/linux/imx6/patches-3.10/011-pci-tweaks.patch +++ b/target/linux/imx6/patches-3.10/011-pci-tweaks.patch @@ -1,14 +1,3 @@ ---- a/arch/arm/boot/dts/imx6qdl.dtsi -+++ b/arch/arm/boot/dts/imx6qdl.dtsi -@@ -119,7 +119,7 @@ - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <0 123 0x04>; -- clocks = <&clks 189>, <&clks 187>, <&clks 205>, <&clks 144>; -+ clocks = <&clks 189>, <&clks 187>, <&clks 198>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; - status = "disabled"; - }; --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem *