From: Dan Handley Date: Wed, 14 May 2014 16:44:19 +0000 (+0100) Subject: Split platform.h into separate headers X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=5f0cdb059d7d5c3a8a834074a7f236b85d014dde;p=project%2Fbcm63xx%2Fatf.git Split platform.h into separate headers Previously, platform.h contained many declarations and definitions used for different purposes. This file has been split so that: * Platform definitions used by common code that must be defined by the platform are now in platform_def.h. The exact include path is exported through $PLAT_INCLUDES in the platform makefile. * Platform definitions specific to the FVP platform are now in /plat/fvp/fvp_def.h. * Platform API declarations specific to the FVP platform are now in /plat/fvp/fvp_private.h. * The remaining platform API declarations that must be ported by each platform are still in platform.h but this file has been moved to /include/plat/common since this can be shared by all platforms. Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a --- diff --git a/Makefile b/Makefile index 1069cd5a..22f1fd6b 100644 --- a/Makefile +++ b/Makefile @@ -160,9 +160,9 @@ INCLUDES += -Iinclude/bl1 \ -Iinclude/drivers/arm \ -Iinclude/lib \ -Iinclude/lib/aarch64 \ + -Iinclude/plat/common \ -Iinclude/stdlib \ -Iinclude/stdlib/sys \ - -Iplat/${PLAT} \ ${PLAT_INCLUDES} \ ${SPD_INCLUDES} diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 1af2a32d..967ba328 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index da81839b..6028f4f1 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include "bl1_private.h" diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 9f02e92c..e348d4fc 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 81fecd67..55ae3c0e 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include "bl2_private.h" diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 4789b33b..7e119c58 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include .globl runtime_exceptions diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 068d3181..15017429 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c index 2e7e62d7..b3dcf2d1 100644 --- a/bl31/context_mgmt.c +++ b/bl31/context_mgmt.c @@ -37,6 +37,7 @@ #include #include #include +#include #include /******************************************************************************* diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index c72fefbd..187915b6 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c index 5719c063..ac45d7af 100644 --- a/bl32/tsp/tsp_interrupt.c +++ b/bl32/tsp/tsp_interrupt.c @@ -34,6 +34,7 @@ #include #include #include +#include /******************************************************************************* * This function updates the TSP statistics for FIQs handled synchronously i.e diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index ad7ee0a2..05737aef 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c index f66ff9fa..366640f4 100644 --- a/bl32/tsp/tsp_timer.c +++ b/bl32/tsp/tsp_timer.c @@ -29,6 +29,7 @@ */ #include #include +#include #include /******************************************************************************* diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c index 02f7f955..af10f214 100644 --- a/drivers/arm/cci400/cci400.c +++ b/drivers/arm/cci400/cci400.c @@ -30,7 +30,7 @@ #include #include -#include +#include static inline unsigned long get_slave_iface_base(unsigned long mpidr) { diff --git a/drivers/arm/pl011/pl011.c b/drivers/arm/pl011/pl011.c index f12bd23d..e296c23f 100644 --- a/drivers/arm/pl011/pl011.c +++ b/drivers/arm/pl011/pl011.c @@ -29,7 +29,6 @@ */ #include -#include #include void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate) diff --git a/drivers/arm/pl011/pl011_console.c b/drivers/arm/pl011/pl011_console.c index 06e357f9..0e82aa21 100644 --- a/drivers/arm/pl011/pl011_console.c +++ b/drivers/arm/pl011/pl011_console.c @@ -30,7 +30,6 @@ #include #include -#include #include static unsigned long uart_base; diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index 8ed7f473..36788a24 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -29,6 +29,7 @@ */ #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include #include +#include #include #include #include diff --git a/include/bl32/payloads/tsp.h b/include/bl32/payloads/tsp.h index 237ad483..2db3b346 100644 --- a/include/bl32/payloads/tsp.h +++ b/include/bl32/payloads/tsp.h @@ -113,7 +113,7 @@ #ifndef __ASSEMBLY__ #include -#include /* For CACHE_WRITEBACK_GRANULE */ +#include /* For CACHE_WRITEBACK_GRANULE */ #include #include diff --git a/include/drivers/io_driver.h b/include/drivers/io_driver.h index f34c71d5..867abbfa 100644 --- a/include/drivers/io_driver.h +++ b/include/drivers/io_driver.h @@ -32,7 +32,7 @@ #define __IO_DRIVER_H__ #include -#include /* For MAX_IO_DEVICES */ +#include /* For MAX_IO_DEVICES */ #include diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 920dfc9b..d89b4fe9 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -394,4 +394,19 @@ #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK +/******************************************************************************* + * Definitions of register offsets and fields in the CNTCTLBase Frame of the + * system level implementation of the Generic Timer. + ******************************************************************************/ +#define CNTNSAR 0x4 +#define CNTNSAR_NS_SHIFT(x) x + +#define CNTACR_BASE(x) (0x40 + (x << 2)) +#define CNTACR_RPCT_SHIFT 0x0 +#define CNTACR_RVCT_SHIFT 0x1 +#define CNTACR_RFRQ_SHIFT 0x2 +#define CNTACR_RVOFF_SHIFT 0x3 +#define CNTACR_RWVT_SHIFT 0x4 +#define CNTACR_RWPT_SHIFT 0x5 + #endif /* __ARCH_H__ */ diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h index e6744a51..037fa7d1 100644 --- a/include/lib/bakery_lock.h +++ b/include/lib/bakery_lock.h @@ -31,7 +31,7 @@ #ifndef __BAKERY_LOCK_H__ #define __BAKERY_LOCK_H__ -#include +#include #define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h new file mode 100644 index 00000000..b3f6806e --- /dev/null +++ b/include/plat/common/platform.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#include + + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct plat_pm_ops; +struct meminfo; +struct image_info; +struct entry_point_info; + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void bl1_plat_arch_setup(void); +void bl2_plat_arch_setup(void); +void bl31_plat_arch_setup(void); +int platform_setup_pm(const struct plat_pm_ops **); +unsigned int platform_get_core_pos(unsigned long mpidr); +void enable_mmu_el1(void); +void enable_mmu_el3(void); +void configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +void configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); +void plat_report_exception(unsigned long); +unsigned long plat_get_ns_image_entrypoint(void); +unsigned long platform_get_stack(unsigned long mpidr); +uint64_t plat_get_syscnt_freq(void); +uint32_t ic_get_pending_interrupt_id(void); +uint32_t ic_get_pending_interrupt_type(void); +uint32_t ic_acknowledge_interrupt(void); +uint32_t ic_get_interrupt_type(uint32_t id); +void ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +int plat_get_max_afflvl(void); +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); +int plat_get_image_source(const char *image_name, + uintptr_t *dev_handle, + uintptr_t *image_spec); + +/* + * Before calling this function BL2 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL2 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl1_plat_set_bl2_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* + * Before calling this function BL31 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL31 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* + * Before calling this function BL32 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL32 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* + * Before calling this function BL33 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL33 and set SPSR and security state. + * On FVP we are only setting the security state, entrypoint + */ +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL32 */ +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); + +/* Gets the memory layout for BL33 */ +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); + + +#endif /* __PLATFORM_H__ */ diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c index 48b07149..4e935a50 100644 --- a/lib/aarch64/xlat_tables.c +++ b/lib/aarch64/xlat_tables.c @@ -29,7 +29,7 @@ */ #include -#include +#include #include #include diff --git a/lib/locks/bakery/bakery_lock.c b/lib/locks/bakery/bakery_lock.c index 6d4ab87b..4e148b5a 100644 --- a/lib/locks/bakery/bakery_lock.c +++ b/lib/locks/bakery/bakery_lock.c @@ -31,6 +31,7 @@ #include #include #include +#include #include /* diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 7e201213..f6ac13eb 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -30,7 +30,7 @@ #include #include -#include +#include .weak platform_get_core_pos diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S index ebbf509b..801ec7fa 100644 --- a/plat/common/aarch64/platform_mp_stack.S +++ b/plat/common/aarch64/platform_mp_stack.S @@ -30,7 +30,7 @@ #include #include -#include +#include .local pcpu_dv_mem_stack diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S index 880793d8..45a96a64 100644 --- a/plat/common/aarch64/platform_up_stack.S +++ b/plat/common/aarch64/platform_up_stack.S @@ -30,7 +30,7 @@ #include #include -#include +#include .local pcpu_dv_mem_stack diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c index 2845f3e4..f0a06d83 100644 --- a/plat/fvp/aarch64/plat_common.c +++ b/plat/fvp/aarch64/plat_common.c @@ -37,6 +37,7 @@ #include #include #include +#include "../fvp_def.h" /******************************************************************************* * This array holds the characteristics of the differences between the three diff --git a/plat/fvp/aarch64/plat_helpers.S b/plat/fvp/aarch64/plat_helpers.S index f1c2c09b..fbb2fce3 100644 --- a/plat/fvp/aarch64/plat_helpers.S +++ b/plat/fvp/aarch64/plat_helpers.S @@ -32,8 +32,8 @@ #include #include #include -#include #include "../drivers/pwrc/fvp_pwrc.h" +#include "../fvp_def.h" .globl platform_get_entrypoint .globl plat_secondary_cold_boot_setup diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c index 45eb7540..5fbebc16 100644 --- a/plat/fvp/bl1_plat_setup.c +++ b/plat/fvp/bl1_plat_setup.c @@ -35,6 +35,9 @@ #include #include #include +#include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c index cf987ff7..87efe28f 100644 --- a/plat/fvp/bl2_plat_setup.c +++ b/plat/fvp/bl2_plat_setup.c @@ -34,7 +34,10 @@ #include #include #include +#include #include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c index 7b60a780..d1e16bd5 100644 --- a/plat/fvp/bl31_plat_setup.c +++ b/plat/fvp/bl31_plat_setup.c @@ -38,6 +38,8 @@ #include #include #include "drivers/pwrc/fvp_pwrc.h" +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_plat_setup.c index 772e972f..79303142 100644 --- a/plat/fvp/bl32_plat_setup.c +++ b/plat/fvp/bl32_plat_setup.c @@ -33,6 +33,8 @@ #include #include #include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout diff --git a/plat/fvp/drivers/pwrc/fvp_pwrc.c b/plat/fvp/drivers/pwrc/fvp_pwrc.c index 7a7f5168..d1feecef 100644 --- a/plat/fvp/drivers/pwrc/fvp_pwrc.c +++ b/plat/fvp/drivers/pwrc/fvp_pwrc.c @@ -30,6 +30,7 @@ #include #include +#include "../../fvp_def.h" #include "fvp_pwrc.h" /* diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h new file mode 100644 index 00000000..9072a220 --- /dev/null +++ b/plat/fvp/fvp_def.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_DEF_H__ +#define __FVP_DEF_H__ + +#include /* for TZROM_SIZE */ + + +/* Firmware Image Package */ +#define FIP_IMAGE_NAME "fip.bin" + +/* Constants for accessing platform configuration */ +#define CONFIG_GICD_ADDR 0 +#define CONFIG_GICC_ADDR 1 +#define CONFIG_GICH_ADDR 2 +#define CONFIG_GICV_ADDR 3 +#define CONFIG_MAX_AFF0 4 +#define CONFIG_MAX_AFF1 5 +/* Indicate whether the CPUECTLR SMP bit should be enabled. */ +#define CONFIG_CPU_SETUP 6 +#define CONFIG_BASE_MMAP 7 +/* Indicates whether CCI should be enabled on the platform. */ +#define CONFIG_HAS_CCI 8 +#define CONFIG_HAS_TZC 9 +#define CONFIG_LIMIT 10 + +/******************************************************************************* + * FVP memory map related constants + ******************************************************************************/ + +#define FLASH0_BASE 0x08000000 +#define FLASH0_SIZE TZROM_SIZE + +#define FLASH1_BASE 0x0c000000 +#define FLASH1_SIZE 0x04000000 + +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x04000000 + +#define VRAM_BASE 0x18000000 +#define VRAM_SIZE 0x02000000 + +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE 0x1a000000 +#define DEVICE0_SIZE 0x12200000 + +#define DEVICE1_BASE 0x2f000000 +#define DEVICE1_SIZE 0x200000 + +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x10000 + +#define MBOX_OFF 0x1000 + +/* Base address where parameters to BL31 are stored */ +#define PARAMS_BASE TZDRAM_BASE + +#define DRAM1_BASE 0x80000000ull +#define DRAM1_SIZE 0x80000000ull +#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) +#define DRAM1_SEC_SIZE 0x01000000ull + +#define DRAM_BASE DRAM1_BASE +#define DRAM_SIZE DRAM1_SIZE + +#define DRAM2_BASE 0x880000000ull +#define DRAM2_SIZE 0x780000000ull +#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) + +#define PCIE_EXP_BASE 0x40000000 +#define TZRNG_BASE 0x7fe60000 +#define TZNVCTR_BASE 0x7fe70000 +#define TZROOTKEY_BASE 0x7fe80000 + +/* Memory mapped Generic timer interfaces */ +#define SYS_CNTCTL_BASE 0x2a430000 +#define SYS_CNTREAD_BASE 0x2a800000 +#define SYS_TIMCTL_BASE 0x2a810000 + +/* V2M motherboard system registers & offsets */ +#define VE_SYSREGS_BASE 0x1c010000 +#define V2M_SYS_ID 0x0 +#define V2M_SYS_LED 0x8 +#define V2M_SYS_CFGDATA 0xa0 +#define V2M_SYS_CFGCTRL 0xa4 + +/* Load address of BL33 in the FVP port */ +#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ + +/* + * V2M sysled bit definitions. The values written to this + * register are defined in arch.h & runtime_svc.h. Only + * used by the primary cpu to diagnose any cold boot issues. + * + * SYS_LED[0] - Security state (S=0/NS=1) + * SYS_LED[2:1] - Exception Level (EL3-EL0) + * SYS_LED[7:3] - Exception Class (Sync/Async & origin) + * + */ +#define SYS_LED_SS_SHIFT 0x0 +#define SYS_LED_EL_SHIFT 0x1 +#define SYS_LED_EC_SHIFT 0x3 + +#define SYS_LED_SS_MASK 0x1 +#define SYS_LED_EL_MASK 0x3 +#define SYS_LED_EC_MASK 0x1f + +/* V2M sysid register bits */ +#define SYS_ID_REV_SHIFT 27 +#define SYS_ID_HBI_SHIFT 16 +#define SYS_ID_BLD_SHIFT 12 +#define SYS_ID_ARCH_SHIFT 8 +#define SYS_ID_FPGA_SHIFT 0 + +#define SYS_ID_REV_MASK 0xf +#define SYS_ID_HBI_MASK 0xfff +#define SYS_ID_BLD_MASK 0xf +#define SYS_ID_ARCH_MASK 0xf +#define SYS_ID_FPGA_MASK 0xff + +#define SYS_ID_BLD_LENGTH 4 + +#define REV_FVP 0x0 +#define HBI_FVP_BASE 0x020 +#define HBI_FOUNDATION 0x010 + +#define BLD_GIC_VE_MMAP 0x0 +#define BLD_GIC_A53A57_MMAP 0x1 + +#define ARCH_MODEL 0x1 + +/* FVP Power controller base address*/ +#define PWRC_BASE 0x1c100000 + + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI400_BASE 0x2c090000 +#define CCI400_SL_IFACE_CLUSTER0 3 +#define CCI400_SL_IFACE_CLUSTER1 4 +#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ + CCI400_SL_IFACE_CLUSTER1 : \ + CCI400_SL_IFACE_CLUSTER0) + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +/* VE compatible GIC memory map */ +#define VE_GICD_BASE 0x2c001000 +#define VE_GICC_BASE 0x2c002000 +#define VE_GICH_BASE 0x2c004000 +#define VE_GICV_BASE 0x2c006000 + +/* Base FVP compatible GIC memory map */ +#define BASE_GICD_BASE 0x2f000000 +#define BASE_GICR_BASE 0x2f100000 +#define BASE_GICC_BASE 0x2c000000 +#define BASE_GICH_BASE 0x2c010000 +#define BASE_GICV_BASE 0x2c02f000 + +#define IRQ_TZ_WDOG 56 +#define IRQ_SEC_PHY_TIMER 29 +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 +#define IRQ_SEC_SGI_8 16 + +/******************************************************************************* + * PL011 related constants + ******************************************************************************/ +#define PL011_UART0_BASE 0x1c090000 +#define PL011_UART1_BASE 0x1c0a0000 +#define PL011_UART2_BASE 0x1c0b0000 +#define PL011_UART3_BASE 0x1c0c0000 + +/******************************************************************************* + * TrustZone address space controller related constants + ******************************************************************************/ +#define TZC400_BASE 0x2a4a0000 + +/* + * The NSAIDs for this platform as used to program the TZC400. + */ + +/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */ +#define FVP_AID_WIDTH 4 + +/* NSAIDs used by devices in TZC filter 0 on FVP */ +#define FVP_NSAID_DEFAULT 0 +#define FVP_NSAID_PCI 1 +#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ +#define FVP_NSAID_AP 9 /* Application Processors */ +#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ + +/* NSAIDs used by devices in TZC filter 2 on FVP */ +#define FVP_NSAID_HDLCD0 2 +#define FVP_NSAID_CLCD 7 + + +#endif /* __FVP_DEF_H__ */ diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h new file mode 100644 index 00000000..cde1fd0a --- /dev/null +++ b/plat/fvp/fvp_private.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PRIVATE_H__ +#define __FVP_PRIVATE_H__ + +#include +#include + + +typedef volatile struct mailbox { + unsigned long value + __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); +} mailbox_t; + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31 e.g. while passing control to it from BL2 which is bl31_params + * and bl31_plat_params and its elements + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +unsigned long platform_get_cfgvar(unsigned int); +int platform_config_setup(void); + +#if RESET_TO_BL31 +void plat_get_entry_point_info(unsigned long target_security, + struct entry_point_info *target_entry_info); +#endif +void fvp_cci_setup(void); + +/* Declarations for fvp_gic.c */ +void gic_cpuif_deactivate(unsigned int); +void gic_cpuif_setup(unsigned int); +void gic_pcpu_distif_setup(unsigned int); +void gic_setup(void); + +/* Declarations for fvp_topology.c */ +int plat_setup_topology(void); + +/* Declarations for plat_io_storage.c */ +void io_setup(void); + +/* Declarations for plat_security.c */ +void plat_security_setup(void); + +/* Sets the entrypoint for BL32 */ +void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep); + +/* Sets the entrypoint for BL33 */ +void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep); + + +#endif /* __FVP_PRIVATE_H__ */ diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S index 0b9b2e26..1fa50fd1 100644 --- a/plat/fvp/include/plat_macros.S +++ b/plat/fvp/include/plat_macros.S @@ -29,7 +29,7 @@ */ #include -#include +#include "../fvp_def.h" .section .rodata.gic_reg_name, "aS" gic_regs: .asciz "gic_iar", "gic_ctlr", "" diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h new file mode 100644 index 00000000..46a9f24c --- /dev/null +++ b/plat/fvp/include/platform_def.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include + + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE 0x800 + +/* Size of coherent stacks for debug and release builds */ +#if DEBUG +#define PCPU_DV_MEM_STACK_SIZE 0x400 +#else +#define PCPU_DV_MEM_STACK_SIZE 0x300 +#endif + +#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r" + +/* Trusted Boot Firmware BL2 */ +#define BL2_IMAGE_NAME "bl2.bin" + +/* EL3 Runtime Firmware BL31 */ +#define BL31_IMAGE_NAME "bl31.bin" + +/* Secure Payload BL32 (Trusted OS) */ +#define BL32_IMAGE_NAME "bl32.bin" + +/* Non-Trusted Firmware BL33 */ +#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ + +#define PLATFORM_CACHE_LINE_SIZE 64 +#define PLATFORM_CLUSTER_COUNT 2ull +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PRIMARY_CPU 0x0 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define TZROM_BASE 0x00000000 +#define TZROM_SIZE 0x04000000 + +#define TZRAM_BASE 0x04000000 +#define TZRAM_SIZE 0x40000 + +/* Location of trusted dram on the base fvp */ +#define TZDRAM_BASE 0x06000000 +#define TZDRAM_SIZE 0x02000000 + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE TZROM_BASE +#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) +#define BL1_RW_BASE TZRAM_BASE +#define BL1_RW_LIMIT BL31_BASE + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000) +#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#define BL31_BASE (TZRAM_BASE + 0x6000) +#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM +#define BL31_LIMIT BL32_BASE +#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM +#define BL31_LIMIT BL2_BASE +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +/* + * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. + */ +#define TSP_IN_TZRAM 0 +#define TSP_IN_TZDRAM 1 + +#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM +# define TSP_SEC_MEM_BASE TZRAM_BASE +# define TSP_SEC_MEM_SIZE TZRAM_SIZE +# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000) +# define BL32_LIMIT BL2_BASE +#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM +# define TSP_SEC_MEM_BASE TZDRAM_BASE +# define TSP_SEC_MEM_SIZE TZDRAM_SIZE +# define BL32_BASE (TZDRAM_BASE + 0x2000) +# define BL32_LIMIT (TZDRAM_BASE + (1 << 21)) +#else +# error "Unsupported TSP_RAM_LOCATION_ID value" +#endif + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 3 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * ID of the secure physical generic timer interrupt. + ******************************************************************************/ +#define IRQ_SEC_PHY_TIMER 29 + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI400_BASE 0x2c090000 +#define CCI400_SL_IFACE_CLUSTER0 3 +#define CCI400_SL_IFACE_CLUSTER1 4 +#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ + CCI400_SL_IFACE_CLUSTER1 : \ + CCI400_SL_IFACE_CLUSTER0) + + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/fvp/plat_gic.c b/plat/fvp/plat_gic.c index 7dec404f..6b29723b 100644 --- a/plat/fvp/plat_gic.c +++ b/plat/fvp/plat_gic.c @@ -37,6 +37,8 @@ #include #include #include +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * This function does some minimal GICv3 configuration. The Firmware itself does diff --git a/plat/fvp/plat_io_storage.c b/plat/fvp/plat_io_storage.c index aac8a960..baa98ffe 100644 --- a/plat/fvp/plat_io_storage.c +++ b/plat/fvp/plat_io_storage.c @@ -35,9 +35,9 @@ #include #include #include -#include #include /* For FOPEN_MODE_... */ #include +#include "fvp_def.h" /* IO devices */ static io_plat_data_t io_data; diff --git a/plat/fvp/plat_pm.c b/plat/fvp/plat_pm.c index c47cdb0f..ad4ce793 100644 --- a/plat/fvp/plat_pm.c +++ b/plat/fvp/plat_pm.c @@ -34,8 +34,11 @@ #include #include #include +#include #include #include "drivers/pwrc/fvp_pwrc.h" +#include "fvp_def.h" +#include "fvp_private.h" /******************************************************************************* * FVP handler called when an affinity instance is about to enter standby. diff --git a/plat/fvp/plat_security.c b/plat/fvp/plat_security.c index 9da56122..976f75e9 100644 --- a/plat/fvp/plat_security.c +++ b/plat/fvp/plat_security.c @@ -29,9 +29,10 @@ */ #include -#include -#include #include +#include +#include "fvp_def.h" +#include "fvp_private.h" /* Used to improve readability for configuring regions. */ #define FILTER_SHIFT(filter) (1 << filter) diff --git a/plat/fvp/plat_topology.c b/plat/fvp/plat_topology.c index 04b409ec..f06b4f74 100644 --- a/plat/fvp/plat_topology.c +++ b/plat/fvp/plat_topology.c @@ -29,7 +29,7 @@ */ #include -#include +#include /* TODO: Reusing psci error codes & state information. Get our own! */ #include #include "drivers/pwrc/fvp_pwrc.h" diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h deleted file mode 100644 index 0e3de5fc..00000000 --- a/plat/fvp/platform.h +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PLATFORM_H__ -#define __PLATFORM_H__ - -#include -#include - - -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ - -/* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x800 - -/* Size of coherent stacks for debug and release builds */ -#if DEBUG -#define PCPU_DV_MEM_STACK_SIZE 0x400 -#else -#define PCPU_DV_MEM_STACK_SIZE 0x300 -#endif - -#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r" - -/* Trusted Boot Firmware BL2 */ -#define BL2_IMAGE_NAME "bl2.bin" - -/* EL3 Runtime Firmware BL31 */ -#define BL31_IMAGE_NAME "bl31.bin" - -/* Secure Payload BL32 (Trusted OS) */ -#define BL32_IMAGE_NAME "bl32.bin" - -/* Non-Trusted Firmware BL33 and its load address */ -#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ -#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ - -/* Firmware Image Package */ -#define FIP_IMAGE_NAME "fip.bin" - -#define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_CLUSTER_COUNT 2ull -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PRIMARY_CPU 0x0 -#define MAX_IO_DEVICES 3 -#define MAX_IO_HANDLES 4 - -/* Constants for accessing platform configuration */ -#define CONFIG_GICD_ADDR 0 -#define CONFIG_GICC_ADDR 1 -#define CONFIG_GICH_ADDR 2 -#define CONFIG_GICV_ADDR 3 -#define CONFIG_MAX_AFF0 4 -#define CONFIG_MAX_AFF1 5 -/* Indicate whether the CPUECTLR SMP bit should be enabled. */ -#define CONFIG_CPU_SETUP 6 -#define CONFIG_BASE_MMAP 7 -/* Indicates whether CCI should be enabled on the platform. */ -#define CONFIG_HAS_CCI 8 -#define CONFIG_HAS_TZC 9 -#define CONFIG_LIMIT 10 - -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define TZROM_BASE 0x00000000 -#define TZROM_SIZE 0x04000000 - -#define TZRAM_BASE 0x04000000 -#define TZRAM_SIZE 0x40000 - -#define FLASH0_BASE 0x08000000 -#define FLASH0_SIZE TZROM_SIZE - -#define FLASH1_BASE 0x0c000000 -#define FLASH1_SIZE 0x04000000 - -#define PSRAM_BASE 0x14000000 -#define PSRAM_SIZE 0x04000000 - -#define VRAM_BASE 0x18000000 -#define VRAM_SIZE 0x02000000 - -/* Aggregate of all devices in the first GB */ -#define DEVICE0_BASE 0x1a000000 -#define DEVICE0_SIZE 0x12200000 - -#define DEVICE1_BASE 0x2f000000 -#define DEVICE1_SIZE 0x200000 - -#define NSRAM_BASE 0x2e000000 -#define NSRAM_SIZE 0x10000 - -/* Location of trusted dram on the base fvp */ -#define TZDRAM_BASE 0x06000000 -#define TZDRAM_SIZE 0x02000000 -#define MBOX_OFF 0x1000 - -/* Base address where parameters to BL31 are stored */ -#define PARAMS_BASE TZDRAM_BASE - - -#define DRAM1_BASE 0x80000000ull -#define DRAM1_SIZE 0x80000000ull -#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) -#define DRAM1_SEC_SIZE 0x01000000ull - -#define DRAM_BASE DRAM1_BASE -#define DRAM_SIZE DRAM1_SIZE - -#define DRAM2_BASE 0x880000000ull -#define DRAM2_SIZE 0x780000000ull -#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) - -#define PCIE_EXP_BASE 0x40000000 -#define TZRNG_BASE 0x7fe60000 -#define TZNVCTR_BASE 0x7fe70000 -#define TZROOTKEY_BASE 0x7fe80000 - -/* Memory mapped Generic timer interfaces */ -#define SYS_CNTCTL_BASE 0x2a430000 -#define SYS_CNTREAD_BASE 0x2a800000 -#define SYS_TIMCTL_BASE 0x2a810000 - -/* Counter timer module offsets */ -#define CNTNSAR 0x4 -#define CNTNSAR_NS_SHIFT(x) x - -#define CNTACR_BASE(x) (0x40 + (x << 2)) -#define CNTACR_RPCT_SHIFT 0x0 -#define CNTACR_RVCT_SHIFT 0x1 -#define CNTACR_RFRQ_SHIFT 0x2 -#define CNTACR_RVOFF_SHIFT 0x3 -#define CNTACR_RWVT_SHIFT 0x4 -#define CNTACR_RWPT_SHIFT 0x5 - -/* V2M motherboard system registers & offsets */ -#define VE_SYSREGS_BASE 0x1c010000 -#define V2M_SYS_ID 0x0 -#define V2M_SYS_LED 0x8 -#define V2M_SYS_CFGDATA 0xa0 -#define V2M_SYS_CFGCTRL 0xa4 - -/* - * V2M sysled bit definitions. The values written to this - * register are defined in arch.h & runtime_svc.h. Only - * used by the primary cpu to diagnose any cold boot issues. - * - * SYS_LED[0] - Security state (S=0/NS=1) - * SYS_LED[2:1] - Exception Level (EL3-EL0) - * SYS_LED[7:3] - Exception Class (Sync/Async & origin) - * - */ -#define SYS_LED_SS_SHIFT 0x0 -#define SYS_LED_EL_SHIFT 0x1 -#define SYS_LED_EC_SHIFT 0x3 - -#define SYS_LED_SS_MASK 0x1 -#define SYS_LED_EL_MASK 0x3 -#define SYS_LED_EC_MASK 0x1f - -/* V2M sysid register bits */ -#define SYS_ID_REV_SHIFT 27 -#define SYS_ID_HBI_SHIFT 16 -#define SYS_ID_BLD_SHIFT 12 -#define SYS_ID_ARCH_SHIFT 8 -#define SYS_ID_FPGA_SHIFT 0 - -#define SYS_ID_REV_MASK 0xf -#define SYS_ID_HBI_MASK 0xfff -#define SYS_ID_BLD_MASK 0xf -#define SYS_ID_ARCH_MASK 0xf -#define SYS_ID_FPGA_MASK 0xff - -#define SYS_ID_BLD_LENGTH 4 - -#define REV_FVP 0x0 -#define HBI_FVP_BASE 0x020 -#define HBI_FOUNDATION 0x010 - -#define BLD_GIC_VE_MMAP 0x0 -#define BLD_GIC_A53A57_MMAP 0x1 - -#define ARCH_MODEL 0x1 - -/* FVP Power controller base address*/ -#define PWRC_BASE 0x1c100000 - -/******************************************************************************* - * Platform specific per affinity states. Distinction between off and suspend - * is made to allow reporting of a suspended cpu as still being on e.g. in the - * affinity_info psci call. - ******************************************************************************/ -#define PLATFORM_MAX_AFF0 4 -#define PLATFORM_MAX_AFF1 2 -#define PLAT_AFF_UNK 0xff - -#define PLAT_AFF0_OFF 0x0 -#define PLAT_AFF0_ONPENDING 0x1 -#define PLAT_AFF0_SUSPEND 0x2 -#define PLAT_AFF0_ON 0x3 - -#define PLAT_AFF1_OFF 0x0 -#define PLAT_AFF1_ONPENDING 0x1 -#define PLAT_AFF1_SUSPEND 0x2 -#define PLAT_AFF1_ON 0x3 - -/******************************************************************************* - * BL1 specific defines. - * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of - * addresses. - ******************************************************************************/ -#define BL1_RO_BASE TZROM_BASE -#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) -#define BL1_RW_BASE TZRAM_BASE -#define BL1_RW_LIMIT BL31_BASE - -/******************************************************************************* - * BL2 specific defines. - ******************************************************************************/ -#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000) -#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -#define BL31_BASE (TZRAM_BASE + 0x6000) -#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM -#define BL31_LIMIT BL32_BASE -#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM -#define BL31_LIMIT BL2_BASE -#endif - -/******************************************************************************* - * BL32 specific defines. - ******************************************************************************/ -/* - * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. - */ -#define TSP_IN_TZRAM 0 -#define TSP_IN_TZDRAM 1 - -#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM -# define TSP_SEC_MEM_BASE TZRAM_BASE -# define TSP_SEC_MEM_SIZE TZRAM_SIZE -# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000) -# define BL32_LIMIT BL2_BASE -#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM -# define TSP_SEC_MEM_BASE TZDRAM_BASE -# define TSP_SEC_MEM_SIZE TZDRAM_SIZE -# define BL32_BASE (TZDRAM_BASE + 0x2000) -# define BL32_LIMIT (TZDRAM_BASE + (1 << 21)) -#else -# error "Unsupported TSP_RAM_LOCATION_ID value" -#endif - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define ADDR_SPACE_SIZE (1ull << 32) -#define MAX_XLAT_TABLES 3 -#define MAX_MMAP_REGIONS 16 - - -/******************************************************************************* - * CCI-400 related constants - ******************************************************************************/ -#define CCI400_BASE 0x2c090000 -#define CCI400_SL_IFACE_CLUSTER0 3 -#define CCI400_SL_IFACE_CLUSTER1 4 -#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ - CCI400_SL_IFACE_CLUSTER1 : \ - CCI400_SL_IFACE_CLUSTER0) - -/******************************************************************************* - * GIC-400 & interrupt handling related constants - ******************************************************************************/ -/* VE compatible GIC memory map */ -#define VE_GICD_BASE 0x2c001000 -#define VE_GICC_BASE 0x2c002000 -#define VE_GICH_BASE 0x2c004000 -#define VE_GICV_BASE 0x2c006000 - -/* Base FVP compatible GIC memory map */ -#define BASE_GICD_BASE 0x2f000000 -#define BASE_GICR_BASE 0x2f100000 -#define BASE_GICC_BASE 0x2c000000 -#define BASE_GICH_BASE 0x2c010000 -#define BASE_GICV_BASE 0x2c02f000 - -#define IRQ_TZ_WDOG 56 -#define IRQ_SEC_PHY_TIMER 29 -#define IRQ_SEC_SGI_0 8 -#define IRQ_SEC_SGI_1 9 -#define IRQ_SEC_SGI_2 10 -#define IRQ_SEC_SGI_3 11 -#define IRQ_SEC_SGI_4 12 -#define IRQ_SEC_SGI_5 13 -#define IRQ_SEC_SGI_6 14 -#define IRQ_SEC_SGI_7 15 -#define IRQ_SEC_SGI_8 16 - -/******************************************************************************* - * PL011 related constants - ******************************************************************************/ -#define PL011_UART0_BASE 0x1c090000 -#define PL011_UART1_BASE 0x1c0a0000 -#define PL011_UART2_BASE 0x1c0b0000 -#define PL011_UART3_BASE 0x1c0c0000 - - -/******************************************************************************* - * TrustZone address space controller related constants - ******************************************************************************/ -#define TZC400_BASE 0x2a4a0000 - -/* - * The NSAIDs for this platform as used to program the TZC400. - */ - -/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */ -#define FVP_AID_WIDTH 4 - -/* NSAIDs used by devices in TZC filter 0 on FVP */ -#define FVP_NSAID_DEFAULT 0 -#define FVP_NSAID_PCI 1 -#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ -#define FVP_NSAID_AP 9 /* Application Processors */ -#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ - -/* NSAIDs used by devices in TZC filter 2 on FVP */ -#define FVP_NSAID_HDLCD0 2 -#define FVP_NSAID_CLCD 7 - - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#ifndef __ASSEMBLY__ - -#include -#include - -typedef volatile struct mailbox { - unsigned long value - __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); -} mailbox_t; - -/******************************************************************************* - * Forward declarations - ******************************************************************************/ -struct plat_pm_ops; -struct meminfo; -struct bl31_params; -struct image_info; -struct entry_point_info; - - -/******************************************************************************* - * This structure represents the superset of information that is passed to - * BL31 e.g. while passing control to it from BL2 which is bl31_params - * and another platform specific params - ******************************************************************************/ -typedef struct bl2_to_bl31_params_mem { - struct bl31_params bl31_params; - struct image_info bl31_image_info; - struct image_info bl32_image_info; - struct image_info bl33_image_info; - struct entry_point_info bl33_ep_info; - struct entry_point_info bl32_ep_info; - struct entry_point_info bl31_ep_info; -} bl2_to_bl31_params_mem_t; - - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void bl1_plat_arch_setup(void); -void bl2_plat_arch_setup(void); -void bl31_plat_arch_setup(void); -int platform_setup_pm(const struct plat_pm_ops **); -unsigned int platform_get_core_pos(unsigned long mpidr); -void enable_mmu_el1(void); -void enable_mmu_el3(void); -void configure_mmu_el1(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); -void configure_mmu_el3(unsigned long total_base, - unsigned long total_size, - unsigned long ro_start, - unsigned long ro_limit, - unsigned long coh_start, - unsigned long coh_limit); -unsigned long platform_get_cfgvar(unsigned int); -int platform_config_setup(void); -void plat_report_exception(unsigned long); -unsigned long plat_get_ns_image_entrypoint(void); -unsigned long platform_get_stack(unsigned long mpidr); -uint64_t plat_get_syscnt_freq(void); -#if RESET_TO_BL31 -void plat_get_entry_point_info(unsigned long target_security, - el_change_info_t *target_entry_info); -#endif -void fvp_cci_setup(void); - -/* Declarations for plat_gic.c */ -uint32_t ic_get_pending_interrupt_id(void); -uint32_t ic_get_pending_interrupt_type(void); -uint32_t ic_acknowledge_interrupt(void); -uint32_t ic_get_interrupt_type(uint32_t id); -void ic_end_of_interrupt(uint32_t id); -void gic_cpuif_deactivate(unsigned int); -void gic_cpuif_setup(unsigned int); -void gic_pcpu_distif_setup(unsigned int); -void gic_setup(void); -uint32_t plat_interrupt_type_to_line(uint32_t type, - uint32_t security_state); - -/* Declarations for plat_topology.c */ -int plat_setup_topology(void); -int plat_get_max_afflvl(void); -unsigned int plat_get_aff_count(unsigned int, unsigned long); -unsigned int plat_get_aff_state(unsigned int, unsigned long); - -/* Declarations for plat_io_storage.c */ -void io_setup(void); -int plat_get_image_source(const char *image_name, - uintptr_t *dev_handle, - uintptr_t *image_spec); - -/* Declarations for plat_security.c */ -void plat_security_setup(void); - -/* - * Before calling this function BL2 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL2 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl1_plat_set_bl2_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL31 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL31 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl31_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL32 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL32 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl32_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* - * Before calling this function BL33 is loaded in memory and its entrypoint - * is set by load_image. This is a placeholder for the platform to change - * the entrypoint of BL33 and set SPSR and security state. - * On FVP we are only setting the security state, entrypoint - */ -void bl2_plat_set_bl33_ep_info(struct image_info *image, - struct entry_point_info *ep); - -/* Gets the memory layout for BL32 */ -void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); - -/* Gets the memory layout for BL33 */ -void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); - -/* Sets the entrypoint for BL32 */ -void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep_info); - -/* Sets the entrypoint for BL33 */ -void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep_info); - - -#endif /*__ASSEMBLY__*/ - -#endif /* __PLATFORM_H__ */ diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c index 2ca6a56a..6b3592e3 100644 --- a/services/spd/tspd/tspd_common.c +++ b/services/spd/tspd/tspd_common.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include "tspd_private.h" diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c index 2f204494..ec4989df 100644 --- a/services/spd/tspd/tspd_pm.c +++ b/services/spd/tspd/tspd_pm.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "tspd_private.h" diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h index fb719225..5d7bf4b6 100644 --- a/services/spd/tspd/tspd_private.h +++ b/services/spd/tspd/tspd_private.h @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include /******************************************************************************* diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c index 360b2860..1e5828ca 100644 --- a/services/std_svc/psci/psci_afflvl_on.c +++ b/services/std_svc/psci/psci_afflvl_on.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include "psci_private.h" diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c index c61e87ad..b1ee10da 100644 --- a/services/std_svc/psci/psci_common.c +++ b/services/std_svc/psci/psci_common.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "psci_private.h" /*