From: Daniel Golle Date: Wed, 5 Oct 2022 17:44:42 +0000 (+0100) Subject: mediatek: filogic: add support for hw i2c, pwm and thermal X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=5d921aa72f329f7ff5d975ad769e0e01bf123b6e;p=openwrt%2Fstaging%2Fnbd.git mediatek: filogic: add support for hw i2c, pwm and thermal Add support for hardware I2C and PWM units found in the Filogic SoCs as well as the CPU thermal support. Signed-off-by: Daniel Golle --- diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index e135fee35a..ade4cebbd5 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -199,6 +200,20 @@ status = "okay"; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_BSEL>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; @@ -240,6 +255,20 @@ status = "disabled"; }; + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@1100a000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; reg = <0 0x1100a000 0 0x100>; @@ -264,6 +293,16 @@ status = "disabled"; }; + auxadc: adc@1100d000 { + compatible = "mediatek,mt7986-auxadc", + "mediatek,mt7622-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "main", "32k"; + #io-channel-cells = <1>; + }; + ssusb: usb@11200000 { compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; @@ -304,6 +343,21 @@ status = "disabled"; }; + thermal: thermal@1100c800 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; @@ -373,7 +427,6 @@ }; }; - efuse: efuse@11d00000 { compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; @@ -609,4 +662,71 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + status = "disabled"; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + + }; + }; }; diff --git a/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch new file mode 100644 index 0000000000..a49fbca4ee --- /dev/null +++ b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch @@ -0,0 +1,66 @@ +--- a/drivers/iio/adc/mt6577_auxadc.c ++++ b/drivers/iio/adc/mt6577_auxadc.c +@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible { + struct mt6577_auxadc_device { + void __iomem *reg_base; + struct clk *adc_clk; ++ struct clk *adc_32k_clk; + struct mutex lock; + const struct mtk_auxadc_compatible *dev_comp; + }; +@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_ + return ret; + } + ++ ret = clk_prepare_enable(adc_dev->adc_32k_clk); ++ if (ret) { ++ pr_err("failed to enable auxadc clock\n"); ++ return ret; ++ } ++ + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + MT6577_AUXADC_PDN_EN, 0); + mdelay(MT6577_AUXADC_POWER_READY_MS); +@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_ + + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + 0, MT6577_AUXADC_PDN_EN); ++ ++ clk_disable_unprepare(adc_dev->adc_32k_clk); + clk_disable_unprepare(adc_dev->adc_clk); + + return 0; +@@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl + return ret; + } + ++ adc_dev->adc_32k_clk = devm_clk_get(&pdev->dev, "32k"); ++ if (IS_ERR(adc_dev->adc_32k_clk)) { ++ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n"); ++ } else { ++ ret = clk_prepare_enable(adc_dev->adc_32k_clk); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n"); ++ return ret; ++ } ++ } ++ + adc_clk_rate = clk_get_rate(adc_dev->adc_clk); + if (!adc_clk_rate) { + ret = -EINVAL; +@@ -306,6 +326,7 @@ err_power_off: + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + 0, MT6577_AUXADC_PDN_EN); + err_disable_clk: ++ clk_disable_unprepare(adc_dev->adc_32k_clk); + clk_disable_unprepare(adc_dev->adc_clk); + return ret; + } +@@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p + mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, + 0, MT6577_AUXADC_PDN_EN); + ++ clk_disable_unprepare(adc_dev->adc_32k_clk); + clk_disable_unprepare(adc_dev->adc_clk); + + return 0; diff --git a/target/linux/mediatek/patches-5.15/800-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch b/target/linux/mediatek/patches-5.15/800-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch new file mode 100644 index 0000000000..e57f742fc8 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/800-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch @@ -0,0 +1,46 @@ +From 44ae4ed142265a6d50a9d3e6f4c395f97b6849ab Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Sat, 6 Nov 2021 20:06:30 +0800 +Subject: [PATCH 2/5] nvmem: mtk-efuse: support minimum one byte access stride + and granularity + +In order to support nvmem bits property, should support minimum 1 byte +read stride and minimum 1 byte read granularity at the same time. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Zhanyong Wang +Change-Id: Iafe1ebf195d58a3e9e3518913f795d14a01dfd3b +--- + drivers/nvmem/mtk-efuse.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +--- a/drivers/nvmem/mtk-efuse.c ++++ b/drivers/nvmem/mtk-efuse.c +@@ -19,11 +19,12 @@ static int mtk_reg_read(void *context, + unsigned int reg, void *_val, size_t bytes) + { + struct mtk_efuse_priv *priv = context; +- u32 *val = _val; +- int i = 0, words = bytes / 4; ++ void __iomem *addr = priv->base + reg; ++ u8 *val = _val; ++ int i; + +- while (words--) +- *val++ = readl(priv->base + reg + (i++ * 4)); ++ for (i = 0; i < bytes; i++, val++) ++ *val = readb(addr + i); + + return 0; + } +@@ -45,8 +46,8 @@ static int mtk_efuse_probe(struct platfo + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + +- econfig.stride = 4; +- econfig.word_size = 4; ++ econfig.stride = 1; ++ econfig.word_size = 1; + econfig.reg_read = mtk_reg_read; + econfig.size = resource_size(res); + econfig.priv = priv; diff --git a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch new file mode 100644 index 0000000000..4c2fd18b3b --- /dev/null +++ b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch @@ -0,0 +1,225 @@ +From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Tue, 25 Jan 2022 16:50:47 +0800 +Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support + +Add PCIe 2 lane efuse support in tphy driver. + +Signed-off-by: Jie Yang +Signed-off-by: Zhanyong Wang +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ + 1 file changed, 140 insertions(+) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -44,6 +44,15 @@ + #define SSUSB_SIFSLV_V2_U3PHYD 0x200 + #define SSUSB_SIFSLV_V2_U3PHYA 0x400 + ++/* version V4 sub-banks offset base address */ ++/* pcie phy banks */ ++#define SSUSB_SIFSLV_V4_SPLLC 0x000 ++#define SSUSB_SIFSLV_V4_CHIP 0x100 ++#define SSUSB_SIFSLV_V4_U3PHYD 0x900 ++#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 ++ ++#define SSUSB_LN1_OFFSET 0x10000 ++ + #define U3P_MISC_REG1 0x04 + #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) + +@@ -320,6 +329,7 @@ enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, + MTK_PHY_V3, ++ MTK_PHY_V4, + }; + + struct mtk_phy_pdata { +@@ -369,6 +379,9 @@ struct mtk_phy_instance { + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; ++ u32 efuse_intr_ln1; ++ u32 efuse_tx_imp_ln1; ++ u32 efuse_rx_imp_ln1; + int eye_src; + int eye_vrt; + int eye_term; +@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk + } + } + ++static void phy_v4_banks_init(struct mtk_tphy *tphy, ++ struct mtk_phy_instance *instance) ++{ ++ struct u2phy_banks *u2_banks = &instance->u2_banks; ++ struct u3phy_banks *u3_banks = &instance->u3_banks; ++ ++ switch (instance->type) { ++ case PHY_TYPE_USB2: ++ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; ++ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; ++ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; ++ break; ++ case PHY_TYPE_USB3: ++ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; ++ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; ++ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; ++ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; ++ break; ++ case PHY_TYPE_PCIE: ++ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; ++ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; ++ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; ++ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; ++ break; ++ default: ++ dev_err(tphy->dev, "incompatible PHY type\n"); ++ return; ++ } ++} ++ + static void phy_parse_property(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + { +@@ -1143,6 +1186,40 @@ static int phy_efuse_get(struct mtk_tphy + + dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", + instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); ++ ++ if (tphy->pdata->version != MTK_PHY_V4) ++ break; ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); ++ break; ++ } ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); ++ break; ++ } ++ ++ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); ++ if (ret) { ++ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); ++ break; ++ } ++ ++ /* no efuse, ignore it */ ++ if (!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) { ++ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); ++ instance->efuse_sw_en = 0; ++ break; ++ } ++ ++ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", ++ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, ++ instance->efuse_tx_imp_ln1); + break; + default: + dev_err(dev, "no sw efuse for type %d\n", instance->type); +@@ -1174,6 +1251,31 @@ static void phy_efuse_set(struct mtk_phy + writel(tmp, u2_banks->com + U3P_USBPHYACR1); + break; + case PHY_TYPE_USB3: ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); ++ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); ++ ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); ++ tmp &= ~P3D_RG_TX_IMPEL; ++ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); ++ tmp |= P3D_RG_FORCE_TX_IMPEL; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); ++ ++ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); ++ tmp &= ~P3D_RG_RX_IMPEL; ++ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); ++ tmp |= P3D_RG_FORCE_RX_IMPEL; ++ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); ++ ++ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); ++ tmp &= ~P3A_RG_IEXT_INTR; ++ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); ++ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); ++ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", ++ __func__, instance->efuse_tx_imp, ++ instance->efuse_rx_imp, instance->efuse_intr); ++ ++ break; + case PHY_TYPE_PCIE: + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; +@@ -1195,6 +1297,34 @@ static void phy_efuse_set(struct mtk_phy + tmp &= ~P3A_RG_IEXT_INTR; + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); ++ if (!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) ++ break; ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); ++ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); ++ tmp &= ~P3D_RG_TX_IMPEL; ++ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); ++ tmp |= P3D_RG_FORCE_TX_IMPEL; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); ++ ++ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); ++ tmp &= ~P3D_RG_RX_IMPEL; ++ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); ++ tmp |= P3D_RG_FORCE_RX_IMPEL; ++ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); ++ ++ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); ++ tmp &= ~P3A_RG_IEXT_INTR; ++ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); ++ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); ++ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", ++ __func__, instance->efuse_tx_imp_ln1, ++ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); + break; + default: + dev_warn(dev, "no sw efuse for type %d\n", instance->type); +@@ -1334,6 +1464,9 @@ static struct phy *mtk_phy_xlate(struct + case MTK_PHY_V3: + phy_v2_banks_init(tphy, instance); + break; ++ case MTK_PHY_V4: ++ phy_v4_banks_init(tphy, instance); ++ break; + default: + dev_err(dev, "phy version is not supported\n"); + return ERR_PTR(-EINVAL); +@@ -1374,6 +1507,12 @@ static const struct mtk_phy_pdata tphy_v + .version = MTK_PHY_V3, + }; + ++static const struct mtk_phy_pdata tphy_v4_pdata = { ++ .avoid_rx_sen_degradation = false, ++ .sw_efuse_supported = true, ++ .version = MTK_PHY_V4, ++}; ++ + static const struct mtk_phy_pdata mt8173_pdata = { + .avoid_rx_sen_degradation = true, + .version = MTK_PHY_V1, +@@ -1393,6 +1532,7 @@ static const struct of_device_id mtk_tph + { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, + { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, + { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, ++ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, + { }, + }; + MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); diff --git a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch new file mode 100644 index 0000000000..67580f1e11 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch @@ -0,0 +1,149 @@ +From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001 +From: Zhanyong Wang +Date: Tue, 25 Jan 2022 19:03:34 +0800 +Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism + support + +add auto-load-valid check mechanism support + +Signed-off-by: Zhanyong Wang +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++-- + 1 file changed, 64 insertions(+), 3 deletions(-) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -376,9 +376,13 @@ struct mtk_phy_instance { + u32 type_sw_reg; + u32 type_sw_index; + u32 efuse_sw_en; ++ bool efuse_alv_en; ++ u32 efuse_autoloadvalid; + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; ++ bool efuse_alv_ln1_en; ++ u32 efuse_ln1_autoloadvalid; + u32 efuse_intr_ln1; + u32 efuse_tx_imp_ln1; + u32 efuse_rx_imp_ln1; +@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy + { + struct device *dev = &instance->phy->dev; + int ret = 0; ++ bool alv = false; + + /* tphy v1 doesn't support sw efuse, skip it */ + if (!tphy->pdata->sw_efuse_supported) { +@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy + + switch (instance->type) { + case PHY_TYPE_USB2: ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); ++ if (alv) { ++ instance->efuse_alv_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", ++ &instance->efuse_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "u2 auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); + if (ret) { + dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); +@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy + + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); ++ if (alv) { ++ instance->efuse_alv_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", ++ &instance->efuse_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "u3 auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); + if (ret) { + dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); +@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy + if (tphy->pdata->version != MTK_PHY_V4) + break; + ++ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1"); ++ if (alv) { ++ instance->efuse_alv_ln1_en = alv; ++ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1", ++ &instance->efuse_ln1_autoloadvalid); ++ if (ret) { ++ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret); ++ break; ++ } ++ dev_info(dev, ++ "pcie auto load valid efuse: ENABLE with value: %u\n", ++ instance->efuse_ln1_autoloadvalid); ++ } ++ + ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); + if (ret) { + dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); +@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy + + switch (instance->type) { + case PHY_TYPE_USB2: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u2_banks->misc + U3P_MISC_REG1); + tmp |= MR1_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u2_banks->misc + U3P_MISC_REG1); +@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy + writel(tmp, u2_banks->com + U3P_USBPHYACR1); + break; + case PHY_TYPE_USB3: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); +@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy + + break; + case PHY_TYPE_PCIE: ++ if (instance->efuse_alv_en && ++ instance->efuse_autoloadvalid == 1) ++ break; ++ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); +@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy + tmp &= ~P3A_RG_IEXT_INTR; + tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); +- if (!instance->efuse_intr_ln1 && +- !instance->efuse_rx_imp_ln1 && +- !instance->efuse_tx_imp_ln1) ++ ++ if ((!instance->efuse_intr_ln1 && ++ !instance->efuse_rx_imp_ln1 && ++ !instance->efuse_tx_imp_ln1) || ++ (instance->efuse_alv_ln1_en && ++ instance->efuse_ln1_autoloadvalid == 1)) + break; + + tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); diff --git a/target/linux/mediatek/patches-5.15/803-i2c-busses-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/803-i2c-busses-add-mt7986-support.patch new file mode 100644 index 0000000000..1860a6da01 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/803-i2c-busses-add-mt7986-support.patch @@ -0,0 +1,30 @@ +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -365,6 +365,19 @@ static const struct mtk_i2c_compatible m + .max_dma_support = 32, + }; + ++static const struct mtk_i2c_compatible mt7986_compat = { ++ .quirks = &mt7622_i2c_quirks, ++ .regs = mt_i2c_regs_v1, ++ .pmic_i2c = 0, ++ .dcm = 1, ++ .auto_restart = 1, ++ .aux_len_reg = 1, ++ .max_dma_support = 32, ++ .timing_adjust = 0, ++ .dma_sync = 1, ++ .ltiming_adjust = 0, ++}; ++ + static const struct mtk_i2c_compatible mt8173_compat = { + .regs = mt_i2c_regs_v1, + .pmic_i2c = 0, +@@ -411,6 +424,7 @@ static const struct of_device_id mtk_i2c + { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, + { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, ++ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, + { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, + { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, diff --git a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch new file mode 100644 index 0000000000..fe095c5633 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch @@ -0,0 +1,23 @@ +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data + .has_ck_26m_sel = true, + }; + ++static const struct pwm_mediatek_of_data mt7986_pwm_data = { ++ .num_pwms = 2, ++ .pwm45_fixup = false, ++ .has_ck_26m_sel = false, ++}; ++ + static const struct pwm_mediatek_of_data mt8516_pwm_data = { + .num_pwms = 5, + .pwm45_fixup = false, +@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, + { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, + { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, ++ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, + { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, + { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, + { }, diff --git a/target/linux/mediatek/patches-5.15/805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch b/target/linux/mediatek/patches-5.15/805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch new file mode 100644 index 0000000000..ff2b71872c --- /dev/null +++ b/target/linux/mediatek/patches-5.15/805-thermal-drivers-mediatek-add-support-for-MT7986-and-.patch @@ -0,0 +1,284 @@ +From cd47d86ab09f1f3ec5c86441d4fe95e0cf597c06 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 13 Sep 2022 00:56:24 +0100 +Subject: [PATCH] thermal/drivers/mediatek: add support for MT7986 and MT7981 + +Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. + +Signed-off-by: Daniel Golle +--- + drivers/thermal/mtk_thermal.c | 202 +++++++++++++++++++++++++++++++++- + 1 file changed, 198 insertions(+), 4 deletions(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -150,6 +150,21 @@ + #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) + #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) + ++/* ++ * Layout of the fuses providing the calibration data ++ * These macros could be used for MT7981 and MT7986. ++ */ ++#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) ++#define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff) ++#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) ++#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) ++#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) ++#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) ++#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) ++#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) ++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) ++#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) ++ + enum { + VTS1, + VTS2, +@@ -163,6 +178,7 @@ enum { + enum mtk_thermal_version { + MTK_THERMAL_V1 = 1, + MTK_THERMAL_V2, ++ MTK_THERMAL_V3, + }; + + /* MT2701 thermal sensors */ +@@ -245,6 +261,27 @@ enum mtk_thermal_version { + /* The calibration coefficient of sensor */ + #define MT8183_CALIBRATION 153 + ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT7986_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT7986 */ ++#define MT7986_NUM_SENSORS 1 ++ ++/* The number of banks in the MT7986 */ ++#define MT7986_NUM_ZONES 1 ++ ++/* The number of sensing points per bank */ ++#define MT7986_NUM_SENSORS_PER_ZONE 1 ++ ++/* MT7986 thermal sensors */ ++#define MT7986_TS1 0 ++ ++/* The number of controller in the MT7986 */ ++#define MT7986_NUM_CONTROLLER 1 ++ ++/* The calibration coefficient of sensor */ ++#define MT7986_CALIBRATION 165 ++ + struct mtk_thermal; + + struct thermal_bank_cfg { +@@ -279,6 +316,7 @@ struct mtk_thermal { + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; ++ struct clk *clk_adc_32k; + /* lock: for getting and putting banks */ + struct mutex lock; + +@@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762 + static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; + static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; + ++/* MT7986 thermal sensor data */ ++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; ++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; ++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; ++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; ++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; ++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; ++ + /* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 +@@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8 + .version = MTK_THERMAL_V1, + }; + ++/* ++ * MT7986 uses AUXADC Channel 11 for raw data access. ++ */ ++static const struct mtk_thermal_data mt7986_thermal_data = { ++ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT7986_NUM_ZONES, ++ .num_sensors = MT7986_NUM_SENSORS, ++ .vts_index = mt7986_vts_index, ++ .cali_val = MT7986_CALIBRATION, ++ .num_controller = MT7986_NUM_CONTROLLER, ++ .controller_offset = mt7986_tc_offset, ++ .need_switch_bank = true, ++ .bank_data = { ++ { ++ .num_sensors = 1, ++ .sensors = mt7986_bank_data, ++ }, ++ }, ++ .msr = mt7986_msr, ++ .adcpnp = mt7986_adcpnp, ++ .sensor_mux_values = mt7986_mux_values, ++ .version = MTK_THERMAL_V3, ++}; ++ + /** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller +@@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk + return (format_2 - tmp) * 100; + } + ++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) ++{ ++ s32 tmp; ++ ++ if (raw == 0) ++ return 0; ++ ++ raw &= 0xfff; ++ tmp = 100000 * 15 / 16 * 10000; ++ tmp /= 4096 - 512 + mt->adc_ge; ++ tmp /= 1490; ++ tmp *= raw - mt->vts[sensno] - 2900; ++ ++ return mt->degc_cali * 500 - tmp; ++} ++ + /** + * mtk_thermal_get_bank - get bank + * @bank: The bank +@@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature( + if (mt->conf->version == MTK_THERMAL_V1) { + temp = raw_to_mcelsius_v1( + mt, conf->bank_data[bank->id].sensors[i], raw); +- } else { ++ } else if (mt->conf->version == MTK_THERMAL_V2) { + temp = raw_to_mcelsius_v2( + mt, conf->bank_data[bank->id].sensors[i], raw); ++ } else { ++ temp = raw_to_mcelsius_v3( ++ mt, conf->bank_data[bank->id].sensors[i], raw); + } + + /* +@@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2( + return 0; + } + ++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) ++{ ++ if (!CALIB_BUF1_VALID_V3(buf[1])) ++ return -EINVAL; ++ ++ mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]); ++ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); ++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); ++ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); ++ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); ++ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); ++ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); ++ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); ++ ++ if (CALIB_BUF1_ID_V3(buf[1]) == 0) ++ mt->o_slope = 0; ++ ++ return 0; ++} ++ + static int mtk_thermal_get_calibration_data(struct device *dev, + struct mtk_thermal *mt) + { +@@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d + + /* Start with default values */ + mt->adc_ge = 512; ++ mt->adc_oe = 512; + for (i = 0; i < mt->conf->num_sensors; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; +@@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d + + if (mt->conf->version == MTK_THERMAL_V1) + ret = mtk_thermal_extract_efuse_v1(mt, buf); +- else ++ else if (mt->conf->version == MTK_THERMAL_V2) + ret = mtk_thermal_extract_efuse_v2(mt, buf); ++ else ++ ret = mtk_thermal_extract_efuse_v3(mt, buf); + + if (ret) { + dev_info(dev, "Device not calibrated, using default calibration values\n"); +@@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the + .data = (void *)&mt7622_thermal_data, + }, + { ++ .compatible = "mediatek,mt7986-thermal", ++ .data = (void *)&mt7986_thermal_data, ++ }, ++ { + .compatible = "mediatek,mt8183-thermal", + .data = (void *)&mt8183_thermal_data, + }, { +@@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + ++ if (mt->conf->version == MTK_THERMAL_V3) { ++ mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k"); ++ if (IS_ERR(mt->clk_adc_32k)) ++ return PTR_ERR(mt->clk_adc_32k); ++ } ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) +@@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat + if (ret) + return ret; + ++ if (mt->conf->version == MTK_THERMAL_V3) { ++ ret = clk_prepare_enable(mt->clk_adc_32k); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret); ++ return ret; ++ } ++ } ++ + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); +- return ret; ++ goto err_disable_clk_adc_32k; + } + + ret = clk_prepare_enable(mt->clk_peri_therm); +@@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat + goto err_disable_clk_auxadc; + } + +- if (mt->conf->version == MTK_THERMAL_V2) { ++ if (mt->conf->version == MTK_THERMAL_V2 || ++ mt->conf->version == MTK_THERMAL_V3) { + mtk_thermal_turn_on_buffer(apmixed_base); + mtk_thermal_release_periodic_ts(mt, auxadc_base); + } +@@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm: + clk_disable_unprepare(mt->clk_peri_therm); + err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); ++err_disable_clk_adc_32k: ++ if (mt->conf->version == MTK_THERMAL_V3) ++ clk_disable_unprepare(mt->clk_adc_32k); + + return ret; + } +@@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + ++ if (mt->conf->version == MTK_THERMAL_V3) ++ clk_disable_unprepare(mt->clk_adc_32k); ++ + return 0; + } + diff --git a/target/linux/mediatek/patches-5.15/815-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch b/target/linux/mediatek/patches-5.15/815-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch deleted file mode 100644 index e57f742fc8..0000000000 --- a/target/linux/mediatek/patches-5.15/815-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 44ae4ed142265a6d50a9d3e6f4c395f97b6849ab Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Sat, 6 Nov 2021 20:06:30 +0800 -Subject: [PATCH 2/5] nvmem: mtk-efuse: support minimum one byte access stride - and granularity - -In order to support nvmem bits property, should support minimum 1 byte -read stride and minimum 1 byte read granularity at the same time. - -Signed-off-by: Chunfeng Yun -Signed-off-by: Zhanyong Wang -Change-Id: Iafe1ebf195d58a3e9e3518913f795d14a01dfd3b ---- - drivers/nvmem/mtk-efuse.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - ---- a/drivers/nvmem/mtk-efuse.c -+++ b/drivers/nvmem/mtk-efuse.c -@@ -19,11 +19,12 @@ static int mtk_reg_read(void *context, - unsigned int reg, void *_val, size_t bytes) - { - struct mtk_efuse_priv *priv = context; -- u32 *val = _val; -- int i = 0, words = bytes / 4; -+ void __iomem *addr = priv->base + reg; -+ u8 *val = _val; -+ int i; - -- while (words--) -- *val++ = readl(priv->base + reg + (i++ * 4)); -+ for (i = 0; i < bytes; i++, val++) -+ *val = readb(addr + i); - - return 0; - } -@@ -45,8 +46,8 @@ static int mtk_efuse_probe(struct platfo - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -- econfig.stride = 4; -- econfig.word_size = 4; -+ econfig.stride = 1; -+ econfig.word_size = 1; - econfig.reg_read = mtk_reg_read; - econfig.size = resource_size(res); - econfig.priv = priv; diff --git a/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch deleted file mode 100644 index 4c2fd18b3b..0000000000 --- a/target/linux/mediatek/patches-5.15/817-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch +++ /dev/null @@ -1,225 +0,0 @@ -From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Tue, 25 Jan 2022 16:50:47 +0800 -Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support - -Add PCIe 2 lane efuse support in tphy driver. - -Signed-off-by: Jie Yang -Signed-off-by: Zhanyong Wang ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ - 1 file changed, 140 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -44,6 +44,15 @@ - #define SSUSB_SIFSLV_V2_U3PHYD 0x200 - #define SSUSB_SIFSLV_V2_U3PHYA 0x400 - -+/* version V4 sub-banks offset base address */ -+/* pcie phy banks */ -+#define SSUSB_SIFSLV_V4_SPLLC 0x000 -+#define SSUSB_SIFSLV_V4_CHIP 0x100 -+#define SSUSB_SIFSLV_V4_U3PHYD 0x900 -+#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 -+ -+#define SSUSB_LN1_OFFSET 0x10000 -+ - #define U3P_MISC_REG1 0x04 - #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) - -@@ -320,6 +329,7 @@ enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, - MTK_PHY_V3, -+ MTK_PHY_V4, - }; - - struct mtk_phy_pdata { -@@ -369,6 +379,9 @@ struct mtk_phy_instance { - u32 efuse_intr; - u32 efuse_tx_imp; - u32 efuse_rx_imp; -+ u32 efuse_intr_ln1; -+ u32 efuse_tx_imp_ln1; -+ u32 efuse_rx_imp_ln1; - int eye_src; - int eye_vrt; - int eye_term; -@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk - } - } - -+static void phy_v4_banks_init(struct mtk_tphy *tphy, -+ struct mtk_phy_instance *instance) -+{ -+ struct u2phy_banks *u2_banks = &instance->u2_banks; -+ struct u3phy_banks *u3_banks = &instance->u3_banks; -+ -+ switch (instance->type) { -+ case PHY_TYPE_USB2: -+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; -+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; -+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; -+ break; -+ case PHY_TYPE_USB3: -+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; -+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; -+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; -+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; -+ break; -+ case PHY_TYPE_PCIE: -+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; -+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; -+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; -+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; -+ break; -+ default: -+ dev_err(tphy->dev, "incompatible PHY type\n"); -+ return; -+ } -+} -+ - static void phy_parse_property(struct mtk_tphy *tphy, - struct mtk_phy_instance *instance) - { -@@ -1143,6 +1186,40 @@ static int phy_efuse_get(struct mtk_tphy - - dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", - instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); -+ -+ if (tphy->pdata->version != MTK_PHY_V4) -+ break; -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); -+ break; -+ } -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); -+ break; -+ } -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); -+ break; -+ } -+ -+ /* no efuse, ignore it */ -+ if (!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) { -+ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); -+ instance->efuse_sw_en = 0; -+ break; -+ } -+ -+ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", -+ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, -+ instance->efuse_tx_imp_ln1); - break; - default: - dev_err(dev, "no sw efuse for type %d\n", instance->type); -@@ -1174,6 +1251,31 @@ static void phy_efuse_set(struct mtk_phy - writel(tmp, u2_banks->com + U3P_USBPHYACR1); - break; - case PHY_TYPE_USB3: -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); -+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -+ -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); -+ tmp &= ~P3D_RG_TX_IMPEL; -+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); -+ tmp |= P3D_RG_FORCE_TX_IMPEL; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); -+ -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); -+ tmp &= ~P3D_RG_RX_IMPEL; -+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); -+ tmp |= P3D_RG_FORCE_RX_IMPEL; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); -+ -+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); -+ tmp &= ~P3A_RG_IEXT_INTR; -+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); -+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -+ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", -+ __func__, instance->efuse_tx_imp, -+ instance->efuse_rx_imp, instance->efuse_intr); -+ -+ break; - case PHY_TYPE_PCIE: - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -@@ -1195,6 +1297,34 @@ static void phy_efuse_set(struct mtk_phy - tmp &= ~P3A_RG_IEXT_INTR; - tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -+ if (!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) -+ break; -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); -+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); -+ tmp &= ~P3D_RG_TX_IMPEL; -+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); -+ tmp |= P3D_RG_FORCE_TX_IMPEL; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); -+ tmp &= ~P3D_RG_RX_IMPEL; -+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); -+ tmp |= P3D_RG_FORCE_RX_IMPEL; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); -+ -+ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); -+ tmp &= ~P3A_RG_IEXT_INTR; -+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); -+ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); -+ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", -+ __func__, instance->efuse_tx_imp_ln1, -+ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); - break; - default: - dev_warn(dev, "no sw efuse for type %d\n", instance->type); -@@ -1334,6 +1464,9 @@ static struct phy *mtk_phy_xlate(struct - case MTK_PHY_V3: - phy_v2_banks_init(tphy, instance); - break; -+ case MTK_PHY_V4: -+ phy_v4_banks_init(tphy, instance); -+ break; - default: - dev_err(dev, "phy version is not supported\n"); - return ERR_PTR(-EINVAL); -@@ -1374,6 +1507,12 @@ static const struct mtk_phy_pdata tphy_v - .version = MTK_PHY_V3, - }; - -+static const struct mtk_phy_pdata tphy_v4_pdata = { -+ .avoid_rx_sen_degradation = false, -+ .sw_efuse_supported = true, -+ .version = MTK_PHY_V4, -+}; -+ - static const struct mtk_phy_pdata mt8173_pdata = { - .avoid_rx_sen_degradation = true, - .version = MTK_PHY_V1, -@@ -1393,6 +1532,7 @@ static const struct of_device_id mtk_tph - { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, - { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, - { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, -+ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, - { }, - }; - MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); diff --git a/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch deleted file mode 100644 index 67580f1e11..0000000000 --- a/target/linux/mediatek/patches-5.15/818-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Tue, 25 Jan 2022 19:03:34 +0800 -Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism - support - -add auto-load-valid check mechanism support - -Signed-off-by: Zhanyong Wang ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++-- - 1 file changed, 64 insertions(+), 3 deletions(-) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -376,9 +376,13 @@ struct mtk_phy_instance { - u32 type_sw_reg; - u32 type_sw_index; - u32 efuse_sw_en; -+ bool efuse_alv_en; -+ u32 efuse_autoloadvalid; - u32 efuse_intr; - u32 efuse_tx_imp; - u32 efuse_rx_imp; -+ bool efuse_alv_ln1_en; -+ u32 efuse_ln1_autoloadvalid; - u32 efuse_intr_ln1; - u32 efuse_tx_imp_ln1; - u32 efuse_rx_imp_ln1; -@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy - { - struct device *dev = &instance->phy->dev; - int ret = 0; -+ bool alv = false; - - /* tphy v1 doesn't support sw efuse, skip it */ - if (!tphy->pdata->sw_efuse_supported) { -@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy - - switch (instance->type) { - case PHY_TYPE_USB2: -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); -+ if (alv) { -+ instance->efuse_alv_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", -+ &instance->efuse_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "u2 auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); - if (ret) { - dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); -@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy - - case PHY_TYPE_USB3: - case PHY_TYPE_PCIE: -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); -+ if (alv) { -+ instance->efuse_alv_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", -+ &instance->efuse_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "u3 auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); - if (ret) { - dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); -@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy - if (tphy->pdata->version != MTK_PHY_V4) - break; - -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1"); -+ if (alv) { -+ instance->efuse_alv_ln1_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1", -+ &instance->efuse_ln1_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "pcie auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_ln1_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); - if (ret) { - dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); -@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy - - switch (instance->type) { - case PHY_TYPE_USB2: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u2_banks->misc + U3P_MISC_REG1); - tmp |= MR1_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u2_banks->misc + U3P_MISC_REG1); -@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy - writel(tmp, u2_banks->com + U3P_USBPHYACR1); - break; - case PHY_TYPE_USB3: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy - - break; - case PHY_TYPE_PCIE: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy - tmp &= ~P3A_RG_IEXT_INTR; - tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -- if (!instance->efuse_intr_ln1 && -- !instance->efuse_rx_imp_ln1 && -- !instance->efuse_tx_imp_ln1) -+ -+ if ((!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) || -+ (instance->efuse_alv_ln1_en && -+ instance->efuse_ln1_autoloadvalid == 1)) - break; - - tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);