From: Laxman Dewangan Date: Fri, 17 Jun 2016 10:51:07 +0000 (+0530) Subject: clk: max77686: Add support for MAX77620 clocks X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=5a227cd1ab3693d36ac7a6f1fc4e21a7129f62f0;p=openwrt%2Fstaging%2Fblogic.git clk: max77686: Add support for MAX77620 clocks Maxim Max77620 has one 32KHz clock output and the clock HW IP used on this PMIC is same as what it is there in the MAX77686. Add clock driver support for MAX77620 on the MAX77686 driver. CC: Krzysztof Kozlowski CC: Javier Martinez Canillas Signed-off-by: Laxman Dewangan Tested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index d7d2993a889c..b3ee99adee4b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -32,10 +32,11 @@ config COMMON_CLK_WM831X source "drivers/clk/versatile/Kconfig" config COMMON_CLK_MAX77686 - tristate "Clock driver for Maxim 77686/77802 MFD" - depends on MFD_MAX77686 + tristate "Clock driver for Maxim 77620/77686/77802 MFD" + depends on MFD_MAX77686 || MFD_MAX77620 ---help--- - This driver supports Maxim 77686/77802 crystal oscillator clock. + This driver supports Maxim 77620/77686/77802 crystal oscillator + clock. config COMMON_CLK_RK808 tristate "Clock driver for RK808/RK818" diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 9aba3a8245e1..19f620856571 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -35,12 +36,14 @@ #include #include +#include #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3 enum max77686_chip_name { CHIP_MAX77686, CHIP_MAX77802, + CHIP_MAX77620, }; struct max77686_hw_clk_info { @@ -97,6 +100,15 @@ max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = { }, }; +static const struct +max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = { + [MAX77620_CLK_32K_OUT0] = { + .name = "32khz_out0", + .clk_reg = MAX77620_REG_CNFG1_32K, + .clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN, + }, +}; + static struct max77686_clk_init_data *to_max77686_clk_init_data( struct clk_hw *hw) { @@ -181,6 +193,11 @@ static int max77686_clk_probe(struct platform_device *pdev) hw_clks = max77802_hw_clks_info; break; + case CHIP_MAX77620: + num_clks = MAX77620_CLKS_NUM; + hw_clks = max77620_hw_clks_info; + break; + default: dev_err(dev, "Unknown Chip ID\n"); return -EINVAL; @@ -284,6 +301,7 @@ static int max77686_clk_remove(struct platform_device *pdev) static const struct platform_device_id max77686_clk_id[] = { { "max77686-clk", .driver_data = CHIP_MAX77686, }, { "max77802-clk", .driver_data = CHIP_MAX77802, }, + { "max77620-clock", .driver_data = CHIP_MAX77620, }, {}, }; MODULE_DEVICE_TABLE(platform, max77686_clk_id);