From: Sylwester Nawrocki Date: Mon, 22 Aug 2016 09:15:39 +0000 (+0200) Subject: clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=58d6506f327e3d192998ba03632f546da221b8d8;p=openwrt%2Fstaging%2Fblogic.git clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks The PDMA{0,1} and EPLL clock IDs are added separately in this patch so the patch can be merged to the arm-soc tree as dependency. Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi --- diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 85b467b3a207..6cb4e90f81fc 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -19,6 +19,7 @@ #define CLK_FOUT_MPLL 4 #define CLK_FOUT_BPLL 5 #define CLK_FOUT_KPLL 6 +#define CLK_FOUT_EPLL 7 /* gate for special clocks (sclk) */ #define CLK_SCLK_UART0 128 @@ -55,6 +56,8 @@ #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 +#define CLK_PDMA0 362 +#define CLK_PDMA1 363 #define CLK_USBH20 365 #define CLK_USBD300 366 #define CLK_USBD301 367