From: Larry Finger Date: Thu, 22 Aug 2013 03:34:07 +0000 (-0500) Subject: staging: r8188eu: Add files for new driver - part 25 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=58c434013a22fccfdb14abc2bb8408ca29073b76;p=openwrt%2Fstaging%2Fblogic.git staging: r8188eu: Add files for new driver - part 25 This commit adds files include/recv_osdep.h, include/rtl8188e_cmd.h, include/rtl8188e_dm.h, include/rtl8188e_hal.h, include/rtl8188e_led.h, include/rtl8188e_recv.h, include/rtl8188e_rf.h, include/rtl8188e_spec.h, include/rtl8188e_sreset.h, and include/rtl8188e_xmit.h. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/rtl8188eu/include/recv_osdep.h b/drivers/staging/rtl8188eu/include/recv_osdep.h new file mode 100644 index 000000000000..691238078075 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/recv_osdep.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RECV_OSDEP_H_ +#define __RECV_OSDEP_H_ + +#include +#include + + +int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); +void _rtw_free_recv_priv(struct recv_priv *precvpriv); + + +s32 rtw_recv_entry(union recv_frame *precv_frame); +int rtw_recv_indicatepkt(struct adapter *adapter, union recv_frame *recv_frame); +void rtw_recv_returnpacket(struct net_device *cnxt, struct sk_buff *retpkt); + +void rtw_hostapd_mlme_rx(struct adapter *padapter, union recv_frame *recv_fr); +void rtw_handle_tkip_mic_err(struct adapter *padapter, u8 bgroup); + +int rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); +void rtw_free_recv_priv(struct recv_priv *precvpriv); + +int rtw_os_recv_resource_init(struct recv_priv *recvpr, struct adapter *adapt); +int rtw_os_recv_resource_alloc(struct adapter *adapt, union recv_frame *recvfr); +void rtw_os_recv_resource_free(struct recv_priv *precvpriv); + +int rtw_os_recvbuf_resource_alloc(struct adapter *adapt, struct recv_buf *buf); +int rtw_os_recvbuf_resource_free(struct adapter *adapt, struct recv_buf *buf); + +void rtw_os_read_port(struct adapter *padapter, struct recv_buf *precvbuf); + +void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); +int nat25_handle_frame(struct adapter *priv, struct sk_buff *skb); +int _netdev_open(struct net_device *pnetdev); +int netdev_open(struct net_device *pnetdev); +int netdev_close(struct net_device *pnetdev); + +#endif /* */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_cmd.h b/drivers/staging/rtl8188eu/include/rtl8188e_cmd.h new file mode 100644 index 000000000000..b32bc28503d0 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_cmd.h @@ -0,0 +1,122 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_CMD_H__ +#define __RTL8188E_CMD_H__ + +enum RTL8188E_H2C_CMD_ID { + /* Class Common */ + H2C_COM_RSVD_PAGE = 0x00, + H2C_COM_MEDIA_STATUS_RPT = 0x01, + H2C_COM_SCAN = 0x02, + H2C_COM_KEEP_ALIVE = 0x03, + H2C_COM_DISCNT_DECISION = 0x04, + H2C_COM_INIT_OFFLOAD = 0x06, + H2C_COM_REMOTE_WAKE_CTL = 0x07, + H2C_COM_AP_OFFLOAD = 0x08, + H2C_COM_BCN_RSVD_PAGE = 0x09, + H2C_COM_PROB_RSP_RSVD_PAGE = 0x0A, + + /* Class PS */ + H2C_PS_PWR_MODE = 0x20, + H2C_PS_TUNE_PARA = 0x21, + H2C_PS_TUNE_PARA_2 = 0x22, + H2C_PS_LPS_PARA = 0x23, + H2C_PS_P2P_OFFLOAD = 0x24, + + /* Class DM */ + H2C_DM_MACID_CFG = 0x40, + H2C_DM_TXBF = 0x41, + + /* Class BT */ + H2C_BT_COEX_MASK = 0x60, + H2C_BT_COEX_GPIO_MODE = 0x61, + H2C_BT_DAC_SWING_VAL = 0x62, + H2C_BT_PSD_RST = 0x63, + + /* Class */ + H2C_RESET_TSF = 0xc0, +}; + +struct cmd_msg_parm { + u8 eid; /* element id */ + u8 sz; /* sz */ + u8 buf[6]; +}; + +enum { + PWRS +}; + +struct setpwrmode_parm { + u8 Mode;/* 0:Active,1:LPS,2:WMMPS */ + u8 SmartPS_RLBM;/* LPS= 0:PS_Poll,1:PS_Poll,2:NullData,WMM= 0:PS_Poll,1:NullData */ + u8 AwakeInterval; /* unit: beacon interval */ + u8 bAllQueueUAPSD; + u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */ +}; + +struct H2C_SS_RFOFF_PARAM { + u8 ROFOn; /* 1: on, 0:off */ + u16 gpio_period; /* unit: 1024 us */ +} __packed; + +struct joinbssrpt_parm { + u8 OpMode; /* RT_MEDIA_STATUS */ +}; + +struct rsvdpage_loc { + u8 LocProbeRsp; + u8 LocPsPoll; + u8 LocNullData; + u8 LocQosNull; + u8 LocBTQosNull; +}; + +struct P2P_PS_Offload_t { + u8 Offload_En:1; + u8 role:1; /* 1: Owner, 0: Client */ + u8 CTWindow_En:1; + u8 NoA0_En:1; + u8 NoA1_En:1; + u8 AllStaSleep:1; /* Only valid in Owner */ + u8 discovery:1; + u8 rsvd:1; +}; + +struct P2P_PS_CTWPeriod_t { + u8 CTWPeriod; /* TU */ +}; + +/* host message to firmware cmd */ +void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode); +void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus); +u8 rtl8188e_set_rssi_cmd(struct adapter *padapter, u8 *param); +u8 rtl8188e_set_raid_cmd(struct adapter *padapter, u32 mask); +void rtl8188e_Add_RateATid(struct adapter *padapter, u32 bitmap, u8 arg, + u8 rssi_level); + +#ifdef CONFIG_88EU_P2P +void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state); +#endif /* CONFIG_88EU_P2P */ + +void CheckFwRsvdPageContent(struct adapter *adapt); +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt); + +#endif/* __RTL8188E_CMD_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_dm.h b/drivers/staging/rtl8188eu/include/rtl8188e_dm.h new file mode 100644 index 000000000000..97a3175250ef --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_dm.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_DM_H__ +#define __RTL8188E_DM_H__ +enum{ + UP_LINK, + DOWN_LINK, +}; +/* duplicate code,will move to ODM ######### */ +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM 9 +#define HP_THERMAL_NUM 8 +/* duplicate code,will move to ODM ######### */ +struct dm_priv { + u8 DM_Type; + u8 DMFlag; + u8 InitDMFlag; + u32 InitODMFlag; + + /* Upper and Lower Signal threshold for Rate Adaptive*/ + int UndecoratedSmoothedPWDB; + int UndecoratedSmoothedCCK; + int EntryMinUndecoratedSmoothedPWDB; + int EntryMaxUndecoratedSmoothedPWDB; + int MinUndecoratedPWDBForDM; + int LastMinUndecoratedPWDBForDM; + + /* for High Power */ + u8 bDynamicTxPowerEnable; + u8 LastDTPLvl; + u8 DynamicTxHighPowerLvl;/* Tx Power Control for Near/Far Range */ + u8 PowerIndex_backup[6]; +}; + +void rtl8188e_init_dm_priv(struct adapter *adapt); +void rtl8188e_deinit_dm_priv(struct adapter *adapt); +void rtl8188e_InitHalDm(struct adapter *adapt); +void rtl8188e_HalDmWatchDog(struct adapter *adapt); + +void AntDivCompare8188E(struct adapter *adapt, struct wlan_bssid_ex *dst, + struct wlan_bssid_ex *src); +u8 AntDivBeforeLink8188E(struct adapter *adapt); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_hal.h b/drivers/staging/rtl8188eu/include/rtl8188e_hal.h new file mode 100644 index 000000000000..fc4adb614bfe --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_hal.h @@ -0,0 +1,487 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_HAL_H__ +#define __RTL8188E_HAL_H__ + + +/* include HAL Related header after HAL Related compiling flags */ +#include "rtl8188e_spec.h" +#include "Hal8188EPhyReg.h" +#include "Hal8188EPhyCfg.h" +#include "rtl8188e_rf.h" +#include "rtl8188e_dm.h" +#include "rtl8188e_recv.h" +#include "rtl8188e_xmit.h" +#include "rtl8188e_cmd.h" +#include "Hal8188EPwrSeq.h" +#include "rtl8188e_sreset.h" +#include "rtw_efuse.h" + +#include "odm_precomp.h" + +/* Fw Array */ +#define Rtl8188E_FwImageArray Rtl8188EFwImgArray +#define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength + +#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" +#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" +#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" +#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" +#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" +#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" +#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" +#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" + +/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */ +#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow +#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow +#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow +#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow +#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow +#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow +#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow +#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow +#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow + +#define DRVINFO_SZ 4 /* unit is 8bytes */ +#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0)) + +/* download firmware related data structure */ +#define FW_8188E_SIZE 0x4000 /* 16384,16k */ +#define FW_8188E_START_ADDRESS 0x1000 +#define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */ + +#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ + +#define IS_FW_HEADER_EXIST(_pFwHdr) \ + ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 || \ + (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 || \ + (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 || \ + (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0) + +enum firmware_source { + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, /* from header file */ +}; + +struct rt_firmware { + enum firmware_source eFWSource; + u8 *szFwBuffer; + u32 ulFwLength; +}; + +/* This structure must be careful with byte-ordering */ + +struct rt_firmware_hdr { + /* 8-byte alinment required */ + /* LONG WORD 0 ---- */ + __le16 Signature; /* 92C0: test chip; 92C, + * 88C0: test chip; 88C1: MP A-cut; + * 92C1: MP A-cut */ + u8 Category; /* AP/NIC and USB/PCI */ + u8 Function; /* Reserved for different FW function + * indcation, for further use when + * driver needs to download different + * FW for different conditions */ + __le16 Version; /* FW Version */ + u8 Subversion; /* FW Subversion, default 0x00 */ + u16 Rsvd1; + + /* LONG WORD 1 ---- */ + u8 Month; /* Release time Month field */ + u8 Date; /* Release time Date field */ + u8 Hour; /* Release time Hour field */ + u8 Minute; /* Release time Minute field */ + __le16 RamCodeSize; /* The size of RAM code */ + u8 Foundry; + u8 Rsvd2; + + /* LONG WORD 2 ---- */ + __le32 SvnIdx; /* The SVN entry index */ + u32 Rsvd3; + + /* LONG WORD 3 ---- */ + u32 Rsvd4; + u32 Rsvd5; +}; + +#define DRIVER_EARLY_INT_TIME 0x05 +#define BCN_DMA_ATIME_INT_TIME 0x02 + +enum usb_rx_agg_mode { + USB_RX_AGG_DISABLE, + USB_RX_AGG_DMA, + USB_RX_AGG_USB, + USB_RX_AGG_MIX +}; + +#define MAX_RX_DMA_BUFFER_SIZE_88E \ + 0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8), + * WOLPattern(16*24)) */ + +#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */ + + +/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */ +#define MAX_TX_QUEUE 9 + +#define TX_SELE_HQ BIT(0) /* High Queue */ +#define TX_SELE_LQ BIT(1) /* Low Queue */ +#define TX_SELE_NQ BIT(2) /* Normal Queue */ + +/* Note: We will divide number of page equally for each queue other + * than public queue! */ +/* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */ +/* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */ +/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS + * null-data */ + +#define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */ + +#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1) + +/* Note: For Normal Chip Setting ,modify later */ +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \ + TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */ +#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \ + (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */ + +/* Chip specific */ +#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) +#define CHIP_BONDING_92C_1T2R 0x1 +#define CHIP_BONDING_88C_USB_MCARD 0x2 +#define CHIP_BONDING_88C_USB_HP 0x1 +#include "HalVerDef.h" +#include "hal_com.h" + +/* Channel Plan */ +enum ChannelPlan { + CHPL_FCC = 0, + CHPL_IC = 1, + CHPL_ETSI = 2, + CHPL_SPA = 3, + CHPL_FRANCE = 4, + CHPL_MKK = 5, + CHPL_MKK1 = 6, + CHPL_ISRAEL = 7, + CHPL_TELEC = 8, + CHPL_GLOBAL = 9, + CHPL_WORLD = 10, +}; + +struct txpowerinfo24g { + u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1]; + /* If only one tx, only BW20 and OFDM are used. */ + s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +}; + +#define EFUSE_REAL_CONTENT_LEN 512 +#define EFUSE_MAP_LEN 128 +#define EFUSE_MAX_SECTION 16 +#define EFUSE_IC_ID_OFFSET 506 /* For some inferior IC purpose*/ +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) +/* To prevent out of boundary programming case, */ +/* leave 1byte and program full section */ +/* 9bytes + 1byt + 5bytes and pre 1byte. */ +/* For worst case: */ +/* | 1byte|----8bytes----|1byte|--5bytes--| */ +/* | | Reserved(14bytes) | */ + +/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ +#define EFUSE_OOB_PROTECT_BYTES 15 + +#define HWSET_MAX_SIZE_88E 512 + +#define EFUSE_REAL_CONTENT_LEN_88E 256 +#define EFUSE_MAP_LEN_88E 512 +#define EFUSE_MAX_SECTION_88E 64 +#define EFUSE_MAX_WORD_UNIT_88E 4 +#define EFUSE_IC_ID_OFFSET_88E 506 +#define AVAILABLE_EFUSE_ADDR_88E(addr) \ + (addr < EFUSE_REAL_CONTENT_LEN_88E) +/* To prevent out of boundary programming case, leave 1byte and program + * full section */ +/* 9bytes + 1byt + 5bytes and pre 1byte. */ +/* For worst case: */ +/* | 2byte|----8bytes----|1byte|--7bytes--| 92D */ +/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */ +#define EFUSE_OOB_PROTECT_BYTES_88E 18 +#define EFUSE_PROTECT_BYTES_BANK_88E 16 + +/* EFUSE for BT definition */ +#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ +#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ +#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ + +#define EFUSE_PROTECT_BYTES_BANK 16 + +/* For RTL8723 WiFi/BT/GPS multi-function configuration. */ +enum rt_multi_func { + RT_MULTI_FUNC_NONE = 0x00, + RT_MULTI_FUNC_WIFI = 0x01, + RT_MULTI_FUNC_BT = 0x02, + RT_MULTI_FUNC_GPS = 0x04, +}; + +/* For RTL8723 regulator mode. */ +enum rt_regulator_mode { + RT_SWITCHING_REGULATOR = 0, + RT_LDO_REGULATOR = 1, +}; + +struct hal_data_8188e { + struct HAL_VERSION VersionID; + enum rt_multi_func MultiFunc; /* For multi-function consideration. */ + enum rt_regulator_mode RegulatorMode; /* switching regulator or LDO */ + u16 CustomerID; + + u16 FirmwareVersion; + u16 FirmwareVersionRev; + u16 FirmwareSubVersion; + u16 FirmwareSignature; + u8 PGMaxGroup; + /* current WIFI_PHY values */ + u32 ReceiveConfig; + enum wireless_mode CurrentWirelessMode; + enum ht_channel_width CurrentChannelBW; + u8 CurrentChannel; + u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ + + u16 BasicRateSet; + + /* rf_ctrl */ + u8 rf_chip; + u8 rf_type; + u8 NumTotalRFPath; + + u8 BoardType; + + /* EEPROM setting. */ + u16 EEPROMVID; + u16 EEPROMPID; + u16 EEPROMSVID; + u16 EEPROMSDID; + u8 EEPROMCustomerID; + u8 EEPROMSubCustomerID; + u8 EEPROMVersion; + u8 EEPROMRegulatory; + + u8 bTXPowerDataReadFromEEPORM; + u8 EEPROMThermalMeter; + u8 bAPKThermalMeterIgnore; + + bool EepromOrEfuse; + /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */ + u8 EfuseMap[2][HWSET_MAX_SIZE_512]; + u8 EfuseUsedPercentage; + struct efuse_hal EfuseHal; + + u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + /* If only one tx, only BW20 and OFDM are used. */ + s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + + u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT 40MHZ pwr */ + u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT 40MHZ pwr */ + u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* HT 20<->40 Pwr diff */ + u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT<->legacy pwr diff */ + u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For power group */ + u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + + u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ + /* The current Tx Power Level */ + u8 CurrentCckTxPwrIdx; + u8 CurrentOfdm24GTxPwrIdx; + u8 CurrentBW2024GTxPwrIdx; + u8 CurrentBW4024GTxPwrIdx; + + + /* Read/write are allow for following hardware information variables */ + u8 framesync; + u32 framesyncC34; + u8 framesyncMonitor; + u8 DefaultInitialGain[4]; + u8 pwrGroupCnt; + u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; + u32 CCKTxPowerLevelOriginalOffset; + + u8 CrystalCap; + u32 AntennaTxPath; /* Antenna path Tx */ + u32 AntennaRxPath; /* Antenna path Rx */ + u8 BluetoothCoexist; + u8 ExternalPA; + + u8 bLedOpenDrain; /* Open-drain support for controlling the LED.*/ + + u8 b1x1RecvCombine; /* for 1T1R receive combining */ + + u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ + + struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */ + + u32 RfRegChnlVal[2]; + + /* RDG enable */ + bool bRDGEnable; + + /* for host message to fw */ + u8 LastHMEBoxNum; + + u8 fw_ractrl; + u8 RegTxPause; + /* Beacon function related global variable. */ + u32 RegBcnCtrlVal; + u8 RegFwHwTxQCtrl; + u8 RegReg542; + u8 RegCR_1; + + struct dm_priv dmpriv; + struct odm_dm_struct odmpriv; + struct sreset_priv srestpriv; + + u8 CurAntenna; + u8 AntDivCfg; + u8 TRxAntDivType; + + + u8 bDumpRxPkt;/* for debug */ + u8 bDumpTxPkt;/* for debug */ + u8 FwRsvdPageStartOffset; /* Reserve page start offset except + * beacon in TxQ. */ + + /* 2010/08/09 MH Add CU power down mode. */ + bool pwrdown; + + /* Add for dual MAC 0--Mac0 1--Mac1 */ + u32 interfaceIndex; + + u8 OutEpQueueSel; + u8 OutEpNumber; + + /* Add for USB aggreation mode dynamic shceme. */ + bool UsbRxHighSpeedMode; + + /* 2010/11/22 MH Add for slim combo debug mode selective. */ + /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. + * HW auto suspend ability. Close BT clock. */ + bool SlimComboDbg; + + u16 EfuseUsedBytes; + +#ifdef CONFIG_88EU_P2P + struct P2P_PS_Offload_t p2p_ps_offload; +#endif + + /* Auto FSM to Turn On, include clock, isolation, power control + * for MAC only */ + u8 bMacPwrCtrlOn; + + u32 UsbBulkOutSize; + + /* Interrupt relatd register information. */ + u32 IntArray[3];/* HISR0,HISR1,HSISR */ + u32 IntrMask[3]; + u8 C2hArray[16]; + u8 UsbTxAggMode; + u8 UsbTxAggDescNum; + u16 HwRxPageSize; /* Hardware setting */ + u32 MaxUsbRxAggBlock; + + enum usb_rx_agg_mode UsbRxAggMode; + u8 UsbRxAggBlockCount; /* USB Block count. Block size is + * 512-byte in high speed and 64-byte + * in full speed */ + u8 UsbRxAggBlockTimeout; + u8 UsbRxAggPageCount; /* 8192C DMA page count */ + u8 UsbRxAggPageTimeout; +}; + +#define GET_HAL_DATA(__pAdapter) \ + ((struct hal_data_8188e *)((__pAdapter)->HalData)) +#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) + +#define INCLUDE_MULTI_FUNC_BT(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) + +/* rtl8188e_hal_init.c */ +s32 rtl8188e_FirmwareDownload(struct adapter *padapter); +void _8051Reset88E(struct adapter *padapter); +void rtl8188e_InitializeFirmwareVars(struct adapter *padapter); + + +s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy); + +/* EFuse */ +u8 GetEEPROMSize8188E(struct adapter *padapter); +void Hal_InitPGData88E(struct adapter *padapter); +void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo); +void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); + +void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent, + bool AutoLoadFail); +void Hal_ReadThermalMeter_88E(struct adapter * dapter, u8 *PROMContent, + bool AutoloadFail); +void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); + +bool HalDetectPwrDownMode88E(struct adapter *Adapter); + +void Hal_InitChannelPlan(struct adapter *padapter); +void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); + +/* register */ +void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits); + +void rtl8188e_clone_haldata(struct adapter *dst, struct adapter *src); +void rtl8188e_start_thread(struct adapter *padapter); +void rtl8188e_stop_thread(struct adapter *padapter); + +void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter, int len); +s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); +void rtw_cancel_all_timer(struct adapter *padapter); +void _ps_open_RF(struct adapter *adapt); + +#endif /* __RTL8188E_HAL_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_led.h b/drivers/staging/rtl8188eu/include/rtl8188e_led.h new file mode 100644 index 000000000000..c0147e73cd8c --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_led.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_LED_H__ +#define __RTL8188E_LED_H__ + +#include +#include + + +/* */ +/* Interface to manipulate LED objects. */ +/* */ +void rtl8188eu_InitSwLeds(struct adapter *padapter); +void rtl8188eu_DeInitSwLeds(struct adapter *padapter); +void SwLedOn(struct adapter *padapter, struct LED_871x *pLed); +void SwLedOff(struct adapter *padapter, struct LED_871x *pLed); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_recv.h b/drivers/staging/rtl8188eu/include/rtl8188e_recv.h new file mode 100644 index 000000000000..02ccb404f53d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_recv.h @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_RECV_H__ +#define __RTL8188E_RECV_H__ + +#define TX_RPT1_PKT_LEN 8 + +#define RECV_BLK_SZ 512 +#define RECV_BLK_CNT 16 +#define RECV_BLK_TH RECV_BLK_CNT +#define RECV_BULK_IN_ADDR 0x80 +#define RECV_INT_IN_ADDR 0x81 + +#define NR_PREALLOC_RECV_SKB (8) + +#define NR_RECVBUFF (4) + +#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ + +struct phy_stat { + unsigned int phydw0; + unsigned int phydw1; + unsigned int phydw2; + unsigned int phydw3; + unsigned int phydw4; + unsigned int phydw5; + unsigned int phydw6; + unsigned int phydw7; +}; + +/* Rx smooth factor */ +#define Rx_Smooth_Factor (20) + +enum rx_packet_type { + NORMAL_RX,/* Normal rx packet */ + TX_REPORT1,/* CCX */ + TX_REPORT2,/* TX RPT */ + HIS_REPORT,/* USB HISR RPT */ +}; + +#define INTERRUPT_MSG_FORMAT_LEN 60 +void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *buf); +s32 rtl8188eu_init_recv_priv(struct adapter *padapter); +void rtl8188eu_free_recv_priv(struct adapter * padapter); +void rtl8188eu_recv_hdl(struct adapter * padapter, struct recv_buf *precvbuf); +void rtl8188eu_recv_tasklet(void *priv); +void rtl8188e_query_rx_phy_status(union recv_frame *fr, struct phy_stat *phy); +void rtl8188e_process_phy_info(struct adapter * padapter, void *prframe); +void update_recvframe_phyinfo_88e(union recv_frame *fra, struct phy_stat *phy); +void update_recvframe_attrib_88e(union recv_frame *fra, struct recv_stat *stat); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_rf.h b/drivers/staging/rtl8188eu/include/rtl8188e_rf.h new file mode 100644 index 000000000000..10fc356e0209 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_rf.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_RF_H__ +#define __RTL8188E_RF_H__ + +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG 0x3F +#define RF6052_MAX_PATH 2 + + +int PHY_RF6052_Config8188E(struct adapter *Adapter); +void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate); +void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, + enum ht_channel_width Bandwidth); +void rtl8188e_PHY_RF6052SetCckTxPower(struct adapter *Adapter, u8 *level); +void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *ofdm, + u8 *pwrbw20, u8 *pwrbw40, u8 channel); + +#endif/* __RTL8188E_RF_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_spec.h b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h new file mode 100644 index 000000000000..c12c56b97343 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h @@ -0,0 +1,1439 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#ifndef __RTL8188E_SPEC_H__ +#define __RTL8188E_SPEC_H__ + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* 8192C Regsiter offset definition */ + +#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ +#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ + +#define MAC_ADDR_LEN 6 +/* 8188E PKT_BUFF_ACCESS_CTRL value */ +#define TXPKT_BUF_SELECT 0x69 +#define RXPKT_BUF_SELECT 0xA5 +#define DISABLE_TRXPKT_BUF_ACCESS 0x0 + + +/* 0x0000h ~ 0x00FFh System Configuration */ +#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_9346CR 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +#define REG_AFE_XTAL_CTRL 0x0024 +#define REG_AFE_PLL_CTRL 0x0028 +#define REG_APE_PLL_CTRL_EXT 0x002c +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS + * Multi-Function GPIO Pin Control. */ +#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS + * Multi-Function GPIO Select. */ +#define REG_BB_PAD_CTRL 0x0064 +#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS + * Multi-Function control source. */ +#define REG_GPIO_OUTPUT 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ +#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ +#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 /* RTL8188E */ +#define REG_MCUTSTCFG 0x0084 +#define REG_HMEBOX_E0 0x0088 +#define REG_HMEBOX_E1 0x008A +#define REG_HMEBOX_E2 0x008C +#define REG_HMEBOX_E3 0x008E +#define REG_HMEBOX_EXT_0 0x01F0 +#define REG_HMEBOX_EXT_1 0x01F4 +#define REG_HMEBOX_EXT_2 0x01F8 +#define REG_HMEBOX_EXT_3 0x01FC +#define REG_HIMR_88E 0x00B0 +#define REG_HISR_88E 0x00B4 +#define REG_HIMRE_88E 0x00B8 +#define REG_HISRE_88E 0x00BC +#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection + * for RTL8723 */ +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ +#define REG_TYPE_ID 0x00FC + +#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 + +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ +#define REG_CR 0x0100 +#define REG_PBP 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011C +/* define REG_HIMR 0x0120 */ +/* define REG_HISR 0x0124 */ +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012C +#define REG_CPWM 0x012F +#define REG_FWIMR 0x0130 +#define REG_FTIMR 0x0138 +#define REG_FWISR 0x0134 +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) +#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) +#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) +#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 + +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_FAIL 0x017C +#define REG_32K_CTRL 0x0194 /* RTL8188E */ +#define REG_C2HEVT_MSG_NORMAL 0x01A0 +#define REG_C2HEVT_CLEAR 0x01AF +#define REG_MCUTST_1 0x01c0 +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX_0 0x01D0 +#define REG_HMEBOX_1 0x01D4 +#define REG_HMEBOX_2 0x01D8 +#define REG_HMEBOX_3 0x01DC + +#define REG_LLT_INIT 0x01E0 + +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +#define REG_RQPN 0x0200 +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 + +/* 0x0280h ~ 0x02FFh RXDMA Configuration */ +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_STATUS 0x0288 + +/* 0x0300h ~ 0x03FFh PCIe */ +#define REG_PCIE_CTRL_REG 0x0300 +#define REG_INT_MIG 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */ +#define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */ +#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/ +#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */ +#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */ +#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */ +#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */ +#define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */ +#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ +#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ +#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ +#define REG_WATCH_DOG 0x0368 + +/* RTL8723 series ------------------------------ */ +#define REG_PCIE_HISR 0x03A0 + +/* spec version 11 */ +/* 0x0400h ~ 0x047Fh Protocol Configuration */ +#define REG_VOQ_INFORMATION 0x0400 +#define REG_VIQ_INFORMATION 0x0404 +#define REG_BEQ_INFORMATION 0x0408 +#define REG_BKQ_INFORMATION 0x040C +#define REG_MGQ_INFORMATION 0x0410 +#define REG_HGQ_INFORMATION 0x0414 +#define REG_BCNQ_INFORMATION 0x0418 +#define REG_TXPKT_EMPTY 0x041A + +#define REG_CPU_MGQ_INFORMATION 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_HWSEQ_CTRL 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY 0x0425 +#define REG_LIFETIME_EN 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 +#define REG_SPEC_SIFS 0x0428 +#define REG_RL 0x042A +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044C +#define REG_ARFR3 0x0450 +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 +#define REG_INIRTS_RATE_SEL 0x0480 +/* define REG_INIDATA_RATE_SEL 0x0484 */ +#define REG_POWER_STATUS 0x04A4 +#define REG_POWER_STAGE1 0x04B4 +#define REG_POWER_STAGE2 0x04B8 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_STBC_SETTING 0x04C4 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_MAX_AGGR_NUM 0x04CA +#define REG_RTS_MAX_AGGR_NUM 0x04CB +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF +#define REG_EARLY_MODE_CONTROL 0x4D0 +#define REG_NQOS_SEQ 0x04DC +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_PKT_LOSE_RPT 0x04E1 +#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_TX_RPT_CTRL 0x04EC +#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ +#define REG_DUMMY 0x04FC + +/* 0x0500h ~ 0x05FFh EDCA Configuration */ +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +/* Format for offset 540h-542h: */ +/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting + * beacon content before TBTT. */ +/* [7:4]: Reserved. */ +/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding + * to send the beacon packet. */ +/* [23:20]: Reserved */ +/* Description: */ +/* | */ +/* |<--Setup--|--Hold------------>| */ +/* --------------|---------------------- */ +/* | */ +/* TBTT */ +/* Note: We cannot update beacon content to HW or send any AC packets during + * the time between Setup and Hold. */ +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 +#define REG_ATIMWND_1 0x0570 +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 + +/* define REG_FW_TSF_SYNC_CNT 0x04A0 */ +#define REG_FW_RESET_TSF_CNT_1 0x05FC +#define REG_FW_RESET_TSF_CNT_0 0x05FD +#define REG_FW_BCN_DIS_CNT 0x05FE + +/* 0x0600h ~ 0x07FFh WMAC Configuration */ +#define REG_APSD_CTRL 0x0600 +#define REG_BWOPMODE 0x0603 +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F + +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG 0x0628 + +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A + +/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ +/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ +#define REG_R2T_SIFS 0x063C +/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ +#define REG_T2T_SIFS 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + +/* RXERR_RPT */ +#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_false_ALARM 1 +#define RXERR_TYPE_OFDM_MPDU_OK 2 +#define RXERR_TYPE_OFDM_MPDU_FAIL 3 +#define RXERR_TYPE_CCK_PPDU 4 +#define RXERR_TYPE_CCK_false_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 6 +#define RXERR_TYPE_CCK_MPDU_FAIL 7 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_false_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 10 +#define RXERR_TYPE_HT_MPDU_OK 11 +#define RXERR_TYPE_HT_MPDU_FAIL 12 +#define RXERR_TYPE_RX_FULL_DROP 15 + +#define RXERR_COUNTER_MASK 0xFFFFF +#define RXERR_RPT_RST BIT(27) +#define _RXERR_RPT_SEL(type) ((type) << 28) + +/* Note: */ +/* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. + * The default value is always too small, but the WiFi TestPlan test + * by 25,000 microseconds of NAV through sending CTS in the air. + * We must update this value greater than 25,000 microseconds to pass + * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and + * the offset should be 0x0652. */ +#define REG_NAV_UPPER 0x0652 /* unit of 128 */ + +/* WMA, BA, CCX */ +/* define REG_NAV_CTRL 0x0650 */ +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 +#define REG_FWDLY 0x0661 +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 + +/* Security */ +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +/* Power */ +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_UAPSD_TID 0x0693 +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_NUM_88E 0x698 +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP2 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BT_COEX_TABLE 0x06C0 + +/* Hardware Port 2 */ +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 + +/* 0xFE00h ~ 0xFE55h USB Configuration */ +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +/* For normal chip */ +#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ +#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ +#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ +#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ + +/* TODO: use these definition when using REG_xxx naming rule. */ +/* NOTE: DO NOT Remove these definition. Use later. */ + +#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ +#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ +#define MSR (REG_CR + 2) /* Media Status reg */ +#define ISR REG_HISR_88E +/* Timing Sync Function Timer Register. */ +#define TSFR REG_TSFTR + +#define PBP REG_PBP + +/* Redifine MACID register, to compatible prior ICs. */ +/* MAC ID Register, Offset 0x0050-0x0053 */ +#define IDR0 REG_MACID +/* MAC ID Register, Offset 0x0054-0x0055 */ +#define IDR4 (REG_MACID + 4) + +/* 9. Security Control Registers (Offset: ) */ +/* IN 8190 Data Sheet is called CAMcmd */ +#define RWCAM REG_CAMCMD +/* Software write CAM input content */ +#define WCAMI REG_CAMWRITE +/* Software read/write CAM config */ +#define RCAMO REG_CAMREAD +#define CAMDBG REG_CAMDBG +/* Security Configuration Register */ +#define SECR REG_SECCFG + +/* Unused register */ +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister + +/* Min Spacing related settings. */ +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +/* EEPROM enable when set 1 */ +#define CmdEEPROM_En BIT5 +/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ +#define CmdEERPOMSEL BIT4 +#define Cmd9346CR_9356SEL BIT4 + +/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ +#define GPIOSEL_GPIO 0 +#define GPIOSEL_ENBT BIT5 + +/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ +/* GPIO pins input value */ +#define GPIO_IN REG_GPIO_PIN_CTRL +/* GPIO pins output value */ +#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) +/* GPIO pins output enable when a bit is set to "1"; otherwise, + * input is configured. */ +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) +#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) + +/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ +#define HSIMR_GPIO12_0_INT_EN BIT0 +#define HSIMR_SPS_OCP_INT_EN BIT5 +#define HSIMR_RON_INT_EN BIT6 +#define HSIMR_PDN_INT_EN BIT7 +#define HSIMR_GPIO9_INT_EN BIT25 + +/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ +#define HSISR_GPIO12_0_INT BIT0 +#define HSISR_SPS_OCP_INT BIT5 +#define HSISR_RON_INT_EN BIT6 +#define HSISR_PDNINT BIT7 +#define HSISR_GPIO9_INT BIT25 + +/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ +/* +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ +#define USB_INTR_CONTENT_C2H_OFFSET 0 +#define USB_INTR_CONTENT_CPWM1_OFFSET 16 +#define USB_INTR_CONTENT_CPWM2_OFFSET 20 +#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISRE_OFFSET 52 + +/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ +/* IOL config for REG_FDHM0(Reg0x88) */ +#define CMD_INIT_LLT BIT0 +#define CMD_READ_EFUSE_MAP BIT1 +#define CMD_EFUSE_PATCH BIT2 +#define CMD_IOCONFIG BIT3 +#define CMD_INIT_LLT_ERR BIT4 +#define CMD_READ_EFUSE_MAP_ERR BIT5 +#define CMD_EFUSE_PATCH_ERR BIT6 +#define CMD_IOCONFIG_ERR BIT7 + +/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ +/* 8192C Response Rate Set Register (offset 0x181, 24bits) */ +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 + +/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ +/* WOL bit information */ +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 + +/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ +#define BW_OPMODE_20MHZ BIT2 +#define BW_OPMODE_5G BIT1 + +/* 8192C CAM Config Setting (offset 0x250, 1 byte) */ +#define CAM_VALID BIT15 +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT5 + +#define CAM_CONTENT_COUNT 8 + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 +#define HALF_CAM_ENTRY 16 + +#define CAM_CONFIG_USEDK true +#define CAM_CONFIG_NO_USEDK false + +#define CAM_WRITE BIT16 +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT31 + +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 + +/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ +#define WOW_PMEN BIT0 /* Power management Enable. */ +#define WOW_WOMEN BIT1 /* WoW function on or off. */ +#define WOW_MAGIC BIT2 /* Magic packet */ +#define WOW_UWF BIT3 /* Unicast Wakeup frame. */ + +/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ +/* 8188 IMR/ISR bits */ +#define IMR_DISABLED_88E 0x0 +/* IMR DW0(0x0060-0063) Bit 0-31 */ +#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ +#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ +#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ +#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ +#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ +#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ +#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ +#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ +#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ +#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ +#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ +#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ +#define IMR_ROK_88E BIT0 /* Receive DMA OK */ + +/* IMR DW1(0x00B4-00B7) Bit 0-31 */ +#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDERR7_88E BIT20 /* Beacon DMA Error Int 7 */ +#define IMR_BCNDERR6_88E BIT19 /* Beacon DMA Error Int 6 */ +#define IMR_BCNDERR5_88E BIT18 /* Beacon DMA Error Int 5 */ +#define IMR_BCNDERR4_88E BIT17 /* Beacon DMA Error Int 4 */ +#define IMR_BCNDERR3_88E BIT16 /* Beacon DMA Error Int 3 */ +#define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */ +#define IMR_BCNDERR1_88E BIT14 /* Beacon DMA Error Int 1 */ +#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */ +#define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */ +#define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ + +#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ + +/* 8192C EFUSE */ +#define HWSET_MAX_SIZE 256 +#define HWSET_MAX_SIZE_88E 512 + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ +/* Note: */ +/* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet + * RTL8192S/RTL8192C are wrong, */ +/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, + * and BK - Bit3. */ +/* 8723 and 88E may be not correct either in the earlier version. */ +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopBK BIT3 +#define StopBE BIT2 +#define StopVI BIT1 +#define StopVO BIT0 + +/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ +#define RCR_APPFCS BIT31 /* WMAC append FCS after payload */ +#define RCR_APP_MIC BIT30 +#define RCR_APP_PHYSTS BIT28 +#define RCR_APP_ICV BIT29 +#define RCR_APP_PHYST_RXFF BIT28 +#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ +#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ +#define RCR_LSIGEN BIT23 +#define RCR_MFBEN BIT22 +#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ +#define RCR_AMF BIT13 /* Accept management type frame */ +#define RCR_ACF BIT12 /* Accept control type frame */ +#define RCR_ADF BIT11 /* Accept data type frame */ +#define RCR_AICV BIT9 /* Accept ICV error packet */ +#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ +#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet + * (Rx beacon, probe rsp) */ +#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/ +#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ +#define RCR_APWRMGT BIT5 /* Accept power management pkt*/ +#define RCR_ADD3 BIT4 /* Accept address 3 match pkt */ +#define RCR_AB BIT3 /* Accept broadcast packet */ +#define RCR_AM BIT2 /* Accept multicast packet */ +#define RCR_APM BIT1 /* Accept physical match pkt */ +#define RCR_AAP BIT0 /* Accept all unicast packet */ +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 + +/* 0xFE00h ~ 0xFE55h USB Configuration */ +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 +/* 8192C Regsiter Bit and Content definition */ +/* 0x0000h ~ 0x00FFh System Configuration */ + +/* 2 SYS_ISO_CTRL */ +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + +/* 2 SYS_FUNC_EN */ +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +/* 2 APS_FSMCO */ +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +/* 2 SYS_CLKR */ +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + +/* 2 9346CR */ + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + +/* 2 SPS0_CTRL */ + +/* 2 SPS_OCP_CFG */ + +/* 2 RF_CTRL */ +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +/* 2 LDOV12D_CTRL */ +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + +/* 2EFUSE_CTRL */ +#define ALD_EN BIT(18) +#define EF_PD BIT(19) +#define EF_FLAG BIT(31) + +/* 2 EFUSE_TEST (For RTL8723 partially) */ +#define EF_TRPT BIT(7) +/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ +#define EF_CELL_SEL (BIT(8)|BIT(9)) +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + +#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ +#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ + +/* 2 8051FWDL */ +/* 2 MCUFWDL */ +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + +/* 2 REG_SYS_CFG */ +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define SW_OFFLOAD_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) /* RTL ID */ +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ +#define CHIP_VER_RTL_SHIFT 12 + +/* 2REG_GPIO_OUTSTS (For RTL8723 only) */ +#define EFS_HCI_SEL (BIT(0)|BIT(1)) +#define PAD_HCI_SEL (BIT(2)|BIT(3)) +#define HCI_SEL (BIT(4)|BIT(5)) +#define PKG_SEL_HCI BIT(6) +#define FEN_GPS BIT(7) +#define FEN_BT BIT(8) +#define FEN_WL BIT(9) +#define FEN_PCI BIT(10) +#define FEN_USB BIT(11) +#define BTRF_HWPDN_N BIT(12) +#define WLRF_HWPDN_N BIT(13) +#define PDN_BT_N BIT(14) +#define PDN_GPS_N BIT(15) +#define BT_CTL_HWPDN BIT(16) +#define GPS_CTL_HWPDN BIT(17) +#define PPHY_SUSB BIT(20) +#define UPHY_SUSB BIT(21) +#define PCI_SUSEN BIT(22) +#define USB_SUSEN BIT(23) +#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) + +/* 2SYS_CFG */ +#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ + +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ + +/* 2 Function Enable Registers */ +/* 2 CR */ + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ + +/* Network type */ +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + +/* 2 PBP - Page Size Register */ +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + +/* 2 TX/RXDMA */ +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +/* For normal driver, 0x10C */ +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + +/* 2 TRXFF_BNDY */ + +/* 2 LLT_INIT */ +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +/* 2RQPN */ +#define _HPQ(x) ((x) & 0xFF) +#define _LPQ(x) (((x) & 0xFF) << 8) +#define _PUBQ(x) (((x) & 0xFF) << 16) +/* NOTE: in RQPN_NPQ register */ +#define _NPQ(x) ((x) & 0xFF) + +#define HPQ_PUBLIC_DIS BIT(24) +#define LPQ_PUBLIC_DIS BIT(25) +#define LD_RQPN BIT(31) + +/* 2TDECTRL */ +#define BCN_VALID BIT(16) +#define BCN_HEAD(x) (((x) & 0xFF) << 8) +#define BCN_HEAD_MASK 0xFF00 + +/* 2 TDECTL */ +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + +/* 2 TXDMA_OFFSET_CHK */ +#define DROP_DATA_EN BIT(9) + +/* 0x0280h ~ 0x028Bh RX DMA Configuration */ + +/* REG_RXDMA_CONTROL, 0x0286h */ + +/* 2 REG_RXPKT_NUM, 0x0284 */ +#define RXPKT_RELEASE_POLL BIT(16) +#define RXDMA_IDLE BIT(17) +#define RW_RELEASE_EN BIT(18) + +/* 0x0400h ~ 0x047Fh Protocol Configuration */ +/* 2 FWHW_TXQ_CTRL */ +#define EN_AMPDU_RTY_NEW BIT(7) + +/* 2 SPEC SIFS */ +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +/* 2 RL */ +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +/* 0x0500h ~ 0x05FFh EDCA Configuration */ + +/* 2 EDCA setting */ +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) + +/* 2 BCN_CTRL */ +#define EN_MBSSID BIT(1) +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) +#define DIS_TSF_UPDATE BIT(3) + +/* The same function but different bit field. */ +#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) +#define DIS_TSF_UDT0_TEST_CHIP BIT(5) +#define STOP_BCNQ BIT(6) + +/* 2 ACMHWCTRL */ +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) + +/* 0x0600h ~ 0x07FFh WMAC Configuration */ +/* 2APSD_CTRL */ +#define APSDOFF BIT(6) +#define APSDOFF_STATUS BIT(7) + +#define RATE_BITMAP_ALL 0xFFFFF + +/* Only use CCK 1M rate for ACK */ +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 + +/* 2 TCR */ +#define TSFRST BIT(0) +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) + +/* 2 RCR */ +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +#define APP_FCS BIT(31) + +/* 2 SECCFG */ +#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ +#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ +#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ +#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ +#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ +#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ +#define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ +#define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ + +/* RTL8188E SDIO Configuration */ + +/* I/O bus domain address mapping */ +#define SDIO_LOCAL_BASE 0x10250000 +#define WLAN_IOREG_BASE 0x10260000 +#define FIRMWARE_FIFO_BASE 0x10270000 +#define TX_HIQ_BASE 0x10310000 +#define TX_MIQ_BASE 0x10320000 +#define TX_LOQ_BASE 0x10330000 +#define RX_RX0FF_BASE 0x10340000 + +/* SDIO host local register space mapping. */ +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ +#define WLAN_RX0FF_MSK 0x0003 + +/* Without ref to the SDIO Device ID */ +#define SDIO_WITHOUT_REF_DEVICE_ID 0 +#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ +#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ +#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ +#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ +#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ +#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ + +/* SDIO Tx Free Page Index */ +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ +#define SDIO_MAX_RX_QUEUE 1 + +/* SDIO Tx Control */ +#define SDIO_REG_TX_CTRL 0x0000 +/* SDIO Host Interrupt Mask */ +#define SDIO_REG_HIMR 0x0014 +/* SDIO Host Interrupt Service Routine */ +#define SDIO_REG_HISR 0x0018 +/* HCI Current Power Mode */ +#define SDIO_REG_HCPWM 0x0019 +/* RXDMA Request Length */ +#define SDIO_REG_RX0_REQ_LEN 0x001C +/* Free Tx Buffer Page */ +#define SDIO_REG_FREE_TXPG 0x0020 +/* HCI Current Power Mode 1 */ +#define SDIO_REG_HCPWM1 0x0024 +/* HCI Current Power Mode 2 */ +#define SDIO_REG_HCPWM2 0x0026 +/* HTSF Informaion */ +#define SDIO_REG_HTSFR_INFO 0x0030 +/* HCI Request Power Mode 1 */ +#define SDIO_REG_HRPWM1 0x0080 +/* HCI Request Power Mode 2 */ +#define SDIO_REG_HRPWM2 0x0082 +/* HCI Power Save Clock */ +#define SDIO_REG_HPS_CLKR 0x0084 +/* SDIO HCI Suspend Control */ +#define SDIO_REG_HSUS_CTRL 0x0086 +/* SDIO Host Extension Interrupt Mask Always */ +#define SDIO_REG_HIMR_ON 0x0090 +/* SDIO Host Extension Interrupt Status Always */ +#define SDIO_REG_HISR_ON 0x0091 + +#define SDIO_HIMR_DISABLED 0 + +/* RTL8188E SDIO Host Interrupt Mask Register */ +#define SDIO_HIMR_RX_REQUEST_MSK BIT0 +#define SDIO_HIMR_AVAL_MSK BIT1 +#define SDIO_HIMR_TXERR_MSK BIT2 +#define SDIO_HIMR_RXERR_MSK BIT3 +#define SDIO_HIMR_TXFOVW_MSK BIT4 +#define SDIO_HIMR_RXFOVW_MSK BIT5 +#define SDIO_HIMR_TXBCNOK_MSK BIT6 +#define SDIO_HIMR_TXBCNERR_MSK BIT7 +#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 +#define SDIO_HIMR_C2HCMD_MSK BIT17 +#define SDIO_HIMR_CPWM1_MSK BIT18 +#define SDIO_HIMR_CPWM2_MSK BIT19 +#define SDIO_HIMR_HSISR_IND_MSK BIT20 +#define SDIO_HIMR_GTINT3_IND_MSK BIT21 +#define SDIO_HIMR_GTINT4_IND_MSK BIT22 +#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 +#define SDIO_HIMR_OCPINT_MSK BIT24 +#define SDIO_HIMR_ATIMEND_MSK BIT25 +#define SDIO_HIMR_ATIMEND_E_MSK BIT26 +#define SDIO_HIMR_CTWEND_MSK BIT27 + +/* RTL8188E SDIO Specific */ +#define SDIO_HIMR_MCU_ERR_MSK BIT28 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 + +/* SDIO Host Interrupt Service Routine */ +#define SDIO_HISR_RX_REQUEST BIT0 +#define SDIO_HISR_AVAL BIT1 +#define SDIO_HISR_TXERR BIT2 +#define SDIO_HISR_RXERR BIT3 +#define SDIO_HISR_TXFOVW BIT4 +#define SDIO_HISR_RXFOVW BIT5 +#define SDIO_HISR_TXBCNOK BIT6 +#define SDIO_HISR_TXBCNERR BIT7 +#define SDIO_HISR_BCNERLY_INT BIT16 +#define SDIO_HISR_C2HCMD BIT17 +#define SDIO_HISR_CPWM1 BIT18 +#define SDIO_HISR_CPWM2 BIT19 +#define SDIO_HISR_HSISR_IND BIT20 +#define SDIO_HISR_GTINT3_IND BIT21 +#define SDIO_HISR_GTINT4_IND BIT22 +#define SDIO_HISR_PSTIME BIT23 +#define SDIO_HISR_OCPINT BIT24 +#define SDIO_HISR_ATIMEND BIT25 +#define SDIO_HISR_ATIMEND_E BIT26 +#define SDIO_HISR_CTWEND BIT27 + +/* RTL8188E SDIO Specific */ +#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 + +#define MASK_SDIO_HISR_CLEAR \ + (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\ + SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\ + SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\ + SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\ + SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT) + +/* SDIO HCI Suspend Control Register */ +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 + +/* SDIO Tx FIFO related */ +/* The number of Tx FIFO free page */ +#define SDIO_TX_FREE_PG_QUEUE 4 +#define SDIO_TX_FIFO_PAGE_SZ 128 + +/* 0xFE00h ~ 0xFE55h USB Configuration */ + +/* 2 USB Information (0xFE17) */ +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +/* 2 Special Option */ +#define USB_AGG_EN BIT(3) + +/* 0; Use interrupt endpoint to upload interrupt pkt */ +/* 1; Use bulk endpoint to upload interrupt pkt, */ +#define INT_BULK_SEL BIT(4) + +/* 2REG_C2HEVT_CLEAR */ +/* Set by driver and notify FW that the driver has read + * the C2H command message */ +#define C2H_EVT_HOST_CLOSE 0x00 +/* Set by FW indicating that FW had set the C2H command + * message and it's not yet read by driver. */ +#define C2H_EVT_FW_CLOSE 0xFF + +/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ +/* Enable GPIO[9] as WiFi HW PDn source */ +#define WL_HWPDN_EN BIT0 +/* WiFi HW PDn polarity control */ +#define WL_HWPDN_SL BIT1 +/* WiFi function enable */ +#define WL_FUNC_EN BIT2 +/* Enable GPIO[9] as WiFi RF HW PDn source */ +#define WL_HWROF_EN BIT3 +/* Enable GPIO[11] as BT HW PDn source */ +#define BT_HWPDN_EN BIT16 +/* BT HW PDn polarity control */ +#define BT_HWPDN_SL BIT17 +/* BT function enable */ +#define BT_FUNC_EN BIT18 +/* Enable GPIO[11] as BT/GPS RF HW PDn source */ +#define BT_HWROF_EN BIT19 +/* Enable GPIO[10] as GPS HW PDn source */ +#define GPS_HWPDN_EN BIT20 +/* GPS HW PDn polarity control */ +#define GPS_HWPDN_SL BIT21 +/* GPS function enable */ +#define GPS_FUNC_EN BIT22 + +/* 3 REG_LIFECTRL_CTRL */ +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ + +/* General definitions */ +#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */ + +#define POLLING_LLT_THRESHOLD 20 +#define POLLING_READY_TIMEOUT_COUNT 1000 +/* GPIO BIT */ +#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 + +/* 8192C EEPROM/EFUSE share register definition. */ + +/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ +#define EEPROM_TX_PWR_INX_88E 0x10 + +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB + +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CUSTOMERID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 + +/* RTL88EE */ +#define EEPROM_MAC_ADDR_88EE 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC + +/* RTL88EU */ +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 +#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 + +/* RTL88ES */ +#define EEPROM_MAC_ADDR_88ES 0x11A + +/* EEPROM/Efuse Value Type */ +#define EETYPE_TX_PWR 0x0 + +/* Default Value for EEPROM or EFUSE!!! */ +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_CrystalCap 0x5 +/* Default: 2X2, RTL8192CE(QFPN68) */ +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Default_HT2T_TxPwr 0x10 + +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_ThermalMeter 0x12 + +#define EEPROM_Default_AntTxPowerDiff 0x0 +#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 +#define EEPROM_Default_TxPowerLevel 0x2A + +#define EEPROM_Default_HT40_2SDiff 0x0 +/* HT20<->40 default Tx Power Index Difference */ +#define EEPROM_Default_HT20_Diff 2 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_HT40_PwrMaxOffset 0 +#define EEPROM_Default_HT20_PwrMaxOffset 0 + +#define EEPROM_Default_CrystalCap_88E 0x20 +#define EEPROM_Default_ThermalMeter_88E 0x18 + +/* New EFUSE deafult value */ +#define EEPROM_DEFAULT_24G_INDEX 0x2D +#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 +#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_5G_INDEX 0X2A +#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_DIFF 0XFE +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x00 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_BT_OPTION 0x10 + +/* For debug */ +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_CustomerID_8188E 0x00 +#define EEPROM_Default_SubCustomerID 0xCD +#define EEPROM_Default_Version 0 + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPA 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_NCC 0xB +#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 /* CCX test. */ +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE +#define RTL_EEPROM_ID 0x8129 + +#endif /* __RTL8188E_SPEC_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_sreset.h b/drivers/staging/rtl8188eu/include/rtl8188e_sreset.h new file mode 100644 index 000000000000..a29e69519794 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_sreset.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL8188E_SRESET_H_ +#define _RTL8188E_SRESET_H_ + +#include +#include +#include + +void rtl8188e_silentreset_for_specific_platform(struct adapter *padapter); +void rtl8188e_sreset_xmit_status_check(struct adapter *padapter); +void rtl8188e_sreset_linked_status_check(struct adapter *padapter); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_xmit.h b/drivers/staging/rtl8188eu/include/rtl8188e_xmit.h new file mode 100644 index 000000000000..cf7267a53659 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_xmit.h @@ -0,0 +1,178 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188E_XMIT_H__ +#define __RTL8188E_XMIT_H__ + +#define MAX_TX_AGG_PACKET_NUMBER 0xFF +/* */ +/* Queue Select Value in TxDesc */ +/* */ +#define QSLT_BK 0x2/* 0x01 */ +#define QSLT_BE 0x0 +#define QSLT_VI 0x5/* 0x4 */ +#define QSLT_VO 0x7/* 0x6 */ +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +/* For 88e early mode */ +#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) +#define SET_EARLYMODE_LEN0(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) +#define SET_EARLYMODE_LEN1(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) +#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) +#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) +#define SET_EARLYMODE_LEN3(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) +#define SET_EARLYMODE_LEN4(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) + +/* */ +/* defined for TX DESC Operation */ +/* */ + +#define MAX_TID (15) + +/* OFFSET 0 */ +#define OFFSET_SZ 0 +#define OFFSET_SHT 16 +#define BMC BIT(24) +#define LSG BIT(26) +#define FSG BIT(27) +#define OWN BIT(31) + + +/* OFFSET 4 */ +#define PKT_OFFSET_SZ 0 +#define QSEL_SHT 8 +#define RATE_ID_SHT 16 +#define NAVUSEHDR BIT(20) +#define SEC_TYPE_SHT 22 +#define PKT_OFFSET_SHT 26 + +/* OFFSET 8 */ +#define AGG_EN BIT(12) +#define AGG_BK BIT(16) +#define AMPDU_DENSITY_SHT 20 +#define ANTSEL_A BIT(24) +#define ANTSEL_B BIT(25) +#define TX_ANT_CCK_SHT 26 +#define TX_ANTL_SHT 28 +#define TX_ANT_HT_SHT 30 + +/* OFFSET 12 */ +#define SEQ_SHT 16 +#define EN_HWSEQ BIT(31) + +/* OFFSET 16 */ +#define QOS BIT(6) +#define HW_SSN BIT(7) +#define USERATE BIT(8) +#define DISDATAFB BIT(10) +#define CTS_2_SELF BIT(11) +#define RTS_EN BIT(12) +#define HW_RTS_EN BIT(13) +#define DATA_SHORT BIT(24) +#define PWR_STATUS_SHT 15 +#define DATA_SC_SHT 20 +#define DATA_BW BIT(25) + +/* OFFSET 20 */ +#define RTY_LMT_EN BIT(17) + +enum TXDESC_SC { + SC_DONT_CARE = 0x00, + SC_UPPER = 0x01, + SC_LOWER = 0x02, + SC_DUPLICATE = 0x03 +}; +/* OFFSET 20 */ +#define SGI BIT(6) +#define USB_TXAGG_NUM_SHT 24 + +#define txdesc_set_ccx_sw_88e(txdesc, value) \ + do { \ + ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \ + ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \ + } while (0) + +struct txrpt_ccx_88e { + /* offset 0 */ + u8 tag1:1; + u8 pkt_num:3; + u8 txdma_underflow:1; + u8 int_bt:1; + u8 int_tri:1; + u8 int_ccx:1; + + /* offset 1 */ + u8 mac_id:6; + u8 pkt_ok:1; + u8 bmc:1; + + /* offset 2 */ + u8 retry_cnt:6; + u8 lifetime_over:1; + u8 retry_over:1; + + /* offset 3 */ + u8 ccx_qtime0; + u8 ccx_qtime1; + + /* offset 5 */ + u8 final_data_rate; + + /* offset 6 */ + u8 sw1:4; + u8 qsel:4; + + /* offset 7 */ + u8 sw0; +}; + +#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) +#define txrpt_ccx_qtime_88e(txrpt_ccx) \ + ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) + +void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc, + u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); +s32 rtl8188eu_init_xmit_priv(struct adapter *padapter); +void rtl8188eu_free_xmit_priv(struct adapter *padapter); +s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *frame); +s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *frame); +s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter); +#define hal_xmit_handler rtl8188eu_xmit_buf_handler +void rtl8188eu_xmit_tasklet(void *priv); +s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, + struct xmit_priv *pxmitpriv, + struct xmit_buf *pxmitbuf); + +void dump_txrpt_ccx_88e(void *buf); +void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf); + +void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag, + struct tx_desc *ptxdesc); + +#endif /* __RTL8188E_XMIT_H__ */