From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Date: Thu, 6 Sep 2018 13:51:50 +0000 (+0300)
Subject: Merge tag 'gvt-next-2018-09-04' of https://github.com/intel/gvt-linux into drm-intel... 
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=5781cf82553ce1c91aa2173f9def10680275cddb;p=openwrt%2Fstaging%2Fblogic.git

Merge tag 'gvt-next-2018-09-04' of https://github.com/intel/gvt-linux into drm-intel-next-queued

gvt-next-2018-09-04

- guest context shadow optimization for restore inhibit one (Yan)
- cmd parser optimization (Yan)
- W=1 warning fixes (Zhenyu)

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

# Conflicts:
#	drivers/gpu/drm/i915/gvt/reg.h
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180904030154.GG20737@zhen-hp.sh.intel.com
---

5781cf82553ce1c91aa2173f9def10680275cddb
diff --cc drivers/gpu/drm/i915/gvt/cmd_parser.c
index 0651e63b25fb,4ba503ef5d2c..865d80919827
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@@ -2902,9 -2909,10 +2909,11 @@@ static int init_cmd_table(struct intel_
  		if (info) {
  			gvt_err("%s %s duplicated\n", e->info->name,
  					info->name);
 +			kfree(e);
  			return -EEXIST;
  		}
+ 		if (cmd_info[i].opcode == OP_MI_NOOP)
+ 			mi_noop_index = i;
  
  		INIT_HLIST_NODE(&e->hlist);
  		add_cmd_entry(gvt, e);
diff --cc drivers/gpu/drm/i915/gvt/reg.h
index c9d6cf6cc623,60dcc6bb8425..428d252344f1
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@@ -77,13 -77,13 +77,22 @@@
  #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
  		I915_GTT_PAGE_SIZE)
  
 +#define PCH_GPIO_BASE	_MMIO(0xc5010)
 +
 +#define PCH_GMBUS0	_MMIO(0xc5100)
 +#define PCH_GMBUS1	_MMIO(0xc5104)
 +#define PCH_GMBUS2	_MMIO(0xc5108)
 +#define PCH_GMBUS3	_MMIO(0xc510c)
 +#define PCH_GMBUS4	_MMIO(0xc5110)
 +#define PCH_GMBUS5	_MMIO(0xc5120)
 +
+ #define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i) * 4)
+ #define TRNULLDETCT		_MMIO(0x4de8)
+ #define TRINVTILEDETCT		_MMIO(0x4dec)
+ #define TRVADR			_MMIO(0x4df0)
+ #define TRTTE			_MMIO(0x4df4)
+ #define RING_EXCC(base)		_MMIO((base) + 0x28)
+ #define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
+ #define VF_GUARDBAND		_MMIO(0x83a4)
+ 
  #endif