From: Gabor Juhos Date: Sat, 5 May 2012 13:56:35 +0000 (+0000) Subject: ar71xx: update 3.3 patches X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=56f2e085371d5fc782385b8ab1b2c2f58560ac56;p=openwrt%2Fstaging%2Fthess.git ar71xx: update 3.3 patches SVN-Revision: 31602 --- diff --git a/target/linux/ar71xx/patches-3.3/000-USB-OHCI-Add-a-generic-platform-device-driver.patch b/target/linux/ar71xx/patches-3.3/000-USB-OHCI-Add-a-generic-platform-device-driver.patch new file mode 100644 index 0000000000..240cca03b2 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/000-USB-OHCI-Add-a-generic-platform-device-driver.patch @@ -0,0 +1,293 @@ +From be77ba57151bd35ce63ccf52d74b6c626fa73817 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Tue, 13 Mar 2012 01:04:47 +0100 +Subject: [PATCH 01/47] USB: OHCI: Add a generic platform device driver + +This adds a generic driver for platform devices. It works like the PCI +driver and is based on it. This is for devices which do not have an own +bus but their OHCI controller works like a PCI controller. It will be +used for the Broadcom bcma and ssb USB OHCI controller. + +Acked-by: Alan Stern +Signed-off-by: Hauke Mehrtens +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/Kconfig | 10 ++ + drivers/usb/host/ohci-hcd.c | 5 + + drivers/usb/host/ohci-platform.c | 194 ++++++++++++++++++++++++++++++++++++++ + include/linux/usb/ohci_pdriver.h | 38 ++++++++ + 4 files changed, 247 insertions(+), 0 deletions(-) + create mode 100644 drivers/usb/host/ohci-platform.c + create mode 100644 include/linux/usb/ohci_pdriver.h + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -393,6 +393,16 @@ config USB_CNS3XXX_OHCI + Enable support for the CNS3XXX SOC's on-chip OHCI controller. + It is needed for low-speed USB 1.0 device support. + ++config USB_OHCI_HCD_PLATFORM ++ bool "Generic OHCI driver for a platform device" ++ depends on USB_OHCI_HCD && EXPERIMENTAL ++ default n ++ ---help--- ++ Adds an OHCI host driver for a generic platform device, which ++ provieds a memory space and an irq. ++ ++ If unsure, say N. ++ + config USB_OHCI_BIG_ENDIAN_DESC + bool + depends on USB_OHCI_HCD +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1121,6 +1121,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ohci_xls_driver + #endif + ++#ifdef CONFIG_USB_OHCI_HCD_PLATFORM ++#include "ohci-platform.c" ++#define PLATFORM_DRIVER ohci_platform_driver ++#endif ++ + #if !defined(PCI_DRIVER) && \ + !defined(PLATFORM_DRIVER) && \ + !defined(OMAP1_PLATFORM_DRIVER) && \ +--- /dev/null ++++ b/drivers/usb/host/ohci-platform.c +@@ -0,0 +1,194 @@ ++/* ++ * Generic platform ohci driver ++ * ++ * Copyright 2007 Michael Buesch ++ * Copyright 2011-2012 Hauke Mehrtens ++ * ++ * Derived from the OCHI-SSB driver ++ * Derived from the OHCI-PCI driver ++ * Copyright 1999 Roman Weissgaerber ++ * Copyright 2000-2002 David Brownell ++ * Copyright 1999 Linus Torvalds ++ * Copyright 1999 Gregory P. Smith ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++#include ++#include ++ ++static int ohci_platform_reset(struct usb_hcd *hcd) ++{ ++ struct platform_device *pdev = to_platform_device(hcd->self.controller); ++ struct usb_ohci_pdata *pdata = pdev->dev.platform_data; ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int err; ++ ++ if (pdata->big_endian_desc) ++ ohci->flags |= OHCI_QUIRK_BE_DESC; ++ if (pdata->big_endian_mmio) ++ ohci->flags |= OHCI_QUIRK_BE_MMIO; ++ if (pdata->no_big_frame_no) ++ ohci->flags |= OHCI_QUIRK_FRAME_NO; ++ ++ ohci_hcd_init(ohci); ++ err = ohci_init(ohci); ++ ++ return err; ++} ++ ++static int ohci_platform_start(struct usb_hcd *hcd) ++{ ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int err; ++ ++ err = ohci_run(ohci); ++ if (err < 0) { ++ ohci_err(ohci, "can't start\n"); ++ ohci_stop(hcd); ++ } ++ ++ return err; ++} ++ ++static const struct hc_driver ohci_platform_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Generic Platform OHCI Controller", ++ .hcd_priv_size = sizeof(struct ohci_hcd), ++ ++ .irq = ohci_irq, ++ .flags = HCD_MEMORY | HCD_USB11, ++ ++ .reset = ohci_platform_reset, ++ .start = ohci_platform_start, ++ .stop = ohci_stop, ++ .shutdown = ohci_shutdown, ++ ++ .urb_enqueue = ohci_urb_enqueue, ++ .urb_dequeue = ohci_urb_dequeue, ++ .endpoint_disable = ohci_endpoint_disable, ++ ++ .get_frame_number = ohci_get_frame, ++ ++ .hub_status_data = ohci_hub_status_data, ++ .hub_control = ohci_hub_control, ++#ifdef CONFIG_PM ++ .bus_suspend = ohci_bus_suspend, ++ .bus_resume = ohci_bus_resume, ++#endif ++ ++ .start_port_reset = ohci_start_port_reset, ++}; ++ ++static int __devinit ohci_platform_probe(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd; ++ struct resource *res_mem; ++ int irq; ++ int err = -ENOMEM; ++ ++ BUG_ON(!dev->dev.platform_data); ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ irq = platform_get_irq(dev, 0); ++ if (irq < 0) { ++ pr_err("no irq provieded"); ++ return irq; ++ } ++ ++ res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!res_mem) { ++ pr_err("no memory recourse provieded"); ++ return -ENXIO; ++ } ++ ++ hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev, ++ dev_name(&dev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ hcd->rsrc_start = res_mem->start; ++ hcd->rsrc_len = resource_size(res_mem); ++ ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ pr_err("controller already in use"); ++ err = -EBUSY; ++ goto err_put_hcd; ++ } ++ ++ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) ++ goto err_release_region; ++ err = usb_add_hcd(hcd, irq, IRQF_SHARED); ++ if (err) ++ goto err_iounmap; ++ ++ platform_set_drvdata(dev, hcd); ++ ++ return err; ++ ++err_iounmap: ++ iounmap(hcd->regs); ++err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err_put_hcd: ++ usb_put_hcd(hcd); ++ return err; ++} ++ ++static int __devexit ohci_platform_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); ++ platform_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++ ++static int ohci_platform_suspend(struct device *dev) ++{ ++ return 0; ++} ++ ++static int ohci_platform_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ ++ ohci_finish_controller_resume(hcd); ++ return 0; ++} ++ ++#else /* !CONFIG_PM */ ++#define ohci_platform_suspend NULL ++#define ohci_platform_resume NULL ++#endif /* CONFIG_PM */ ++ ++static const struct platform_device_id ohci_platform_table[] = { ++ { "ohci-platform", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(platform, ohci_platform_table); ++ ++static const struct dev_pm_ops ohci_platform_pm_ops = { ++ .suspend = ohci_platform_suspend, ++ .resume = ohci_platform_resume, ++}; ++ ++static struct platform_driver ohci_platform_driver = { ++ .id_table = ohci_platform_table, ++ .probe = ohci_platform_probe, ++ .remove = __devexit_p(ohci_platform_remove), ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "ohci-platform", ++ .pm = &ohci_platform_pm_ops, ++ } ++}; +--- /dev/null ++++ b/include/linux/usb/ohci_pdriver.h +@@ -0,0 +1,38 @@ ++/* ++ * Copyright (C) 2012 Hauke Mehrtens ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __USB_CORE_OHCI_PDRIVER_H ++#define __USB_CORE_OHCI_PDRIVER_H ++ ++/** ++ * struct usb_ohci_pdata - platform_data for generic ohci driver ++ * ++ * @big_endian_desc: BE descriptors ++ * @big_endian_mmio: BE registers ++ * @no_big_frame_no: no big endian frame_no shift ++ * ++ * These are general configuration options for the OHCI controller. All of ++ * these options are activating more or less workarounds for some hardware. ++ */ ++struct usb_ohci_pdata { ++ unsigned big_endian_desc:1; ++ unsigned big_endian_mmio:1; ++ unsigned no_big_frame_no:1; ++}; ++ ++#endif /* __USB_CORE_OHCI_PDRIVER_H */ diff --git a/target/linux/ar71xx/patches-3.3/001-USB-EHCI-Add-a-generic-platform-device-driver.patch b/target/linux/ar71xx/patches-3.3/001-USB-EHCI-Add-a-generic-platform-device-driver.patch new file mode 100644 index 0000000000..f94f39c2e8 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/001-USB-EHCI-Add-a-generic-platform-device-driver.patch @@ -0,0 +1,305 @@ +From 4fa3face95f1ca2e396dd59324a6c6ef01df24cc Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Tue, 13 Mar 2012 01:04:48 +0100 +Subject: [PATCH 02/47] USB: EHCI: Add a generic platform device driver + +This adds a generic driver for platform devices. It works like the PCI +driver and is based on it. This is for devices which do not have an own +bus but their EHCI controller works like a PCI controller. It will be +used for the Broadcom bcma and ssb USB EHCI controller. + +Acked-by: Alan Stern +Signed-off-by: Hauke Mehrtens +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/Kconfig | 10 ++ + drivers/usb/host/ehci-hcd.c | 5 + + drivers/usb/host/ehci-platform.c | 198 ++++++++++++++++++++++++++++++++++++++ + include/linux/usb/ehci_pdriver.h | 46 +++++++++ + 4 files changed, 259 insertions(+), 0 deletions(-) + create mode 100644 drivers/usb/host/ehci-platform.c + create mode 100644 include/linux/usb/ehci_pdriver.h + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -403,6 +403,16 @@ config USB_OHCI_HCD_PLATFORM + + If unsure, say N. + ++config USB_EHCI_HCD_PLATFORM ++ bool "Generic EHCI driver for a platform device" ++ depends on USB_EHCI_HCD && EXPERIMENTAL ++ default n ++ ---help--- ++ Adds an EHCI host driver for a generic platform device, which ++ provieds a memory space and an irq. ++ ++ If unsure, say N. ++ + config USB_OHCI_BIG_ENDIAN_DESC + bool + depends on USB_OHCI_HCD +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1381,6 +1381,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ehci_mv_driver + #endif + ++#ifdef CONFIG_USB_EHCI_HCD_PLATFORM ++#include "ehci-platform.c" ++#define PLATFORM_DRIVER ehci_platform_driver ++#endif ++ + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ + !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ + !defined(XILINX_OF_PLATFORM_DRIVER) +--- /dev/null ++++ b/drivers/usb/host/ehci-platform.c +@@ -0,0 +1,198 @@ ++/* ++ * Generic platform ehci driver ++ * ++ * Copyright 2007 Steven Brown ++ * Copyright 2010-2012 Hauke Mehrtens ++ * ++ * Derived from the ohci-ssb driver ++ * Copyright 2007 Michael Buesch ++ * ++ * Derived from the EHCI-PCI driver ++ * Copyright (c) 2000-2004 by David Brownell ++ * ++ * Derived from the ohci-pci driver ++ * Copyright 1999 Roman Weissgaerber ++ * Copyright 2000-2002 David Brownell ++ * Copyright 1999 Linus Torvalds ++ * Copyright 1999 Gregory P. Smith ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++#include ++#include ++ ++static int ehci_platform_reset(struct usb_hcd *hcd) ++{ ++ struct platform_device *pdev = to_platform_device(hcd->self.controller); ++ struct usb_ehci_pdata *pdata = pdev->dev.platform_data; ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int retval; ++ ++ hcd->has_tt = pdata->has_tt; ++ ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug; ++ ehci->big_endian_desc = pdata->big_endian_desc; ++ ehci->big_endian_mmio = pdata->big_endian_mmio; ++ ++ ehci->caps = hcd->regs + pdata->caps_offset; ++ retval = ehci_setup(hcd); ++ if (retval) ++ return retval; ++ ++ if (pdata->port_power_on) ++ ehci_port_power(ehci, 1); ++ if (pdata->port_power_off) ++ ehci_port_power(ehci, 0); ++ ++ return 0; ++} ++ ++static const struct hc_driver ehci_platform_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Generic Platform EHCI Controller", ++ .hcd_priv_size = sizeof(struct ehci_hcd), ++ ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ .reset = ehci_platform_reset, ++ .start = ehci_run, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, ++ ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ .endpoint_reset = ehci_endpoint_reset, ++ ++ .get_frame_number = ehci_get_frame, ++ ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#if defined(CONFIG_PM) ++ .bus_suspend = ehci_bus_suspend, ++ .bus_resume = ehci_bus_resume, ++#endif ++ .relinquish_port = ehci_relinquish_port, ++ .port_handed_over = ehci_port_handed_over, ++ ++ .update_device = ehci_update_device, ++ ++ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++}; ++ ++static int __devinit ehci_platform_probe(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd; ++ struct resource *res_mem; ++ int irq; ++ int err = -ENOMEM; ++ ++ BUG_ON(!dev->dev.platform_data); ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ irq = platform_get_irq(dev, 0); ++ if (irq < 0) { ++ pr_err("no irq provieded"); ++ return irq; ++ } ++ res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!res_mem) { ++ pr_err("no memory recourse provieded"); ++ return -ENXIO; ++ } ++ ++ hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev, ++ dev_name(&dev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ hcd->rsrc_start = res_mem->start; ++ hcd->rsrc_len = resource_size(res_mem); ++ ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ pr_err("controller already in use"); ++ err = -EBUSY; ++ goto err_put_hcd; ++ } ++ ++ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) ++ goto err_release_region; ++ err = usb_add_hcd(hcd, irq, IRQF_SHARED); ++ if (err) ++ goto err_iounmap; ++ ++ platform_set_drvdata(dev, hcd); ++ ++ return err; ++ ++err_iounmap: ++ iounmap(hcd->regs); ++err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err_put_hcd: ++ usb_put_hcd(hcd); ++ return err; ++} ++ ++static int __devexit ehci_platform_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); ++ platform_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++ ++static int ehci_platform_suspend(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ bool wakeup = device_may_wakeup(dev); ++ ++ ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), wakeup); ++ return 0; ++} ++ ++static int ehci_platform_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ ++ ehci_prepare_ports_for_controller_resume(hcd_to_ehci(hcd)); ++ return 0; ++} ++ ++#else /* !CONFIG_PM */ ++#define ehci_platform_suspend NULL ++#define ehci_platform_resume NULL ++#endif /* CONFIG_PM */ ++ ++static const struct platform_device_id ehci_platform_table[] = { ++ { "ehci-platform", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(platform, ehci_platform_table); ++ ++static const struct dev_pm_ops ehci_platform_pm_ops = { ++ .suspend = ehci_platform_suspend, ++ .resume = ehci_platform_resume, ++}; ++ ++static struct platform_driver ehci_platform_driver = { ++ .id_table = ehci_platform_table, ++ .probe = ehci_platform_probe, ++ .remove = __devexit_p(ehci_platform_remove), ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "ehci-platform", ++ .pm = &ehci_platform_pm_ops, ++ } ++}; +--- /dev/null ++++ b/include/linux/usb/ehci_pdriver.h +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (C) 2012 Hauke Mehrtens ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software Foundation, ++ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __USB_CORE_EHCI_PDRIVER_H ++#define __USB_CORE_EHCI_PDRIVER_H ++ ++/** ++ * struct usb_ehci_pdata - platform_data for generic ehci driver ++ * ++ * @caps_offset: offset of the EHCI Capability Registers to the start of ++ * the io memory region provided to the driver. ++ * @has_tt: set to 1 if TT is integrated in root hub. ++ * @port_power_on: set to 1 if the controller needs a power up after ++ * initialization. ++ * @port_power_off: set to 1 if the controller needs to be powered down ++ * after initialization. ++ * ++ * These are general configuration options for the EHCI controller. All of ++ * these options are activating more or less workarounds for some hardware. ++ */ ++struct usb_ehci_pdata { ++ int caps_offset; ++ unsigned has_tt:1; ++ unsigned has_synopsys_hc_bug:1; ++ unsigned big_endian_desc:1; ++ unsigned big_endian_mmio:1; ++ unsigned port_power_on:1; ++ unsigned port_power_off:1; ++}; ++ ++#endif /* __USB_CORE_EHCI_PDRIVER_H */ diff --git a/target/linux/ar71xx/patches-3.3/002-USB-use-generic-platform-driver-on-ath79.patch b/target/linux/ar71xx/patches-3.3/002-USB-use-generic-platform-driver-on-ath79.patch new file mode 100644 index 0000000000..d3a3b7106a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/002-USB-use-generic-platform-driver-on-ath79.patch @@ -0,0 +1,544 @@ +From dbcbcdd001c5943adbb18db3b8f0dafc405559eb Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Tue, 13 Mar 2012 01:04:53 +0100 +Subject: [PATCH 03/47] USB: use generic platform driver on ath79 + +The ath79 usb driver doesn't do anything special and is now converted +to the generic ehci and ohci driver. +This was tested on a TP-Link TL-WR1043ND (AR9132) + +Acked-by: Gabor Juhos +CC: Imre Kaloz +CC: linux-mips@linux-mips.org +CC: Ralf Baechle +Signed-off-by: Hauke Mehrtens +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/ath79/dev-usb.c | 31 +++++- + drivers/usb/host/Kconfig | 12 ++- + drivers/usb/host/ehci-ath79.c | 208 ----------------------------------------- + drivers/usb/host/ehci-hcd.c | 5 - + drivers/usb/host/ohci-ath79.c | 151 ----------------------------- + drivers/usb/host/ohci-hcd.c | 5 - + 6 files changed, 35 insertions(+), 377 deletions(-) + delete mode 100644 drivers/usb/host/ehci-ath79.c + delete mode 100644 drivers/usb/host/ohci-ath79.c + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -17,6 +17,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -36,14 +38,19 @@ static struct resource ath79_ohci_resour + }; + + static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); ++ ++static struct usb_ohci_pdata ath79_ohci_pdata = { ++}; ++ + static struct platform_device ath79_ohci_device = { +- .name = "ath79-ohci", ++ .name = "ohci-platform", + .id = -1, + .resource = ath79_ohci_resources, + .num_resources = ARRAY_SIZE(ath79_ohci_resources), + .dev = { + .dma_mask = &ath79_ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &ath79_ohci_pdata, + }, + }; + +@@ -60,8 +67,20 @@ static struct resource ath79_ehci_resour + }; + + static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); ++ ++static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { ++ .has_synopsys_hc_bug = 1, ++ .port_power_off = 1, ++}; ++ ++static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { ++ .caps_offset = 0x100, ++ .has_tt = 1, ++ .port_power_off = 1, ++}; ++ + static struct platform_device ath79_ehci_device = { +- .name = "ath79-ehci", ++ .name = "ehci-platform", + .id = -1, + .resource = ath79_ehci_resources, + .num_resources = ARRAY_SIZE(ath79_ehci_resources), +@@ -101,7 +120,7 @@ static void __init ath79_usb_setup(void) + + ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; + ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar71xx-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; + platform_device_register(&ath79_ehci_device); + } + +@@ -142,7 +161,7 @@ static void __init ar724x_usb_setup(void + + ath79_ehci_resources[0].start = AR724X_EHCI_BASE; + ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar724x-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } + +@@ -159,7 +178,7 @@ static void __init ar913x_usb_setup(void + + ath79_ehci_resources[0].start = AR913X_EHCI_BASE; + ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar913x-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } + +@@ -176,7 +195,7 @@ static void __init ar933x_usb_setup(void + + ath79_ehci_resources[0].start = AR933X_EHCI_BASE; + ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; +- ath79_ehci_device.name = "ar933x-ehci"; ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -218,11 +218,15 @@ config USB_CNS3XXX_EHCI + support. + + config USB_EHCI_ATH79 +- bool "EHCI support for AR7XXX/AR9XXX SoCs" ++ bool "EHCI support for AR7XXX/AR9XXX SoCs (DEPRECATED)" + depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) + select USB_EHCI_ROOT_HUB_TT ++ select USB_EHCI_HCD_PLATFORM + default y + ---help--- ++ This option is deprecated now and the driver was removed, use ++ USB_EHCI_HCD_PLATFORM instead. ++ + Enables support for the built-in EHCI controller present + on the Atheros AR7XXX/AR9XXX SoCs. + +@@ -312,10 +316,14 @@ config USB_OHCI_HCD_OMAP3 + OMAP3 and later chips. + + config USB_OHCI_ATH79 +- bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs" ++ bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs (DEPRECATED)" + depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X) ++ select USB_OHCI_HCD_PLATFORM + default y + help ++ This option is deprecated now and the driver was removed, use ++ USB_OHCI_HCD_PLATFORM instead. ++ + Enables support for the built-in OHCI controller present on the + Atheros AR71XX/AR7240 SoCs. + +--- a/drivers/usb/host/ehci-ath79.c ++++ /dev/null +@@ -1,208 +0,0 @@ +-/* +- * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller. +- * +- * Copyright (C) 2008-2011 Gabor Juhos +- * Copyright (C) 2008 Imre Kaloz +- * +- * Parts of this file are based on Atheros' 2.6.15 BSP +- * Copyright (C) 2007 Atheros Communications, Inc. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include +- +-enum { +- EHCI_ATH79_IP_V1 = 0, +- EHCI_ATH79_IP_V2, +-}; +- +-static const struct platform_device_id ehci_ath79_id_table[] = { +- { +- .name = "ar71xx-ehci", +- .driver_data = EHCI_ATH79_IP_V1, +- }, +- { +- .name = "ar724x-ehci", +- .driver_data = EHCI_ATH79_IP_V2, +- }, +- { +- .name = "ar913x-ehci", +- .driver_data = EHCI_ATH79_IP_V2, +- }, +- { +- .name = "ar933x-ehci", +- .driver_data = EHCI_ATH79_IP_V2, +- }, +- { +- /* terminating entry */ +- }, +-}; +- +-MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table); +- +-static int ehci_ath79_init(struct usb_hcd *hcd) +-{ +- struct ehci_hcd *ehci = hcd_to_ehci(hcd); +- struct platform_device *pdev = to_platform_device(hcd->self.controller); +- const struct platform_device_id *id; +- int ret; +- +- id = platform_get_device_id(pdev); +- if (!id) { +- dev_err(hcd->self.controller, "missing device id\n"); +- return -EINVAL; +- } +- +- switch (id->driver_data) { +- case EHCI_ATH79_IP_V1: +- ehci->has_synopsys_hc_bug = 1; +- +- ehci->caps = hcd->regs; +- ehci->regs = hcd->regs + +- HC_LENGTH(ehci, +- ehci_readl(ehci, &ehci->caps->hc_capbase)); +- break; +- +- case EHCI_ATH79_IP_V2: +- hcd->has_tt = 1; +- +- ehci->caps = hcd->regs + 0x100; +- ehci->regs = hcd->regs + 0x100 + +- HC_LENGTH(ehci, +- ehci_readl(ehci, &ehci->caps->hc_capbase)); +- break; +- +- default: +- BUG(); +- } +- +- dbg_hcs_params(ehci, "reset"); +- dbg_hcc_params(ehci, "reset"); +- ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); +- ehci->sbrn = 0x20; +- +- ehci_reset(ehci); +- +- ret = ehci_init(hcd); +- if (ret) +- return ret; +- +- ehci_port_power(ehci, 0); +- +- return 0; +-} +- +-static const struct hc_driver ehci_ath79_hc_driver = { +- .description = hcd_name, +- .product_desc = "Atheros built-in EHCI controller", +- .hcd_priv_size = sizeof(struct ehci_hcd), +- .irq = ehci_irq, +- .flags = HCD_MEMORY | HCD_USB2, +- +- .reset = ehci_ath79_init, +- .start = ehci_run, +- .stop = ehci_stop, +- .shutdown = ehci_shutdown, +- +- .urb_enqueue = ehci_urb_enqueue, +- .urb_dequeue = ehci_urb_dequeue, +- .endpoint_disable = ehci_endpoint_disable, +- .endpoint_reset = ehci_endpoint_reset, +- +- .get_frame_number = ehci_get_frame, +- +- .hub_status_data = ehci_hub_status_data, +- .hub_control = ehci_hub_control, +- +- .relinquish_port = ehci_relinquish_port, +- .port_handed_over = ehci_port_handed_over, +- +- .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +-}; +- +-static int ehci_ath79_probe(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd; +- struct resource *res; +- int irq; +- int ret; +- +- if (usb_disabled()) +- return -ENODEV; +- +- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no IRQ specified\n"); +- return -ENODEV; +- } +- irq = res->start; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no base address specified\n"); +- return -ENODEV; +- } +- +- hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev, +- dev_name(&pdev->dev)); +- if (!hcd) +- return -ENOMEM; +- +- hcd->rsrc_start = res->start; +- hcd->rsrc_len = resource_size(res); +- +- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { +- dev_dbg(&pdev->dev, "controller already in use\n"); +- ret = -EBUSY; +- goto err_put_hcd; +- } +- +- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); +- if (!hcd->regs) { +- dev_dbg(&pdev->dev, "error mapping memory\n"); +- ret = -EFAULT; +- goto err_release_region; +- } +- +- ret = usb_add_hcd(hcd, irq, IRQF_SHARED); +- if (ret) +- goto err_iounmap; +- +- return 0; +- +-err_iounmap: +- iounmap(hcd->regs); +- +-err_release_region: +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +-err_put_hcd: +- usb_put_hcd(hcd); +- return ret; +-} +- +-static int ehci_ath79_remove(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd = platform_get_drvdata(pdev); +- +- usb_remove_hcd(hcd); +- iounmap(hcd->regs); +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +- usb_put_hcd(hcd); +- +- return 0; +-} +- +-static struct platform_driver ehci_ath79_driver = { +- .probe = ehci_ath79_probe, +- .remove = ehci_ath79_remove, +- .id_table = ehci_ath79_id_table, +- .driver = { +- .owner = THIS_MODULE, +- .name = "ath79-ehci", +- } +-}; +- +-MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci"); +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1356,11 +1356,6 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER s5p_ehci_driver + #endif + +-#ifdef CONFIG_USB_EHCI_ATH79 +-#include "ehci-ath79.c" +-#define PLATFORM_DRIVER ehci_ath79_driver +-#endif +- + #ifdef CONFIG_SPARC_LEON + #include "ehci-grlib.c" + #define PLATFORM_DRIVER ehci_grlib_driver +--- a/drivers/usb/host/ohci-ath79.c ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * OHCI HCD (Host Controller Driver) for USB. +- * +- * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller. +- * +- * Copyright (C) 2008-2011 Gabor Juhos +- * Copyright (C) 2008 Imre Kaloz +- * +- * Parts of this file are based on Atheros' 2.6.15 BSP +- * Copyright (C) 2007 Atheros Communications, Inc. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include +- +-static int __devinit ohci_ath79_start(struct usb_hcd *hcd) +-{ +- struct ohci_hcd *ohci = hcd_to_ohci(hcd); +- int ret; +- +- ret = ohci_init(ohci); +- if (ret < 0) +- return ret; +- +- ret = ohci_run(ohci); +- if (ret < 0) +- goto err; +- +- return 0; +- +-err: +- ohci_stop(hcd); +- return ret; +-} +- +-static const struct hc_driver ohci_ath79_hc_driver = { +- .description = hcd_name, +- .product_desc = "Atheros built-in OHCI controller", +- .hcd_priv_size = sizeof(struct ohci_hcd), +- +- .irq = ohci_irq, +- .flags = HCD_USB11 | HCD_MEMORY, +- +- .start = ohci_ath79_start, +- .stop = ohci_stop, +- .shutdown = ohci_shutdown, +- +- .urb_enqueue = ohci_urb_enqueue, +- .urb_dequeue = ohci_urb_dequeue, +- .endpoint_disable = ohci_endpoint_disable, +- +- /* +- * scheduling support +- */ +- .get_frame_number = ohci_get_frame, +- +- /* +- * root hub support +- */ +- .hub_status_data = ohci_hub_status_data, +- .hub_control = ohci_hub_control, +- .start_port_reset = ohci_start_port_reset, +-}; +- +-static int ohci_ath79_probe(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd; +- struct resource *res; +- int irq; +- int ret; +- +- if (usb_disabled()) +- return -ENODEV; +- +- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no IRQ specified\n"); +- return -ENODEV; +- } +- irq = res->start; +- +- hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev, +- dev_name(&pdev->dev)); +- if (!hcd) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) { +- dev_dbg(&pdev->dev, "no base address specified\n"); +- ret = -ENODEV; +- goto err_put_hcd; +- } +- hcd->rsrc_start = res->start; +- hcd->rsrc_len = resource_size(res); +- +- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { +- dev_dbg(&pdev->dev, "controller already in use\n"); +- ret = -EBUSY; +- goto err_put_hcd; +- } +- +- hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); +- if (!hcd->regs) { +- dev_dbg(&pdev->dev, "error mapping memory\n"); +- ret = -EFAULT; +- goto err_release_region; +- } +- +- ohci_hcd_init(hcd_to_ohci(hcd)); +- +- ret = usb_add_hcd(hcd, irq, 0); +- if (ret) +- goto err_stop_hcd; +- +- return 0; +- +-err_stop_hcd: +- iounmap(hcd->regs); +-err_release_region: +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +-err_put_hcd: +- usb_put_hcd(hcd); +- return ret; +-} +- +-static int ohci_ath79_remove(struct platform_device *pdev) +-{ +- struct usb_hcd *hcd = platform_get_drvdata(pdev); +- +- usb_remove_hcd(hcd); +- iounmap(hcd->regs); +- release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +- usb_put_hcd(hcd); +- +- return 0; +-} +- +-static struct platform_driver ohci_hcd_ath79_driver = { +- .probe = ohci_ath79_probe, +- .remove = ohci_ath79_remove, +- .shutdown = usb_hcd_platform_shutdown, +- .driver = { +- .name = "ath79-ohci", +- .owner = THIS_MODULE, +- }, +-}; +- +-MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci"); +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1111,11 +1111,6 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver + #endif + +-#ifdef CONFIG_USB_OHCI_ATH79 +-#include "ohci-ath79.c" +-#define PLATFORM_DRIVER ohci_hcd_ath79_driver +-#endif +- + #ifdef CONFIG_CPU_XLR + #include "ohci-xls.c" + #define PLATFORM_DRIVER ohci_xls_driver diff --git a/target/linux/ar71xx/patches-3.3/003-MIPS-ath79-fix-AR933X-WMAC-reset-code.patch b/target/linux/ar71xx/patches-3.3/003-MIPS-ath79-fix-AR933X-WMAC-reset-code.patch new file mode 100644 index 0000000000..e5807c71f4 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/003-MIPS-ath79-fix-AR933X-WMAC-reset-code.patch @@ -0,0 +1,31 @@ +From 51233d66e030239f99755b2983753eff9b748365 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:28:35 +0100 +Subject: [PATCH 04/47] MIPS: ath79: fix AR933X WMAC reset code + +The current code puts the built-in WMAC device of the +AR933X SoCs into reset instead of starting it. This +causes a hard lock on AR933X based boards when the +wireless driver tries to access the device. + +Signed-off-by: Gabor Juhos +Cc: stable@vger.kernel.org +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3484/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/dev-wmac.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(voi + + static int ar933x_wmac_reset(void) + { +- ath79_device_reset_clear(AR933X_RESET_WMAC); + ath79_device_reset_set(AR933X_RESET_WMAC); ++ ath79_device_reset_clear(AR933X_RESET_WMAC); + + return 0; + } diff --git a/target/linux/ar71xx/patches-3.3/100-MIPS-ath79-separate-common-PCI-code.patch b/target/linux/ar71xx/patches-3.3/100-MIPS-ath79-separate-common-PCI-code.patch new file mode 100644 index 0000000000..6062c894fb --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/100-MIPS-ath79-separate-common-PCI-code.patch @@ -0,0 +1,150 @@ +From 9d9c0d49315520754660c8df3f42d93ecf7dba7a Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:21 +0100 +Subject: [PATCH 05/47] MIPS: ath79: separate common PCI code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The 'pcibios_map_irq' and 'pcibios_plat_dev_init' +are common functions and only instance one of them +can be present in a single kernel. + +Currently these functions can be built only if the +CONFIG_SOC_AR724X option is selected. However the +ath79 platform contain support for the AR71XX SoCs,. +The AR71XX SoCs have a differnet PCI controller, +and those will require a different code. + +Move the common PCI code into a separeate file in +order to be able to use that with other SoCs as +well. + +Signed-off-by: Gabor Juhos +Acked-by: René Bolldorf +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3485/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Makefile | 1 + + arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++ + arch/mips/pci/pci-ath724x.c | 34 ------------------------------- + 3 files changed, 47 insertions(+), 34 deletions(-) + create mode 100644 arch/mips/ath79/pci.c + +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -11,6 +11,7 @@ + obj-y := prom.o setup.o irq.o common.o clock.o gpio.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++obj-$(CONFIG_PCI) += pci.o + + # + # Devices +--- /dev/null ++++ b/arch/mips/ath79/pci.c +@@ -0,0 +1,46 @@ ++/* ++ * Atheros AR71XX/AR724X specific PCI setup code ++ * ++ * Copyright (C) 2011 René Bolldorf ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++static struct ath724x_pci_data *pci_data; ++static int pci_data_size; ++ ++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) ++{ ++ pci_data = data; ++ pci_data_size = size; ++} ++ ++int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) ++{ ++ unsigned int devfn = dev->devfn; ++ int irq = -1; ++ ++ if (devfn > pci_data_size - 1) ++ return irq; ++ ++ irq = pci_data[devfn].irq; ++ ++ return irq; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ unsigned int devfn = dev->devfn; ++ ++ if (devfn > pci_data_size - 1) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ dev->dev.platform_data = pci_data[devfn].pdata; ++ ++ return PCIBIOS_SUCCESSFUL; ++} +--- a/arch/mips/pci/pci-ath724x.c ++++ b/arch/mips/pci/pci-ath724x.c +@@ -9,7 +9,6 @@ + */ + + #include +-#include + + #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) + #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +@@ -19,8 +18,6 @@ + #define ATH724X_PCI_MEM_SIZE 0x08000000 + + static DEFINE_SPINLOCK(ath724x_pci_lock); +-static struct ath724x_pci_data *pci_data; +-static int pci_data_size; + + static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) +@@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci + .mem_resource = &ath724x_mem_resource, + }; + +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) +-{ +- pci_data = data; +- pci_data_size = size; +-} +- +-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) +-{ +- unsigned int devfn = dev->devfn; +- int irq = -1; +- +- if (devfn > pci_data_size - 1) +- return irq; +- +- irq = pci_data[devfn].irq; +- +- return irq; +-} +- +-int pcibios_plat_dev_init(struct pci_dev *dev) +-{ +- unsigned int devfn = dev->devfn; +- +- if (devfn > pci_data_size - 1) +- return PCIBIOS_DEVICE_NOT_FOUND; +- +- dev->dev.platform_data = pci_data[devfn].pdata; +- +- return PCIBIOS_SUCCESSFUL; +-} +- + static int __init ath724x_pcibios_init(void) + { + register_pci_controller(&ath724x_pci_controller); diff --git a/target/linux/ar71xx/patches-3.3/101-MIPS-ath79-rename-pci-ath724x.h.patch b/target/linux/ar71xx/patches-3.3/101-MIPS-ath79-rename-pci-ath724x.h.patch new file mode 100644 index 0000000000..f28f20cb23 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/101-MIPS-ath79-rename-pci-ath724x.h.patch @@ -0,0 +1,102 @@ +From 293dcf4142717d8059540bd69d1517c442617569 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:22 +0100 +Subject: [PATCH 06/47] MIPS: ath79: rename pci-ath724x.h +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The declared function in this header file is used by the +ath79 platform code only. Move the header to the platform +directory. + +Signed-off-by: Gabor Juhos +Acked-by: René Bolldorf +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3486/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 2 +- + arch/mips/ath79/pci.c | 2 +- + arch/mips/ath79/pci.h | 21 +++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 --------------------- + 4 files changed, 23 insertions(+), 23 deletions(-) + create mode 100644 arch/mips/ath79/pci.h + delete mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -15,13 +15,13 @@ + + #ifdef CONFIG_PCI + #include +-#include + #endif /* CONFIG_PCI */ + + #include "machtypes.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" ++#include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 + #define UBNT_XM_GPIO_LED_L2 1 +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -9,7 +9,7 @@ + */ + + #include +-#include ++#include "pci.h" + + static struct ath724x_pci_data *pci_data; + static int pci_data_size; +--- /dev/null ++++ b/arch/mips/ath79/pci.h +@@ -0,0 +1,21 @@ ++/* ++ * Atheros 724x PCI support ++ * ++ * Copyright (C) 2011 René Bolldorf ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H ++#define __ASM_MACH_ATH79_PCI_ATH724X_H ++ ++struct ath724x_pci_data { ++ int irq; ++ void *pdata; ++}; ++ ++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); ++ ++#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ +--- a/arch/mips/include/asm/mach-ath79/pci-ath724x.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-/* +- * Atheros 724x PCI support +- * +- * Copyright (C) 2011 René Bolldorf +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H +-#define __ASM_MACH_ATH79_PCI_ATH724X_H +- +-struct ath724x_pci_data { +- int irq; +- void *pdata; +-}; +- +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); +- +-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ diff --git a/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch b/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch new file mode 100644 index 0000000000..9696a75228 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch @@ -0,0 +1,61 @@ +From a9e38566ebe755219db10fa155fa8f0f4efc20d9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:23 +0100 +Subject: [PATCH 07/47] MIPS: ath79: make ath724x_pcibios_init visible for external code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: René Bolldorf +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3487/ +Signed-off-by: Ralf Baechle +--- + arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++ + arch/mips/pci/pci-ath724x.c | 3 ++- + 2 files changed, 22 insertions(+), 1 deletions(-) + create mode 100644 arch/mips/include/asm/mach-ath79/pci.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -0,0 +1,20 @@ ++/* ++ * Atheros 724x PCI support ++ * ++ * Copyright (C) 2011 René Bolldorf ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_PCI_H ++#define __ASM_MACH_ATH79_PCI_H ++ ++#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) ++int ath724x_pcibios_init(void); ++#else ++static inline int ath724x_pcibios_init(void) { return 0; } ++#endif ++ ++#endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ath724x.c ++++ b/arch/mips/pci/pci-ath724x.c +@@ -9,6 +9,7 @@ + */ + + #include ++#include + + #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) + #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +@@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci + .mem_resource = &ath724x_mem_resource, + }; + +-static int __init ath724x_pcibios_init(void) ++int __init ath724x_pcibios_init(void) + { + register_pci_controller(&ath724x_pci_controller); + diff --git a/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-separate-common-PCI-code.patch b/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-separate-common-PCI-code.patch deleted file mode 100644 index 547f4fbd27..0000000000 --- a/target/linux/ar71xx/patches-3.3/102-MIPS-ath79-separate-common-PCI-code.patch +++ /dev/null @@ -1,151 +0,0 @@ -From c98b48027516a2e71688a5957e4e0120f4aa8c61 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 09:47:44 +0100 -Subject: [PATCH 02/35] MIPS: ath79: separate common PCI code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The 'pcibios_map_irq' and 'pcibios_plat_dev_init' -are common functions and only instance one of them -can be present in a single kernel. - -Currently these functions can be built only if the -CONFIG_SOC_AR724X option is selected. However the -ath79 platform contain support for the AR71XX SoCs,. -The AR71XX SoCs have a differnet PCI controller, -and those will require a different code. - -Move the common PCI code into a separeate file in -order to be able to use that with other SoCs as -well. - -Signed-off-by: Gabor Juhos -Acked-by: René Bolldorf - -v4: - add an Acked-by tag from René -v3: - no changes -v2: - no changes ---- - arch/mips/ath79/Makefile | 1 + - arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++ - arch/mips/pci/pci-ath724x.c | 34 ------------------------------- - 3 files changed, 47 insertions(+), 34 deletions(-) - create mode 100644 arch/mips/ath79/pci.c - ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -11,6 +11,7 @@ - obj-y := prom.o setup.o irq.o common.o clock.o gpio.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_PCI) += pci.o - - # - # Devices ---- /dev/null -+++ b/arch/mips/ath79/pci.c -@@ -0,0 +1,46 @@ -+/* -+ * Atheros AR71XX/AR724X specific PCI setup code -+ * -+ * Copyright (C) 2011 René Bolldorf -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+static struct ath724x_pci_data *pci_data; -+static int pci_data_size; -+ -+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) -+{ -+ pci_data = data; -+ pci_data_size = size; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -+{ -+ unsigned int devfn = dev->devfn; -+ int irq = -1; -+ -+ if (devfn > pci_data_size - 1) -+ return irq; -+ -+ irq = pci_data[devfn].irq; -+ -+ return irq; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ unsigned int devfn = dev->devfn; -+ -+ if (devfn > pci_data_size - 1) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ dev->dev.platform_data = pci_data[devfn].pdata; -+ -+ return PCIBIOS_SUCCESSFUL; -+} ---- a/arch/mips/pci/pci-ath724x.c -+++ b/arch/mips/pci/pci-ath724x.c -@@ -9,7 +9,6 @@ - */ - - #include --#include - - #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) - #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) -@@ -19,8 +18,6 @@ - #define ATH724X_PCI_MEM_SIZE 0x08000000 - - static DEFINE_SPINLOCK(ath724x_pci_lock); --static struct ath724x_pci_data *pci_data; --static int pci_data_size; - - static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t *value) -@@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci - .mem_resource = &ath724x_mem_resource, - }; - --void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) --{ -- pci_data = data; -- pci_data_size = size; --} -- --int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) --{ -- unsigned int devfn = dev->devfn; -- int irq = -1; -- -- if (devfn > pci_data_size - 1) -- return irq; -- -- irq = pci_data[devfn].irq; -- -- return irq; --} -- --int pcibios_plat_dev_init(struct pci_dev *dev) --{ -- unsigned int devfn = dev->devfn; -- -- if (devfn > pci_data_size - 1) -- return PCIBIOS_DEVICE_NOT_FOUND; -- -- dev->dev.platform_data = pci_data[devfn].pdata; -- -- return PCIBIOS_SUCCESSFUL; --} -- - static int __init ath724x_pcibios_init(void) - { - register_pci_controller(&ath724x_pci_controller); diff --git a/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-add-a-common-PCI-registration-function.patch b/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-add-a-common-PCI-registration-function.patch new file mode 100644 index 0000000000..34587b63a1 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-add-a-common-PCI-registration-function.patch @@ -0,0 +1,78 @@ +From e3edaac2e967f07ae3b726e64e1c290233361bc7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:24 +0100 +Subject: [PATCH 08/47] MIPS: ath79: add a common PCI registration function + +The current code unconditionally registers the AR724X +specific PCI controller, even if the kernel is running +on a different SoC. + +Add a common function for PCI controller registration, +and only register the AR724X PCI controller if the kernel +is running on an AR724X SoC. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3488/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 1 + + arch/mips/ath79/pci.c | 10 ++++++++++ + arch/mips/ath79/pci.h | 6 ++++++ + arch/mips/pci/pci-ath724x.c | 2 -- + 4 files changed, 17 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void) + ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + #endif /* CONFIG_PCI */ + ++ ath79_register_pci(); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -9,6 +9,8 @@ + */ + + #include ++#include ++#include + #include "pci.h" + + static struct ath724x_pci_data *pci_data; +@@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev + + return PCIBIOS_SUCCESSFUL; + } ++ ++int __init ath79_register_pci(void) ++{ ++ if (soc_is_ar724x()) ++ return ath724x_pcibios_init(); ++ ++ return -ENODEV; ++} +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -18,4 +18,10 @@ struct ath724x_pci_data { + + void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); + ++#ifdef CONFIG_PCI ++int ath79_register_pci(void); ++#else ++static inline int ath79_register_pci(void) { return 0; } ++#endif ++ + #endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ +--- a/arch/mips/pci/pci-ath724x.c ++++ b/arch/mips/pci/pci-ath724x.c +@@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void) + + return PCIBIOS_SUCCESSFUL; + } +- +-arch_initcall(ath724x_pcibios_init); diff --git a/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-rename-pci-ath724x.h.patch b/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-rename-pci-ath724x.h.patch deleted file mode 100644 index a5c25b19ba..0000000000 --- a/target/linux/ar71xx/patches-3.3/103-MIPS-ath79-rename-pci-ath724x.h.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 204fd70abd99099f6c2e2213a2baa1d51c03a039 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 09:50:50 +0100 -Subject: [PATCH 03/35] MIPS: ath79: rename pci-ath724x.h -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The declared function in this header file is used by the -ath79 platform code only. Move the header to the platform -directory. - -Signed-off-by: Gabor Juhos -Acked-by: René Bolldorf - -v4: - add an Acked-by tag from René -v3: - move include "pci.h" out of the #ifdef CONFIG_PCI section -v2: - no changes ---- - arch/mips/ath79/mach-ubnt-xm.c | 2 +- - arch/mips/ath79/pci.c | 2 +- - arch/mips/ath79/pci.h | 21 +++++++++++++++++++++ - arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 --------------------- - 4 files changed, 23 insertions(+), 23 deletions(-) - create mode 100644 arch/mips/ath79/pci.h - delete mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -15,13 +15,13 @@ - - #ifdef CONFIG_PCI - #include --#include - #endif /* CONFIG_PCI */ - - #include "machtypes.h" - #include "dev-gpio-buttons.h" - #include "dev-leds-gpio.h" - #include "dev-spi.h" -+#include "pci.h" - - #define UBNT_XM_GPIO_LED_L1 0 - #define UBNT_XM_GPIO_LED_L2 1 ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -9,7 +9,7 @@ - */ - - #include --#include -+#include "pci.h" - - static struct ath724x_pci_data *pci_data; - static int pci_data_size; ---- /dev/null -+++ b/arch/mips/ath79/pci.h -@@ -0,0 +1,21 @@ -+/* -+ * Atheros 724x PCI support -+ * -+ * Copyright (C) 2011 René Bolldorf -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H -+#define __ASM_MACH_ATH79_PCI_ATH724X_H -+ -+struct ath724x_pci_data { -+ int irq; -+ void *pdata; -+}; -+ -+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); -+ -+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ ---- a/arch/mips/include/asm/mach-ath79/pci-ath724x.h -+++ /dev/null -@@ -1,21 +0,0 @@ --/* -- * Atheros 724x PCI support -- * -- * Copyright (C) 2011 René Bolldorf -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H --#define __ASM_MACH_ATH79_PCI_ATH724X_H -- --struct ath724x_pci_data { -- int irq; -- void *pdata; --}; -- --void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); -- --#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ diff --git a/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch b/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch deleted file mode 100644 index 42fa5c8a42..0000000000 --- a/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-make-ath724x_pcibios_init-visible-for-ext.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 7e59b95e3424c078de0d75d699433da0dd289fc1 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 10:13:37 +0100 -Subject: [PATCH 04/35] MIPS: ath79: make ath724x_pcibios_init visible for external code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: René Bolldorf -Signed-off-by: Gabor Juhos - -v4: - add a sob tag -v3: - no changes -v2: - fix a typo in my e-mail address ---- - arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++ - arch/mips/pci/pci-ath724x.c | 3 ++- - 2 files changed, 22 insertions(+), 1 deletions(-) - create mode 100644 arch/mips/include/asm/mach-ath79/pci.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -0,0 +1,20 @@ -+/* -+ * Atheros 724x PCI support -+ * -+ * Copyright (C) 2011 René Bolldorf -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_ATH79_PCI_H -+#define __ASM_MACH_ATH79_PCI_H -+ -+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) -+int ath724x_pcibios_init(void); -+#else -+static inline int ath724x_pcibios_init(void) { return 0 }; -+#endif -+ -+#endif /* __ASM_MACH_ATH79_PCI_H */ ---- a/arch/mips/pci/pci-ath724x.c -+++ b/arch/mips/pci/pci-ath724x.c -@@ -9,6 +9,7 @@ - */ - - #include -+#include - - #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) - #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) -@@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci - .mem_resource = &ath724x_mem_resource, - }; - --static int __init ath724x_pcibios_init(void) -+int __init ath724x_pcibios_init(void) - { - register_pci_controller(&ath724x_pci_controller); - diff --git a/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch b/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch new file mode 100644 index 0000000000..e7189289cc --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch @@ -0,0 +1,316 @@ +From 36dfdaa097ee1b12139187dc89cfa23fbb92b53b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:25 +0100 +Subject: [PATCH 09/47] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Gabor Juhos +Acked-by: René Bolldorf +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3489/ +Signed-off-by: Ralf Baechle +--- + arch/mips/pci/Makefile | 2 +- + arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++ + arch/mips/pci/pci-ath724x.c | 139 ------------------------------------------- + 3 files changed, 140 insertions(+), 140 deletions(-) + create mode 100644 arch/mips/pci/pci-ar724x.c + delete mode 100644 arch/mips/pci/pci-ath724x.c + +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o +-obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o ++obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o + + # + # These are still pretty much in the old state, watch, go blind. +--- /dev/null ++++ b/arch/mips/pci/pci-ar724x.c +@@ -0,0 +1,139 @@ ++/* ++ * Atheros 724x PCI support ++ * ++ * Copyright (C) 2011 René Bolldorf ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) ++#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) ++ ++#define ATH724X_PCI_DEV_BASE 0x14000000 ++#define ATH724X_PCI_MEM_BASE 0x10000000 ++#define ATH724X_PCI_MEM_SIZE 0x08000000 ++ ++static DEFINE_SPINLOCK(ath724x_pci_lock); ++ ++static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, uint32_t *value) ++{ ++ unsigned long flags, addr, tval, mask; ++ ++ if (devfn) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ if (where & (size - 1)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ spin_lock_irqsave(&ath724x_pci_lock, flags); ++ ++ switch (size) { ++ case 1: ++ addr = where & ~3; ++ mask = 0xff000000 >> ((where % 4) * 8); ++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = tval & ~mask; ++ *value = (tval >> ((4 - (where % 4))*8)); ++ break; ++ case 2: ++ addr = where & ~3; ++ mask = 0xffff0000 >> ((where % 4)*8); ++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = tval & ~mask; ++ *value = (tval >> ((4 - (where % 4))*8)); ++ break; ++ case 4: ++ *value = reg_read(ATH724X_PCI_DEV_BASE + where); ++ break; ++ default: ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, uint32_t value) ++{ ++ unsigned long flags, tval, addr, mask; ++ ++ if (devfn) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ if (where & (size - 1)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ spin_lock_irqsave(&ath724x_pci_lock, flags); ++ ++ switch (size) { ++ case 1: ++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ mask = 0xff000000 >> ((where % 4)*8); ++ tval = reg_read(addr); ++ tval = tval & ~mask; ++ tval |= (value << ((4 - (where % 4))*8)) & mask; ++ reg_write(addr, tval); ++ break; ++ case 2: ++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ mask = 0xffff0000 >> ((where % 4)*8); ++ tval = reg_read(addr); ++ tval = tval & ~mask; ++ tval |= (value << ((4 - (where % 4))*8)) & mask; ++ reg_write(addr, tval); ++ break; ++ case 4: ++ reg_write((ATH724X_PCI_DEV_BASE + where), value); ++ break; ++ default: ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static struct pci_ops ath724x_pci_ops = { ++ .read = ath724x_pci_read, ++ .write = ath724x_pci_write, ++}; ++ ++static struct resource ath724x_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ath724x_mem_resource = { ++ .name = "PCI memory space", ++ .start = ATH724X_PCI_MEM_BASE, ++ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_controller ath724x_pci_controller = { ++ .pci_ops = &ath724x_pci_ops, ++ .io_resource = &ath724x_io_resource, ++ .mem_resource = &ath724x_mem_resource, ++}; ++ ++int __init ath724x_pcibios_init(void) ++{ ++ register_pci_controller(&ath724x_pci_controller); ++ ++ return PCIBIOS_SUCCESSFUL; ++} +--- a/arch/mips/pci/pci-ath724x.c ++++ /dev/null +@@ -1,139 +0,0 @@ +-/* +- * Atheros 724x PCI support +- * +- * Copyright (C) 2011 René Bolldorf +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- */ +- +-#include +-#include +- +-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) +-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +- +-#define ATH724X_PCI_DEV_BASE 0x14000000 +-#define ATH724X_PCI_MEM_BASE 0x10000000 +-#define ATH724X_PCI_MEM_SIZE 0x08000000 +- +-static DEFINE_SPINLOCK(ath724x_pci_lock); +- +-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, +- int size, uint32_t *value) +-{ +- unsigned long flags, addr, tval, mask; +- +- if (devfn) +- return PCIBIOS_DEVICE_NOT_FOUND; +- +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- +- spin_lock_irqsave(&ath724x_pci_lock, flags); +- +- switch (size) { +- case 1: +- addr = where & ~3; +- mask = 0xff000000 >> ((where % 4) * 8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); +- break; +- case 2: +- addr = where & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); +- break; +- case 4: +- *value = reg_read(ATH724X_PCI_DEV_BASE + where); +- break; +- default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_BAD_REGISTER_NUMBER; +- } +- +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_SUCCESSFUL; +-} +- +-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, +- int size, uint32_t value) +-{ +- unsigned long flags, tval, addr, mask; +- +- if (devfn) +- return PCIBIOS_DEVICE_NOT_FOUND; +- +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- +- spin_lock_irqsave(&ath724x_pci_lock, flags); +- +- switch (size) { +- case 1: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; +- mask = 0xff000000 >> ((where % 4)*8); +- tval = reg_read(addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); +- break; +- case 2: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); +- break; +- case 4: +- reg_write((ATH724X_PCI_DEV_BASE + where), value); +- break; +- default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_BAD_REGISTER_NUMBER; +- } +- +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); +- +- return PCIBIOS_SUCCESSFUL; +-} +- +-static struct pci_ops ath724x_pci_ops = { +- .read = ath724x_pci_read, +- .write = ath724x_pci_write, +-}; +- +-static struct resource ath724x_io_resource = { +- .name = "PCI IO space", +- .start = 0, +- .end = 0, +- .flags = IORESOURCE_IO, +-}; +- +-static struct resource ath724x_mem_resource = { +- .name = "PCI memory space", +- .start = ATH724X_PCI_MEM_BASE, +- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-static struct pci_controller ath724x_pci_controller = { +- .pci_ops = &ath724x_pci_ops, +- .io_resource = &ath724x_io_resource, +- .mem_resource = &ath724x_mem_resource, +-}; +- +-int __init ath724x_pcibios_init(void) +-{ +- register_pci_controller(&ath724x_pci_controller); +- +- return PCIBIOS_SUCCESSFUL; +-} diff --git a/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-add-a-common-PCI-registration-function.patch b/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-add-a-common-PCI-registration-function.patch deleted file mode 100644 index 1b52f25e5e..0000000000 --- a/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-add-a-common-PCI-registration-function.patch +++ /dev/null @@ -1,80 +0,0 @@ -From fbf38a9b03d0c47ed602f090ebb2d8ecc0d51d04 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 10:25:26 +0100 -Subject: [PATCH 05/35] MIPS: ath79: add a common PCI registration function - -The current code unconditionally registers the AR724X -specific PCI controller, even if the kernel is running -on a different SoC. - -Add a common function for PCI controller registration, -and only register the AR724X PCI controller if the kernel -is running on an AR724X SoC. - -Signed-off-by: Gabor Juhos - -v4: - simplify ath79_register_pci function -v3: - fix compile error if CONFIG_PCI is not defined - - add __init annotation to ath79_register_pci -v2: - no changes ---- - arch/mips/ath79/mach-ubnt-xm.c | 1 + - arch/mips/ath79/pci.c | 10 ++++++++++ - arch/mips/ath79/pci.h | 6 ++++++ - arch/mips/pci/pci-ath724x.c | 2 -- - 4 files changed, 17 insertions(+), 2 deletions(-) - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void) - ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); - #endif /* CONFIG_PCI */ - -+ ath79_register_pci(); - } - - MIPS_MACHINE(ATH79_MACH_UBNT_XM, ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -9,6 +9,8 @@ - */ - - #include -+#include -+#include - #include "pci.h" - - static struct ath724x_pci_data *pci_data; -@@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev - - return PCIBIOS_SUCCESSFUL; - } -+ -+int __init ath79_register_pci(void) -+{ -+ if (soc_is_ar724x()) -+ return ath724x_pcibios_init(); -+ -+ return -ENODEV; -+} ---- a/arch/mips/ath79/pci.h -+++ b/arch/mips/ath79/pci.h -@@ -18,4 +18,10 @@ struct ath724x_pci_data { - - void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); - -+#ifdef CONFIG_PCI -+int ath79_register_pci(void); -+#else -+static inline int ath79_register_pci(void) { return 0; } -+#endif -+ - #endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ ---- a/arch/mips/pci/pci-ath724x.c -+++ b/arch/mips/pci/pci-ath724x.c -@@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void) - - return PCIBIOS_SUCCESSFUL; - } -- --arch_initcall(ath724x_pcibios_init); diff --git a/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-replace-ath724x-to-ar724x.patch b/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-replace-ath724x-to-ar724x.patch new file mode 100644 index 0000000000..0a224ed54d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/105-MIPS-ath79-replace-ath724x-to-ar724x.patch @@ -0,0 +1,264 @@ +From 9f0c37b1d071355d4c027958f370823c8f891480 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:26 +0100 +Subject: [PATCH 10/47] MIPS: ath79: replace ath724x to ar724x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace the 'ath724x' to 'ar724x' in function, variable and +structure names to reflect the name of the real SoC. + +Signed-off-by: Gabor Juhos +Acked-by: René Bolldorf +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3490/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 4 +- + arch/mips/ath79/pci.c | 6 ++-- + arch/mips/ath79/pci.h | 10 +++--- + arch/mips/include/asm/mach-ath79/pci.h | 4 +- + arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++---------------- + 5 files changed, 43 insertions(+), 43 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub + #ifdef CONFIG_PCI + static struct ath9k_platform_data ubnt_xm_eeprom_data; + +-static struct ath724x_pci_data ubnt_xm_pci_data[] = { ++static struct ar724x_pci_data ubnt_xm_pci_data[] = { + { + .irq = UBNT_XM_PCI_IRQ, + .pdata = &ubnt_xm_eeprom_data, +@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void) + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + +- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ++ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + #endif /* CONFIG_PCI */ + + ath79_register_pci(); +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -13,10 +13,10 @@ + #include + #include "pci.h" + +-static struct ath724x_pci_data *pci_data; ++static struct ar724x_pci_data *pci_data; + static int pci_data_size; + +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) ++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) + { + pci_data = data; + pci_data_size = size; +@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev + int __init ath79_register_pci(void) + { + if (soc_is_ar724x()) +- return ath724x_pcibios_init(); ++ return ar724x_pcibios_init(); + + return -ENODEV; + } +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -8,15 +8,15 @@ + * by the Free Software Foundation. + */ + +-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H +-#define __ASM_MACH_ATH79_PCI_ATH724X_H ++#ifndef _ATH79_PCI_H ++#define _ATH79_PCI_H + +-struct ath724x_pci_data { ++struct ar724x_pci_data { + int irq; + void *pdata; + }; + +-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); ++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); + + #ifdef CONFIG_PCI + int ath79_register_pci(void); +@@ -24,4 +24,4 @@ int ath79_register_pci(void); + static inline int ath79_register_pci(void) { return 0; } + #endif + +-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ ++#endif /* _ATH79_PCI_H */ +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -12,9 +12,9 @@ + #define __ASM_MACH_ATH79_PCI_H + + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) +-int ath724x_pcibios_init(void); ++int ar724x_pcibios_init(void); + #else +-static inline int ath724x_pcibios_init(void) { return 0; } ++static inline int ar724x_pcibios_init(void) { return 0; } + #endif + + #endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -14,13 +14,13 @@ + #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) + #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) + +-#define ATH724X_PCI_DEV_BASE 0x14000000 +-#define ATH724X_PCI_MEM_BASE 0x10000000 +-#define ATH724X_PCI_MEM_SIZE 0x08000000 ++#define AR724X_PCI_DEV_BASE 0x14000000 ++#define AR724X_PCI_MEM_BASE 0x10000000 ++#define AR724X_PCI_MEM_SIZE 0x08000000 + +-static DEFINE_SPINLOCK(ath724x_pci_lock); ++static DEFINE_SPINLOCK(ar724x_pci_lock); + +-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, ++static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { + unsigned long flags, addr, tval, mask; +@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + +- spin_lock_irqsave(&ath724x_pci_lock, flags); ++ spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: + addr = where & ~3; + mask = 0xff000000 >> ((where % 4) * 8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = reg_read(AR724X_PCI_DEV_BASE + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 2: + addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); ++ tval = reg_read(AR724X_PCI_DEV_BASE + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 4: +- *value = reg_read(ATH724X_PCI_DEV_BASE + where); ++ *value = reg_read(AR724X_PCI_DEV_BASE + where); + break; + default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; + } + +-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, ++static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t value) + { + unsigned long flags, tval, addr, mask; +@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_ + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + +- spin_lock_irqsave(&ath724x_pci_lock, flags); ++ spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ addr = (AR724X_PCI_DEV_BASE + where) & ~3; + mask = 0xff000000 >> ((where % 4)*8); + tval = reg_read(addr); + tval = tval & ~mask; +@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_ + reg_write(addr, tval); + break; + case 2: +- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; ++ addr = (AR724X_PCI_DEV_BASE + where) & ~3; + mask = 0xffff0000 >> ((where % 4)*8); + tval = reg_read(addr); + tval = tval & ~mask; +@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_ + reg_write(addr, tval); + break; + case 4: +- reg_write((ATH724X_PCI_DEV_BASE + where), value); ++ reg_write((AR724X_PCI_DEV_BASE + where), value); + break; + default: +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_BAD_REGISTER_NUMBER; + } + +- spin_unlock_irqrestore(&ath724x_pci_lock, flags); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; + } + +-static struct pci_ops ath724x_pci_ops = { +- .read = ath724x_pci_read, +- .write = ath724x_pci_write, ++static struct pci_ops ar724x_pci_ops = { ++ .read = ar724x_pci_read, ++ .write = ar724x_pci_write, + }; + +-static struct resource ath724x_io_resource = { ++static struct resource ar724x_io_resource = { + .name = "PCI IO space", + .start = 0, + .end = 0, + .flags = IORESOURCE_IO, + }; + +-static struct resource ath724x_mem_resource = { ++static struct resource ar724x_mem_resource = { + .name = "PCI memory space", +- .start = ATH724X_PCI_MEM_BASE, +- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, ++ .start = AR724X_PCI_MEM_BASE, ++ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }; + +-static struct pci_controller ath724x_pci_controller = { +- .pci_ops = &ath724x_pci_ops, +- .io_resource = &ath724x_io_resource, +- .mem_resource = &ath724x_mem_resource, ++static struct pci_controller ar724x_pci_controller = { ++ .pci_ops = &ar724x_pci_ops, ++ .io_resource = &ar724x_io_resource, ++ .mem_resource = &ar724x_mem_resource, + }; + +-int __init ath724x_pcibios_init(void) ++int __init ar724x_pcibios_init(void) + { +- register_pci_controller(&ath724x_pci_controller); ++ register_pci_controller(&ar724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; + } diff --git a/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch b/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch deleted file mode 100644 index 55adff0a70..0000000000 --- a/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch +++ /dev/null @@ -1,318 +0,0 @@ -From 9510a9988638ae2386277a832fab2df8ca37d75a Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 11:07:26 +0100 -Subject: [PATCH 06/35] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Gabor Juhos -Acked-by: René Bolldorf - -v4: - add an Acked-by tag from René -v4: - no changes -v3: - no changes -v2: - no changes ---- - arch/mips/pci/Makefile | 2 +- - arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++ - arch/mips/pci/pci-ath724x.c | 139 ------------------------------------------- - 3 files changed, 140 insertions(+), 140 deletions(-) - create mode 100644 arch/mips/pci/pci-ar724x.c - delete mode 100644 arch/mips/pci/pci-ath724x.c - ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o - obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o --obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o -+obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. ---- /dev/null -+++ b/arch/mips/pci/pci-ar724x.c -@@ -0,0 +1,139 @@ -+/* -+ * Atheros 724x PCI support -+ * -+ * Copyright (C) 2011 René Bolldorf -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) -+#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) -+ -+#define ATH724X_PCI_DEV_BASE 0x14000000 -+#define ATH724X_PCI_MEM_BASE 0x10000000 -+#define ATH724X_PCI_MEM_SIZE 0x08000000 -+ -+static DEFINE_SPINLOCK(ath724x_pci_lock); -+ -+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, -+ int size, uint32_t *value) -+{ -+ unsigned long flags, addr, tval, mask; -+ -+ if (devfn) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ if (where & (size - 1)) -+ return PCIBIOS_BAD_REGISTER_NUMBER; -+ -+ spin_lock_irqsave(&ath724x_pci_lock, flags); -+ -+ switch (size) { -+ case 1: -+ addr = where & ~3; -+ mask = 0xff000000 >> ((where % 4) * 8); -+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr); -+ tval = tval & ~mask; -+ *value = (tval >> ((4 - (where % 4))*8)); -+ break; -+ case 2: -+ addr = where & ~3; -+ mask = 0xffff0000 >> ((where % 4)*8); -+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr); -+ tval = tval & ~mask; -+ *value = (tval >> ((4 - (where % 4))*8)); -+ break; -+ case 4: -+ *value = reg_read(ATH724X_PCI_DEV_BASE + where); -+ break; -+ default: -+ spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ -+ return PCIBIOS_BAD_REGISTER_NUMBER; -+ } -+ -+ spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, -+ int size, uint32_t value) -+{ -+ unsigned long flags, tval, addr, mask; -+ -+ if (devfn) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ if (where & (size - 1)) -+ return PCIBIOS_BAD_REGISTER_NUMBER; -+ -+ spin_lock_irqsave(&ath724x_pci_lock, flags); -+ -+ switch (size) { -+ case 1: -+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3; -+ mask = 0xff000000 >> ((where % 4)*8); -+ tval = reg_read(addr); -+ tval = tval & ~mask; -+ tval |= (value << ((4 - (where % 4))*8)) & mask; -+ reg_write(addr, tval); -+ break; -+ case 2: -+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3; -+ mask = 0xffff0000 >> ((where % 4)*8); -+ tval = reg_read(addr); -+ tval = tval & ~mask; -+ tval |= (value << ((4 - (where % 4))*8)) & mask; -+ reg_write(addr, tval); -+ break; -+ case 4: -+ reg_write((ATH724X_PCI_DEV_BASE + where), value); -+ break; -+ default: -+ spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ -+ return PCIBIOS_BAD_REGISTER_NUMBER; -+ } -+ -+ spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static struct pci_ops ath724x_pci_ops = { -+ .read = ath724x_pci_read, -+ .write = ath724x_pci_write, -+}; -+ -+static struct resource ath724x_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ath724x_mem_resource = { -+ .name = "PCI memory space", -+ .start = ATH724X_PCI_MEM_BASE, -+ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct pci_controller ath724x_pci_controller = { -+ .pci_ops = &ath724x_pci_ops, -+ .io_resource = &ath724x_io_resource, -+ .mem_resource = &ath724x_mem_resource, -+}; -+ -+int __init ath724x_pcibios_init(void) -+{ -+ register_pci_controller(&ath724x_pci_controller); -+ -+ return PCIBIOS_SUCCESSFUL; -+} ---- a/arch/mips/pci/pci-ath724x.c -+++ /dev/null -@@ -1,139 +0,0 @@ --/* -- * Atheros 724x PCI support -- * -- * Copyright (C) 2011 René Bolldorf -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- */ -- --#include --#include -- --#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) --#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) -- --#define ATH724X_PCI_DEV_BASE 0x14000000 --#define ATH724X_PCI_MEM_BASE 0x10000000 --#define ATH724X_PCI_MEM_SIZE 0x08000000 -- --static DEFINE_SPINLOCK(ath724x_pci_lock); -- --static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, -- int size, uint32_t *value) --{ -- unsigned long flags, addr, tval, mask; -- -- if (devfn) -- return PCIBIOS_DEVICE_NOT_FOUND; -- -- if (where & (size - 1)) -- return PCIBIOS_BAD_REGISTER_NUMBER; -- -- spin_lock_irqsave(&ath724x_pci_lock, flags); -- -- switch (size) { -- case 1: -- addr = where & ~3; -- mask = 0xff000000 >> ((where % 4) * 8); -- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); -- tval = tval & ~mask; -- *value = (tval >> ((4 - (where % 4))*8)); -- break; -- case 2: -- addr = where & ~3; -- mask = 0xffff0000 >> ((where % 4)*8); -- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); -- tval = tval & ~mask; -- *value = (tval >> ((4 - (where % 4))*8)); -- break; -- case 4: -- *value = reg_read(ATH724X_PCI_DEV_BASE + where); -- break; -- default: -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -- -- return PCIBIOS_BAD_REGISTER_NUMBER; -- } -- -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -- -- return PCIBIOS_SUCCESSFUL; --} -- --static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, -- int size, uint32_t value) --{ -- unsigned long flags, tval, addr, mask; -- -- if (devfn) -- return PCIBIOS_DEVICE_NOT_FOUND; -- -- if (where & (size - 1)) -- return PCIBIOS_BAD_REGISTER_NUMBER; -- -- spin_lock_irqsave(&ath724x_pci_lock, flags); -- -- switch (size) { -- case 1: -- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; -- mask = 0xff000000 >> ((where % 4)*8); -- tval = reg_read(addr); -- tval = tval & ~mask; -- tval |= (value << ((4 - (where % 4))*8)) & mask; -- reg_write(addr, tval); -- break; -- case 2: -- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; -- mask = 0xffff0000 >> ((where % 4)*8); -- tval = reg_read(addr); -- tval = tval & ~mask; -- tval |= (value << ((4 - (where % 4))*8)) & mask; -- reg_write(addr, tval); -- break; -- case 4: -- reg_write((ATH724X_PCI_DEV_BASE + where), value); -- break; -- default: -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -- -- return PCIBIOS_BAD_REGISTER_NUMBER; -- } -- -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -- -- return PCIBIOS_SUCCESSFUL; --} -- --static struct pci_ops ath724x_pci_ops = { -- .read = ath724x_pci_read, -- .write = ath724x_pci_write, --}; -- --static struct resource ath724x_io_resource = { -- .name = "PCI IO space", -- .start = 0, -- .end = 0, -- .flags = IORESOURCE_IO, --}; -- --static struct resource ath724x_mem_resource = { -- .name = "PCI memory space", -- .start = ATH724X_PCI_MEM_BASE, -- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -- --static struct pci_controller ath724x_pci_controller = { -- .pci_ops = &ath724x_pci_ops, -- .io_resource = &ath724x_io_resource, -- .mem_resource = &ath724x_mem_resource, --}; -- --int __init ath724x_pcibios_init(void) --{ -- register_pci_controller(&ath724x_pci_controller); -- -- return PCIBIOS_SUCCESSFUL; --} diff --git a/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch b/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch new file mode 100644 index 0000000000..108ac10e43 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/106-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch @@ -0,0 +1,131 @@ +From 0f5728e7e6fa7f0969ec79bd623261d3d830e5e7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:29:27 +0100 +Subject: [PATCH 11/47] MIPS: ath79: use io-accessor macros in pci-ar724x.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Gabor Juhos +Acked-by: René Bolldorf +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3491/ +Signed-off-by: Ralf Baechle +--- + arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++-------------- + 1 files changed, 24 insertions(+), 14 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -11,19 +11,19 @@ + #include + #include + +-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) +-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) +- +-#define AR724X_PCI_DEV_BASE 0x14000000 ++#define AR724X_PCI_CFG_BASE 0x14000000 ++#define AR724X_PCI_CFG_SIZE 0x1000 + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + + static DEFINE_SPINLOCK(ar724x_pci_lock); ++static void __iomem *ar724x_pci_devcfg_base; + + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { + unsigned long flags, addr, tval, mask; ++ void __iomem *base; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + ++ base = ar724x_pci_devcfg_base; ++ + spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: + addr = where & ~3; + mask = 0xff000000 >> ((where % 4) * 8); +- tval = reg_read(AR724X_PCI_DEV_BASE + addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 2: + addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(AR724X_PCI_DEV_BASE + addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + *value = (tval >> ((4 - (where % 4))*8)); + break; + case 4: +- *value = reg_read(AR724X_PCI_DEV_BASE + where); ++ *value = __raw_readl(base + where); + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b + int size, uint32_t value) + { + unsigned long flags, tval, addr, mask; ++ void __iomem *base; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b + if (where & (size - 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + ++ base = ar724x_pci_devcfg_base; ++ + spin_lock_irqsave(&ar724x_pci_lock, flags); + + switch (size) { + case 1: +- addr = (AR724X_PCI_DEV_BASE + where) & ~3; ++ addr = where & ~3; + mask = 0xff000000 >> ((where % 4)*8); +- tval = reg_read(addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); ++ __raw_writel(tval, base + addr); + break; + case 2: +- addr = (AR724X_PCI_DEV_BASE + where) & ~3; ++ addr = where & ~3; + mask = 0xffff0000 >> ((where % 4)*8); +- tval = reg_read(addr); ++ tval = __raw_readl(base + addr); + tval = tval & ~mask; + tval |= (value << ((4 - (where % 4))*8)) & mask; +- reg_write(addr, tval); ++ __raw_writel(tval, base + addr); + break; + case 4: +- reg_write((AR724X_PCI_DEV_BASE + where), value); ++ __raw_writel(value, (base + where)); + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_ + + int __init ar724x_pcibios_init(void) + { ++ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, ++ AR724X_PCI_CFG_SIZE); ++ if (ar724x_pci_devcfg_base == NULL) ++ return -ENOMEM; ++ + register_pci_controller(&ar724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; diff --git a/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch b/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch new file mode 100644 index 0000000000..9ce1c396e6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch @@ -0,0 +1,38 @@ +From e9889bee75d03338daf7ed422661ae28f3aa7063 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:03 +0100 +Subject: [PATCH 12/47] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c + +The alignment of the 'where' parameters are checked +in the core PCI code already. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3492/ +Signed-off-by: Ralf Baechle +--- + arch/mips/pci/pci-ar724x.c | 6 ------ + 1 files changed, 0 insertions(+), 6 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bu + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); +@@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_b + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (where & (size - 1)) +- return PCIBIOS_BAD_REGISTER_NUMBER; +- + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); diff --git a/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-replace-ath724x-to-ar724x.patch b/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-replace-ath724x-to-ar724x.patch deleted file mode 100644 index 7e5df9f0d4..0000000000 --- a/target/linux/ar71xx/patches-3.3/107-MIPS-ath79-replace-ath724x-to-ar724x.patch +++ /dev/null @@ -1,266 +0,0 @@ -From 0cbee5634678ffbd10bee9e302d013392dd8289e Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 11:16:33 +0100 -Subject: [PATCH 07/35] MIPS: ath79: replace ath724x to ar724x -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Replace the 'ath724x' to 'ar724x' in function, variable and -structure names to reflect the name of the real SoC. - -Signed-off-by: Gabor Juhos -Acked-by: René Bolldorf - -v4: - add an Acked-by tag from René - - refreshed due to the changes in a previous patch -v3: - no changes -v2: - no changes ---- - arch/mips/ath79/mach-ubnt-xm.c | 4 +- - arch/mips/ath79/pci.c | 6 ++-- - arch/mips/ath79/pci.h | 10 +++--- - arch/mips/include/asm/mach-ath79/pci.h | 4 +- - arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++---------------- - 5 files changed, 43 insertions(+), 43 deletions(-) - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub - #ifdef CONFIG_PCI - static struct ath9k_platform_data ubnt_xm_eeprom_data; - --static struct ath724x_pci_data ubnt_xm_pci_data[] = { -+static struct ar724x_pci_data ubnt_xm_pci_data[] = { - { - .irq = UBNT_XM_PCI_IRQ, - .pdata = &ubnt_xm_eeprom_data, -@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void) - memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, - sizeof(ubnt_xm_eeprom_data.eeprom_data)); - -- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); -+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); - #endif /* CONFIG_PCI */ - - ath79_register_pci(); ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -13,10 +13,10 @@ - #include - #include "pci.h" - --static struct ath724x_pci_data *pci_data; -+static struct ar724x_pci_data *pci_data; - static int pci_data_size; - --void ath724x_pci_add_data(struct ath724x_pci_data *data, int size) -+void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) - { - pci_data = data; - pci_data_size = size; -@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev - int __init ath79_register_pci(void) - { - if (soc_is_ar724x()) -- return ath724x_pcibios_init(); -+ return ar724x_pcibios_init(); - - return -ENODEV; - } ---- a/arch/mips/ath79/pci.h -+++ b/arch/mips/ath79/pci.h -@@ -8,15 +8,15 @@ - * by the Free Software Foundation. - */ - --#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H --#define __ASM_MACH_ATH79_PCI_ATH724X_H -+#ifndef _ATH79_PCI_H -+#define _ATH79_PCI_H - --struct ath724x_pci_data { -+struct ar724x_pci_data { - int irq; - void *pdata; - }; - --void ath724x_pci_add_data(struct ath724x_pci_data *data, int size); -+void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); - - #ifdef CONFIG_PCI - int ath79_register_pci(void); -@@ -24,4 +24,4 @@ int ath79_register_pci(void); - static inline int ath79_register_pci(void) { return 0; } - #endif - --#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */ -+#endif /* _ATH79_PCI_H */ ---- a/arch/mips/include/asm/mach-ath79/pci.h -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -12,9 +12,9 @@ - #define __ASM_MACH_ATH79_PCI_H - - #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) --int ath724x_pcibios_init(void); -+int ar724x_pcibios_init(void); - #else --static inline int ath724x_pcibios_init(void) { return 0 }; -+static inline int ar724x_pcibios_init(void) { return 0 }; - #endif - - #endif /* __ASM_MACH_ATH79_PCI_H */ ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -14,13 +14,13 @@ - #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) - #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) - --#define ATH724X_PCI_DEV_BASE 0x14000000 --#define ATH724X_PCI_MEM_BASE 0x10000000 --#define ATH724X_PCI_MEM_SIZE 0x08000000 -+#define AR724X_PCI_DEV_BASE 0x14000000 -+#define AR724X_PCI_MEM_BASE 0x10000000 -+#define AR724X_PCI_MEM_SIZE 0x08000000 - --static DEFINE_SPINLOCK(ath724x_pci_lock); -+static DEFINE_SPINLOCK(ar724x_pci_lock); - --static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, -+static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t *value) - { - unsigned long flags, addr, tval, mask; -@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b - if (where & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - -- spin_lock_irqsave(&ath724x_pci_lock, flags); -+ spin_lock_irqsave(&ar724x_pci_lock, flags); - - switch (size) { - case 1: - addr = where & ~3; - mask = 0xff000000 >> ((where % 4) * 8); -- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); -+ tval = reg_read(AR724X_PCI_DEV_BASE + addr); - tval = tval & ~mask; - *value = (tval >> ((4 - (where % 4))*8)); - break; - case 2: - addr = where & ~3; - mask = 0xffff0000 >> ((where % 4)*8); -- tval = reg_read(ATH724X_PCI_DEV_BASE + addr); -+ tval = reg_read(AR724X_PCI_DEV_BASE + addr); - tval = tval & ~mask; - *value = (tval >> ((4 - (where % 4))*8)); - break; - case 4: -- *value = reg_read(ATH724X_PCI_DEV_BASE + where); -+ *value = reg_read(AR724X_PCI_DEV_BASE + where); - break; - default: -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); - - return PCIBIOS_BAD_REGISTER_NUMBER; - } - -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; - } - --static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, -+static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t value) - { - unsigned long flags, tval, addr, mask; -@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_ - if (where & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - -- spin_lock_irqsave(&ath724x_pci_lock, flags); -+ spin_lock_irqsave(&ar724x_pci_lock, flags); - - switch (size) { - case 1: -- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; -+ addr = (AR724X_PCI_DEV_BASE + where) & ~3; - mask = 0xff000000 >> ((where % 4)*8); - tval = reg_read(addr); - tval = tval & ~mask; -@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_ - reg_write(addr, tval); - break; - case 2: -- addr = (ATH724X_PCI_DEV_BASE + where) & ~3; -+ addr = (AR724X_PCI_DEV_BASE + where) & ~3; - mask = 0xffff0000 >> ((where % 4)*8); - tval = reg_read(addr); - tval = tval & ~mask; -@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_ - reg_write(addr, tval); - break; - case 4: -- reg_write((ATH724X_PCI_DEV_BASE + where), value); -+ reg_write((AR724X_PCI_DEV_BASE + where), value); - break; - default: -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); - - return PCIBIOS_BAD_REGISTER_NUMBER; - } - -- spin_unlock_irqrestore(&ath724x_pci_lock, flags); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; - } - --static struct pci_ops ath724x_pci_ops = { -- .read = ath724x_pci_read, -- .write = ath724x_pci_write, -+static struct pci_ops ar724x_pci_ops = { -+ .read = ar724x_pci_read, -+ .write = ar724x_pci_write, - }; - --static struct resource ath724x_io_resource = { -+static struct resource ar724x_io_resource = { - .name = "PCI IO space", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO, - }; - --static struct resource ath724x_mem_resource = { -+static struct resource ar724x_mem_resource = { - .name = "PCI memory space", -- .start = ATH724X_PCI_MEM_BASE, -- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1, -+ .start = AR724X_PCI_MEM_BASE, -+ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, - }; - --static struct pci_controller ath724x_pci_controller = { -- .pci_ops = &ath724x_pci_ops, -- .io_resource = &ath724x_io_resource, -- .mem_resource = &ath724x_mem_resource, -+static struct pci_controller ar724x_pci_controller = { -+ .pci_ops = &ar724x_pci_ops, -+ .io_resource = &ar724x_io_resource, -+ .mem_resource = &ar724x_mem_resource, - }; - --int __init ath724x_pcibios_init(void) -+int __init ar724x_pcibios_init(void) - { -- register_pci_controller(&ath724x_pci_controller); -+ register_pci_controller(&ar724x_pci_controller); - - return PCIBIOS_SUCCESSFUL; - } diff --git a/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch b/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch new file mode 100644 index 0000000000..97db6de9a8 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch @@ -0,0 +1,134 @@ +From 39f3275077a5b143616fcb3e7a6457a5c42739ee Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:04 +0100 +Subject: [PATCH 13/47] MIPS: ath79: fix broken ar724x_pci_{read,write} functions + +The current ar724x_pci_{read,write} functions are +broken. Due to that, pci_read_config_byte returns +with bogus values, and pci_write_config_{byte,word} +unconditionally clears the accessed PCI configuration +registers instead of changing the value of them. + +The patch fixes the broken functions, thus the PCI +configuration space can be accessed correctly. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3493/ +Signed-off-by: Ralf Baechle +--- + arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++---------------------- + 1 files changed, 26 insertions(+), 26 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { +- unsigned long flags, addr, tval, mask; ++ unsigned long flags; + void __iomem *base; ++ u32 data; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); + + switch (size) { + case 1: +- addr = where & ~3; +- mask = 0xff000000 >> ((where % 4) * 8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); ++ if (where & 1) ++ data >>= 8; ++ if (where & 2) ++ data >>= 16; ++ data &= 0xff; + break; + case 2: +- addr = where & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- *value = (tval >> ((4 - (where % 4))*8)); ++ if (where & 2) ++ data >>= 16; ++ data &= 0xffff; + break; + case 4: +- *value = __raw_readl(base + where); + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu + } + + spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++ *value = data; + + return PCIBIOS_SUCCESSFUL; + } +@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu + static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t value) + { +- unsigned long flags, tval, addr, mask; ++ unsigned long flags; + void __iomem *base; ++ u32 data; ++ int s; + + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; +@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); + + switch (size) { + case 1: +- addr = where & ~3; +- mask = 0xff000000 >> ((where % 4)*8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- __raw_writel(tval, base + addr); ++ s = ((where & 3) * 8); ++ data &= ~(0xff << s); ++ data |= ((value & 0xff) << s); + break; + case 2: +- addr = where & ~3; +- mask = 0xffff0000 >> ((where % 4)*8); +- tval = __raw_readl(base + addr); +- tval = tval & ~mask; +- tval |= (value << ((4 - (where % 4))*8)) & mask; +- __raw_writel(tval, base + addr); ++ s = ((where & 2) * 8); ++ data &= ~(0xffff << s); ++ data |= ((value & 0xffff) << s); + break; + case 4: +- __raw_writel(value, (base + where)); ++ data = value; + break; + default: + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b + return PCIBIOS_BAD_REGISTER_NUMBER; + } + ++ __raw_writel(data, base + (where & ~3)); ++ /* flush write */ ++ __raw_readl(base + (where & ~3)); + spin_unlock_irqrestore(&ar724x_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; diff --git a/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch b/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch deleted file mode 100644 index adc7f18713..0000000000 --- a/target/linux/ar71xx/patches-3.3/108-MIPS-ath79-use-io-accessor-macros-in-pci-ar724x.c.patch +++ /dev/null @@ -1,132 +0,0 @@ -From db464f2ad82c03f847d8eabbb8251b5c567e6720 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 11:52:41 +0100 -Subject: [PATCH 08/35] MIPS: ath79: use io-accessor macros in pci-ar724x.c -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Gabor Juhos -Acked-by: René Bolldorf - -v4: - add an Acked-by tag from René -v3: - no changes -v2: - no changes ---- - arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++-------------- - 1 files changed, 24 insertions(+), 14 deletions(-) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -11,19 +11,19 @@ - #include - #include - --#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys)) --#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val)) -- --#define AR724X_PCI_DEV_BASE 0x14000000 -+#define AR724X_PCI_CFG_BASE 0x14000000 -+#define AR724X_PCI_CFG_SIZE 0x1000 - #define AR724X_PCI_MEM_BASE 0x10000000 - #define AR724X_PCI_MEM_SIZE 0x08000000 - - static DEFINE_SPINLOCK(ar724x_pci_lock); -+static void __iomem *ar724x_pci_devcfg_base; - - static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t *value) - { - unsigned long flags, addr, tval, mask; -+ void __iomem *base; - - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; -@@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu - if (where & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - -+ base = ar724x_pci_devcfg_base; -+ - spin_lock_irqsave(&ar724x_pci_lock, flags); - - switch (size) { - case 1: - addr = where & ~3; - mask = 0xff000000 >> ((where % 4) * 8); -- tval = reg_read(AR724X_PCI_DEV_BASE + addr); -+ tval = __raw_readl(base + addr); - tval = tval & ~mask; - *value = (tval >> ((4 - (where % 4))*8)); - break; - case 2: - addr = where & ~3; - mask = 0xffff0000 >> ((where % 4)*8); -- tval = reg_read(AR724X_PCI_DEV_BASE + addr); -+ tval = __raw_readl(base + addr); - tval = tval & ~mask; - *value = (tval >> ((4 - (where % 4))*8)); - break; - case 4: -- *value = reg_read(AR724X_PCI_DEV_BASE + where); -+ *value = __raw_readl(base + where); - break; - default: - spin_unlock_irqrestore(&ar724x_pci_lock, flags); -@@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b - int size, uint32_t value) - { - unsigned long flags, tval, addr, mask; -+ void __iomem *base; - - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; -@@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b - if (where & (size - 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - -+ base = ar724x_pci_devcfg_base; -+ - spin_lock_irqsave(&ar724x_pci_lock, flags); - - switch (size) { - case 1: -- addr = (AR724X_PCI_DEV_BASE + where) & ~3; -+ addr = where & ~3; - mask = 0xff000000 >> ((where % 4)*8); -- tval = reg_read(addr); -+ tval = __raw_readl(base + addr); - tval = tval & ~mask; - tval |= (value << ((4 - (where % 4))*8)) & mask; -- reg_write(addr, tval); -+ __raw_writel(tval, base + addr); - break; - case 2: -- addr = (AR724X_PCI_DEV_BASE + where) & ~3; -+ addr = where & ~3; - mask = 0xffff0000 >> ((where % 4)*8); -- tval = reg_read(addr); -+ tval = __raw_readl(base + addr); - tval = tval & ~mask; - tval |= (value << ((4 - (where % 4))*8)) & mask; -- reg_write(addr, tval); -+ __raw_writel(tval, base + addr); - break; - case 4: -- reg_write((AR724X_PCI_DEV_BASE + where), value); -+ __raw_writel(value, (base + where)); - break; - default: - spin_unlock_irqrestore(&ar724x_pci_lock, flags); -@@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_ - - int __init ar724x_pcibios_init(void) - { -+ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, -+ AR724X_PCI_CFG_SIZE); -+ if (ar724x_pci_devcfg_base == NULL) -+ return -ENOMEM; -+ - register_pci_controller(&ar724x_pci_controller); - - return PCIBIOS_SUCCESSFUL; diff --git a/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch b/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch new file mode 100644 index 0000000000..8ed823b59a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch @@ -0,0 +1,134 @@ +From 14eaf9b1cda516b4182e56f61c21fa2eaa9ade6b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:05 +0100 +Subject: [PATCH 14/47] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs + +The PCI controller of the AR724X SoCs has a hardware +bag. If the BAR0 register of the PCI device is set to +the proper base address, the memory address space of +the device is not accessible. + +When the device driver tries to access the memory +address space of the PCI device, it leads to data +bus error, similiar to this: + +Data bus error, epc == 801f69a0, ra == 801f698c +Oops[#1]: +Cpu 0 +$ 0 : 00000000 00000061 deadbeef 000000ff +$ 4 : 00000000 000000ff 00000014 00000000 +$ 8 : ff000000 fffffffc 00000000 00000000 +$12 : 000001f5 00000006 00000000 6e637920 +$16 : 81ca4000 81ca0260 81ca4000 804d70f0 +$20 : fffffff4 0000002b 803ad4c4 00000000 +$24 : 00000003 00000000 +$28 : 81c20000 81c21c60 00000000 801f698c +Hi : 00000000 +Lo : 00000000 +epc : 801f69a0 ath9k_hw_init+0xd0/0xa70 + Not tainted +ra : 801f698c ath9k_hw_init+0xbc/0xa70 +Status: 1000c103 KERNEL EXL IE +Cause : 1080001c +PrId : 00019374 (MIPS 24Kc) +Modules linked in: +Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) +Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0 + 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b + 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c + 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000 + 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320 + ... +Call Trace: +[<801f69a0>] ath9k_hw_init+0xd0/0xa70 +[<801e3ae8>] ath9k_init_device+0x174/0x680 +[<801f08a4>] ath_pci_probe+0x27c/0x380 +[<8019e490>] pci_device_probe+0x74/0x9c +[<801bfadc>] driver_probe_device+0x9c/0x1b4 +[<801bfcb0>] __driver_attach+0xbc/0xc4 +[<801bea0c>] bus_for_each_dev+0x5c/0x98 +[<801bf394>] bus_add_driver+0x1d0/0x2a4 +[<801c0364>] driver_register+0x8c/0x16c +[<8019e72c>] __pci_register_driver+0x4c/0xe4 +[<803d3d40>] ath9k_init+0x3c/0x88 +[<80060930>] do_one_initcall+0x3c/0x1cc +[<803c297c>] kernel_init+0xa4/0x138 +[<80063c04>] kernel_thread_helper+0x10/0x18 + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3494/ +Signed-off-by: Ralf Baechle +--- + arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++- + 1 files changed, 35 insertions(+), 1 deletions(-) + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -9,6 +9,7 @@ + */ + + #include ++#include + #include + + #define AR724X_PCI_CFG_BASE 0x14000000 +@@ -16,9 +17,14 @@ + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + ++#define AR7240_BAR0_WAR_VALUE 0xffff ++ + static DEFINE_SPINLOCK(ar724x_pci_lock); + static void __iomem *ar724x_pci_devcfg_base; + ++static u32 ar724x_pci_bar0_value; ++static bool ar724x_pci_bar0_is_cached; ++ + static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, uint32_t *value) + { +@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu + } + + spin_unlock_irqrestore(&ar724x_pci_lock, flags); +- *value = data; ++ ++ if (where == PCI_BASE_ADDRESS_0 && size == 4 && ++ ar724x_pci_bar0_is_cached) { ++ /* use the cached value */ ++ *value = ar724x_pci_bar0_value; ++ } else { ++ *value = data; ++ } + + return PCIBIOS_SUCCESSFUL; + } +@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b + if (devfn) + return PCIBIOS_DEVICE_NOT_FOUND; + ++ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) { ++ if (value != 0xffffffff) { ++ /* ++ * WAR for a hw issue. If the BAR0 register of the ++ * device is set to the proper base address, the ++ * memory space of the device is not accessible. ++ * ++ * Cache the intended value so it can be read back, ++ * and write a SoC specific constant value to the ++ * BAR0 register in order to make the device memory ++ * accessible. ++ */ ++ ar724x_pci_bar0_is_cached = true; ++ ar724x_pci_bar0_value = value; ++ ++ value = AR7240_BAR0_WAR_VALUE; ++ } else { ++ ar724x_pci_bar0_is_cached = false; ++ } ++ } ++ + base = ar724x_pci_devcfg_base; + + spin_lock_irqsave(&ar724x_pci_lock, flags); diff --git a/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch b/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch deleted file mode 100644 index 1fb03c6cdf..0000000000 --- a/target/linux/ar71xx/patches-3.3/109-MIPS-ath79-remove-superfluous-alignment-checks-from-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 744ffdd4e90cd6671f46eadf9d7cf55b07618d73 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 21:37:17 +0100 -Subject: [PATCH 09/35] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c - -The alignment of the 'where' parameters are checked -in the core PCI code already. - -Signed-off-by: Gabor Juhos - -v2: - no changes ---- - arch/mips/pci/pci-ar724x.c | 6 ------ - 1 files changed, 0 insertions(+), 6 deletions(-) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bu - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; - -- if (where & (size - 1)) -- return PCIBIOS_BAD_REGISTER_NUMBER; -- - base = ar724x_pci_devcfg_base; - - spin_lock_irqsave(&ar724x_pci_lock, flags); -@@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_b - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; - -- if (where & (size - 1)) -- return PCIBIOS_BAD_REGISTER_NUMBER; -- - base = ar724x_pci_devcfg_base; - - spin_lock_irqsave(&ar724x_pci_lock, flags); diff --git a/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch b/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch new file mode 100644 index 0000000000..8702e65fc0 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-a-wrong-IRQ-number.patch @@ -0,0 +1,73 @@ +From d710990df726cceffb62488e597ecfc4a9e13aa5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:06 +0100 +Subject: [PATCH 15/47] MIPS: ath79: fix a wrong IRQ number + +The Ubiquiti XM board setup code uses an invalid +IRQ number, because it if above of NR_IRQS. This +leads to failed 'request_irq' calls: + + ath9k 0000:00:00.0: request_irq failed + ath9k: probe of 0000:00:00.0 failed with error -22 + +Preserve some IRQ numbers for the built-in IRQ +controller of PCI host controllers in the +AR71XX/AR724X SoCs, and use the correct IRQ +number in the board setup code. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3495/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 5 +++-- + arch/mips/include/asm/mach-ath79/irq.h | 6 +++++- + 2 files changed, 8 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -17,6 +17,8 @@ + #include + #endif /* CONFIG_PCI */ + ++#include ++ + #include "machtypes.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +@@ -33,7 +35,6 @@ + #define UBNT_XM_KEYS_POLL_INTERVAL 20 + #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +-#define UBNT_XM_PCI_IRQ 48 + #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { +@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x + + static struct ar724x_pci_data ubnt_xm_pci_data[] = { + { +- .irq = UBNT_XM_PCI_IRQ, ++ .irq = ATH79_PCI_IRQ(0), + .pdata = &ubnt_xm_eeprom_data, + }, + }; +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,11 +10,15 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 40 ++#define NR_IRQS 46 + + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 + ++#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) ++#define ATH79_PCI_IRQ_COUNT 6 ++#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) ++ + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) + #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) + #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) diff --git a/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch b/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch deleted file mode 100644 index c3637e8eca..0000000000 --- a/target/linux/ar71xx/patches-3.3/110-MIPS-ath79-fix-broken-ar724x_pci_-read-write-functio.patch +++ /dev/null @@ -1,219 +0,0 @@ -From 2e535c334018d58b0bf6df583486abda5bfb2003 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 18 Nov 2011 22:25:30 +0100 -Subject: [PATCH 10/35] MIPS: ath79: fix broken ar724x_pci_{read,write} functions - -The current ar724x_pci_{read,write} functions are -broken. Due to that, pci_read_config_byte returns -with bogus values, and pci_write_config_{byte,word} -unconditionally clears the accessed PCI configuration -registers instead of changing the value of them. - -The patch fixes the broken functions, thus the PCI -configuration space can be accessed correctly. - -Signed-off-by: Gabor Juhos - -v2: - no changes - -Output of 'lspci -vv' without the patch: - -00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless -Network Adapter (PCI-Express) (rev 01) - Subsystem: Atheros Communications Inc. Device a091 - Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- - Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- ---- - arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++---------------------- - 1 files changed, 26 insertions(+), 26 deletions(-) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b - static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t *value) - { -- unsigned long flags, addr, tval, mask; -+ unsigned long flags; - void __iomem *base; -+ u32 data; - - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; -@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu - base = ar724x_pci_devcfg_base; - - spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); - - switch (size) { - case 1: -- addr = where & ~3; -- mask = 0xff000000 >> ((where % 4) * 8); -- tval = __raw_readl(base + addr); -- tval = tval & ~mask; -- *value = (tval >> ((4 - (where % 4))*8)); -+ if (where & 1) -+ data >>= 8; -+ if (where & 2) -+ data >>= 16; -+ data &= 0xff; - break; - case 2: -- addr = where & ~3; -- mask = 0xffff0000 >> ((where % 4)*8); -- tval = __raw_readl(base + addr); -- tval = tval & ~mask; -- *value = (tval >> ((4 - (where % 4))*8)); -+ if (where & 2) -+ data >>= 16; -+ data &= 0xffff; - break; - case 4: -- *value = __raw_readl(base + where); - break; - default: - spin_unlock_irqrestore(&ar724x_pci_lock, flags); -@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu - } - - spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+ *value = data; - - return PCIBIOS_SUCCESSFUL; - } -@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu - static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t value) - { -- unsigned long flags, tval, addr, mask; -+ unsigned long flags; - void __iomem *base; -+ u32 data; -+ int s; - - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; -@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b - base = ar724x_pci_devcfg_base; - - spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); - - switch (size) { - case 1: -- addr = where & ~3; -- mask = 0xff000000 >> ((where % 4)*8); -- tval = __raw_readl(base + addr); -- tval = tval & ~mask; -- tval |= (value << ((4 - (where % 4))*8)) & mask; -- __raw_writel(tval, base + addr); -+ s = ((where & 3) * 8); -+ data &= ~(0xff << s); -+ data |= ((value & 0xff) << s); - break; - case 2: -- addr = where & ~3; -- mask = 0xffff0000 >> ((where % 4)*8); -- tval = __raw_readl(base + addr); -- tval = tval & ~mask; -- tval |= (value << ((4 - (where % 4))*8)) & mask; -- __raw_writel(tval, base + addr); -+ s = ((where & 2) * 8); -+ data &= ~(0xffff << s); -+ data |= ((value & 0xffff) << s); - break; - case 4: -- __raw_writel(value, (base + where)); -+ data = value; - break; - default: - spin_unlock_irqrestore(&ar724x_pci_lock, flags); -@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b - return PCIBIOS_BAD_REGISTER_NUMBER; - } - -+ __raw_writel(data, base + (where & ~3)); -+ /* flush write */ -+ __raw_readl(base + (where & ~3)); - spin_unlock_irqrestore(&ar724x_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; diff --git a/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch b/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch new file mode 100644 index 0000000000..0c15a54967 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch @@ -0,0 +1,213 @@ +From 1fd24b552708544ca6233ff7ba60342e9f7e5582 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:07 +0100 +Subject: [PATCH 16/47] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs + +The PCI Host Controller of the AR724x SoC has a +built-in IRQ controller. The current code does +not supports that, so the IRQ lines wired to this +controller are not usable. This leads to failed +'request_irq' calls: + + ath9k 0000:00:00.0: request_irq failed + ath9k: probe of 0000:00:00.0 failed with error -89 + +This patch adds support for the IRQ controller +in order to make PCI IRQs work. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3496/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/pci.c | 3 +- + arch/mips/include/asm/mach-ath79/pci.h | 4 +- + arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++- + 3 files changed, 120 insertions(+), 5 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -10,6 +10,7 @@ + + #include + #include ++#include + #include + #include "pci.h" + +@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev + int __init ath79_register_pci(void) + { + if (soc_is_ar724x()) +- return ar724x_pcibios_init(); ++ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + + return -ENODEV; + } +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -12,9 +12,9 @@ + #define __ASM_MACH_ATH79_PCI_H + + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) +-int ar724x_pcibios_init(void); ++int ar724x_pcibios_init(int irq); + #else +-static inline int ar724x_pcibios_init(void) { return 0; } ++static inline int ar724x_pcibios_init(int irq) { return 0; } + #endif + + #endif /* __ASM_MACH_ATH79_PCI_H */ +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -8,19 +8,32 @@ + * by the Free Software Foundation. + */ + ++#include + #include + #include ++#include + #include + + #define AR724X_PCI_CFG_BASE 0x14000000 + #define AR724X_PCI_CFG_SIZE 0x1000 ++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) ++#define AR724X_PCI_CTRL_SIZE 0x100 ++ + #define AR724X_PCI_MEM_BASE 0x10000000 + #define AR724X_PCI_MEM_SIZE 0x08000000 + ++#define AR724X_PCI_REG_INT_STATUS 0x4c ++#define AR724X_PCI_REG_INT_MASK 0x50 ++ ++#define AR724X_PCI_INT_DEV0 BIT(14) ++ ++#define AR724X_PCI_IRQ_COUNT 1 ++ + #define AR7240_BAR0_WAR_VALUE 0xffff + + static DEFINE_SPINLOCK(ar724x_pci_lock); + static void __iomem *ar724x_pci_devcfg_base; ++static void __iomem *ar724x_pci_ctrl_base; + + static u32 ar724x_pci_bar0_value; + static bool ar724x_pci_bar0_is_cached; +@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_ + .mem_resource = &ar724x_mem_resource, + }; + +-int __init ar724x_pcibios_init(void) ++static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base; ++ u32 pending; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ ++ if (pending & AR724X_PCI_INT_DEV0) ++ generic_handle_irq(ATH79_PCI_IRQ(0)); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar724x_pci_irq_unmask(struct irq_data *d) ++{ ++ void __iomem *base; ++ u32 t; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ switch (d->irq) { ++ case ATH79_PCI_IRQ(0): ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ /* flush write */ ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ } ++} ++ ++static void ar724x_pci_irq_mask(struct irq_data *d) ++{ ++ void __iomem *base; ++ u32 t; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ switch (d->irq) { ++ case ATH79_PCI_IRQ(0): ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t & ~AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ ++ /* flush write */ ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ ++ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_STATUS); ++ ++ /* flush write */ ++ __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ } ++} ++ ++static struct irq_chip ar724x_pci_irq_chip = { ++ .name = "AR724X PCI ", ++ .irq_mask = ar724x_pci_irq_mask, ++ .irq_unmask = ar724x_pci_irq_unmask, ++ .irq_mask_ack = ar724x_pci_irq_mask, ++}; ++ ++static void __init ar724x_pci_irq_init(int irq) ++{ ++ void __iomem *base; ++ int i; ++ ++ base = ar724x_pci_ctrl_base; ++ ++ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); ++ ++ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); ++ ++ for (i = ATH79_PCI_IRQ_BASE; ++ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(irq, ar724x_pci_irq_handler); ++} ++ ++int __init ar724x_pcibios_init(int irq) + { ++ int ret; ++ ++ ret = -ENOMEM; ++ + ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, + AR724X_PCI_CFG_SIZE); + if (ar724x_pci_devcfg_base == NULL) +- return -ENOMEM; ++ goto err; + ++ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_CTRL_SIZE); ++ if (ar724x_pci_ctrl_base == NULL) ++ goto err_unmap_devcfg; ++ ++ ar724x_pci_irq_init(irq); + register_pci_controller(&ar724x_pci_controller); + + return PCIBIOS_SUCCESSFUL; ++ ++err_unmap_devcfg: ++ iounmap(ar724x_pci_devcfg_base); ++err: ++ return ret; + } diff --git a/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch b/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch deleted file mode 100644 index 11391abe69..0000000000 --- a/target/linux/ar71xx/patches-3.3/111-MIPS-ath79-add-a-workaround-for-a-PCI-controller-bug.patch +++ /dev/null @@ -1,134 +0,0 @@ -From b2ee3bd8706521c9bbf43405c767010927c101e5 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 21 Nov 2011 17:57:51 +0100 -Subject: [PATCH 11/35] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs - -The PCI controller of the AR724X SoCs has a hardware -bag. If the BAR0 register of the PCI device is set to -the proper base address, the memory address space of -the device is not accessible. - -When the device driver tries to access the memory -address space of the PCI device, it leads to data -bus error, similiar to this: - -Data bus error, epc == 801f69a0, ra == 801f698c -Oops[#1]: -Cpu 0 -$ 0 : 00000000 00000061 deadbeef 000000ff -$ 4 : 00000000 000000ff 00000014 00000000 -$ 8 : ff000000 fffffffc 00000000 00000000 -$12 : 000001f5 00000006 00000000 6e637920 -$16 : 81ca4000 81ca0260 81ca4000 804d70f0 -$20 : fffffff4 0000002b 803ad4c4 00000000 -$24 : 00000003 00000000 -$28 : 81c20000 81c21c60 00000000 801f698c -Hi : 00000000 -Lo : 00000000 -epc : 801f69a0 ath9k_hw_init+0xd0/0xa70 - Not tainted -ra : 801f698c ath9k_hw_init+0xbc/0xa70 -Status: 1000c103 KERNEL EXL IE -Cause : 1080001c -PrId : 00019374 (MIPS 24Kc) -Modules linked in: -Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) -Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0 - 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b - 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c - 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000 - 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320 - ... -Call Trace: -[<801f69a0>] ath9k_hw_init+0xd0/0xa70 -[<801e3ae8>] ath9k_init_device+0x174/0x680 -[<801f08a4>] ath_pci_probe+0x27c/0x380 -[<8019e490>] pci_device_probe+0x74/0x9c -[<801bfadc>] driver_probe_device+0x9c/0x1b4 -[<801bfcb0>] __driver_attach+0xbc/0xc4 -[<801bea0c>] bus_for_each_dev+0x5c/0x98 -[<801bf394>] bus_add_driver+0x1d0/0x2a4 -[<801c0364>] driver_register+0x8c/0x16c -[<8019e72c>] __pci_register_driver+0x4c/0xe4 -[<803d3d40>] ath9k_init+0x3c/0x88 -[<80060930>] do_one_initcall+0x3c/0x1cc -[<803c297c>] kernel_init+0xa4/0x138 -[<80063c04>] kernel_thread_helper+0x10/0x18 - -Signed-off-by: Gabor Juhos - -v2: - apply the workaround on AR7240 only - - remove unrelated defines ---- - arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++- - 1 files changed, 35 insertions(+), 1 deletions(-) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -9,6 +9,7 @@ - */ - - #include -+#include - #include - - #define AR724X_PCI_CFG_BASE 0x14000000 -@@ -16,9 +17,14 @@ - #define AR724X_PCI_MEM_BASE 0x10000000 - #define AR724X_PCI_MEM_SIZE 0x08000000 - -+#define AR7240_BAR0_WAR_VALUE 0xffff -+ - static DEFINE_SPINLOCK(ar724x_pci_lock); - static void __iomem *ar724x_pci_devcfg_base; - -+static u32 ar724x_pci_bar0_value; -+static bool ar724x_pci_bar0_is_cached; -+ - static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t *value) - { -@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu - } - - spin_unlock_irqrestore(&ar724x_pci_lock, flags); -- *value = data; -+ -+ if (where == PCI_BASE_ADDRESS_0 && size == 4 && -+ ar724x_pci_bar0_is_cached) { -+ /* use the cached value */ -+ *value = ar724x_pci_bar0_value; -+ } else { -+ *value = data; -+ } - - return PCIBIOS_SUCCESSFUL; - } -@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b - if (devfn) - return PCIBIOS_DEVICE_NOT_FOUND; - -+ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) { -+ if (value != 0xffffffff) { -+ /* -+ * WAR for a hw issue. If the BAR0 register of the -+ * device is set to the proper base address, the -+ * memory space of the device is not accessible. -+ * -+ * Cache the intended value so it can be read back, -+ * and write a SoC specific constant value to the -+ * BAR0 register in order to make the device memory -+ * accessible. -+ */ -+ ar724x_pci_bar0_is_cached = true; -+ ar724x_pci_bar0_value = value; -+ -+ value = AR7240_BAR0_WAR_VALUE; -+ } else { -+ ar724x_pci_bar0_is_cached = false; -+ } -+ } -+ - base = ar724x_pci_devcfg_base; - - spin_lock_irqsave(&ar724x_pci_lock, flags); diff --git a/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-fix-a-wrong-IRQ-number.patch b/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-fix-a-wrong-IRQ-number.patch deleted file mode 100644 index ccb721d366..0000000000 --- a/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-fix-a-wrong-IRQ-number.patch +++ /dev/null @@ -1,75 +0,0 @@ -From cfb725275ea25857e8f0e3bf358fff7c84cc787c Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 22 Nov 2011 13:59:39 +0100 -Subject: [PATCH 12/35] MIPS: ath79: fix a wrong IRQ number - -The Ubiquiti XM board setup code uses an invalid -IRQ number, because it if above of NR_IRQS. This -leads to failed 'request_irq' calls: - - ath9k 0000:00:00.0: request_irq failed - ath9k: probe of 0000:00:00.0 failed with error -22 - -Preserve some IRQ numbers for the built-in IRQ -controller of PCI host controllers in the -AR71XX/AR724X SoCs, and use the correct IRQ -number in the board setup code. - -Signed-off-by: Gabor Juhos - -v2: - no changes - -The IRQ controller code is also missing, that will be -added in a separate patch. ---- - arch/mips/ath79/mach-ubnt-xm.c | 5 +++-- - arch/mips/include/asm/mach-ath79/irq.h | 6 +++++- - 2 files changed, 8 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -17,6 +17,8 @@ - #include - #endif /* CONFIG_PCI */ - -+#include -+ - #include "machtypes.h" - #include "dev-gpio-buttons.h" - #include "dev-leds-gpio.h" -@@ -33,7 +35,6 @@ - #define UBNT_XM_KEYS_POLL_INTERVAL 20 - #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) - --#define UBNT_XM_PCI_IRQ 48 - #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) - - static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { -@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x - - static struct ar724x_pci_data ubnt_xm_pci_data[] = { - { -- .irq = UBNT_XM_PCI_IRQ, -+ .irq = ATH79_PCI_IRQ(0), - .pdata = &ubnt_xm_eeprom_data, - }, - }; ---- a/arch/mips/include/asm/mach-ath79/irq.h -+++ b/arch/mips/include/asm/mach-ath79/irq.h -@@ -10,11 +10,15 @@ - #define __ASM_MACH_ATH79_IRQ_H - - #define MIPS_CPU_IRQ_BASE 0 --#define NR_IRQS 40 -+#define NR_IRQS 46 - - #define ATH79_MISC_IRQ_BASE 8 - #define ATH79_MISC_IRQ_COUNT 32 - -+#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) -+#define ATH79_PCI_IRQ_COUNT 6 -+#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) -+ - #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) - #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) - #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) diff --git a/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch b/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch new file mode 100644 index 0000000000..4ef080541d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/112-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch @@ -0,0 +1,64 @@ +From b2ab491ed634a4c0b7af5f11940e0ca42b1a87c8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:08 +0100 +Subject: [PATCH 17/47] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c + +Remove a superfluous ifdef around an include. Also +reorganize the board setup code a bit, so another +ifdef can be removed. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3497/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++----------- + 1 files changed, 12 insertions(+), 11 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -12,10 +12,7 @@ + + #include + #include +- +-#ifdef CONFIG_PCI + #include +-#endif /* CONFIG_PCI */ + + #include + +@@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pc + .pdata = &ubnt_xm_eeprom_data, + }, + }; ++ ++static void __init ubnt_xm_pci_init(void) ++{ ++ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, ++ sizeof(ubnt_xm_eeprom_data.eeprom_data)); ++ ++ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ++ ath79_register_pci(); ++} ++#else ++static inline void ubnt_xm_pci_init(void) {} + #endif /* CONFIG_PCI */ + + static void __init ubnt_xm_init(void) +@@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void) + ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, + ARRAY_SIZE(ubnt_xm_spi_info)); + +-#ifdef CONFIG_PCI +- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, +- sizeof(ubnt_xm_eeprom_data.eeprom_data)); +- +- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); +-#endif /* CONFIG_PCI */ +- +- ath79_register_pci(); ++ ubnt_xm_pci_init(); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch b/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch deleted file mode 100644 index 6da2df4993..0000000000 --- a/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-add-PCI-IRQ-handling-code-for-AR724X-SoCs.patch +++ /dev/null @@ -1,213 +0,0 @@ -From a4fbc2dec67a5d760e25e3c3a6c392191a5405c6 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 22 Nov 2011 14:11:19 +0100 -Subject: [PATCH 13/35] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs - -The PCI Host Controller of the AR724x SoC has a -built-in IRQ controller. The current code does -not supports that, so the IRQ lines wired to this -controller are not usable. This leads to failed -'request_irq' calls: - - ath9k 0000:00:00.0: request_irq failed - ath9k: probe of 0000:00:00.0 failed with error -89 - -This patch adds support for the IRQ controller -in order to make PCI IRQs work. - -Signed-off-by: Gabor Juhos - -v2: - move the interrupt controller related defines from - the workaround patch ---- - arch/mips/ath79/pci.c | 3 +- - arch/mips/include/asm/mach-ath79/pci.h | 4 +- - arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++- - 3 files changed, 120 insertions(+), 5 deletions(-) - ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -10,6 +10,7 @@ - - #include - #include -+#include - #include - #include "pci.h" - -@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev - int __init ath79_register_pci(void) - { - if (soc_is_ar724x()) -- return ar724x_pcibios_init(); -+ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); - - return -ENODEV; - } ---- a/arch/mips/include/asm/mach-ath79/pci.h -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -12,9 +12,9 @@ - #define __ASM_MACH_ATH79_PCI_H - - #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) --int ar724x_pcibios_init(void); -+int ar724x_pcibios_init(int irq); - #else --static inline int ar724x_pcibios_init(void) { return 0 }; -+static inline int ar724x_pcibios_init(int irq) { return 0 }; - #endif - - #endif /* __ASM_MACH_ATH79_PCI_H */ ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -8,19 +8,32 @@ - * by the Free Software Foundation. - */ - -+#include - #include - #include -+#include - #include - - #define AR724X_PCI_CFG_BASE 0x14000000 - #define AR724X_PCI_CFG_SIZE 0x1000 -+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) -+#define AR724X_PCI_CTRL_SIZE 0x100 -+ - #define AR724X_PCI_MEM_BASE 0x10000000 - #define AR724X_PCI_MEM_SIZE 0x08000000 - -+#define AR724X_PCI_REG_INT_STATUS 0x4c -+#define AR724X_PCI_REG_INT_MASK 0x50 -+ -+#define AR724X_PCI_INT_DEV0 BIT(14) -+ -+#define AR724X_PCI_IRQ_COUNT 1 -+ - #define AR7240_BAR0_WAR_VALUE 0xffff - - static DEFINE_SPINLOCK(ar724x_pci_lock); - static void __iomem *ar724x_pci_devcfg_base; -+static void __iomem *ar724x_pci_ctrl_base; - - static u32 ar724x_pci_bar0_value; - static bool ar724x_pci_bar0_is_cached; -@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_ - .mem_resource = &ar724x_mem_resource, - }; - --int __init ar724x_pcibios_init(void) -+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base; -+ u32 pending; -+ -+ base = ar724x_pci_ctrl_base; -+ -+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ if (pending & AR724X_PCI_INT_DEV0) -+ generic_handle_irq(ATH79_PCI_IRQ(0)); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar724x_pci_irq_unmask(struct irq_data *d) -+{ -+ void __iomem *base; -+ u32 t; -+ -+ base = ar724x_pci_ctrl_base; -+ -+ switch (d->irq) { -+ case ATH79_PCI_IRQ(0): -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ /* flush write */ -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ } -+} -+ -+static void ar724x_pci_irq_mask(struct irq_data *d) -+{ -+ void __iomem *base; -+ u32 t; -+ -+ base = ar724x_pci_ctrl_base; -+ -+ switch (d->irq) { -+ case ATH79_PCI_IRQ(0): -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t & ~AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ -+ /* flush write */ -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_STATUS); -+ -+ /* flush write */ -+ __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ } -+} -+ -+static struct irq_chip ar724x_pci_irq_chip = { -+ .name = "AR724X PCI ", -+ .irq_mask = ar724x_pci_irq_mask, -+ .irq_unmask = ar724x_pci_irq_unmask, -+ .irq_mask_ack = ar724x_pci_irq_mask, -+}; -+ -+static void __init ar724x_pci_irq_init(int irq) -+{ -+ void __iomem *base; -+ int i; -+ -+ base = ar724x_pci_ctrl_base; -+ -+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); -+ -+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); -+ -+ for (i = ATH79_PCI_IRQ_BASE; -+ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(irq, ar724x_pci_irq_handler); -+} -+ -+int __init ar724x_pcibios_init(int irq) - { -+ int ret; -+ -+ ret = -ENOMEM; -+ - ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, - AR724X_PCI_CFG_SIZE); - if (ar724x_pci_devcfg_base == NULL) -- return -ENOMEM; -+ goto err; - -+ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, -+ AR724X_PCI_CTRL_SIZE); -+ if (ar724x_pci_ctrl_base == NULL) -+ goto err_unmap_devcfg; -+ -+ ar724x_pci_irq_init(irq); - register_pci_controller(&ar724x_pci_controller); - - return PCIBIOS_SUCCESSFUL; -+ -+err_unmap_devcfg: -+ iounmap(ar724x_pci_devcfg_base); -+err: -+ return ret; - } diff --git a/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch b/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch new file mode 100644 index 0000000000..38765b0a9e --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/113-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch @@ -0,0 +1,141 @@ +From 2b62c9d685d9bb048a006b695683b2a812c0a847 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:09 +0100 +Subject: [PATCH 18/47] MIPS: ath79: allow to use board specific pci_plat_dev_init functions + +Th current implementation causes NULL pointer dereference +if 'pci_data' is not set: + +pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit] +pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI +address [0x10000000-0x1000ffff]) +CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4 +Oops[#1]: +Cpu 0 +$ 0 : 00000000 80420000 00000000 00000000 +$ 4 : 00000000 00000000 00000001 00000001 +$ 8 : 00000001 0000032c 81c54700 00000001 +$12 : 0000032d 0000000f 00000000 ffffffff +$16 : 81c14c00 00000001 802dac74 80195f98 +$20 : 802ea050 00000000 00000000 00000000 +$24 : 00000003 800617f0 +$28 : 81c20000 81c21e70 00000000 802e78a4 +Hi : 00000000 +Lo : 4190ab00 +epc : 802daca0 0x802daca0 + Not tainted +ra : 802e78a4 0x802e78a4 +Status: 1000c003 KERNEL EXL IE +Cause : 00800008 +BadVA : 00000000 +PrId : 00019374 (MIPS 24Kc) +Modules linked in: +Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) +Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000 + 802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290 + 80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000 + 00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000 + 00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000 + +This can be avoided by calling the 'ar724x_pci_add_data' +function from the board specific setup code. However it +makes no sense to use that function for every board, +especially when the board does not needs to set the +platform_data field of any PCI device. + +The patch allows the board setup code to specify a board +specific function if that is required. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3499/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++- + arch/mips/ath79/pci.c | 14 ++++++++------ + arch/mips/ath79/pci.h | 4 +++- + 3 files changed, 23 insertions(+), 8 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_x + static struct ar724x_pci_data ubnt_xm_pci_data[] = { + { + .irq = ATH79_PCI_IRQ(0), +- .pdata = &ubnt_xm_eeprom_data, + }, + }; + ++static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &ubnt_xm_eeprom_data; ++ break; ++ } ++ ++ return 0; ++} ++ + static void __init ubnt_xm_pci_init(void) + { + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + + ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); ++ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); + ath79_register_pci(); + } + #else +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -14,6 +14,7 @@ + #include + #include "pci.h" + ++static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); + static struct ar724x_pci_data *pci_data; + static int pci_data_size; + +@@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct + + int pcibios_plat_dev_init(struct pci_dev *dev) + { +- unsigned int devfn = dev->devfn; +- +- if (devfn > pci_data_size - 1) +- return PCIBIOS_DEVICE_NOT_FOUND; ++ if (ath79_pci_plat_dev_init) ++ return ath79_pci_plat_dev_init(dev); + +- dev->dev.platform_data = pci_data[devfn].pdata; ++ return 0; ++} + +- return PCIBIOS_SUCCESSFUL; ++void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) ++{ ++ ath79_pci_plat_dev_init = func; + } + + int __init ath79_register_pci(void) +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -13,14 +13,16 @@ + + struct ar724x_pci_data { + int irq; +- void *pdata; + }; + + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); + + #ifdef CONFIG_PCI ++void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); + int ath79_register_pci(void); + #else ++static inline void ++ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} + static inline int ath79_register_pci(void) { return 0; } + #endif + diff --git a/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch b/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch new file mode 100644 index 0000000000..4021af2ca6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch @@ -0,0 +1,436 @@ +From 4201b6aeb059b481571c241a2fc96fd3f41032e9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:10 +0100 +Subject: [PATCH 19/47] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs + +The Atheros AR71XX SoCs have a built-in PCI Host Controller. +This patch adds a driver for that, and modifies the relevant +files in order to allow to register the PCI controller from +board specific setup. + +Signed-off-by: Gabor Juhos +Signed-off-by: Imre Kaloz +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3498/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Kconfig | 1 + + arch/mips/include/asm/mach-ath79/pci.h | 6 + + arch/mips/pci/Makefile | 1 + + arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++ + 4 files changed, 383 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/pci/pci-ar71xx.c + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -52,6 +52,7 @@ endmenu + config SOC_AR71XX + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI ++ select HW_HAS_PCI + def_bool n + + config SOC_AR724X +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -11,6 +11,12 @@ + #ifndef __ASM_MACH_ATH79_PCI_H + #define __ASM_MACH_ATH79_PCI_H + ++#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) ++int ar71xx_pcibios_init(void); ++#else ++static inline int ar71xx_pcibios_init(void) { return 0; } ++#endif ++ + #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) + int ar724x_pcibios_init(int irq); + #else +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o ++obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o + obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o + + # +--- /dev/null ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -0,0 +1,375 @@ ++/* ++ * Atheros AR71xx PCI host controller driver ++ * ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define AR71XX_PCI_MEM_BASE 0x10000000 ++#define AR71XX_PCI_MEM_SIZE 0x08000000 ++ ++#define AR71XX_PCI_WIN0_OFFS 0x10000000 ++#define AR71XX_PCI_WIN1_OFFS 0x11000000 ++#define AR71XX_PCI_WIN2_OFFS 0x12000000 ++#define AR71XX_PCI_WIN3_OFFS 0x13000000 ++#define AR71XX_PCI_WIN4_OFFS 0x14000000 ++#define AR71XX_PCI_WIN5_OFFS 0x15000000 ++#define AR71XX_PCI_WIN6_OFFS 0x16000000 ++#define AR71XX_PCI_WIN7_OFFS 0x07000000 ++ ++#define AR71XX_PCI_CFG_BASE \ ++ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) ++#define AR71XX_PCI_CFG_SIZE 0x100 ++ ++#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 ++#define AR71XX_PCI_REG_CRP_WRDATA 0x04 ++#define AR71XX_PCI_REG_CRP_RDDATA 0x08 ++#define AR71XX_PCI_REG_CFG_AD 0x0c ++#define AR71XX_PCI_REG_CFG_CBE 0x10 ++#define AR71XX_PCI_REG_CFG_WRDATA 0x14 ++#define AR71XX_PCI_REG_CFG_RDDATA 0x18 ++#define AR71XX_PCI_REG_PCI_ERR 0x1c ++#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20 ++#define AR71XX_PCI_REG_AHB_ERR 0x24 ++#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28 ++ ++#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000 ++#define AR71XX_PCI_CRP_CMD_READ 0x00000000 ++#define AR71XX_PCI_CFG_CMD_READ 0x0000000a ++#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b ++ ++#define AR71XX_PCI_INT_CORE BIT(4) ++#define AR71XX_PCI_INT_DEV2 BIT(2) ++#define AR71XX_PCI_INT_DEV1 BIT(1) ++#define AR71XX_PCI_INT_DEV0 BIT(0) ++ ++#define AR71XX_PCI_IRQ_COUNT 5 ++ ++static DEFINE_SPINLOCK(ar71xx_pci_lock); ++static void __iomem *ar71xx_pcicfg_base; ++ ++/* Byte lane enable bits */ ++static const u8 ar71xx_pci_ble_table[4][4] = { ++ {0x0, 0xf, 0xf, 0xf}, ++ {0xe, 0xd, 0xb, 0x7}, ++ {0xc, 0xf, 0x3, 0xf}, ++ {0xf, 0xf, 0xf, 0xf}, ++}; ++ ++static const u32 ar71xx_pci_read_mask[8] = { ++ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 ++}; ++ ++static inline u32 ar71xx_pci_get_ble(int where, int size, int local) ++{ ++ u32 t; ++ ++ t = ar71xx_pci_ble_table[size & 3][where & 3]; ++ BUG_ON(t == 0xf); ++ t <<= (local) ? 20 : 4; ++ ++ return t; ++} ++ ++static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ u32 ret; ++ ++ if (!bus->number) { ++ /* type 0 */ ++ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | ++ (where & ~3); ++ } else { ++ /* type 1 */ ++ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) | ++ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; ++ } ++ ++ return ret; ++} ++ ++static int ar71xx_pci_check_error(int quiet) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 pci_err; ++ u32 ahb_err; ++ ++ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; ++ if (pci_err) { ++ if (!quiet) { ++ u32 addr; ++ ++ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); ++ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", ++ "PCI", pci_err, addr); ++ } ++ ++ /* clear PCI error status */ ++ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); ++ } ++ ++ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; ++ if (ahb_err) { ++ if (!quiet) { ++ u32 addr; ++ ++ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); ++ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", ++ "AHB", ahb_err, addr); ++ } ++ ++ /* clear AHB error status */ ++ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); ++ } ++ ++ return !!(ahb_err | pci_err); ++} ++ ++static inline void ar71xx_pci_local_write(int where, int size, u32 value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 ad_cbe; ++ ++ value = value << (8 * (where & 3)); ++ ++ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3); ++ ad_cbe |= ar71xx_pci_get_ble(where, size, 1); ++ ++ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); ++ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); ++} ++ ++static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, ++ unsigned int devfn, ++ int where, int size, u32 cmd) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 addr; ++ ++ addr = ar71xx_pci_bus_addr(bus, devfn, where); ++ ++ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); ++ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), ++ base + AR71XX_PCI_REG_CFG_CBE); ++ ++ return ar71xx_pci_check_error(1); ++} ++ ++static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ unsigned long flags; ++ u32 data; ++ int err; ++ int ret; ++ ++ ret = PCIBIOS_SUCCESSFUL; ++ data = ~0; ++ ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ AR71XX_PCI_CFG_CMD_READ); ++ if (err) ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ else ++ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); ++ ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ++ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; ++ ++ return ret; ++} ++ ++static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ unsigned long flags; ++ int err; ++ int ret; ++ ++ value = value << (8 * (where & 3)); ++ ret = PCIBIOS_SUCCESSFUL; ++ ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ AR71XX_PCI_CFG_CMD_WRITE); ++ if (err) ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ else ++ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); ++ ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ++ return ret; ++} ++ ++static struct pci_ops ar71xx_pci_ops = { ++ .read = ar71xx_pci_read_config, ++ .write = ar71xx_pci_write_config, ++}; ++ ++static struct resource ar71xx_pci_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ar71xx_pci_mem_resource = { ++ .name = "PCI memory space", ++ .start = AR71XX_PCI_MEM_BASE, ++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct pci_controller ar71xx_pci_controller = { ++ .pci_ops = &ar71xx_pci_ops, ++ .mem_resource = &ar71xx_pci_mem_resource, ++ .io_resource = &ar71xx_pci_io_resource, ++}; ++ ++static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base = ath79_reset_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ if (pending & AR71XX_PCI_INT_DEV0) ++ generic_handle_irq(ATH79_PCI_IRQ(0)); ++ ++ else if (pending & AR71XX_PCI_INT_DEV1) ++ generic_handle_irq(ATH79_PCI_IRQ(1)); ++ ++ else if (pending & AR71XX_PCI_INT_DEV2) ++ generic_handle_irq(ATH79_PCI_IRQ(2)); ++ ++ else if (pending & AR71XX_PCI_INT_CORE) ++ generic_handle_irq(ATH79_PCI_IRQ(4)); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar71xx_pci_irq_unmask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; ++ void __iomem *base = ath79_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ /* flush write */ ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} ++ ++static void ar71xx_pci_irq_mask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; ++ void __iomem *base = ath79_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ /* flush write */ ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} ++ ++static struct irq_chip ar71xx_pci_irq_chip = { ++ .name = "AR71XX PCI", ++ .irq_mask = ar71xx_pci_irq_mask, ++ .irq_unmask = ar71xx_pci_irq_unmask, ++ .irq_mask_ack = ar71xx_pci_irq_mask, ++}; ++ ++static __init void ar71xx_pci_irq_init(void) ++{ ++ void __iomem *base = ath79_reset_base; ++ int i; ++ ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); ++ ++ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); ++ ++ for (i = ATH79_PCI_IRQ_BASE; ++ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); ++} ++ ++static __init void ar71xx_pci_reset(void) ++{ ++ void __iomem *ddr_base = ath79_ddr_base; ++ ++ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); ++ mdelay(100); ++ ++ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); ++ mdelay(100); ++ ++ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); ++ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); ++ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); ++ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); ++ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); ++ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); ++ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); ++ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); ++ ++ mdelay(100); ++} ++ ++__init int ar71xx_pcibios_init(void) ++{ ++ u32 t; ++ ++ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); ++ if (ar71xx_pcicfg_base == NULL) ++ return -ENOMEM; ++ ++ ar71xx_pci_reset(); ++ ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE ++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ++ ar71xx_pci_local_write(PCI_COMMAND, 4, t); ++ ++ /* clear bus errors */ ++ ar71xx_pci_check_error(1); ++ ++ ar71xx_pci_irq_init(); ++ ++ register_pci_controller(&ar71xx_pci_controller); ++ ++ return 0; ++} diff --git a/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch b/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch deleted file mode 100644 index 17776ada90..0000000000 --- a/target/linux/ar71xx/patches-3.3/114-MIPS-ath79-get-rid-of-some-ifdefs-in-mach-ubnt-xm.c.patch +++ /dev/null @@ -1,63 +0,0 @@ -From adeefb0860e92f44c7d66d5fccdb217fccfb8a81 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 20 Nov 2011 10:19:08 +0100 -Subject: [PATCH 14/35] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c - -Remove a superfluous ifdef around an include. Also -reorganize the board setup code a bit, so another -ifdef can be removed. - -Signed-off-by: Gabor Juhos - -v2: - no changes ---- - arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++----------- - 1 files changed, 12 insertions(+), 11 deletions(-) - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -12,10 +12,7 @@ - - #include - #include -- --#ifdef CONFIG_PCI - #include --#endif /* CONFIG_PCI */ - - #include - -@@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pc - .pdata = &ubnt_xm_eeprom_data, - }, - }; -+ -+static void __init ubnt_xm_pci_init(void) -+{ -+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, -+ sizeof(ubnt_xm_eeprom_data.eeprom_data)); -+ -+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); -+ ath79_register_pci(); -+} -+#else -+static inline void ubnt_xm_pci_init(void) {} - #endif /* CONFIG_PCI */ - - static void __init ubnt_xm_init(void) -@@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void) - ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, - ARRAY_SIZE(ubnt_xm_spi_info)); - --#ifdef CONFIG_PCI -- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, -- sizeof(ubnt_xm_eeprom_data.eeprom_data)); -- -- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); --#endif /* CONFIG_PCI */ -- -- ath79_register_pci(); -+ ubnt_xm_pci_init(); - } - - MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch b/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch new file mode 100644 index 0000000000..7daaf1923b --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch @@ -0,0 +1,165 @@ +From fd1dd2f2c317bc0fc2c30fba440d911654bf592e Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:11 +0100 +Subject: [PATCH 20/47] MIPS: ath79: allow to use SoC specific PCI IRQ maps + +The PCI controllers in the AR71XX and in the +AR724X SoCs are different, and both of them +uses different IRQ wiring. + +The patch modifies the 'pcibios_map_irq' function +in order to allow to use different IRQ maps for +the different SoCs. The patch also adds a function, +which lets the board setup code to override the +default IRQ map. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3500/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++--- + arch/mips/ath79/pci.h | 9 ++++++ + 2 files changed, 77 insertions(+), 4 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -8,6 +8,7 @@ + * by the Free Software Foundation. + */ + ++#include + #include + #include + #include +@@ -15,9 +16,35 @@ + #include "pci.h" + + static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); ++static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; ++static unsigned ath79_pci_nr_irqs __initdata; + static struct ar724x_pci_data *pci_data; + static int pci_data_size; + ++static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { ++ { ++ .slot = 17, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, { ++ .slot = 18, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(1), ++ }, { ++ .slot = 19, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(2), ++ } ++}; ++ ++static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ } ++}; ++ + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) + { + pci_data = data; +@@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p + + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { +- unsigned int devfn = dev->devfn; + int irq = -1; ++ int i; + +- if (devfn > pci_data_size - 1) +- return irq; +- +- irq = pci_data[devfn].irq; ++ if (ath79_pci_nr_irqs == 0 || ++ ath79_pci_irq_map == NULL) { ++ if (soc_is_ar71xx()) { ++ ath79_pci_irq_map = ar71xx_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); ++ } else if (soc_is_ar724x()) { ++ ath79_pci_irq_map = ar724x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); ++ } else { ++ pr_crit("pci %s: invalid irq map\n", ++ pci_name((struct pci_dev *) dev)); ++ return irq; ++ } ++ } ++ ++ for (i = 0; i < ath79_pci_nr_irqs; i++) { ++ const struct ath79_pci_irq *entry; ++ ++ entry = &ath79_pci_irq_map[i]; ++ if (entry->slot == slot && entry->pin == pin) { ++ irq = entry->irq; ++ break; ++ } ++ } ++ ++ if (irq < 0) ++ pr_crit("pci %s: no irq found for pin %u\n", ++ pci_name((struct pci_dev *) dev), pin); ++ else ++ pr_info("pci %s: using irq %d for pin %u\n", ++ pci_name((struct pci_dev *) dev), irq, pin); + + return irq; + } +@@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev + return 0; + } + ++void __init ath79_pci_set_irq_map(unsigned nr_irqs, ++ const struct ath79_pci_irq *map) ++{ ++ ath79_pci_nr_irqs = nr_irqs; ++ ath79_pci_irq_map = map; ++} ++ + void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) + { + ath79_pci_plat_dev_init = func; +@@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init( + + int __init ath79_register_pci(void) + { ++ if (soc_is_ar71xx()) ++ return ar71xx_pcibios_init(); ++ + if (soc_is_ar724x()) + return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -15,13 +15,22 @@ struct ar724x_pci_data { + int irq; + }; + ++struct ath79_pci_irq { ++ u8 slot; ++ u8 pin; ++ int irq; ++}; ++ + void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); + + #ifdef CONFIG_PCI ++void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); + void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); + int ath79_register_pci(void); + #else + static inline void ++ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} ++static inline void + ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} + static inline int ath79_register_pci(void) { return 0; } + #endif diff --git a/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch b/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch deleted file mode 100644 index 91430a4a1a..0000000000 --- a/target/linux/ar71xx/patches-3.3/115-MIPS-ath79-allow-to-use-board-specific-pci_plat_dev_.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 83d74abc7d549f5d6292b0474be080983239c0bd Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 20 Nov 2011 10:29:36 +0100 -Subject: [PATCH 15/35] MIPS: ath79: allow to use board specific pci_plat_dev_init functions - -Th current implementation causes NULL pointer dereference -if 'pci_data' is not set: - -pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit] -pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI -address [0x10000000-0x1000ffff]) -CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4 -Oops[#1]: -Cpu 0 -$ 0 : 00000000 80420000 00000000 00000000 -$ 4 : 00000000 00000000 00000001 00000001 -$ 8 : 00000001 0000032c 81c54700 00000001 -$12 : 0000032d 0000000f 00000000 ffffffff -$16 : 81c14c00 00000001 802dac74 80195f98 -$20 : 802ea050 00000000 00000000 00000000 -$24 : 00000003 800617f0 -$28 : 81c20000 81c21e70 00000000 802e78a4 -Hi : 00000000 -Lo : 4190ab00 -epc : 802daca0 0x802daca0 - Not tainted -ra : 802e78a4 0x802e78a4 -Status: 1000c003 KERNEL EXL IE -Cause : 00800008 -BadVA : 00000000 -PrId : 00019374 (MIPS 24Kc) -Modules linked in: -Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) -Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000 - 802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290 - 80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000 - 00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000 - 00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000 - -This can be avoided by calling the 'ar724x_pci_add_data' -function from the board specific setup code. However it -makes no sense to use that function for every board, -especially when the board does not needs to set the -platform_data field of any PCI device. - -The patch allows the board setup code to specify a board -specific function if that is required. - -Signed-off-by: Gabor Juhos - -v2: - no changes - -The pci_irq_map function can throw another NULL pointer -dereference, that will be fixed in a subsequent patch. ---- - arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++- - arch/mips/ath79/pci.c | 14 ++++++++------ - arch/mips/ath79/pci.h | 4 +++- - 3 files changed, 23 insertions(+), 8 deletions(-) - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_x - static struct ar724x_pci_data ubnt_xm_pci_data[] = { - { - .irq = ATH79_PCI_IRQ(0), -- .pdata = &ubnt_xm_eeprom_data, - }, - }; - -+static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 0: -+ dev->dev.platform_data = &ubnt_xm_eeprom_data; -+ break; -+ } -+ -+ return 0; -+} -+ - static void __init ubnt_xm_pci_init(void) - { - memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, - sizeof(ubnt_xm_eeprom_data.eeprom_data)); - - ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); -+ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); - ath79_register_pci(); - } - #else ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -14,6 +14,7 @@ - #include - #include "pci.h" - -+static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); - static struct ar724x_pci_data *pci_data; - static int pci_data_size; - -@@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct - - int pcibios_plat_dev_init(struct pci_dev *dev) - { -- unsigned int devfn = dev->devfn; -- -- if (devfn > pci_data_size - 1) -- return PCIBIOS_DEVICE_NOT_FOUND; -+ if (ath79_pci_plat_dev_init) -+ return ath79_pci_plat_dev_init(dev); - -- dev->dev.platform_data = pci_data[devfn].pdata; -+ return 0; -+} - -- return PCIBIOS_SUCCESSFUL; -+void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) -+{ -+ ath79_pci_plat_dev_init = func; - } - - int __init ath79_register_pci(void) ---- a/arch/mips/ath79/pci.h -+++ b/arch/mips/ath79/pci.h -@@ -13,14 +13,16 @@ - - struct ar724x_pci_data { - int irq; -- void *pdata; - }; - - void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); - - #ifdef CONFIG_PCI -+void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); - int ath79_register_pci(void); - #else -+static inline void -+ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} - static inline int ath79_register_pci(void) { return 0; } - #endif - diff --git a/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch b/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch deleted file mode 100644 index 78e8bd56c6..0000000000 --- a/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch +++ /dev/null @@ -1,435 +0,0 @@ -From 9f6d46372cf2a493eaeeffbefe0a796379f838fa Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 22 Nov 2011 22:54:32 +0100 -Subject: [PATCH 16/35] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs - -The Atheros AR71XX SoCs have a built-in PCI Host Controller. -This patch adds a driver for that, and modifies the relevant -files in order to allow to register the PCI controller from -board specific setup. - -Signed-off-by: Gabor Juhos -Signed-off-by: Imre Kaloz - -v2: - add missing pci-ar71xx.c ---- - arch/mips/ath79/Kconfig | 1 + - arch/mips/include/asm/mach-ath79/pci.h | 6 + - arch/mips/pci/Makefile | 1 + - arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++ - 4 files changed, 383 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/pci/pci-ar71xx.c - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -52,6 +52,7 @@ endmenu - config SOC_AR71XX - select USB_ARCH_HAS_EHCI - select USB_ARCH_HAS_OHCI -+ select HW_HAS_PCI - def_bool n - - config SOC_AR724X ---- a/arch/mips/include/asm/mach-ath79/pci.h -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -11,6 +11,12 @@ - #ifndef __ASM_MACH_ATH79_PCI_H - #define __ASM_MACH_ATH79_PCI_H - -+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) -+int ar71xx_pcibios_init(void); -+#else -+static inline int ar71xx_pcibios_init(void) { return 0 }; -+#endif -+ - #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) - int ar724x_pcibios_init(int irq); - #else ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o - obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o -+obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o - obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o - - # ---- /dev/null -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -0,0 +1,375 @@ -+/* -+ * Atheros AR71xx PCI host controller driver -+ * -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define AR71XX_PCI_MEM_BASE 0x10000000 -+#define AR71XX_PCI_MEM_SIZE 0x08000000 -+ -+#define AR71XX_PCI_WIN0_OFFS 0x10000000 -+#define AR71XX_PCI_WIN1_OFFS 0x11000000 -+#define AR71XX_PCI_WIN2_OFFS 0x12000000 -+#define AR71XX_PCI_WIN3_OFFS 0x13000000 -+#define AR71XX_PCI_WIN4_OFFS 0x14000000 -+#define AR71XX_PCI_WIN5_OFFS 0x15000000 -+#define AR71XX_PCI_WIN6_OFFS 0x16000000 -+#define AR71XX_PCI_WIN7_OFFS 0x07000000 -+ -+#define AR71XX_PCI_CFG_BASE \ -+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) -+#define AR71XX_PCI_CFG_SIZE 0x100 -+ -+#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 -+#define AR71XX_PCI_REG_CRP_WRDATA 0x04 -+#define AR71XX_PCI_REG_CRP_RDDATA 0x08 -+#define AR71XX_PCI_REG_CFG_AD 0x0c -+#define AR71XX_PCI_REG_CFG_CBE 0x10 -+#define AR71XX_PCI_REG_CFG_WRDATA 0x14 -+#define AR71XX_PCI_REG_CFG_RDDATA 0x18 -+#define AR71XX_PCI_REG_PCI_ERR 0x1c -+#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20 -+#define AR71XX_PCI_REG_AHB_ERR 0x24 -+#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28 -+ -+#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000 -+#define AR71XX_PCI_CRP_CMD_READ 0x00000000 -+#define AR71XX_PCI_CFG_CMD_READ 0x0000000a -+#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b -+ -+#define AR71XX_PCI_INT_CORE BIT(4) -+#define AR71XX_PCI_INT_DEV2 BIT(2) -+#define AR71XX_PCI_INT_DEV1 BIT(1) -+#define AR71XX_PCI_INT_DEV0 BIT(0) -+ -+#define AR71XX_PCI_IRQ_COUNT 5 -+ -+static DEFINE_SPINLOCK(ar71xx_pci_lock); -+static void __iomem *ar71xx_pcicfg_base; -+ -+/* Byte lane enable bits */ -+static const u8 ar71xx_pci_ble_table[4][4] = { -+ {0x0, 0xf, 0xf, 0xf}, -+ {0xe, 0xd, 0xb, 0x7}, -+ {0xc, 0xf, 0x3, 0xf}, -+ {0xf, 0xf, 0xf, 0xf}, -+}; -+ -+static const u32 ar71xx_pci_read_mask[8] = { -+ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 -+}; -+ -+static inline u32 ar71xx_pci_get_ble(int where, int size, int local) -+{ -+ u32 t; -+ -+ t = ar71xx_pci_ble_table[size & 3][where & 3]; -+ BUG_ON(t == 0xf); -+ t <<= (local) ? 20 : 4; -+ -+ return t; -+} -+ -+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ u32 ret; -+ -+ if (!bus->number) { -+ /* type 0 */ -+ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | -+ (where & ~3); -+ } else { -+ /* type 1 */ -+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) | -+ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; -+ } -+ -+ return ret; -+} -+ -+static int ar71xx_pci_check_error(int quiet) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 pci_err; -+ u32 ahb_err; -+ -+ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; -+ if (pci_err) { -+ if (!quiet) { -+ u32 addr; -+ -+ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); -+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", -+ "PCI", pci_err, addr); -+ } -+ -+ /* clear PCI error status */ -+ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); -+ } -+ -+ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; -+ if (ahb_err) { -+ if (!quiet) { -+ u32 addr; -+ -+ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); -+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", -+ "AHB", ahb_err, addr); -+ } -+ -+ /* clear AHB error status */ -+ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); -+ } -+ -+ return !!(ahb_err | pci_err); -+} -+ -+static inline void ar71xx_pci_local_write(int where, int size, u32 value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 ad_cbe; -+ -+ value = value << (8 * (where & 3)); -+ -+ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3); -+ ad_cbe |= ar71xx_pci_get_ble(where, size, 1); -+ -+ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); -+ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); -+} -+ -+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, -+ unsigned int devfn, -+ int where, int size, u32 cmd) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 addr; -+ -+ addr = ar71xx_pci_bus_addr(bus, devfn, where); -+ -+ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); -+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), -+ base + AR71XX_PCI_REG_CFG_CBE); -+ -+ return ar71xx_pci_check_error(1); -+} -+ -+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ unsigned long flags; -+ u32 data; -+ int err; -+ int ret; -+ -+ ret = PCIBIOS_SUCCESSFUL; -+ data = ~0; -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ AR71XX_PCI_CFG_CMD_READ); -+ if (err) -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ else -+ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); -+ -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; -+ -+ return ret; -+} -+ -+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ unsigned long flags; -+ int err; -+ int ret; -+ -+ value = value << (8 * (where & 3)); -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ AR71XX_PCI_CFG_CMD_WRITE); -+ if (err) -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ else -+ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); -+ -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ return ret; -+} -+ -+static struct pci_ops ar71xx_pci_ops = { -+ .read = ar71xx_pci_read_config, -+ .write = ar71xx_pci_write_config, -+}; -+ -+static struct resource ar71xx_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar71xx_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar71xx_pci_controller = { -+ .pci_ops = &ar71xx_pci_ops, -+ .mem_resource = &ar71xx_pci_mem_resource, -+ .io_resource = &ar71xx_pci_io_resource, -+}; -+ -+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ath79_reset_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ if (pending & AR71XX_PCI_INT_DEV0) -+ generic_handle_irq(ATH79_PCI_IRQ(0)); -+ -+ else if (pending & AR71XX_PCI_INT_DEV1) -+ generic_handle_irq(ATH79_PCI_IRQ(1)); -+ -+ else if (pending & AR71XX_PCI_INT_DEV2) -+ generic_handle_irq(ATH79_PCI_IRQ(2)); -+ -+ else if (pending & AR71XX_PCI_INT_CORE) -+ generic_handle_irq(ATH79_PCI_IRQ(4)); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_pci_irq_unmask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; -+ void __iomem *base = ath79_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static void ar71xx_pci_irq_mask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; -+ void __iomem *base = ath79_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static struct irq_chip ar71xx_pci_irq_chip = { -+ .name = "AR71XX PCI", -+ .irq_mask = ar71xx_pci_irq_mask, -+ .irq_unmask = ar71xx_pci_irq_unmask, -+ .irq_mask_ack = ar71xx_pci_irq_mask, -+}; -+ -+static __init void ar71xx_pci_irq_init(void) -+{ -+ void __iomem *base = ath79_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); -+ -+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); -+ -+ for (i = ATH79_PCI_IRQ_BASE; -+ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); -+} -+ -+static __init void ar71xx_pci_reset(void) -+{ -+ void __iomem *ddr_base = ath79_ddr_base; -+ -+ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); -+ mdelay(100); -+ -+ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); -+ mdelay(100); -+ -+ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); -+ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); -+ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); -+ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); -+ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); -+ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); -+ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); -+ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); -+ -+ mdelay(100); -+} -+ -+__init int ar71xx_pcibios_init(void) -+{ -+ u32 t; -+ -+ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); -+ if (ar71xx_pcicfg_base == NULL) -+ return -ENOMEM; -+ -+ ar71xx_pci_reset(); -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE -+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; -+ ar71xx_pci_local_write(PCI_COMMAND, 4, t); -+ -+ /* clear bus errors */ -+ ar71xx_pci_check_error(1); -+ -+ ar71xx_pci_irq_init(); -+ -+ register_pci_controller(&ar71xx_pci_controller); -+ -+ return 0; -+} diff --git a/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-remove-ar724x_pci_add_data-function.patch b/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-remove-ar724x_pci_add_data-function.patch new file mode 100644 index 0000000000..70013c8d92 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/116-MIPS-ath79-remove-ar724x_pci_add_data-function.patch @@ -0,0 +1,86 @@ +From 29398cf1212afc9a6474127259cbb3a48d0751e5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:12 +0100 +Subject: [PATCH 21/47] MIPS: ath79: remove ar724x_pci_add_data function + +The variables set by this function are not used anymore. +Remove the function and the relevant variables as well. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3501/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-ubnt-xm.c | 7 ------- + arch/mips/ath79/pci.c | 8 -------- + arch/mips/ath79/pci.h | 6 ------ + 3 files changed, 0 insertions(+), 21 deletions(-) + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ub + #ifdef CONFIG_PCI + static struct ath9k_platform_data ubnt_xm_eeprom_data; + +-static struct ar724x_pci_data ubnt_xm_pci_data[] = { +- { +- .irq = ATH79_PCI_IRQ(0), +- }, +-}; +- + static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) + { + switch (PCI_SLOT(dev->devfn)) { +@@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void + memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, + sizeof(ubnt_xm_eeprom_data.eeprom_data)); + +- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); + ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); + ath79_register_pci(); + } +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -18,8 +18,6 @@ + static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); + static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; + static unsigned ath79_pci_nr_irqs __initdata; +-static struct ar724x_pci_data *pci_data; +-static int pci_data_size; + + static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { + { +@@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x + } + }; + +-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) +-{ +- pci_data = data; +- pci_data_size = size; +-} +- + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { + int irq = -1; +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -11,18 +11,12 @@ + #ifndef _ATH79_PCI_H + #define _ATH79_PCI_H + +-struct ar724x_pci_data { +- int irq; +-}; +- + struct ath79_pci_irq { + u8 slot; + u8 pin; + int irq; + }; + +-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); +- + #ifdef CONFIG_PCI + void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); + void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); diff --git a/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch b/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch deleted file mode 100644 index 251de55e54..0000000000 --- a/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-allow-to-use-SoC-specific-PCI-IRQ-maps.patch +++ /dev/null @@ -1,164 +0,0 @@ -From 8a1a5852aa7f8cfc027b2b0bb51cbbac4309e144 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 20 Nov 2011 14:32:09 +0100 -Subject: [PATCH 17/35] MIPS: ath79: allow to use SoC specific PCI IRQ maps - -The PCI controllers in the AR71XX and in the -AR724X SoCs are different, and both of them -uses different IRQ wiring. - -The patch modifies the 'pcibios_map_irq' function -in order to allow to use different IRQ maps for -the different SoCs. The patch also adds a function, -which lets the board setup code to override the -default IRQ map. - -Signed-off-by: Gabor Juhos - -v2: - no changes ---- - arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++--- - arch/mips/ath79/pci.h | 9 ++++++ - 2 files changed, 77 insertions(+), 4 deletions(-) - ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -8,6 +8,7 @@ - * by the Free Software Foundation. - */ - -+#include - #include - #include - #include -@@ -15,9 +16,35 @@ - #include "pci.h" - - static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); -+static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; -+static unsigned ath79_pci_nr_irqs __initdata; - static struct ar724x_pci_data *pci_data; - static int pci_data_size; - -+static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { -+ { -+ .slot = 17, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(0), -+ }, { -+ .slot = 18, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(1), -+ }, { -+ .slot = 19, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(2), -+ } -+}; -+ -+static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(0), -+ } -+}; -+ - void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) - { - pci_data = data; -@@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p - - int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) - { -- unsigned int devfn = dev->devfn; - int irq = -1; -+ int i; - -- if (devfn > pci_data_size - 1) -- return irq; -- -- irq = pci_data[devfn].irq; -+ if (ath79_pci_nr_irqs == 0 || -+ ath79_pci_irq_map == NULL) { -+ if (soc_is_ar71xx()) { -+ ath79_pci_irq_map = ar71xx_pci_irq_map; -+ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); -+ } else if (soc_is_ar724x()) { -+ ath79_pci_irq_map = ar724x_pci_irq_map; -+ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); -+ } else { -+ pr_crit("pci %s: invalid irq map\n", -+ pci_name((struct pci_dev *) dev)); -+ return irq; -+ } -+ } -+ -+ for (i = 0; i < ath79_pci_nr_irqs; i++) { -+ const struct ath79_pci_irq *entry; -+ -+ entry = &ath79_pci_irq_map[i]; -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) -+ pr_crit("pci %s: no irq found for pin %u\n", -+ pci_name((struct pci_dev *) dev), pin); -+ else -+ pr_info("pci %s: using irq %d for pin %u\n", -+ pci_name((struct pci_dev *) dev), irq, pin); - - return irq; - } -@@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev - return 0; - } - -+void __init ath79_pci_set_irq_map(unsigned nr_irqs, -+ const struct ath79_pci_irq *map) -+{ -+ ath79_pci_nr_irqs = nr_irqs; -+ ath79_pci_irq_map = map; -+} -+ - void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) - { - ath79_pci_plat_dev_init = func; -@@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init( - - int __init ath79_register_pci(void) - { -+ if (soc_is_ar71xx()) -+ return ar71xx_pcibios_init(); -+ - if (soc_is_ar724x()) - return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); - ---- a/arch/mips/ath79/pci.h -+++ b/arch/mips/ath79/pci.h -@@ -15,13 +15,22 @@ struct ar724x_pci_data { - int irq; - }; - -+struct ath79_pci_irq { -+ u8 slot; -+ u8 pin; -+ int irq; -+}; -+ - void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); - - #ifdef CONFIG_PCI -+void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); - void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); - int ath79_register_pci(void); - #else - static inline void -+ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} -+static inline void - ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} - static inline int ath79_register_pci(void) { return 0; } - #endif diff --git a/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch b/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch new file mode 100644 index 0000000000..969b79d8b2 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/117-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch @@ -0,0 +1,34 @@ +From 12db6a98b438a50799873bfd2b736a3b02a4bd57 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:13 +0100 +Subject: [PATCH 22/47] MIPS: ath79: register PCI controller on the PB44 board + +The PB44 reference board has two miniPCI slots. Register +the PCI controller to make those usable. + +Signed-off-by: Gabor Juhos +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3502/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/mach-pb44.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -19,6 +19,7 @@ + #include "dev-leds-gpio.h" + #include "dev-spi.h" + #include "dev-usb.h" ++#include "pci.h" + + #define PB44_GPIO_I2C_SCL 0 + #define PB44_GPIO_I2C_SDA 1 +@@ -114,6 +115,7 @@ static void __init pb44_init(void) + ath79_register_spi(&pb44_spi_data, pb44_spi_info, + ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); ++ ath79_register_pci(); + } + + MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-remove-ar724x_pci_add_data-function.patch b/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-remove-ar724x_pci_add_data-function.patch deleted file mode 100644 index 1ce9804370..0000000000 --- a/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-remove-ar724x_pci_add_data-function.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 0b026adc7a471edd018a060427e62d06e54be2bc Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 20 Nov 2011 15:50:32 +0100 -Subject: [PATCH 18/35] MIPS: ath79: remove ar724x_pci_add_data function - -The variables set by this function are not used anymore. -Remove the function and the relevant variables as well. - -Signed-off-by: Gabor Juhos - -v2: - no changes ---- - arch/mips/ath79/mach-ubnt-xm.c | 7 ------- - arch/mips/ath79/pci.c | 8 -------- - arch/mips/ath79/pci.h | 6 ------ - 3 files changed, 0 insertions(+), 21 deletions(-) - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ub - #ifdef CONFIG_PCI - static struct ath9k_platform_data ubnt_xm_eeprom_data; - --static struct ar724x_pci_data ubnt_xm_pci_data[] = { -- { -- .irq = ATH79_PCI_IRQ(0), -- }, --}; -- - static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) - { - switch (PCI_SLOT(dev->devfn)) { -@@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void - memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, - sizeof(ubnt_xm_eeprom_data.eeprom_data)); - -- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data)); - ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); - ath79_register_pci(); - } ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -18,8 +18,6 @@ - static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); - static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; - static unsigned ath79_pci_nr_irqs __initdata; --static struct ar724x_pci_data *pci_data; --static int pci_data_size; - - static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { - { -@@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x - } - }; - --void ar724x_pci_add_data(struct ar724x_pci_data *data, int size) --{ -- pci_data = data; -- pci_data_size = size; --} -- - int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) - { - int irq = -1; ---- a/arch/mips/ath79/pci.h -+++ b/arch/mips/ath79/pci.h -@@ -11,18 +11,12 @@ - #ifndef _ATH79_PCI_H - #define _ATH79_PCI_H - --struct ar724x_pci_data { -- int irq; --}; -- - struct ath79_pci_irq { - u8 slot; - u8 pin; - int irq; - }; - --void ar724x_pci_add_data(struct ar724x_pci_data *data, int size); -- - #ifdef CONFIG_PCI - void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); - void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); diff --git a/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch b/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch new file mode 100644 index 0000000000..da173a5f1d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/118-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch @@ -0,0 +1,71 @@ +From d3b5329b89d1bc733c56e4d609a89b429bf6cd4e Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:36:14 +0100 +Subject: [PATCH 23/47] MIPS: ath79: update copyright headers of PCI related files + +Add copyright records according to the recent changes in +the PCI code. Also fix up the descriptions. + +Signed-off-by: Gabor Juhos +Signed-off-by: Imre Kaloz +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/3503/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/pci.c | 4 ++++ + arch/mips/ath79/pci.h | 4 +++- + arch/mips/include/asm/mach-ath79/pci.h | 4 +++- + arch/mips/pci/pci-ar724x.c | 3 ++- + 4 files changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -2,6 +2,10 @@ + * Atheros AR71XX/AR724X specific PCI setup code + * + * Copyright (C) 2011 René Bolldorf ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +--- a/arch/mips/ath79/pci.h ++++ b/arch/mips/ath79/pci.h +@@ -1,7 +1,9 @@ + /* +- * Atheros 724x PCI support ++ * Atheros AR71XX/AR724X PCI support + * + * Copyright (C) 2011 René Bolldorf ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -1,7 +1,9 @@ + /* +- * Atheros 724x PCI support ++ * Atheros AR71XX/AR724X PCI support + * + * Copyright (C) 2011 René Bolldorf ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -1,7 +1,8 @@ + /* +- * Atheros 724x PCI support ++ * Atheros AR724X PCI host controller driver + * + * Copyright (C) 2011 René Bolldorf ++ * Copyright (C) 2009-2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published diff --git a/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-add-early_printk-support-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-add-early_printk-support-for-AR934X.patch new file mode 100644 index 0000000000..512f2da100 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-add-early_printk-support-for-AR934X.patch @@ -0,0 +1,56 @@ +From 5c1f1041309ede56d48eb3c665025e87c9824a64 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:19 +0100 +Subject: [PATCH 24/47] MIPS: ath79: add early_printk support for AR934X + +The patch allows to see kernel messages on AR934X SoCs in +early boot stage. + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3504/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/early_printk.c | 3 +++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++- + 2 files changed, 8 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -71,6 +71,9 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR7241: + case REV_ID_MAJOR_AR7242: + case REV_ID_MAJOR_AR913X: ++ case REV_ID_MAJOR_AR9341: ++ case REV_ID_MAJOR_AR9342: ++ case REV_ID_MAJOR_AR9344: + _prom_putchar = prom_putchar_ar71xx; + break; + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1,10 +1,11 @@ + /* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * +- * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +@@ -249,6 +250,9 @@ + #define REV_ID_MAJOR_AR7242 0x1100 + #define REV_ID_MAJOR_AR9330 0x0110 + #define REV_ID_MAJOR_AR9331 0x1110 ++#define REV_ID_MAJOR_AR9341 0x0120 ++#define REV_ID_MAJOR_AR9342 0x1120 ++#define REV_ID_MAJOR_AR9344 0x2120 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 + #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch b/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch deleted file mode 100644 index 36d17e9fa1..0000000000 --- a/target/linux/ar71xx/patches-3.3/119-MIPS-ath79-register-PCI-controller-on-the-PB44-board.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 1759a5bc87d0eb8dbb0d8a9794b336813057eb88 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Thu, 25 Nov 2010 17:59:28 +0100 -Subject: [PATCH 19/35] MIPS: ath79: register PCI controller on the PB44 board - -The PB44 reference board has two miniPCI slots. Register -the PCI controller to make those usable. - -Signed-off-by: Gabor Juhos - -v2: - no changes ---- - arch/mips/ath79/mach-pb44.c | 2 ++ - 1 files changed, 2 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/mach-pb44.c -+++ b/arch/mips/ath79/mach-pb44.c -@@ -19,6 +19,7 @@ - #include "dev-leds-gpio.h" - #include "dev-spi.h" - #include "dev-usb.h" -+#include "pci.h" - - #define PB44_GPIO_I2C_SCL 0 - #define PB44_GPIO_I2C_SDA 1 -@@ -114,6 +115,7 @@ static void __init pb44_init(void) - ath79_register_spi(&pb44_spi_data, pb44_spi_info, - ARRAY_SIZE(pb44_spi_info)); - ath79_register_usb(); -+ ath79_register_pci(); - } - - MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", diff --git a/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch b/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch new file mode 100644 index 0000000000..afbb04e4fc --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch @@ -0,0 +1,58 @@ +From ccb089bbbe49949063cc348743605b3d813ca1c0 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:20 +0100 +Subject: [PATCH 25/47] MIPS: ath79: sort case statements in ath79_detect_sys_type + +Sort the case statements alphabetically in order to improve +readability. + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3505/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/setup.c | 24 ++++++++++++------------ + 1 files changed, 12 insertions(+), 12 deletions(-) + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + +- case REV_ID_MAJOR_AR9330: +- ath79_soc = ATH79_SOC_AR9330; +- chip = "9330"; +- rev = id & AR933X_REV_ID_REVISION_MASK; +- break; +- +- case REV_ID_MAJOR_AR9331: +- ath79_soc = ATH79_SOC_AR9331; +- chip = "9331"; +- rev = id & AR933X_REV_ID_REVISION_MASK; +- break; +- + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; +@@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type + } + break; + ++ case REV_ID_MAJOR_AR9330: ++ ath79_soc = ATH79_SOC_AR9330; ++ chip = "9330"; ++ rev = id & AR933X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9331: ++ ath79_soc = ATH79_SOC_AR9331; ++ chip = "9331"; ++ rev = id & AR933X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } diff --git a/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch b/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch deleted file mode 100644 index 486e6f97c3..0000000000 --- a/target/linux/ar71xx/patches-3.3/120-MIPS-ath79-update-copyright-headers-of-PCI-related-f.patch +++ /dev/null @@ -1,77 +0,0 @@ -From e83c294ff219ff709b8179cbff64f293199a6dad Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 22 Nov 2011 21:13:58 +0100 -Subject: [PATCH 20/35] MIPS: ath79: update copyright headers of PCI related files - -Add copyright records according to the recent changes in -the PCI code. Also fix up the descriptions. - -Signed-off-by: Gabor Juhos -Signed-off-by: Imre Kaloz - -Just in case if someone is curious about why 2008 and 2009 years are -present in this change: - -The recent PCI specific changes were based on an existing -code which can be found in the OpenWrt repository, and we -are working on that since 2008. - -v2: - no changes ---- - arch/mips/ath79/pci.c | 4 ++++ - arch/mips/ath79/pci.h | 4 +++- - arch/mips/include/asm/mach-ath79/pci.h | 4 +++- - arch/mips/pci/pci-ar724x.c | 3 ++- - 4 files changed, 12 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -2,6 +2,10 @@ - * Atheros AR71XX/AR724X specific PCI setup code - * - * Copyright (C) 2011 René Bolldorf -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published ---- a/arch/mips/ath79/pci.h -+++ b/arch/mips/ath79/pci.h -@@ -1,7 +1,9 @@ - /* -- * Atheros 724x PCI support -+ * Atheros AR71XX/AR724X PCI support - * - * Copyright (C) 2011 René Bolldorf -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published ---- a/arch/mips/include/asm/mach-ath79/pci.h -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -1,7 +1,9 @@ - /* -- * Atheros 724x PCI support -+ * Atheros AR71XX/AR724X PCI support - * - * Copyright (C) 2011 René Bolldorf -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -1,7 +1,8 @@ - /* -- * Atheros 724x PCI support -+ * Atheros AR724X PCI host controller driver - * - * Copyright (C) 2011 René Bolldorf -+ * Copyright (C) 2009-2011 Gabor Juhos - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published diff --git a/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch new file mode 100644 index 0000000000..59bb3d8c5d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch @@ -0,0 +1,124 @@ +From bf5cb424312f28e51803286a53cb8613bedc5bc8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:21 +0100 +Subject: [PATCH 26/47] MIPS: ath79: add SoC detection code for AR934X + +Also add 'soc_is_ar934[124x]' helper functions and a Kconfig +symbol for the AR934X SoCs. + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3506/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/ath79/setup.c | 21 ++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++ + 4 files changed, 49 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -69,6 +69,10 @@ config SOC_AR933X + select USB_ARCH_HAS_EHCI + def_bool n + ++config SOC_AR934X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config ATH79_DEV_GPIO_BUTTONS + def_bool n + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -1,10 +1,11 @@ + /* + * Atheros AR71XX/AR724X/AR913X specific setup + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * +- * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_AR9341: ++ ath79_soc = ATH79_SOC_AR9341; ++ chip = "9341"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9342: ++ ath79_soc = ATH79_SOC_AR9342; ++ chip = "9342"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9344: ++ ath79_soc = ATH79_SOC_AR9344; ++ chip = "9344"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -271,6 +271,8 @@ + + #define AR724X_REV_ID_REVISION_MASK 0x3 + ++#define AR934X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -29,6 +29,9 @@ enum ath79_soc_type { + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, ++ ATH79_SOC_AR9341, ++ ATH79_SOC_AR9342, ++ ATH79_SOC_AR9344, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void) + ath79_soc == ATH79_SOC_AR9331); + } + ++static inline int soc_is_ar9341(void) ++{ ++ return (ath79_soc == ATH79_SOC_AR9341); ++} ++ ++static inline int soc_is_ar9342(void) ++{ ++ return (ath79_soc == ATH79_SOC_AR9342); ++} ++ ++static inline int soc_is_ar9344(void) ++{ ++ return (ath79_soc == ATH79_SOC_AR9344); ++} ++ ++static inline int soc_is_ar934x(void) ++{ ++ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; diff --git a/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-early_printk-support-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-early_printk-support-for-AR934X.patch deleted file mode 100644 index d22aedec6a..0000000000 --- a/target/linux/ar71xx/patches-3.3/121-MIPS-ath79-add-early_printk-support-for-AR934X.patch +++ /dev/null @@ -1,52 +0,0 @@ -From f60aed87f838ecfa4033ff1f63f97d05359b3b51 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 11 Dec 2011 17:36:08 +0100 -Subject: [PATCH 21/35] MIPS: ath79: add early_printk support for AR934X - -The patch allows to see kernel messages on AR934X SoCs in -early boot stage. - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/early_printk.c | 3 +++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++- - 2 files changed, 8 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -71,6 +71,9 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_AR7241: - case REV_ID_MAJOR_AR7242: - case REV_ID_MAJOR_AR913X: -+ case REV_ID_MAJOR_AR9341: -+ case REV_ID_MAJOR_AR9342: -+ case REV_ID_MAJOR_AR9344: - _prom_putchar = prom_putchar_ar71xx; - break; - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1,10 +1,11 @@ - /* - * Atheros AR71XX/AR724X/AR913X SoC register definitions - * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan - * Copyright (C) 2008-2010 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * -- * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published -@@ -249,6 +250,9 @@ - #define REV_ID_MAJOR_AR7242 0x1100 - #define REV_ID_MAJOR_AR9330 0x0110 - #define REV_ID_MAJOR_AR9331 0x1110 -+#define REV_ID_MAJOR_AR9341 0x0120 -+#define REV_ID_MAJOR_AR9342 0x1120 -+#define REV_ID_MAJOR_AR9344 0x2120 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 - #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch new file mode 100644 index 0000000000..39e161cc20 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch @@ -0,0 +1,198 @@ +From e9706fc0a97feb7992a98806b69a1fc1fcb910c7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:22 +0100 +Subject: [PATCH 27/47] MIPS: ath79: add clock initialization code for AR934X + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3507/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++ + 2 files changed, 134 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -1,8 +1,11 @@ + /* + * Atheros AR71XX/AR724X/AR913X common routines + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2011 Gabor Juhos + * ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo + ath79_uart_clk.rate = ath79_ref_clk.rate; + } + ++static void __init ar934x_clocks_init(void) ++{ ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) ++ ath79_ref_clk.rate = 40 * 1000 * 1000; ++ else ++ ath79_ref_clk.rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ath79_ref_clk.rate / ref_div; ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ath79_ref_clk.rate / ref_div; ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) ++ ath79_cpu_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); ++ else ++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) ++ ath79_ddr_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) ++ ath79_ahb_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); ++ ++ ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_uart_clk.rate = ath79_ref_clk.rate; ++} ++ + void __init ath79_clocks_init(void) + { + if (soc_is_ar71xx()) +@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void) + ar913x_clocks_init(); + else if (soc_is_ar933x()) + ar933x_clocks_init(); ++ else if (soc_is_ar934x()) ++ ar934x_clocks_init(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -151,6 +151,41 @@ + #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 + #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + ++#define AR934X_PLL_CPU_CONFIG_REG 0x00 ++#define AR934X_PLL_DDR_CONFIG_REG 0x04 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 ++ ++#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 ++ ++#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + /* + * USB_CONFIG block + */ +@@ -186,6 +221,8 @@ + #define AR933X_RESET_REG_RESET_MODULE 0x1c + #define AR933X_RESET_REG_BOOTSTRAP 0xac + ++#define AR934X_RESET_REG_BOOTSTRAP 0xb0 ++ + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) + #define MISC_INT_TIMER3 BIT(9) +@@ -242,6 +279,22 @@ + + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + ++#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) ++#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) ++#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) ++#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) ++#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) ++#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) ++#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) ++#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) ++#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) ++#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) ++#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) ++#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) ++#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) ++#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) ++#define AR934X_BOOTSTRAP_DDR1 BIT(0) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch b/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch deleted file mode 100644 index dc545330d6..0000000000 --- a/target/linux/ar71xx/patches-3.3/122-MIPS-ath79-sort-case-statements-in-ath79_detect_sys_.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 655a57ed2df5e34c32645e08c3244facba70ae5f Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 14:39:04 +0100 -Subject: [PATCH 22/35] MIPS: ath79: sort case statements in ath79_detect_sys_type - -Sort the case statements alphabetically in order to improve -readability. - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/setup.c | 24 ++++++++++++------------ - 1 files changed, 12 insertions(+), 12 deletions(-) - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type - rev = id & AR724X_REV_ID_REVISION_MASK; - break; - -- case REV_ID_MAJOR_AR9330: -- ath79_soc = ATH79_SOC_AR9330; -- chip = "9330"; -- rev = id & AR933X_REV_ID_REVISION_MASK; -- break; -- -- case REV_ID_MAJOR_AR9331: -- ath79_soc = ATH79_SOC_AR9331; -- chip = "9331"; -- rev = id & AR933X_REV_ID_REVISION_MASK; -- break; -- - case REV_ID_MAJOR_AR913X: - minor = id & AR913X_REV_ID_MINOR_MASK; - rev = id >> AR913X_REV_ID_REVISION_SHIFT; -@@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type - } - break; - -+ case REV_ID_MAJOR_AR9330: -+ ath79_soc = ATH79_SOC_AR9330; -+ chip = "9330"; -+ rev = id & AR933X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR9331: -+ ath79_soc = ATH79_SOC_AR9331; -+ chip = "9331"; -+ rev = id & AR933X_REV_ID_REVISION_MASK; -+ break; -+ - default: - panic("ath79: unknown SoC, id:0x%08x", id); - } diff --git a/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch new file mode 100644 index 0000000000..77c8d5a57c --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch @@ -0,0 +1,102 @@ +From 77bb01d1919bcb6787d5cde9056936420288ab34 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:23 +0100 +Subject: [PATCH 28/47] MIPS: ath79: add GPIO support code for AR934X + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3508/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 47 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -1,9 +1,12 @@ + /* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * +- * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s + return 0; + } + ++static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ ++static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ++ int value) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ if (value) ++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); ++ else ++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ + static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, +@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR913X_GPIO_COUNT; + else if (soc_is_ar933x()) + ath79_gpio_count = AR933X_GPIO_COUNT; ++ else if (soc_is_ar934x()) ++ ath79_gpio_count = AR934X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; ++ if (soc_is_ar934x()) { ++ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; ++ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; ++ } + + err = gpiochip_add(&ath79_gpio_chip); + if (err) +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -367,5 +367,6 @@ + #define AR724X_GPIO_COUNT 18 + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 ++#define AR934X_GPIO_COUNT 23 + + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch deleted file mode 100644 index f503ad1956..0000000000 --- a/target/linux/ar71xx/patches-3.3/123-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 9c19e86a7eccf8efd159ba213290830164f33a71 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 11 Dec 2011 17:36:42 +0100 -Subject: [PATCH 23/35] MIPS: ath79: add SoC detection code for AR934X - -Also add 'soc_is_ar934[124x]' helper functions and a Kconfig -symbol for the AR934X SoCs. - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/Kconfig | 4 ++++ - arch/mips/ath79/setup.c | 21 ++++++++++++++++++++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ - arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++ - 4 files changed, 49 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -69,6 +69,10 @@ config SOC_AR933X - select USB_ARCH_HAS_EHCI - def_bool n - -+config SOC_AR934X -+ select USB_ARCH_HAS_EHCI -+ def_bool n -+ - config ATH79_DEV_GPIO_BUTTONS - def_bool n - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -1,10 +1,11 @@ - /* - * Atheros AR71XX/AR724X/AR913X specific setup - * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * -- * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published -@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type - rev = id & AR933X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_AR9341: -+ ath79_soc = ATH79_SOC_AR9341; -+ chip = "9341"; -+ rev = id & AR934X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR9342: -+ ath79_soc = ATH79_SOC_AR9342; -+ chip = "9342"; -+ rev = id & AR934X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR9344: -+ ath79_soc = ATH79_SOC_AR9344; -+ chip = "9344"; -+ rev = id & AR934X_REV_ID_REVISION_MASK; -+ break; -+ - default: - panic("ath79: unknown SoC, id:0x%08x", id); - } ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -271,6 +271,8 @@ - - #define AR724X_REV_ID_REVISION_MASK 0x3 - -+#define AR934X_REV_ID_REVISION_MASK 0xf -+ - /* - * SPI block - */ ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -29,6 +29,9 @@ enum ath79_soc_type { - ATH79_SOC_AR9132, - ATH79_SOC_AR9330, - ATH79_SOC_AR9331, -+ ATH79_SOC_AR9341, -+ ATH79_SOC_AR9342, -+ ATH79_SOC_AR9344, - }; - - extern enum ath79_soc_type ath79_soc; -@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void) - ath79_soc == ATH79_SOC_AR9331); - } - -+static inline int soc_is_ar9341(void) -+{ -+ return (ath79_soc == ATH79_SOC_AR9341); -+} -+ -+static inline int soc_is_ar9342(void) -+{ -+ return (ath79_soc == ATH79_SOC_AR9342); -+} -+ -+static inline int soc_is_ar9344(void) -+{ -+ return (ath79_soc == ATH79_SOC_AR9344); -+} -+ -+static inline int soc_is_ar934x(void) -+{ -+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); -+} -+ - extern void __iomem *ath79_ddr_base; - extern void __iomem *ath79_pll_base; - extern void __iomem *ath79_reset_base; diff --git a/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch deleted file mode 100644 index fd7976faf0..0000000000 --- a/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch +++ /dev/null @@ -1,194 +0,0 @@ -From 783addfa256e79892f889e95ec5cda34f4e91eb7 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 20:36:32 +0100 -Subject: [PATCH 24/35] MIPS: ath79: add clock initialization code for AR934X - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++ - 2 files changed, 134 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -1,8 +1,11 @@ - /* - * Atheros AR71XX/AR724X/AR913X common routines - * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan - * Copyright (C) 2011 Gabor Juhos - * -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP -+ * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. -@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo - ath79_uart_clk.rate = ath79_ref_clk.rate; - } - -+static void __init ar934x_clocks_init(void) -+{ -+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) -+ ath79_ref_clk.rate = 40 * 1000 * 1000; -+ else -+ ath79_ref_clk.rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK; -+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & -+ AR934X_PLL_CPU_CONFIG_NINT_MASK; -+ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & -+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK; -+ -+ cpu_pll = nint * ath79_ref_clk.rate / ref_div; -+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK; -+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & -+ AR934X_PLL_DDR_CONFIG_NINT_MASK; -+ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & -+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK; -+ -+ ddr_pll = nint * ath79_ref_clk.rate / ref_div; -+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) -+ ath79_cpu_clk.rate = ath79_ref_clk.rate; -+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) -+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); -+ else -+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) -+ ath79_ddr_clk.rate = ath79_ref_clk.rate; -+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) -+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); -+ else -+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) -+ ath79_ahb_clk.rate = ath79_ref_clk.rate; -+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); -+ else -+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); -+ -+ ath79_wdt_clk.rate = ath79_ref_clk.rate; -+ ath79_uart_clk.rate = ath79_ref_clk.rate; -+} -+ - void __init ath79_clocks_init(void) - { - if (soc_is_ar71xx()) -@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void) - ar913x_clocks_init(); - else if (soc_is_ar933x()) - ar933x_clocks_init(); -+ else if (soc_is_ar934x()) -+ ar934x_clocks_init(); - else - BUG(); - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -151,6 +151,41 @@ - #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 - #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 - -+#define AR934X_PLL_CPU_CONFIG_REG 0x00 -+#define AR934X_PLL_DDR_CONFIG_REG 0x04 -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 -+ -+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 -+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f -+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 -+ -+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 -+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f -+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ - /* - * USB_CONFIG block - */ -@@ -186,6 +221,8 @@ - #define AR933X_RESET_REG_RESET_MODULE 0x1c - #define AR933X_RESET_REG_BOOTSTRAP 0xac - -+#define AR934X_RESET_REG_BOOTSTRAP 0xb0 -+ - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) - #define MISC_INT_TIMER3 BIT(9) -@@ -242,6 +279,22 @@ - - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - -+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) -+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) -+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) -+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) -+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) -+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) -+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) -+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) -+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) -+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) -+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) -+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) -+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -+#define AR934X_BOOTSTRAP_DDR1 BIT(0) -+ - #define REV_ID_MAJOR_MASK 0xfff0 - #define REV_ID_MAJOR_AR71XX 0x00a0 - #define REV_ID_MAJOR_AR913X 0x00b0 diff --git a/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch b/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch new file mode 100644 index 0000000000..0f30d3836f --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch @@ -0,0 +1,158 @@ +From f44c70eb5368c0742a8f401ccf39f2ba7252f5a7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:24 +0100 +Subject: [PATCH 29/47] MIPS: ath79: rework IP2/IP3 interrupt handling + +The current implementation assumes that flushing the +DDR writeback buffer is required for IP2/IP3 interrupts, +however this is not true for all SoCs. + +Use SoC specific IP2/IP3 handlers instead of flushing +the buffers in the dispatcher code. + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3509/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++----------- + 1 files changed, 72 insertions(+), 20 deletions(-) + +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -1,7 +1,7 @@ + /* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * +- * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP +@@ -23,8 +23,8 @@ + #include + #include "common.h" + +-static unsigned int ath79_ip2_flush_reg; +-static unsigned int ath79_ip3_flush_reg; ++static void (*ath79_ip2_handler)(void); ++static void (*ath79_ip3_handler)(void); + + static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) + { +@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void) + if (pending & STATUSF_IP7) + do_IRQ(ATH79_CPU_IRQ_TIMER); + +- else if (pending & STATUSF_IP2) { +- ath79_ddr_wb_flush(ath79_ip2_flush_reg); +- do_IRQ(ATH79_CPU_IRQ_IP2); +- } ++ else if (pending & STATUSF_IP2) ++ ath79_ip2_handler(); + + else if (pending & STATUSF_IP4) + do_IRQ(ATH79_CPU_IRQ_GE0); +@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void) + else if (pending & STATUSF_IP5) + do_IRQ(ATH79_CPU_IRQ_GE1); + +- else if (pending & STATUSF_IP3) { +- ath79_ddr_wb_flush(ath79_ip3_flush_reg); +- do_IRQ(ATH79_CPU_IRQ_USB); +- } ++ else if (pending & STATUSF_IP3) ++ ath79_ip3_handler(); + + else if (pending & STATUSF_IP6) + do_IRQ(ATH79_CPU_IRQ_MISC); +@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void) + spurious_interrupt(); + } + ++/* ++ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for ++ * these devices typically allocate coherent DMA memory, however the ++ * DMA controller may still have some unsynchronized data in the FIFO. ++ * Issue a flush in the handlers to ensure that the driver sees ++ * the update. ++ */ ++static void ar71xx_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar724x_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar913x_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar933x_ip2_handler(void) ++{ ++ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ ++static void ar71xx_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ ++static void ar724x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ ++static void ar913x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ ++static void ar933x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ + void __init arch_init_irq(void) + { + if (soc_is_ar71xx()) { +- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; +- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; ++ ath79_ip2_handler = ar71xx_ip2_handler; ++ ath79_ip3_handler = ar71xx_ip3_handler; + } else if (soc_is_ar724x()) { +- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; +- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; ++ ath79_ip2_handler = ar724x_ip2_handler; ++ ath79_ip3_handler = ar724x_ip3_handler; + } else if (soc_is_ar913x()) { +- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; +- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; ++ ath79_ip2_handler = ar913x_ip2_handler; ++ ath79_ip3_handler = ar913x_ip3_handler; + } else if (soc_is_ar933x()) { +- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; +- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; +- } else ++ ath79_ip2_handler = ar933x_ip2_handler; ++ ath79_ip3_handler = ar933x_ip3_handler; ++ } else { + BUG(); ++ } + + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); diff --git a/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch deleted file mode 100644 index f406db90e6..0000000000 --- a/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-GPIO-support-code-for-AR934X.patch +++ /dev/null @@ -1,98 +0,0 @@ -From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 20:53:47 +0100 -Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + - 2 files changed, 47 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -1,9 +1,12 @@ - /* - * Atheros AR71XX/AR724X/AR913X GPIO API support - * -- * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP -+ * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. -@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s - return 0; - } - -+static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+{ -+ void __iomem *base = ath79_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ath79_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), -+ base + AR71XX_GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ath79_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, -+ int value) -+{ -+ void __iomem *base = ath79_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ath79_gpio_lock, flags); -+ -+ if (value) -+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); -+ else -+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); -+ -+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), -+ base + AR71XX_GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ath79_gpio_lock, flags); -+ -+ return 0; -+} -+ - static struct gpio_chip ath79_gpio_chip = { - .label = "ath79", - .get = ath79_gpio_get_value, -@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void) - ath79_gpio_count = AR913X_GPIO_COUNT; - else if (soc_is_ar933x()) - ath79_gpio_count = AR933X_GPIO_COUNT; -+ else if (soc_is_ar934x()) -+ ath79_gpio_count = AR934X_GPIO_COUNT; - else - BUG(); - - ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); - ath79_gpio_chip.ngpio = ath79_gpio_count; -+ if (soc_is_ar934x()) { -+ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; -+ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; -+ } - - err = gpiochip_add(&ath79_gpio_chip); - if (err) ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -367,5 +367,6 @@ - #define AR724X_GPIO_COUNT 18 - #define AR913X_GPIO_COUNT 22 - #define AR933X_GPIO_COUNT 30 -+#define AR934X_GPIO_COUNT 23 - - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch new file mode 100644 index 0000000000..1268077255 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch @@ -0,0 +1,194 @@ +From b16fdecf14d24fe213c81409c0c2dca66d5b7bc9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:25 +0100 +Subject: [PATCH 30/47] MIPS: ath79: add IRQ handling code for AR934X + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3510/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++ + arch/mips/include/asm/mach-ath79/irq.h | 6 ++- + 3 files changed, 83 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -1,10 +1,11 @@ + /* + * Atheros AR71xx/AR724x/AR913x specific interrupt handling + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * +- * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published +@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; +- else if (soc_is_ar724x() || soc_is_ar933x()) ++ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else + BUG(); +@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v + irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); + } + ++static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); ++ ++ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { ++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE); ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { ++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC); ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } else { ++ spurious_interrupt(); ++ } ++ ++ enable_irq(irq); ++} ++ ++static void ar934x_ip2_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); ++} ++ + asmlinkage void plat_irq_dispatch(void) + { + unsigned long pending; +@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void) + do_IRQ(ATH79_CPU_IRQ_IP2); + } + ++static void ar934x_ip2_handler(void) ++{ ++ do_IRQ(ATH79_CPU_IRQ_IP2); ++} ++ + static void ar71xx_ip3_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); +@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void) + do_IRQ(ATH79_CPU_IRQ_USB); + } + ++static void ar934x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ_USB); ++} ++ + void __init arch_init_irq(void) + { + if (soc_is_ar71xx()) { +@@ -240,6 +285,9 @@ void __init arch_init_irq(void) + } else if (soc_is_ar933x()) { + ath79_ip2_handler = ar933x_ip2_handler; + ath79_ip3_handler = ar933x_ip3_handler; ++ } else if (soc_is_ar934x()) { ++ ath79_ip2_handler = ar934x_ip2_handler; ++ ath79_ip3_handler = ar934x_ip3_handler; + } else { + BUG(); + } +@@ -247,4 +295,7 @@ void __init arch_init_irq(void) + cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; + mips_cpu_irq_init(); + ath79_misc_irq_init(); ++ ++ if (soc_is_ar934x()) ++ ar934x_ip2_irq_init(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -92,6 +92,12 @@ + #define AR933X_DDR_REG_FLUSH_USB 0x84 + #define AR933X_DDR_REG_FLUSH_WMAC 0x88 + ++#define AR934X_DDR_REG_FLUSH_GE0 0x9c ++#define AR934X_DDR_REG_FLUSH_GE1 0xa0 ++#define AR934X_DDR_REG_FLUSH_USB 0xa4 ++#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 ++#define AR934X_DDR_REG_FLUSH_WMAC 0xac ++ + /* + * PLL block + */ +@@ -222,6 +228,7 @@ + #define AR933X_RESET_REG_BOOTSTRAP 0xac + + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 ++#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) +@@ -295,6 +302,24 @@ + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) ++#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) ++#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) ++#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) ++#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) ++#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ ++ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ ++ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) ++ ++#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ ++ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ ++ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ ++ AR934X_PCIE_WMAC_INT_PCIE_RC3) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,7 +10,7 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 46 ++#define NR_IRQS 48 + + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 +@@ -19,6 +19,10 @@ + #define ATH79_PCI_IRQ_COUNT 6 + #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) + ++#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT) ++#define ATH79_IP2_IRQ_COUNT 2 ++#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) ++ + #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) + #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) + #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) diff --git a/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch b/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch new file mode 100644 index 0000000000..14d4a27d16 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch @@ -0,0 +1,60 @@ +From 98bfbb0b3f126d93076377fcd9553a493e45e304 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:26 +0100 +Subject: [PATCH 31/47] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set} + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3511/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/common.c | 9 ++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 9 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -1,9 +1,12 @@ + /* + * Atheros AR71XX/AR724X/AR913X common routines + * +- * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * ++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; + else + BUG(); + +@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -227,6 +227,7 @@ + #define AR933X_RESET_REG_RESET_MODULE 0x1c + #define AR933X_RESET_REG_BOOTSTRAP 0xac + ++#define AR934X_RESET_REG_RESET_MODULE 0x1c + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + diff --git a/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch b/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch deleted file mode 100644 index 144acacf4a..0000000000 --- a/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch +++ /dev/null @@ -1,154 +0,0 @@ -From e69d89040d4884ea4069352338f555694e65fe70 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 21:30:03 +0100 -Subject: [PATCH 26/35] MIPS: ath79: rework IP2/IP3 interrupt handling - -The current implementation assumes that flushing the -DDR writeback buffer is required for IP2/IP3 interrupts, -however this is not true for all SoCs. - -Use SoC specific IP2/IP3 handlers instead of flushing -the buffers in the dispatcher code. - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++----------- - 1 files changed, 72 insertions(+), 20 deletions(-) - ---- a/arch/mips/ath79/irq.c -+++ b/arch/mips/ath79/irq.c -@@ -1,7 +1,7 @@ - /* - * Atheros AR71xx/AR724x/AR913x specific interrupt handling - * -- * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * - * Parts of this file are based on Atheros' 2.6.15 BSP -@@ -23,8 +23,8 @@ - #include - #include "common.h" - --static unsigned int ath79_ip2_flush_reg; --static unsigned int ath79_ip3_flush_reg; -+static void (*ath79_ip2_handler)(void); -+static void (*ath79_ip3_handler)(void); - - static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) - { -@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void) - if (pending & STATUSF_IP7) - do_IRQ(ATH79_CPU_IRQ_TIMER); - -- else if (pending & STATUSF_IP2) { -- ath79_ddr_wb_flush(ath79_ip2_flush_reg); -- do_IRQ(ATH79_CPU_IRQ_IP2); -- } -+ else if (pending & STATUSF_IP2) -+ ath79_ip2_handler(); - - else if (pending & STATUSF_IP4) - do_IRQ(ATH79_CPU_IRQ_GE0); -@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void) - else if (pending & STATUSF_IP5) - do_IRQ(ATH79_CPU_IRQ_GE1); - -- else if (pending & STATUSF_IP3) { -- ath79_ddr_wb_flush(ath79_ip3_flush_reg); -- do_IRQ(ATH79_CPU_IRQ_USB); -- } -+ else if (pending & STATUSF_IP3) -+ ath79_ip3_handler(); - - else if (pending & STATUSF_IP6) - do_IRQ(ATH79_CPU_IRQ_MISC); -@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void) - spurious_interrupt(); - } - -+/* -+ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for -+ * these devices typically allocate coherent DMA memory, however the -+ * DMA controller may still have some unsynchronized data in the FIFO. -+ * Issue a flush in the handlers to ensure that the driver sees -+ * the update. -+ */ -+static void ar71xx_ip2_handler(void) -+{ -+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); -+ do_IRQ(ATH79_CPU_IRQ_IP2); -+} -+ -+static void ar724x_ip2_handler(void) -+{ -+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); -+ do_IRQ(ATH79_CPU_IRQ_IP2); -+} -+ -+static void ar913x_ip2_handler(void) -+{ -+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); -+ do_IRQ(ATH79_CPU_IRQ_IP2); -+} -+ -+static void ar933x_ip2_handler(void) -+{ -+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); -+ do_IRQ(ATH79_CPU_IRQ_IP2); -+} -+ -+static void ar71xx_ip3_handler(void) -+{ -+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); -+ do_IRQ(ATH79_CPU_IRQ_USB); -+} -+ -+static void ar724x_ip3_handler(void) -+{ -+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); -+ do_IRQ(ATH79_CPU_IRQ_USB); -+} -+ -+static void ar913x_ip3_handler(void) -+{ -+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); -+ do_IRQ(ATH79_CPU_IRQ_USB); -+} -+ -+static void ar933x_ip3_handler(void) -+{ -+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); -+ do_IRQ(ATH79_CPU_IRQ_USB); -+} -+ - void __init arch_init_irq(void) - { - if (soc_is_ar71xx()) { -- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; -- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; -+ ath79_ip2_handler = ar71xx_ip2_handler; -+ ath79_ip3_handler = ar71xx_ip3_handler; - } else if (soc_is_ar724x()) { -- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; -- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; -+ ath79_ip2_handler = ar724x_ip2_handler; -+ ath79_ip3_handler = ar724x_ip3_handler; - } else if (soc_is_ar913x()) { -- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; -- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; -+ ath79_ip2_handler = ar913x_ip2_handler; -+ ath79_ip3_handler = ar913x_ip3_handler; - } else if (soc_is_ar933x()) { -- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; -- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; -- } else -+ ath79_ip2_handler = ar933x_ip2_handler; -+ ath79_ip3_handler = ar933x_ip3_handler; -+ } else { - BUG(); -+ } - - cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; - mips_cpu_irq_init(); diff --git a/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch deleted file mode 100644 index 083ca33189..0000000000 --- a/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 9db6021011556948d2d28d6957cee451bc2985aa Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 21:59:50 +0100 -Subject: [PATCH 27/35] MIPS: ath79: add IRQ handling code for AR934X - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++ - arch/mips/include/asm/mach-ath79/irq.h | 6 ++- - 3 files changed, 83 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/irq.c -+++ b/arch/mips/ath79/irq.c -@@ -1,10 +1,11 @@ - /* - * Atheros AR71xx/AR724x/AR913x specific interrupt handling - * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * -- * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published -@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v - - if (soc_is_ar71xx() || soc_is_ar913x()) - ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; -- else if (soc_is_ar724x() || soc_is_ar933x()) -+ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) - ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; - else - BUG(); -@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v - irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); - } - -+static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) -+{ -+ u32 status; -+ -+ disable_irq_nosync(irq); -+ -+ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); -+ -+ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { -+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE); -+ generic_handle_irq(ATH79_IP2_IRQ(0)); -+ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { -+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC); -+ generic_handle_irq(ATH79_IP2_IRQ(1)); -+ } else { -+ spurious_interrupt(); -+ } -+ -+ enable_irq(irq); -+} -+ -+static void ar934x_ip2_irq_init(void) -+{ -+ int i; -+ -+ for (i = ATH79_IP2_IRQ_BASE; -+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &dummy_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); -+} -+ - asmlinkage void plat_irq_dispatch(void) - { - unsigned long pending; -@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void) - do_IRQ(ATH79_CPU_IRQ_IP2); - } - -+static void ar934x_ip2_handler(void) -+{ -+ do_IRQ(ATH79_CPU_IRQ_IP2); -+} -+ - static void ar71xx_ip3_handler(void) - { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); -@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void) - do_IRQ(ATH79_CPU_IRQ_USB); - } - -+static void ar934x_ip3_handler(void) -+{ -+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); -+ do_IRQ(ATH79_CPU_IRQ_USB); -+} -+ - void __init arch_init_irq(void) - { - if (soc_is_ar71xx()) { -@@ -240,6 +285,9 @@ void __init arch_init_irq(void) - } else if (soc_is_ar933x()) { - ath79_ip2_handler = ar933x_ip2_handler; - ath79_ip3_handler = ar933x_ip3_handler; -+ } else if (soc_is_ar934x()) { -+ ath79_ip2_handler = ar934x_ip2_handler; -+ ath79_ip3_handler = ar934x_ip3_handler; - } else { - BUG(); - } -@@ -247,4 +295,7 @@ void __init arch_init_irq(void) - cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; - mips_cpu_irq_init(); - ath79_misc_irq_init(); -+ -+ if (soc_is_ar934x()) -+ ar934x_ip2_irq_init(); - } ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -92,6 +92,12 @@ - #define AR933X_DDR_REG_FLUSH_USB 0x84 - #define AR933X_DDR_REG_FLUSH_WMAC 0x88 - -+#define AR934X_DDR_REG_FLUSH_GE0 0x9c -+#define AR934X_DDR_REG_FLUSH_GE1 0xa0 -+#define AR934X_DDR_REG_FLUSH_USB 0xa4 -+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 -+#define AR934X_DDR_REG_FLUSH_WMAC 0xac -+ - /* - * PLL block - */ -@@ -222,6 +228,7 @@ - #define AR933X_RESET_REG_BOOTSTRAP 0xac - - #define AR934X_RESET_REG_BOOTSTRAP 0xb0 -+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) -@@ -295,6 +302,24 @@ - #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) - #define AR934X_BOOTSTRAP_DDR1 BIT(0) - -+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) -+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) -+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) -+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ -+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ -+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) -+ -+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ -+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ -+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ -+ AR934X_PCIE_WMAC_INT_PCIE_RC3) -+ - #define REV_ID_MAJOR_MASK 0xfff0 - #define REV_ID_MAJOR_AR71XX 0x00a0 - #define REV_ID_MAJOR_AR913X 0x00b0 ---- a/arch/mips/include/asm/mach-ath79/irq.h -+++ b/arch/mips/include/asm/mach-ath79/irq.h -@@ -10,7 +10,7 @@ - #define __ASM_MACH_ATH79_IRQ_H - - #define MIPS_CPU_IRQ_BASE 0 --#define NR_IRQS 46 -+#define NR_IRQS 48 - - #define ATH79_MISC_IRQ_BASE 8 - #define ATH79_MISC_IRQ_COUNT 32 -@@ -19,6 +19,10 @@ - #define ATH79_PCI_IRQ_COUNT 6 - #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x)) - -+#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT) -+#define ATH79_IP2_IRQ_COUNT 2 -+#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) -+ - #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) - #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) - #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) diff --git a/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch b/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch new file mode 100644 index 0000000000..2c7eecabf7 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch @@ -0,0 +1,27 @@ +From 2d4ed1c7405d05da812b67830eaac15f43b862b7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:27 +0100 +Subject: [PATCH 32/47] MIPS: ath79: register UART device for AR934X SoCs + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3512/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/dev-common.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -89,7 +89,8 @@ void __init ath79_register_uart(void) + + if (soc_is_ar71xx() || + soc_is_ar724x() || +- soc_is_ar913x()) { ++ soc_is_ar913x() || ++ soc_is_ar934x()) { + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { diff --git a/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch b/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch deleted file mode 100644 index dc9df92fcf..0000000000 --- a/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-AR934X-specific-glue-to-ath79_device_.patch +++ /dev/null @@ -1,56 +0,0 @@ -From da0f20f8a99de9193fc484a25d1f9edc913c98fd Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sat, 10 Dec 2011 20:09:39 +0100 -Subject: [PATCH 28/35] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set} - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/common.c | 9 ++++++++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + - 2 files changed, 9 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -1,9 +1,12 @@ - /* - * Atheros AR71XX/AR724X/AR913X common routines - * -- * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * -+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP -+ * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. -@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask) - reg = AR913X_RESET_REG_RESET_MODULE; - else if (soc_is_ar933x()) - reg = AR933X_RESET_REG_RESET_MODULE; -+ else if (soc_is_ar934x()) -+ reg = AR934X_RESET_REG_RESET_MODULE; - else - BUG(); - -@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask) - reg = AR913X_RESET_REG_RESET_MODULE; - else if (soc_is_ar933x()) - reg = AR933X_RESET_REG_RESET_MODULE; -+ else if (soc_is_ar934x()) -+ reg = AR934X_RESET_REG_RESET_MODULE; - else - BUG(); - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -227,6 +227,7 @@ - #define AR933X_RESET_REG_RESET_MODULE 0x1c - #define AR933X_RESET_REG_BOOTSTRAP 0xac - -+#define AR934X_RESET_REG_RESET_MODULE 0x1c - #define AR934X_RESET_REG_BOOTSTRAP 0xb0 - #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - diff --git a/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch new file mode 100644 index 0000000000..adbe3e4bb5 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/128-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch @@ -0,0 +1,116 @@ +From d677877e2688813e5e0c12d0228a631021ed70c4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:28 +0100 +Subject: [PATCH 33/47] MIPS: ath79: add WMAC registration code for AR934X + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3513/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Kconfig | 2 +- + arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++ + 3 files changed, 32 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -86,7 +86,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) + def_bool n + + endif +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -1,9 +1,12 @@ + /* + * Atheros AR913X/AR933X SoC built-in WMAC device support + * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * ++ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP ++ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. +@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resour + /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_MEM, + }, { +- .start = ATH79_CPU_IRQ_IP2, +- .end = ATH79_CPU_IRQ_IP2, ++ /* .start and .end fields are filled dynamically */ + .flags = IORESOURCE_IRQ, + }, + }; +@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(voi + + ath79_wmac_resources[0].start = AR913X_WMAC_BASE; + ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; + } + + +@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(voi + + ath79_wmac_resources[0].start = AR933X_WMAC_BASE; + ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (t & AR933X_BOOTSTRAP_REF_CLK_40) +@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(voi + ath79_wmac_data.external_reset = ar933x_wmac_reset; + } + ++static void ar934x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "ar934x_wmac"; ++ ++ ath79_wmac_resources[0].start = AR934X_WMAC_BASE; ++ ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (t & AR934X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data) + { + if (soc_is_ar913x()) + ar913x_wmac_setup(); + else if (soc_is_ar933x()) + ar933x_wmac_setup(); ++ else if (soc_is_ar934x()) ++ ar934x_wmac_setup(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -61,6 +61,9 @@ + #define AR933X_EHCI_BASE 0x1b000000 + #define AR933X_EHCI_SIZE 0x1000 + ++#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define AR934X_WMAC_SIZE 0x20000 ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch b/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch new file mode 100644 index 0000000000..27a46e6388 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch @@ -0,0 +1,66 @@ +From 27a5b2948831f4fd8e66e2e1a98b4c23902728cc Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:29 +0100 +Subject: [PATCH 34/47] MIPS: ath79: add PCI_AR724X Kconfig symbol + +The AR724X specific PCI code can be used for the +AR934X SoCs, however it can be selected only if +SOC_AR724X is set. + +Introduce a new Kconfig symbol in order to be able +to use the code for AR934X as well. + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3514/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/include/asm/mach-ath79/pci.h | 2 +- + arch/mips/pci/Makefile | 2 +- + 3 files changed, 6 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -59,6 +59,7 @@ config SOC_AR724X + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + select HW_HAS_PCI ++ select PCI_AR724X if PCI + def_bool n + + config SOC_AR913X +@@ -73,6 +74,9 @@ config SOC_AR934X + select USB_ARCH_HAS_EHCI + def_bool n + ++config PCI_AR724X ++ def_bool n ++ + config ATH79_DEV_GPIO_BUTTONS + def_bool n + +--- a/arch/mips/include/asm/mach-ath79/pci.h ++++ b/arch/mips/include/asm/mach-ath79/pci.h +@@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void); + static inline int ar71xx_pcibios_init(void) { return 0; } + #endif + +-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) ++#if defined(CONFIG_PCI_AR724X) + int ar724x_pcibios_init(int irq); + #else + static inline int ar724x_pcibios_init(int irq) { return 0; } +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o + obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o +-obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o ++obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o + + # + # These are still pretty much in the old state, watch, go blind. diff --git a/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch b/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch deleted file mode 100644 index db5ae6164a..0000000000 --- a/target/linux/ar71xx/patches-3.3/129-MIPS-ath79-register-UART-device-for-AR934X-SoCs.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 6b6803a249a27aa708bc5f24aa15270e30f3de61 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sat, 10 Dec 2011 19:55:05 +0100 -Subject: [PATCH 29/35] MIPS: ath79: register UART device for AR934X SoCs - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/dev-common.c | 3 ++- - 1 files changed, 2 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/dev-common.c -+++ b/arch/mips/ath79/dev-common.c -@@ -89,7 +89,8 @@ void __init ath79_register_uart(void) - - if (soc_is_ar71xx() || - soc_is_ar724x() || -- soc_is_ar913x()) { -+ soc_is_ar913x() || -+ soc_is_ar934x()) { - ath79_uart_data[0].uartclk = clk_get_rate(clk); - platform_device_register(&ath79_uart_device); - } else if (soc_is_ar933x()) { diff --git a/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch new file mode 100644 index 0000000000..bd9386d8c9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch @@ -0,0 +1,62 @@ +From 902b348cdddd4c858993e02aced615aa6caf04d0 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 10:45:30 +0100 +Subject: [PATCH 35/47] MIPS: ath79: add PCI registration code for AR934X + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3516/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Kconfig | 2 ++ + arch/mips/ath79/pci.c | 13 ++++++++++++- + 2 files changed, 14 insertions(+), 1 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -72,6 +72,8 @@ config SOC_AR933X + + config SOC_AR934X + select USB_ARCH_HAS_EHCI ++ select HW_HAS_PCI ++ select PCI_AR724X if PCI + def_bool n + + config PCI_AR724X +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -14,6 +14,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct + if (soc_is_ar71xx()) { + ath79_pci_irq_map = ar71xx_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); +- } else if (soc_is_ar724x()) { ++ } else if (soc_is_ar724x() || ++ soc_is_ar9342() || ++ soc_is_ar9344()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); + } else { +@@ -115,5 +118,13 @@ int __init ath79_register_pci(void) + if (soc_is_ar724x()) + return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + ++ if (soc_is_ar9342() || soc_is_ar9344()) { ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) ++ return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); ++ } ++ + return -ENODEV; + } diff --git a/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch deleted file mode 100644 index ca7c9289ca..0000000000 --- a/target/linux/ar71xx/patches-3.3/130-MIPS-ath79-add-WMAC-registration-code-for-AR934X.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 58b69cf52387a7351ec13b52d3d6a495fe611c29 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 22:07:23 +0100 -Subject: [PATCH 30/35] MIPS: ath79: add WMAC registration code for AR934X - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/Kconfig | 2 +- - arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++ - 3 files changed, 32 insertions(+), 3 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -86,7 +86,7 @@ config ATH79_DEV_USB - def_bool n - - config ATH79_DEV_WMAC -- depends on (SOC_AR913X || SOC_AR933X) -+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) - def_bool n - - endif ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -1,9 +1,12 @@ - /* - * Atheros AR913X/AR933X SoC built-in WMAC device support - * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan - * Copyright (C) 2008-2011 Gabor Juhos - * Copyright (C) 2008 Imre Kaloz - * -+ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP -+ * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. -@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resour - /* .start and .end fields are filled dynamically */ - .flags = IORESOURCE_MEM, - }, { -- .start = ATH79_CPU_IRQ_IP2, -- .end = ATH79_CPU_IRQ_IP2, -+ /* .start and .end fields are filled dynamically */ - .flags = IORESOURCE_IRQ, - }, - }; -@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(voi - - ath79_wmac_resources[0].start = AR913X_WMAC_BASE; - ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; -+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; -+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; - } - - -@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(voi - - ath79_wmac_resources[0].start = AR933X_WMAC_BASE; - ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; -+ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; -+ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; - - t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); - if (t & AR933X_BOOTSTRAP_REF_CLK_40) -@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(voi - ath79_wmac_data.external_reset = ar933x_wmac_reset; - } - -+static void ar934x_wmac_setup(void) -+{ -+ u32 t; -+ -+ ath79_wmac_device.name = "ar934x_wmac"; -+ -+ ath79_wmac_resources[0].start = AR934X_WMAC_BASE; -+ ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; -+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -+ -+ t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -+ if (t & AR934X_BOOTSTRAP_REF_CLK_40) -+ ath79_wmac_data.is_clk_25mhz = false; -+ else -+ ath79_wmac_data.is_clk_25mhz = true; -+} -+ - void __init ath79_register_wmac(u8 *cal_data) - { - if (soc_is_ar913x()) - ar913x_wmac_setup(); - else if (soc_is_ar933x()) - ar933x_wmac_setup(); -+ else if (soc_is_ar934x()) -+ ar934x_wmac_setup(); - else - BUG(); - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -61,6 +61,9 @@ - #define AR933X_EHCI_BASE 0x1b000000 - #define AR933X_EHCI_SIZE 0x1000 - -+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define AR934X_WMAC_SIZE 0x20000 -+ - /* - * DDR_CTRL block - */ diff --git a/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch deleted file mode 100644 index 7ac304fe81..0000000000 --- a/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 2d832612094b5592641364773c5ab2a3658f7120 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 11 Dec 2011 18:34:13 +0100 -Subject: [PATCH 31/35] MIPS: ath79: add USB platform setup code for AR934X - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/dev-usb.c | 28 +++++++++++++++++++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 35 ++++++++++++++++++++++++ - 2 files changed, 63 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -180,6 +180,32 @@ static void __init ar933x_usb_setup(void - platform_device_register(&ath79_ehci_device); - } - -+static void __init ar934x_usb_setup(void) -+{ -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) -+ return; -+ -+ ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE); -+ udelay(1000); -+ -+ ath79_device_reset_set(AR934X_RESET_USB_PHY); -+ udelay(1000); -+ -+ ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG); -+ udelay(1000); -+ -+ ath79_device_reset_set(AR934X_RESET_USB_HOST); -+ udelay(1000); -+ -+ ath79_ehci_resources[0].start = AR934X_EHCI_BASE; -+ ath79_ehci_resources[0].end = AR934X_EHCI_BASE + AR934X_EHCI_SIZE - 1; -+ ath79_ehci_device.name = "ar934x-ehci"; -+ platform_device_register(&ath79_ehci_device); -+} -+ - void __init ath79_register_usb(void) - { - if (soc_is_ar71xx()) -@@ -192,6 +218,8 @@ void __init ath79_register_usb(void) - ar913x_usb_setup(); - else if (soc_is_ar933x()) - ar933x_usb_setup(); -+ else if (soc_is_ar934x()) -+ ar934x_usb_setup(); - else - BUG(); - } ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -63,6 +63,8 @@ - - #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define AR934X_WMAC_SIZE 0x20000 -+#define AR934X_EHCI_BASE 0x1b000000 -+#define AR934X_EHCI_SIZE 0x1000 - - /* - * DDR_CTRL block -@@ -288,6 +290,39 @@ - #define AR933X_RESET_USB_PHY BIT(4) - #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) - -+#define AR934X_RESET_HOST BIT(31) -+#define AR934X_RESET_SLIC BIT(30) -+#define AR934X_RESET_HDMA BIT(29) -+#define AR934X_RESET_EXTERNAL BIT(28) -+#define AR934X_RESET_RTC BIT(27) -+#define AR934X_RESET_PCIE_EP_INT BIT(26) -+#define AR934X_RESET_CHKSUM_ACC BIT(25) -+#define AR934X_RESET_FULL_CHIP BIT(24) -+#define AR934X_RESET_GE1_MDIO BIT(23) -+#define AR934X_RESET_GE0_MDIO BIT(22) -+#define AR934X_RESET_CPU_NMI BIT(21) -+#define AR934X_RESET_CPU_COLD BIT(20) -+#define AR934X_RESET_HOST_RESET_INT BIT(19) -+#define AR934X_RESET_PCIE_EP BIT(18) -+#define AR934X_RESET_UART1 BIT(17) -+#define AR934X_RESET_DDR BIT(16) -+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -+#define AR934X_RESET_NANDF BIT(14) -+#define AR934X_RESET_GE1_MAC BIT(13) -+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) -+#define AR934X_RESET_USB_PHY_ANALOG BIT(11) -+#define AR934X_RESET_HOST_DMA_INT BIT(10) -+#define AR934X_RESET_GE0_MAC BIT(9) -+#define AR934X_RESET_ETH_SIWTCH BIT(8) -+#define AR934X_RESET_PCIE_PHY BIT(7) -+#define AR934X_RESET_PCIE BIT(6) -+#define AR934X_RESET_USB_HOST BIT(5) -+#define AR934X_RESET_USB_PHY BIT(4) -+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) -+#define AR934X_RESET_LUT BIT(2) -+#define AR934X_RESET_MBOX BIT(1) -+#define AR934X_RESET_I2S BIT(0) -+ - #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - - #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) diff --git a/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch b/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch new file mode 100644 index 0000000000..30c2c1b187 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/131-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch @@ -0,0 +1,196 @@ +From 4921cb7d9f6997b6f7aefd37c7cfd50324e8fd75 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 14 Mar 2012 20:39:35 +0100 +Subject: [PATCH 36/47] MIPS: ath79: add initial support for the Atheros DB120 board + +Signed-off-by: Gabor Juhos +Acked-by: Luis R. Rodriguez +Cc: linux-mips@linux-mips.org +Cc: mcgrof@infradead.org +Patchwork: https://patchwork.linux-mips.org/patch/3517/ +Signed-off-by: Ralf Baechle +--- + arch/mips/ath79/Kconfig | 12 ++++ + arch/mips/ath79/Makefile | 1 + + arch/mips/ath79/mach-db120.c | 134 ++++++++++++++++++++++++++++++++++++++++++ + arch/mips/ath79/machtypes.h | 1 + + 4 files changed, 148 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/ath79/mach-db120.c + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -26,6 +26,18 @@ config ATH79_MACH_AP81 + Say 'Y' here if you want your kernel to support the + Atheros AP81 reference board. + ++config ATH79_MACH_DB120 ++ bool "Atheros DB120 reference board" ++ select SOC_AR934X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros DB120 reference board. ++ + config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o + obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o +--- /dev/null ++++ b/arch/mips/ath79/mach-db120.c +@@ -0,0 +1,134 @@ ++/* ++ * Atheros DB120 reference board support ++ * ++ * Copyright (c) 2011 Qualcomm Atheros ++ * Copyright (c) 2011 Gabor Juhos ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++ ++#include "machtypes.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-spi.h" ++#include "dev-wmac.h" ++#include "pci.h" ++ ++#define DB120_GPIO_LED_WLAN_5G 12 ++#define DB120_GPIO_LED_WLAN_2G 13 ++#define DB120_GPIO_LED_STATUS 14 ++#define DB120_GPIO_LED_WPS 15 ++ ++#define DB120_GPIO_BTN_WPS 16 ++ ++#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) ++ ++#define DB120_WMAC_CALDATA_OFFSET 0x1000 ++#define DB120_PCIE_CALDATA_OFFSET 0x5000 ++ ++static struct gpio_led db120_leds_gpio[] __initdata = { ++ { ++ .name = "db120:green:status", ++ .gpio = DB120_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, ++ { ++ .name = "db120:green:wps", ++ .gpio = DB120_GPIO_LED_WPS, ++ .active_low = 1, ++ }, ++ { ++ .name = "db120:green:wlan-5g", ++ .gpio = DB120_GPIO_LED_WLAN_5G, ++ .active_low = 1, ++ }, ++ { ++ .name = "db120:green:wlan-2g", ++ .gpio = DB120_GPIO_LED_WLAN_2G, ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_keys_button db120_gpio_keys[] __initdata = { ++ { ++ .desc = "WPS button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DB120_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, ++}; ++ ++static struct spi_board_info db120_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "s25sl064a", ++ } ++}; ++ ++static struct ath79_spi_platform_data db120_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 1, ++}; ++ ++#ifdef CONFIG_PCI ++static struct ath9k_platform_data db120_ath9k_data; ++ ++static int db120_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &db120_ath9k_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++static void __init db120_pci_init(u8 *eeprom) ++{ ++ memcpy(db120_ath9k_data.eeprom_data, eeprom, ++ sizeof(db120_ath9k_data.eeprom_data)); ++ ++ ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); ++ ath79_register_pci(); ++} ++#else ++static inline void db120_pci_init(void) {} ++#endif /* CONFIG_PCI */ ++ ++static void __init db120_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), ++ db120_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(db120_gpio_keys), ++ db120_gpio_keys); ++ ath79_register_spi(&db120_spi_data, db120_spi_info, ++ ARRAY_SIZE(db120_spi_info)); ++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); ++ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); ++} ++ ++MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", ++ db120_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -18,6 +18,7 @@ enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ++ ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ + }; diff --git a/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch b/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch deleted file mode 100644 index 62e95df955..0000000000 --- a/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-add-PCI_AR724X-Kconfig-symbol.patch +++ /dev/null @@ -1,62 +0,0 @@ -From f299f36542f81f05cff7cdebb50abde202faf6df Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sat, 17 Dec 2011 10:04:18 +0100 -Subject: [PATCH 32/35] MIPS: ath79: add PCI_AR724X Kconfig symbol - -The AR724X specific PCI code can be used for the -AR934X SoCs, however it can be selected only if -SOC_AR724X is set. - -Introduce a new Kconfig symbol in order to be able -to use the code for AR934X as well. - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/Kconfig | 4 ++++ - arch/mips/include/asm/mach-ath79/pci.h | 2 +- - arch/mips/pci/Makefile | 2 +- - 3 files changed, 6 insertions(+), 2 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -59,6 +59,7 @@ config SOC_AR724X - select USB_ARCH_HAS_EHCI - select USB_ARCH_HAS_OHCI - select HW_HAS_PCI -+ select PCI_AR724X if PCI - def_bool n - - config SOC_AR913X -@@ -73,6 +74,9 @@ config SOC_AR934X - select USB_ARCH_HAS_EHCI - def_bool n - -+config PCI_AR724X -+ def_bool n -+ - config ATH79_DEV_GPIO_BUTTONS - def_bool n - ---- a/arch/mips/include/asm/mach-ath79/pci.h -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void); - static inline int ar71xx_pcibios_init(void) { return 0 }; - #endif - --#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X) -+#if defined(CONFIG_PCI_AR724X) - int ar724x_pcibios_init(int irq); - #else - static inline int ar724x_pcibios_init(int irq) { return 0 }; ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o - ops-bcm63xx.o - obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o - obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o --obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o -+obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. diff --git a/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-use-correct-IRQ-number-for-the-OHCI-contr.patch b/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-use-correct-IRQ-number-for-the-OHCI-contr.patch new file mode 100644 index 0000000000..07ddb512d6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/132-MIPS-ath79-use-correct-IRQ-number-for-the-OHCI-contr.patch @@ -0,0 +1,37 @@ +From fe0cc1327ddfb69b171102019a8148a9c8b352b8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 28 Mar 2012 11:00:19 +0200 +Subject: [PATCH 37/47] MIPS: ath79: use correct IRQ number for the OHCI controller on AR7240 + +The currently assigned IRQ number to the OHCI +controller is incorrect for the AR7240 SoC, and +that leads to the following error message from +the OHCI driver: + +ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +ath79-ohci ath79-ohci: Atheros built-in OHCI controller +ath79-ohci ath79-ohci: new USB bus registered, assigned bus number 1 +ath79-ohci ath79-ohci: irq 14, io mem 0x1b000000 +hub 1-0:1.0: USB hub found +hub 1-0:1.0: 1 port detected +usb 1-1: new full-speed USB device number 2 using ath79-ohci +ath79-ohci ath79-ohci: Unlink after no-IRQ? Controller is probably using the wrong IRQ. + +Fix this by using the correct IRQ number. + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/dev-usb.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -145,6 +145,8 @@ static void __init ar7240_usb_setup(void + + ath79_ohci_resources[0].start = AR7240_OHCI_BASE; + ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; ++ ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; ++ ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; + platform_device_register(&ath79_ohci_device); + } + diff --git a/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch deleted file mode 100644 index 7f168b33e7..0000000000 --- a/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch +++ /dev/null @@ -1,58 +0,0 @@ -From e30d942814a606c5258c7adafc6bbb49836573e9 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sat, 17 Dec 2011 10:13:08 +0100 -Subject: [PATCH 33/35] MIPS: ath79: add PCI registration code for AR934X - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/Kconfig | 2 ++ - arch/mips/ath79/pci.c | 13 ++++++++++++- - 2 files changed, 14 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -72,6 +72,8 @@ config SOC_AR933X - - config SOC_AR934X - select USB_ARCH_HAS_EHCI -+ select HW_HAS_PCI -+ select PCI_AR724X if PCI - def_bool n - - config PCI_AR724X ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -14,6 +14,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct - if (soc_is_ar71xx()) { - ath79_pci_irq_map = ar71xx_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); -- } else if (soc_is_ar724x()) { -+ } else if (soc_is_ar724x() || -+ soc_is_ar9342() || -+ soc_is_ar9344()) { - ath79_pci_irq_map = ar724x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); - } else { -@@ -115,5 +118,13 @@ int __init ath79_register_pci(void) - if (soc_is_ar724x()) - return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); - -+ if (soc_is_ar9342() || soc_is_ar9344()) { -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) -+ return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); -+ } -+ - return -ENODEV; - } diff --git a/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-use-a-helper-function-for-USB-resource-in.patch b/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-use-a-helper-function-for-USB-resource-in.patch new file mode 100644 index 0000000000..0def09f130 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/133-MIPS-ath79-use-a-helper-function-for-USB-resource-in.patch @@ -0,0 +1,140 @@ +From 30b15d9a4b05e38ae19e340b63e1a2bca917d557 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 28 Mar 2012 14:15:23 +0200 +Subject: [PATCH 38/47] MIPS: ath79: use a helper function for USB resource initialization + +This improves code readability, and ensures that +all resource fields will be initialized correctly. +Additionally, it helps to reduce the size of the +kernel image by using uninitialized resource +variables. + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/dev-usb.c | 64 +++++++++++++++++++------------------------- + 1 files changed, 28 insertions(+), 36 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -25,17 +25,7 @@ + #include "common.h" + #include "dev-usb.h" + +-static struct resource ath79_ohci_resources[] = { +- [0] = { +- /* .start and .end fields are filled dynamically */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = ATH79_MISC_IRQ_OHCI, +- .end = ATH79_MISC_IRQ_OHCI, +- .flags = IORESOURCE_IRQ, +- }, +-}; ++static struct resource ath79_ohci_resources[2]; + + static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); + +@@ -54,17 +44,7 @@ static struct platform_device ath79_ohci + }, + }; + +-static struct resource ath79_ehci_resources[] = { +- [0] = { +- /* .start and .end fields are filled dynamically */ +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = ATH79_CPU_IRQ_USB, +- .end = ATH79_CPU_IRQ_USB, +- .flags = IORESOURCE_IRQ, +- }, +-}; ++static struct resource ath79_ehci_resources[2]; + + static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); + +@@ -90,6 +70,20 @@ static struct platform_device ath79_ehci + }, + }; + ++static void __init ath79_usb_init_resource(struct resource res[2], ++ unsigned long base, ++ unsigned long size, ++ int irq) ++{ ++ res[0].flags = IORESOURCE_MEM; ++ res[0].start = base; ++ res[0].end = base + size - 1; ++ ++ res[1].flags = IORESOURCE_IRQ; ++ res[1].start = irq; ++ res[1].end = irq; ++} ++ + #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ + AR71XX_RESET_USB_PHY | \ + AR71XX_RESET_USB_OHCI_DLL) +@@ -114,12 +108,12 @@ static void __init ath79_usb_setup(void) + + mdelay(900); + +- ath79_ohci_resources[0].start = AR71XX_OHCI_BASE; +- ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, ++ AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); + platform_device_register(&ath79_ohci_device); + +- ath79_ehci_resources[0].start = AR71XX_EHCI_BASE; +- ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, ++ AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; + platform_device_register(&ath79_ehci_device); + } +@@ -143,10 +137,8 @@ static void __init ar7240_usb_setup(void + + iounmap(usb_ctrl_base); + +- ath79_ohci_resources[0].start = AR7240_OHCI_BASE; +- ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; +- ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; +- ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; ++ ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, ++ AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); + platform_device_register(&ath79_ohci_device); + } + +@@ -161,8 +153,8 @@ static void __init ar724x_usb_setup(void + ath79_device_reset_clear(AR724X_RESET_USB_PHY); + mdelay(10); + +- ath79_ehci_resources[0].start = AR724X_EHCI_BASE; +- ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, ++ AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -178,8 +170,8 @@ static void __init ar913x_usb_setup(void + ath79_device_reset_clear(AR913X_RESET_USB_PHY); + mdelay(10); + +- ath79_ehci_resources[0].start = AR913X_EHCI_BASE; +- ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, ++ AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -195,8 +187,8 @@ static void __init ar933x_usb_setup(void + ath79_device_reset_clear(AR933X_RESET_USB_PHY); + mdelay(10); + +- ath79_ehci_resources[0].start = AR933X_EHCI_BASE; +- ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1; ++ ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, ++ AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } diff --git a/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch b/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch new file mode 100644 index 0000000000..2a287ecaa6 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch @@ -0,0 +1,78 @@ +From 635d5a2ac8aa483c3a0635c60bff8ea8978ff6a7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Sun, 11 Dec 2011 18:34:13 +0100 +Subject: [PATCH 39/47] MIPS: ath79: add USB platform setup code for AR934X + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/dev-usb.c | 28 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 ++++++ + 2 files changed, 35 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -193,6 +193,32 @@ static void __init ar933x_usb_setup(void + platform_device_register(&ath79_ehci_device); + } + ++static void __init ar934x_usb_setup(void) ++{ ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) ++ return; ++ ++ ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); ++ udelay(1000); ++ ++ ath79_device_reset_clear(AR934X_RESET_USB_PHY); ++ udelay(1000); ++ ++ ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); ++ udelay(1000); ++ ++ ath79_device_reset_clear(AR934X_RESET_USB_HOST); ++ udelay(1000); ++ ++ ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, ++ AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; ++ platform_device_register(&ath79_ehci_device); ++} ++ + void __init ath79_register_usb(void) + { + if (soc_is_ar71xx()) +@@ -205,6 +231,8 @@ void __init ath79_register_usb(void) + ar913x_usb_setup(); + else if (soc_is_ar933x()) + ar933x_usb_setup(); ++ else if (soc_is_ar934x()) ++ ar934x_usb_setup(); + else + BUG(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -63,6 +63,8 @@ + + #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR934X_WMAC_SIZE 0x20000 ++#define AR934X_EHCI_BASE 0x1b000000 ++#define AR934X_EHCI_SIZE 0x1000 + + /* + * DDR_CTRL block +@@ -288,6 +290,11 @@ + #define AR933X_RESET_USB_PHY BIT(4) + #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + ++#define AR934X_RESET_USB_PHY_ANALOG BIT(11) ++#define AR934X_RESET_USB_HOST BIT(5) ++#define AR934X_RESET_USB_PHY BIT(4) ++#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) ++ + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + + #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) diff --git a/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch b/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch deleted file mode 100644 index 3f6c3e2adb..0000000000 --- a/target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch +++ /dev/null @@ -1,213 +0,0 @@ -From a01e8727327cf0fb6382ca8700a3a3f73d93202a Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 9 Dec 2011 22:23:02 +0100 -Subject: [PATCH 34/35] MIPS: ath79: add initial support for the Atheros DB120 board - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez ---- - arch/mips/ath79/Kconfig | 12 +++ - arch/mips/ath79/Makefile | 1 + - arch/mips/ath79/mach-db120.c | 155 ++++++++++++++++++++++++++++++++++++++++++ - arch/mips/ath79/machtypes.h | 1 + - 4 files changed, 169 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/ath79/mach-db120.c - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -26,6 +26,18 @@ config ATH79_MACH_AP81 - Say 'Y' here if you want your kernel to support the - Atheros AP81 reference board. - -+config ATH79_MACH_DB120 -+ bool "Atheros DB120 reference board" -+ select SOC_AR934X -+ select ATH79_DEV_GPIO_BUTTONS -+ select ATH79_DEV_LEDS_GPIO -+ select ATH79_DEV_SPI -+ select ATH79_DEV_USB -+ select ATH79_DEV_WMAC -+ help -+ Say 'Y' here if you want your kernel to support the -+ Atheros DB120 reference board. -+ - config ATH79_MACH_PB44 - bool "Atheros PB44 reference board" - select SOC_AR71XX ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma - # - obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o - obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o -+obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o - obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o - obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o ---- /dev/null -+++ b/arch/mips/ath79/mach-db120.c -@@ -0,0 +1,155 @@ -+/* -+ * Atheros DB120 reference board support -+ * -+ * Copyright (c) 2011 Qualcomm Atheros -+ * Copyright (c) 2011 Gabor Juhos -+ * -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted (subject to the limitations in the -+ * disclaimer below) provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of Qualcomm Atheros nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+ -+#include "machtypes.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-spi.h" -+#include "dev-usb.h" -+#include "dev-wmac.h" -+#include "pci.h" -+ -+#define DB120_GPIO_LED_WLAN_5G 12 -+#define DB120_GPIO_LED_WLAN_2G 13 -+#define DB120_GPIO_LED_STATUS 14 -+#define DB120_GPIO_LED_WPS 15 -+ -+#define DB120_GPIO_BTN_WPS 16 -+ -+#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) -+ -+#define DB120_WMAC_CALDATA_OFFSET 0x1000 -+#define DB120_PCIE_CALDATA_OFFSET 0x5000 -+ -+static struct gpio_led db120_leds_gpio[] __initdata = { -+ { -+ .name = "db120:green:status", -+ .gpio = DB120_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, -+ { -+ .name = "db120:green:wps", -+ .gpio = DB120_GPIO_LED_WPS, -+ .active_low = 1, -+ }, -+ { -+ .name = "db120:green:wlan-5g", -+ .gpio = DB120_GPIO_LED_WLAN_5G, -+ .active_low = 1, -+ }, -+ { -+ .name = "db120:green:wlan-2g", -+ .gpio = DB120_GPIO_LED_WLAN_2G, -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_keys_button db120_gpio_keys[] __initdata = { -+ { -+ .desc = "WPS button", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DB120_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, -+}; -+ -+static struct spi_board_info db120_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "s25sl064a", -+ } -+}; -+ -+static struct ath79_spi_platform_data db120_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 1, -+}; -+ -+#ifdef CONFIG_PCI -+static struct ath9k_platform_data db120_ath9k_data; -+ -+static int db120_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 0: -+ dev->dev.platform_data = &db120_ath9k_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void __init db120_pci_init(u8 *eeprom) -+{ -+ memcpy(db120_ath9k_data.eeprom_data, eeprom, -+ sizeof(db120_ath9k_data.eeprom_data)); -+ -+ ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); -+ ath79_register_pci(); -+} -+#else -+static inline void db120_pci_init(void) {} -+#endif /* CONFIG_PCI */ -+ -+static void __init db120_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), -+ db120_leds_gpio); -+ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(db120_gpio_keys), -+ db120_gpio_keys); -+ ath79_register_spi(&db120_spi_data, db120_spi_info, -+ ARRAY_SIZE(db120_spi_info)); -+ ath79_register_usb(); -+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); -+ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); -+} -+ -+MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", -+ db120_setup); ---- a/arch/mips/ath79/machtypes.h -+++ b/arch/mips/ath79/machtypes.h -@@ -18,6 +18,7 @@ enum ath79_mach_type { - ATH79_MACH_GENERIC = 0, - ATH79_MACH_AP121, /* Atheros AP121 reference board */ - ATH79_MACH_AP81, /* Atheros AP81 reference board */ -+ ATH79_MACH_DB120, /* Atheros DB120 reference board */ - ATH79_MACH_PB44, /* Atheros PB44 reference board */ - ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ - }; diff --git a/target/linux/ar71xx/patches-3.3/135-MIPS-ath79-register-USB-host-controller-on-the-DB120.patch b/target/linux/ar71xx/patches-3.3/135-MIPS-ath79-register-USB-host-controller-on-the-DB120.patch new file mode 100644 index 0000000000..e82da3daac --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/135-MIPS-ath79-register-USB-host-controller-on-the-DB120.patch @@ -0,0 +1,28 @@ +From 932c1688e960bff170f1fc8072b3d3e958407a60 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 13 Mar 2012 13:51:09 +0100 +Subject: [PATCH 40/47] MIPS: ath79: register USB host controller on the DB120 board + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/mach-db120.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -25,6 +25,7 @@ + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" ++#include "dev-usb.h" + #include "dev-wmac.h" + #include "pci.h" + +@@ -126,6 +127,7 @@ static void __init db120_setup(void) + db120_gpio_keys); + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); ++ ath79_register_usb(); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); + } diff --git a/target/linux/ar71xx/patches-3.3/135-USB-ehci-ath79-add-device_id-entry-for-the-AR934X-So.patch b/target/linux/ar71xx/patches-3.3/135-USB-ehci-ath79-add-device_id-entry-for-the-AR934X-So.patch deleted file mode 100644 index d84bf37b6e..0000000000 --- a/target/linux/ar71xx/patches-3.3/135-USB-ehci-ath79-add-device_id-entry-for-the-AR934X-So.patch +++ /dev/null @@ -1,41 +0,0 @@ -From cbf8930fe259777fb746f0387bf821729061c122 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 11 Dec 2011 22:09:20 +0100 -Subject: [PATCH 35/35] USB: ehci-ath79: add device_id entry for the AR934X SoCs - -Also make the USB_EHCI_ATH79 selectable for the AR934X SoCs. - -Signed-off-by: Gabor Juhos -Acked-by: Luis R. Rodriguez -Cc: Alan Stern -Cc: Greg Kroah-Hartman -Cc: linux-usb@vger.kernel.org ---- - drivers/usb/host/Kconfig | 2 +- - drivers/usb/host/ehci-ath79.c | 4 ++++ - 2 files changed, 5 insertions(+), 1 deletions(-) - ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -219,7 +219,7 @@ config USB_CNS3XXX_EHCI - - config USB_EHCI_ATH79 - bool "EHCI support for AR7XXX/AR9XXX SoCs" -- depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) -+ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X || SOC_AR934X) - select USB_EHCI_ROOT_HUB_TT - default y - ---help--- ---- a/drivers/usb/host/ehci-ath79.c -+++ b/drivers/usb/host/ehci-ath79.c -@@ -37,6 +37,10 @@ static const struct platform_device_id e - .driver_data = EHCI_ATH79_IP_V2, - }, - { -+ .name = "ar934x-ehci", -+ .driver_data = EHCI_ATH79_IP_V2, -+ }, -+ { - /* terminating entry */ - }, - }; diff --git a/target/linux/ar71xx/patches-3.3/200-spi-ath79-add-delay-between-SCK-changes.patch b/target/linux/ar71xx/patches-3.3/200-spi-ath79-add-delay-between-SCK-changes.patch new file mode 100644 index 0000000000..6b3b15b2df --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/200-spi-ath79-add-delay-between-SCK-changes.patch @@ -0,0 +1,122 @@ +From 5e5ffd34e38fbbfa0a78833f35aa3c4d5d77e122 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Jan 2012 20:06:35 +0100 +Subject: [PATCH 41/47] spi/ath79: add delay between SCK changes + +The driver uses the "as fast as it can" approach +to drive the SCK signal. However this does not +work with certain low speed SPI chips (e.g. the +PCF2123 RTC chip). Add per-bit slowdowns in order +to be able to use the driver with such chips as +well. + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-ath79.c | 44 +++++++++++++++++++++++++++++++++++++++++++- + 1 files changed, 43 insertions(+), 1 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -24,17 +24,24 @@ + #include + #include + #include ++#include ++#include + + #include + #include + + #define DRV_NAME "ath79-spi" + ++#define ATH79_SPI_RRW_DELAY_FACTOR 12000 ++#define MHZ (1000 * 1000) ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; + u32 reg_ctrl; + void __iomem *base; ++ struct clk *clk; ++ unsigned rrw_delay; + }; + + static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp + return spi_master_get_devdata(spi->master); + } + ++static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) ++{ ++ if (nsecs > sp->rrw_delay) ++ ndelay(nsecs - sp->rrw_delay); ++} ++ + static void ath79_spi_chipselect(struct spi_device *spi, int is_active) + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); +@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s + + /* setup MSB (to slave) on trailing edge */ + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); ++ ath79_spi_delay(sp, nsecs); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); ++ ath79_spi_delay(sp, nsecs); + + word <<= 1; + } +@@ -198,6 +213,7 @@ static __devinit int ath79_spi_probe(str + struct ath79_spi *sp; + struct ath79_spi_platform_data *pdata; + struct resource *r; ++ unsigned long rate; + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); +@@ -239,12 +255,36 @@ static __devinit int ath79_spi_probe(str + goto err_put_master; + } + ++ sp->clk = clk_get(&pdev->dev, "ahb"); ++ if (IS_ERR(sp->clk)) { ++ ret = PTR_ERR(sp->clk); ++ goto err_unmap; ++ } ++ ++ ret = clk_enable(sp->clk); ++ if (ret) ++ goto err_clk_put; ++ ++ rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); ++ if (!rate) { ++ ret = -EINVAL; ++ goto err_clk_disable; ++ } ++ ++ sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; ++ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", ++ sp->rrw_delay); ++ + ret = spi_bitbang_start(&sp->bitbang); + if (ret) +- goto err_unmap; ++ goto err_clk_disable; + + return 0; + ++err_clk_disable: ++ clk_disable(sp->clk); ++err_clk_put: ++ clk_put(sp->clk); + err_unmap: + iounmap(sp->base); + err_put_master: +@@ -259,6 +299,8 @@ static __devexit int ath79_spi_remove(st + struct ath79_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); ++ clk_disable(sp->clk); ++ clk_put(sp->clk); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); diff --git a/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-delay-between-SCK-changes.patch b/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-delay-between-SCK-changes.patch deleted file mode 100644 index 9294133d45..0000000000 --- a/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-delay-between-SCK-changes.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 8e948c035dd7983eccc3a889f2497e64044f3a31 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Wed, 11 Jan 2012 20:06:35 +0100 -Subject: [PATCH 1/7] spi/ath79: add delay between SCK changes - -The driver uses the "as fast as it can" approach -to drive the SCK signal. However this does not -work with certain low speed SPI chips (e.g. the -PCF2123 RTC chip). Add per-bit slowdowns in order -to be able to use the driver with such chips as -well. - -Signed-off-by: Gabor Juhos ---- - drivers/spi/spi-ath79.c | 44 +++++++++++++++++++++++++++++++++++++++++++- - 1 files changed, 43 insertions(+), 1 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -24,17 +24,24 @@ - #include - #include - #include -+#include -+#include - - #include - #include - - #define DRV_NAME "ath79-spi" - -+#define ATH79_SPI_RRW_DELAY_FACTOR 12000 -+#define MHZ (1000 * 1000) -+ - struct ath79_spi { - struct spi_bitbang bitbang; - u32 ioc_base; - u32 reg_ctrl; - void __iomem *base; -+ struct clk *clk; -+ unsigned rrw_delay; - }; - - static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) -@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp - return spi_master_get_devdata(spi->master); - } - -+static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) -+{ -+ if (nsecs > sp->rrw_delay) -+ ndelay(nsecs - sp->rrw_delay); -+} -+ - static void ath79_spi_chipselect(struct spi_device *spi, int is_active) - { - struct ath79_spi *sp = ath79_spidev_to_sp(spi); -@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s - - /* setup MSB (to slave) on trailing edge */ - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); -+ ath79_spi_delay(sp, nsecs); - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); -+ ath79_spi_delay(sp, nsecs); - - word <<= 1; - } -@@ -198,6 +213,7 @@ static __devinit int ath79_spi_probe(str - struct ath79_spi *sp; - struct ath79_spi_platform_data *pdata; - struct resource *r; -+ unsigned long rate; - int ret; - - master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -@@ -239,12 +255,36 @@ static __devinit int ath79_spi_probe(str - goto err_put_master; - } - -+ sp->clk = clk_get(&pdev->dev, "ahb"); -+ if (IS_ERR(sp->clk)) { -+ ret = PTR_ERR(sp->clk); -+ goto err_unmap; -+ } -+ -+ ret = clk_enable(sp->clk); -+ if (ret) -+ goto err_clk_put; -+ -+ rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); -+ if (!rate) { -+ ret = -EINVAL; -+ goto err_clk_disable; -+ } -+ -+ sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; -+ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", -+ sp->rrw_delay); -+ - ret = spi_bitbang_start(&sp->bitbang); - if (ret) -- goto err_unmap; -+ goto err_clk_disable; - - return 0; - -+err_clk_disable: -+ clk_disable(sp->clk); -+err_clk_put: -+ clk_put(sp->clk); - err_unmap: - iounmap(sp->base); - err_put_master: -@@ -259,6 +299,8 @@ static __devexit int ath79_spi_remove(st - struct ath79_spi *sp = platform_get_drvdata(pdev); - - spi_bitbang_stop(&sp->bitbang); -+ clk_disable(sp->clk); -+ clk_put(sp->clk); - iounmap(sp->base); - platform_set_drvdata(pdev, NULL); - spi_master_put(sp->bitbang.master); diff --git a/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch b/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch new file mode 100644 index 0000000000..4558a3dd6a --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch @@ -0,0 +1,21 @@ +From 52fa804e11c1722ec56de2e3888a9f8dfb96404b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Jan 2012 20:33:41 +0100 +Subject: [PATCH 42/47] spi/ath79: add missing HIGH->LOW SCK transition + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-ath79.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s + ath79_spi_delay(sp, nsecs); + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); + ath79_spi_delay(sp, nsecs); ++ if (bits == 1) ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); + + word <<= 1; + } diff --git a/target/linux/ar71xx/patches-3.3/202-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch b/target/linux/ar71xx/patches-3.3/202-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch deleted file mode 100644 index 08a76f5d27..0000000000 --- a/target/linux/ar71xx/patches-3.3/202-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch +++ /dev/null @@ -1,21 +0,0 @@ -From ea7e40aedae58b7a0f0ccd8658063de499734874 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Wed, 11 Jan 2012 20:33:41 +0100 -Subject: [PATCH 2/7] spi/ath79: add missing HIGH->LOW SCK transition - -Signed-off-by: Gabor Juhos ---- - drivers/spi/spi-ath79.c | 2 ++ - 1 files changed, 2 insertions(+), 0 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s - ath79_spi_delay(sp, nsecs); - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); - ath79_spi_delay(sp, nsecs); -+ if (bits == 1) -+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); - - word <<= 1; - } diff --git a/target/linux/ar71xx/patches-3.3/202-spi-ath79-remove-superfluous-chip-select-code.patch b/target/linux/ar71xx/patches-3.3/202-spi-ath79-remove-superfluous-chip-select-code.patch new file mode 100644 index 0000000000..8a12f5b9b9 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/202-spi-ath79-remove-superfluous-chip-select-code.patch @@ -0,0 +1,30 @@ +From 3ba7fd81798169e8d40bc7e4800c6a0e691c40b7 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Mon, 9 Jan 2012 15:03:28 +0100 +Subject: [PATCH 43/47] spi/ath79: remove superfluous chip select code + +The spi_bitbang driver calls the chipselect function +of the driver from spi_bitbang_setup in order to +deselect the given SPI chip, so we don't have to +initialize the CS line here. + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-ath79.c | 6 ------ + 1 files changed, 0 insertions(+), 6 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi + gpio_free(cdata->gpio); + return status; + } +- } else { +- if (spi->mode & SPI_CS_HIGH) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; +- else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; +- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + + return 0; diff --git a/target/linux/ar71xx/patches-3.3/203-spi-ath79-remove-superfluous-chip-select-code.patch b/target/linux/ar71xx/patches-3.3/203-spi-ath79-remove-superfluous-chip-select-code.patch deleted file mode 100644 index 02d283ccec..0000000000 --- a/target/linux/ar71xx/patches-3.3/203-spi-ath79-remove-superfluous-chip-select-code.patch +++ /dev/null @@ -1,30 +0,0 @@ -From ecf57a64feb737dec1da72aab21dccd30a88ba19 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 9 Jan 2012 15:03:28 +0100 -Subject: [PATCH 3/7] spi/ath79: remove superfluous chip select code - -The spi_bitbang driver calls the chipselect function -of the driver from spi_bitbang_setup in order to -deselect the given SPI chip, so we don't have to -initialize the CS line here. - -Signed-off-by: Gabor Juhos ---- - drivers/spi/spi-ath79.c | 6 ------ - 1 files changed, 0 insertions(+), 6 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi - gpio_free(cdata->gpio); - return status; - } -- } else { -- if (spi->mode & SPI_CS_HIGH) -- sp->ioc_base |= AR71XX_SPI_IOC_CS0; -- else -- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; -- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); - } - - return 0; diff --git a/target/linux/ar71xx/patches-3.3/203-spi-ath79-use-gpio_request_one.patch b/target/linux/ar71xx/patches-3.3/203-spi-ath79-use-gpio_request_one.patch new file mode 100644 index 0000000000..0c0ab63887 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/203-spi-ath79-use-gpio_request_one.patch @@ -0,0 +1,56 @@ +From 07f515fc0f69d18110cb2369e0b5d0fb4bdd7dfa Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Mon, 9 Jan 2012 15:04:21 +0100 +Subject: [PATCH 44/47] spi/ath79: use gpio_request_one + +Use gpio_request_one() instead of multiple gpiolib calls. + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-ath79.c | 26 +++++++++++++------------- + 1 files changed, 13 insertions(+), 13 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + struct ath79_spi_controller_data *cdata; ++ int status; + + cdata = spi->controller_data; + if (spi->chip_select && !cdata) +@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi + /* TODO: setup speed? */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + ++ status = 0; + if (spi->chip_select) { +- int status = 0; ++ unsigned long flags; + +- status = gpio_request(cdata->gpio, dev_name(&spi->dev)); +- if (status) +- return status; +- +- status = gpio_direction_output(cdata->gpio, +- spi->mode & SPI_CS_HIGH); +- if (status) { +- gpio_free(cdata->gpio); +- return status; +- } ++ flags = GPIOF_DIR_OUT; ++ if (spi->mode & SPI_CS_HIGH) ++ flags |= GPIOF_INIT_HIGH; ++ else ++ flags |= GPIOF_INIT_LOW; ++ ++ status = gpio_request_one(cdata->gpio, flags, ++ dev_name(&spi->dev)); + } + +- return 0; ++ return status; + } + + static void ath79_spi_cleanup_cs(struct spi_device *spi) diff --git a/target/linux/ar71xx/patches-3.3/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.3/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch new file mode 100644 index 0000000000..e318d887ea --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch @@ -0,0 +1,108 @@ +From 47fdda225880ab0aaa8a75f61991a72fade591ab Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Mon, 9 Jan 2012 15:00:46 +0100 +Subject: [PATCH 45/47] spi/ath79: avoid multiple initialization of the SPI controller + +Currently we are initializing the SPI controller in +the chip select line function, and that function is +called once for each SPI device on the bus. If a +board has multiple SPI devices, the controller will +be initialized multiple times. + +Introduce ath79_spi_{en,dis}able helper functions, +and call those from probe/response in order to avoid +the mutliple initialization of the controller. + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-ath79.c | 41 ++++++++++++++++++++++++----------------- + 1 files changed, 24 insertions(+), 17 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct + + } + +-static int ath79_spi_setup_cs(struct spi_device *spi) ++static void ath79_spi_enable(struct ath79_spi *sp) + { +- struct ath79_spi *sp = ath79_spidev_to_sp(spi); +- struct ath79_spi_controller_data *cdata; +- int status; +- +- cdata = spi->controller_data; +- if (spi->chip_select && !cdata) +- return -EINVAL; +- + /* enable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + +@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi + + /* TODO: setup speed? */ + ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); ++} ++ ++static void ath79_spi_disable(struct ath79_spi *sp) ++{ ++ /* restore CTRL register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++} ++ ++static int ath79_spi_setup_cs(struct spi_device *spi) ++{ ++ struct ath79_spi_controller_data *cdata; ++ int status; ++ ++ cdata = spi->controller_data; ++ if (spi->chip_select && !cdata) ++ return -EINVAL; + + status = 0; + if (spi->chip_select) { +@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- struct ath79_spi *sp = ath79_spidev_to_sp(spi); +- + if (spi->chip_select) { + struct ath79_spi_controller_data *cdata = spi->controller_data; + gpio_free(cdata->gpio); + } +- +- /* restore CTRL register */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); +- /* disable GPIO mode */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); + } + + static int ath79_spi_setup(struct spi_device *spi) +@@ -271,12 +274,15 @@ static __devinit int ath79_spi_probe(str + dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", + sp->rrw_delay); + ++ ath79_spi_enable(sp); + ret = spi_bitbang_start(&sp->bitbang); + if (ret) +- goto err_clk_disable; ++ goto err_disable; + + return 0; + ++err_disable: ++ ath79_spi_disable(sp); + err_clk_disable: + clk_disable(sp->clk); + err_clk_put: +@@ -295,6 +301,7 @@ static __devexit int ath79_spi_remove(st + struct ath79_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); ++ ath79_spi_disable(sp); + clk_disable(sp->clk); + clk_put(sp->clk); + iounmap(sp->base); diff --git a/target/linux/ar71xx/patches-3.3/204-spi-ath79-use-gpio_request_one.patch b/target/linux/ar71xx/patches-3.3/204-spi-ath79-use-gpio_request_one.patch deleted file mode 100644 index 6bdb85579d..0000000000 --- a/target/linux/ar71xx/patches-3.3/204-spi-ath79-use-gpio_request_one.patch +++ /dev/null @@ -1,56 +0,0 @@ -From dd5b424b0b3f0370f9b63594ad53c16989b6ad78 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 9 Jan 2012 15:04:21 +0100 -Subject: [PATCH 4/7] spi/ath79: use gpio_request_one - -Use gpio_request_one() instead of multiple gpiolib calls. - -Signed-off-by: Gabor Juhos ---- - drivers/spi/spi-ath79.c | 26 +++++++++++++------------- - 1 files changed, 13 insertions(+), 13 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi - { - struct ath79_spi *sp = ath79_spidev_to_sp(spi); - struct ath79_spi_controller_data *cdata; -+ int status; - - cdata = spi->controller_data; - if (spi->chip_select && !cdata) -@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi - /* TODO: setup speed? */ - ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); - -+ status = 0; - if (spi->chip_select) { -- int status = 0; -+ unsigned long flags; - -- status = gpio_request(cdata->gpio, dev_name(&spi->dev)); -- if (status) -- return status; -- -- status = gpio_direction_output(cdata->gpio, -- spi->mode & SPI_CS_HIGH); -- if (status) { -- gpio_free(cdata->gpio); -- return status; -- } -+ flags = GPIOF_DIR_OUT; -+ if (spi->mode & SPI_CS_HIGH) -+ flags |= GPIOF_INIT_HIGH; -+ else -+ flags |= GPIOF_INIT_LOW; -+ -+ status = gpio_request_one(cdata->gpio, flags, -+ dev_name(&spi->dev)); - } - -- return 0; -+ return status; - } - - static void ath79_spi_cleanup_cs(struct spi_device *spi) diff --git a/target/linux/ar71xx/patches-3.3/205-spi-ath79-add-shutdown-handler.patch b/target/linux/ar71xx/patches-3.3/205-spi-ath79-add-shutdown-handler.patch new file mode 100644 index 0000000000..aeb8540dd2 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/205-spi-ath79-add-shutdown-handler.patch @@ -0,0 +1,45 @@ +From 8f30eb1354f54684d1d09599b2466f1a0e69d9c3 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Jan 2012 22:19:32 +0100 +Subject: [PATCH 46/47] spi/ath79: add shutdown handler + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-ath79.c | 12 +++++++++++- + 1 files changed, 11 insertions(+), 1 deletions(-) + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -296,7 +296,7 @@ err_put_master: + return ret; + } + +-static __devexit int ath79_spi_remove(struct platform_device *pdev) ++static void __ath79_spi_remove(struct platform_device *pdev) + { + struct ath79_spi *sp = platform_get_drvdata(pdev); + +@@ -307,13 +307,23 @@ static __devexit int ath79_spi_remove(st + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); ++} + ++static __devexit int ath79_spi_remove(struct platform_device *pdev) ++{ ++ __ath79_spi_remove(pdev); + return 0; + } + ++static void ath79_spi_shutdown(struct platform_device *pdev) ++{ ++ __ath79_spi_remove(pdev); ++} ++ + static struct platform_driver ath79_spi_driver = { + .probe = ath79_spi_probe, + .remove = __devexit_p(ath79_spi_remove), ++ .shutdown = ath79_spi_shutdown, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, diff --git a/target/linux/ar71xx/patches-3.3/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.3/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch deleted file mode 100644 index 6230e5d97b..0000000000 --- a/target/linux/ar71xx/patches-3.3/205-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 25e681989198e94656eab9df22b8b761abd2ae26 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 9 Jan 2012 15:00:46 +0100 -Subject: [PATCH 5/7] spi/ath79: avoid multiple initialization of the SPI controller - -Currently we are initializing the SPI controller in -the chip select line function, and that function is -called once for each SPI device on the bus. If a -board has multiple SPI devices, the controller will -be initialized multiple times. - -Introduce ath79_spi_{en,dis}able helper functions, -and call those from probe/response in order to avoid -the mutliple initialization of the controller. - -Signed-off-by: Gabor Juhos ---- - drivers/spi/spi-ath79.c | 41 ++++++++++++++++++++++++----------------- - 1 files changed, 24 insertions(+), 17 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct - - } - --static int ath79_spi_setup_cs(struct spi_device *spi) -+static void ath79_spi_enable(struct ath79_spi *sp) - { -- struct ath79_spi *sp = ath79_spidev_to_sp(spi); -- struct ath79_spi_controller_data *cdata; -- int status; -- -- cdata = spi->controller_data; -- if (spi->chip_select && !cdata) -- return -EINVAL; -- - /* enable GPIO mode */ - ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); - -@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi - - /* TODO: setup speed? */ - ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); -+} -+ -+static void ath79_spi_disable(struct ath79_spi *sp) -+{ -+ /* restore CTRL register */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); -+} -+ -+static int ath79_spi_setup_cs(struct spi_device *spi) -+{ -+ struct ath79_spi_controller_data *cdata; -+ int status; -+ -+ cdata = spi->controller_data; -+ if (spi->chip_select && !cdata) -+ return -EINVAL; - - status = 0; - if (spi->chip_select) { -@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi - - static void ath79_spi_cleanup_cs(struct spi_device *spi) - { -- struct ath79_spi *sp = ath79_spidev_to_sp(spi); -- - if (spi->chip_select) { - struct ath79_spi_controller_data *cdata = spi->controller_data; - gpio_free(cdata->gpio); - } -- -- /* restore CTRL register */ -- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); -- /* disable GPIO mode */ -- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); - } - - static int ath79_spi_setup(struct spi_device *spi) -@@ -271,12 +274,15 @@ static __devinit int ath79_spi_probe(str - dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", - sp->rrw_delay); - -+ ath79_spi_enable(sp); - ret = spi_bitbang_start(&sp->bitbang); - if (ret) -- goto err_clk_disable; -+ goto err_disable; - - return 0; - -+err_disable: -+ ath79_spi_disable(sp); - err_clk_disable: - clk_disable(sp->clk); - err_clk_put: -@@ -295,6 +301,7 @@ static __devexit int ath79_spi_remove(st - struct ath79_spi *sp = platform_get_drvdata(pdev); - - spi_bitbang_stop(&sp->bitbang); -+ ath79_spi_disable(sp); - clk_disable(sp->clk); - clk_put(sp->clk); - iounmap(sp->base); diff --git a/target/linux/ar71xx/patches-3.3/206-spi-ath79-add-shutdown-handler.patch b/target/linux/ar71xx/patches-3.3/206-spi-ath79-add-shutdown-handler.patch deleted file mode 100644 index 93edda312b..0000000000 --- a/target/linux/ar71xx/patches-3.3/206-spi-ath79-add-shutdown-handler.patch +++ /dev/null @@ -1,45 +0,0 @@ -From e01dcc2835017b55e936bd150ddab29bfcf2c63c Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Wed, 11 Jan 2012 22:19:32 +0100 -Subject: [PATCH 6/7] spi/ath79: add shutdown handler - -Signed-off-by: Gabor Juhos ---- - drivers/spi/spi-ath79.c | 12 +++++++++++- - 1 files changed, 11 insertions(+), 1 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -296,7 +296,7 @@ err_put_master: - return ret; - } - --static __devexit int ath79_spi_remove(struct platform_device *pdev) -+static void __ath79_spi_remove(struct platform_device *pdev) - { - struct ath79_spi *sp = platform_get_drvdata(pdev); - -@@ -307,13 +307,23 @@ static __devexit int ath79_spi_remove(st - iounmap(sp->base); - platform_set_drvdata(pdev, NULL); - spi_master_put(sp->bitbang.master); -+} - -+static __devexit int ath79_spi_remove(struct platform_device *pdev) -+{ -+ __ath79_spi_remove(pdev); - return 0; - } - -+static void ath79_spi_shutdown(struct platform_device *pdev) -+{ -+ __ath79_spi_remove(pdev); -+} -+ - static struct platform_driver ath79_spi_driver = { - .probe = ath79_spi_probe, - .remove = __devexit_p(ath79_spi_remove), -+ .shutdown = ath79_spi_shutdown, - .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, diff --git a/target/linux/ar71xx/patches-3.3/206-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-3.3/206-spi-ath79-make-chipselect-logic-more-flexible.patch new file mode 100644 index 0000000000..9cf14b0a7d --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/206-spi-ath79-make-chipselect-logic-more-flexible.patch @@ -0,0 +1,288 @@ +From 16535fe56591ff85acd6776f53ff515799b037ba Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Jan 2012 22:25:11 +0100 +Subject: [PATCH 47/47] spi/ath79: make chipselect logic more flexible + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/mach-ap121.c | 6 ++ + arch/mips/ath79/mach-ap81.c | 6 ++ + arch/mips/ath79/mach-db120.c | 6 ++ + arch/mips/ath79/mach-pb44.c | 6 ++ + arch/mips/ath79/mach-ubnt-xm.c | 6 ++ + .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++- + drivers/spi/spi-ath79.c | 70 +++++++++++++------- + 7 files changed, 82 insertions(+), 26 deletions(-) + +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi + } + }; + ++static struct ath79_spi_controller_data ap121_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ap121_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l1606e", ++ .controller_data = &ap121_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio + } + }; + ++static struct ath79_spi_controller_data ap81_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ap81_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .controller_data = &ap81_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -76,12 +76,18 @@ static struct gpio_keys_button db120_gpi + }, + }; + ++static struct ath79_spi_controller_data db120_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info db120_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "s25sl064a", ++ .controller_data = &db120_spi0_data, + } + }; + +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio + } + }; + ++static struct ath79_spi_controller_data pb44_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .controller_data = &pb44_spi0_data, + }, + }; + +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + ++static struct ath79_spi_controller_data ubnt_xm_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info ubnt_xm_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "mx25l6405d", ++ .controller_data = &ubnt_xm_spi0_data, + } + }; + +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -16,8 +16,14 @@ struct ath79_spi_platform_data { + unsigned num_chipselect; + }; + ++enum ath79_spi_cs_type { ++ ATH79_SPI_CS_TYPE_INTERNAL, ++ ATH79_SPI_CS_TYPE_GPIO, ++}; ++ + struct ath79_spi_controller_data { +- unsigned gpio; ++ enum ath79_spi_cs_type cs_type; ++ unsigned cs_line; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -35,6 +35,8 @@ + #define ATH79_SPI_RRW_DELAY_FACTOR 12000 + #define MHZ (1000 * 1000) + ++#define ATH79_SPI_CS_LINE_MAX 2 ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; ++ struct ath79_spi_controller_data *cdata = spi->controller_data; + + if (is_active) { + /* set initial clock polarity */ +@@ -80,20 +83,21 @@ static void ath79_spi_chipselect(struct + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- +- /* SPI is normally active-low */ +- gpio_set_value(cdata->gpio, cs_high); +- } else { ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: + if (cs_high) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; ++ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line); + else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ++ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line); + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); +- } ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: ++ /* SPI is normally active-low */ ++ gpio_set_value(cdata->cs_line, cs_high); ++ break; ++ } + } + + static void ath79_spi_enable(struct ath79_spi *sp) +@@ -120,24 +124,30 @@ static void ath79_spi_disable(struct ath + static int ath79_spi_setup_cs(struct spi_device *spi) + { + struct ath79_spi_controller_data *cdata; ++ unsigned long flags; + int status; + + cdata = spi->controller_data; +- if (spi->chip_select && !cdata) ++ if (!cdata) + return -EINVAL; + + status = 0; +- if (spi->chip_select) { +- unsigned long flags; ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX) ++ status = -EINVAL; ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: + flags = GPIOF_DIR_OUT; + if (spi->mode & SPI_CS_HIGH) + flags |= GPIOF_INIT_HIGH; + else + flags |= GPIOF_INIT_LOW; + +- status = gpio_request_one(cdata->gpio, flags, ++ status = gpio_request_one(cdata->cs_line, flags, + dev_name(&spi->dev)); ++ break; + } + + return status; +@@ -145,9 +155,19 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- gpio_free(cdata->gpio); ++ struct ath79_spi_controller_data *cdata; ++ ++ cdata = spi->controller_data; ++ if (!cdata) ++ return; ++ ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ /* nothing to do */ ++ break; ++ case ATH79_SPI_CS_TYPE_GPIO: ++ gpio_free(cdata->cs_line); ++ break; + } + } + +@@ -155,6 +175,9 @@ static int ath79_spi_setup(struct spi_de + { + int status = 0; + ++ if (spi->controller_data == NULL) ++ return -EINVAL; ++ + if (spi->bits_per_word > 32) + return -EINVAL; + +@@ -215,6 +238,10 @@ static __devinit int ath79_spi_probe(str + unsigned long rate; + int ret; + ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; ++ + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); +@@ -224,17 +251,10 @@ static __devinit int ath79_spi_probe(str + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + +- pdata = pdev->dev.platform_data; +- + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; +- if (pdata) { +- master->bus_num = pdata->bus_num; +- master->num_chipselect = pdata->num_chipselect; +- } else { +- master->bus_num = -1; +- master->num_chipselect = 1; +- } ++ master->bus_num = pdata->bus_num; ++ master->num_chipselect = pdata->num_chipselect; + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ar71xx/patches-3.3/207-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-3.3/207-spi-ath79-make-chipselect-logic-more-flexible.patch deleted file mode 100644 index 08d544fc45..0000000000 --- a/target/linux/ar71xx/patches-3.3/207-spi-ath79-make-chipselect-logic-more-flexible.patch +++ /dev/null @@ -1,252 +0,0 @@ -From bdbd9b2861ba73557795915598bb276a8568d130 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Wed, 11 Jan 2012 22:25:11 +0100 -Subject: [PATCH 7/7] spi/ath79: make chipselect logic more flexible - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/mach-ap121.c | 6 ++ - arch/mips/ath79/mach-ap81.c | 6 ++ - arch/mips/ath79/mach-pb44.c | 6 ++ - arch/mips/ath79/mach-ubnt-xm.c | 6 ++ - .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++- - drivers/spi/spi-ath79.c | 63 ++++++++++++-------- - 6 files changed, 69 insertions(+), 26 deletions(-) - ---- a/arch/mips/ath79/mach-ap121.c -+++ b/arch/mips/ath79/mach-ap121.c -@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi - } - }; - -+static struct ath79_spi_controller_data ap121_spi0_data = { -+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, -+ .cs_line = 0, -+}; -+ - static struct spi_board_info ap121_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "mx25l1606e", -+ .controller_data = &ap121_spi0_data, - } - }; - ---- a/arch/mips/ath79/mach-ap81.c -+++ b/arch/mips/ath79/mach-ap81.c -@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio - } - }; - -+static struct ath79_spi_controller_data ap81_spi0_data = { -+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, -+ .cs_line = 0, -+}; -+ - static struct spi_board_info ap81_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p64", -+ .controller_data = &ap81_spi0_data, - } - }; - ---- a/arch/mips/ath79/mach-pb44.c -+++ b/arch/mips/ath79/mach-pb44.c -@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio - } - }; - -+static struct ath79_spi_controller_data pb44_spi0_data = { -+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, -+ .cs_line = 0, -+}; -+ - static struct spi_board_info pb44_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p64", -+ .controller_data = &pb44_spi0_data, - }, - }; - ---- a/arch/mips/ath79/mach-ubnt-xm.c -+++ b/arch/mips/ath79/mach-ubnt-xm.c -@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g - } - }; - -+static struct ath79_spi_controller_data ubnt_xm_spi0_data = { -+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, -+ .cs_line = 0, -+}; -+ - static struct spi_board_info ubnt_xm_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "mx25l6405d", -+ .controller_data = &ubnt_xm_spi0_data, - } - }; - ---- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h -+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h -@@ -16,8 +16,14 @@ struct ath79_spi_platform_data { - unsigned num_chipselect; - }; - -+enum ath79_spi_cs_type { -+ ATH79_SPI_CS_TYPE_INTERNAL, -+ ATH79_SPI_CS_TYPE_GPIO, -+}; -+ - struct ath79_spi_controller_data { -- unsigned gpio; -+ enum ath79_spi_cs_type cs_type; -+ unsigned cs_line; - }; - - #endif /* _ATH79_SPI_PLATFORM_H */ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -35,6 +35,8 @@ - #define ATH79_SPI_RRW_DELAY_FACTOR 12000 - #define MHZ (1000 * 1000) - -+#define ATH79_SPI_CS_LINE_MAX 2 -+ - struct ath79_spi { - struct spi_bitbang bitbang; - u32 ioc_base; -@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct - { - struct ath79_spi *sp = ath79_spidev_to_sp(spi); - int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; -+ struct ath79_spi_controller_data *cdata = spi->controller_data; - - if (is_active) { - /* set initial clock polarity */ -@@ -80,20 +83,21 @@ static void ath79_spi_chipselect(struct - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); - } - -- if (spi->chip_select) { -- struct ath79_spi_controller_data *cdata = spi->controller_data; -- -- /* SPI is normally active-low */ -- gpio_set_value(cdata->gpio, cs_high); -- } else { -+ switch (cdata->cs_type) { -+ case ATH79_SPI_CS_TYPE_INTERNAL: - if (cs_high) -- sp->ioc_base |= AR71XX_SPI_IOC_CS0; -+ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line); - else -- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; -+ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line); - - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); -- } -+ break; - -+ case ATH79_SPI_CS_TYPE_GPIO: -+ /* SPI is normally active-low */ -+ gpio_set_value(cdata->cs_line, cs_high); -+ break; -+ } - } - - static void ath79_spi_enable(struct ath79_spi *sp) -@@ -120,24 +124,30 @@ static void ath79_spi_disable(struct ath - static int ath79_spi_setup_cs(struct spi_device *spi) - { - struct ath79_spi_controller_data *cdata; -+ unsigned long flags; - int status; - - cdata = spi->controller_data; -- if (spi->chip_select && !cdata) -+ if (!cdata) - return -EINVAL; - - status = 0; -- if (spi->chip_select) { -- unsigned long flags; -+ switch (cdata->cs_type) { -+ case ATH79_SPI_CS_TYPE_INTERNAL: -+ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX) -+ status = -EINVAL; -+ break; - -+ case ATH79_SPI_CS_TYPE_GPIO: - flags = GPIOF_DIR_OUT; - if (spi->mode & SPI_CS_HIGH) - flags |= GPIOF_INIT_HIGH; - else - flags |= GPIOF_INIT_LOW; - -- status = gpio_request_one(cdata->gpio, flags, -+ status = gpio_request_one(cdata->cs_line, flags, - dev_name(&spi->dev)); -+ break; - } - - return status; -@@ -145,9 +155,15 @@ static int ath79_spi_setup_cs(struct spi - - static void ath79_spi_cleanup_cs(struct spi_device *spi) - { -- if (spi->chip_select) { -- struct ath79_spi_controller_data *cdata = spi->controller_data; -- gpio_free(cdata->gpio); -+ struct ath79_spi_controller_data *cdata = spi->controller_data; -+ -+ switch (cdata->cs_type) { -+ case ATH79_SPI_CS_TYPE_INTERNAL: -+ /* nothing to do */ -+ break; -+ case ATH79_SPI_CS_TYPE_GPIO: -+ gpio_free(cdata->cs_line); -+ break; - } - } - -@@ -215,6 +231,10 @@ static __devinit int ath79_spi_probe(str - unsigned long rate; - int ret; - -+ pdata = pdev->dev.platform_data; -+ if (!pdata) -+ return -EINVAL; -+ - master = spi_alloc_master(&pdev->dev, sizeof(*sp)); - if (master == NULL) { - dev_err(&pdev->dev, "failed to allocate spi master\n"); -@@ -224,17 +244,10 @@ static __devinit int ath79_spi_probe(str - sp = spi_master_get_devdata(master); - platform_set_drvdata(pdev, sp); - -- pdata = pdev->dev.platform_data; -- - master->setup = ath79_spi_setup; - master->cleanup = ath79_spi_cleanup; -- if (pdata) { -- master->bus_num = pdata->bus_num; -- master->num_chipselect = pdata->num_chipselect; -- } else { -- master->bus_num = -1; -- master->num_chipselect = 1; -- } -+ master->bus_num = pdata->bus_num; -+ master->num_chipselect = pdata->num_chipselect; - - sp->bitbang.master = spi_master_get(master); - sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ar71xx/patches-3.3/208-MIPS-ath79-db120-spi-chipselect-fix.patch b/target/linux/ar71xx/patches-3.3/208-MIPS-ath79-db120-spi-chipselect-fix.patch deleted file mode 100644 index 3b7705739e..0000000000 --- a/target/linux/ar71xx/patches-3.3/208-MIPS-ath79-db120-spi-chipselect-fix.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/mips/ath79/mach-db120.c -+++ b/arch/mips/ath79/mach-db120.c -@@ -95,12 +95,18 @@ static struct gpio_keys_button db120_gpi - }, - }; - -+static struct ath79_spi_controller_data db120_spi0_data = { -+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, -+ .cs_line = 0, -+}; -+ - static struct spi_board_info db120_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "s25sl064a", -+ .controller_data = &db120_spi0_data, - } - }; - diff --git a/target/linux/ar71xx/patches-3.3/210-MIPS-ath79-fix-gpio-count-for-ar7241.patch b/target/linux/ar71xx/patches-3.3/210-MIPS-ath79-fix-gpio-count-for-ar7241.patch deleted file mode 100644 index ca0d3cc701..0000000000 --- a/target/linux/ar71xx/patches-3.3/210-MIPS-ath79-fix-gpio-count-for-ar7241.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -188,8 +188,10 @@ void __init ath79_gpio_init(void) - - if (soc_is_ar71xx()) - ath79_gpio_count = AR71XX_GPIO_COUNT; -- else if (soc_is_ar724x()) -- ath79_gpio_count = AR724X_GPIO_COUNT; -+ else if (soc_is_ar7240()) -+ ath79_gpio_count = AR7240_GPIO_COUNT; -+ else if (soc_is_ar7241() || soc_is_ar7242()) -+ ath79_gpio_count = AR7241_GPIO_COUNT; - else if (soc_is_ar913x()) - ath79_gpio_count = AR913X_GPIO_COUNT; - else if (soc_is_ar933x()) ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -428,7 +428,8 @@ - #define AR71XX_GPIO_REG_FUNC 0x28 - - #define AR71XX_GPIO_COUNT 16 --#define AR724X_GPIO_COUNT 18 -+#define AR7240_GPIO_COUNT 18 -+#define AR7241_GPIO_COUNT 20 - #define AR913X_GPIO_COUNT 22 - #define AR933X_GPIO_COUNT 30 - #define AR934X_GPIO_COUNT 23 diff --git a/target/linux/ar71xx/patches-3.3/211-MIPS-ath79-fix-ar933x_wmac_reset.patch b/target/linux/ar71xx/patches-3.3/211-MIPS-ath79-fix-ar933x_wmac_reset.patch deleted file mode 100644 index 9438844f29..0000000000 --- a/target/linux/ar71xx/patches-3.3/211-MIPS-ath79-fix-ar933x_wmac_reset.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -62,8 +62,8 @@ static void __init ar913x_wmac_setup(voi - - static int ar933x_wmac_reset(void) - { -- ath79_device_reset_clear(AR933X_RESET_WMAC); - ath79_device_reset_set(AR933X_RESET_WMAC); -+ ath79_device_reset_clear(AR933X_RESET_WMAC); - - return 0; - } diff --git a/target/linux/ar71xx/patches-3.3/212-MIPS-ath79-fix-build-error-if-PCI-not-enabled.patch b/target/linux/ar71xx/patches-3.3/212-MIPS-ath79-fix-build-error-if-PCI-not-enabled.patch deleted file mode 100644 index a3d0498899..0000000000 --- a/target/linux/ar71xx/patches-3.3/212-MIPS-ath79-fix-build-error-if-PCI-not-enabled.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/pci.h -+++ b/arch/mips/include/asm/mach-ath79/pci.h -@@ -16,13 +16,13 @@ - #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX) - int ar71xx_pcibios_init(void); - #else --static inline int ar71xx_pcibios_init(void) { return 0 }; -+static inline int ar71xx_pcibios_init(void) { return 0; } - #endif - - #if defined(CONFIG_PCI_AR724X) - int ar724x_pcibios_init(int irq); - #else --static inline int ar724x_pcibios_init(int irq) { return 0 }; -+static inline int ar724x_pcibios_init(int irq) { return 0; } - #endif - - #endif /* __ASM_MACH_ATH79_PCI_H */ diff --git a/target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h b/target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h deleted file mode 100644 index 9069edd4d4..0000000000 --- a/target/linux/ar71xx/patches-3.3/213-MIPS-ath79-fix-a-typo-in-ar71xx_regs.h +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -313,7 +313,7 @@ - #define AR934X_RESET_USB_PHY_ANALOG BIT(11) - #define AR934X_RESET_HOST_DMA_INT BIT(10) - #define AR934X_RESET_GE0_MAC BIT(9) --#define AR934X_RESET_ETH_SIWTCH BIT(8) -+#define AR934X_RESET_ETH_SWITCH BIT(8) - #define AR934X_RESET_PCIE_PHY BIT(7) - #define AR934X_RESET_PCIE BIT(6) - #define AR934X_RESET_USB_HOST BIT(5) diff --git a/target/linux/ar71xx/patches-3.3/214-MIPS-ath79-fix-IRQ-number-for-AR7240-OHCI.patch b/target/linux/ar71xx/patches-3.3/214-MIPS-ath79-fix-IRQ-number-for-AR7240-OHCI.patch deleted file mode 100644 index 0be5aa89fa..0000000000 --- a/target/linux/ar71xx/patches-3.3/214-MIPS-ath79-fix-IRQ-number-for-AR7240-OHCI.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -126,6 +126,8 @@ static void __init ar7240_usb_setup(void - - ath79_ohci_resources[0].start = AR7240_OHCI_BASE; - ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1; -+ ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB; -+ ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB; - platform_device_register(&ath79_ohci_device); - } - diff --git a/target/linux/ar71xx/patches-3.3/215-ar934x_fix_usb_reset.patch b/target/linux/ar71xx/patches-3.3/215-ar934x_fix_usb_reset.patch deleted file mode 100644 index e92353bdf2..0000000000 --- a/target/linux/ar71xx/patches-3.3/215-ar934x_fix_usb_reset.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -190,16 +190,16 @@ static void __init ar934x_usb_setup(void - if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) - return; - -- ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE); -+ ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); - udelay(1000); - -- ath79_device_reset_set(AR934X_RESET_USB_PHY); -+ ath79_device_reset_clear(AR934X_RESET_USB_PHY); - udelay(1000); - -- ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG); -+ ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); - udelay(1000); - -- ath79_device_reset_set(AR934X_RESET_USB_HOST); -+ ath79_device_reset_clear(AR934X_RESET_USB_HOST); - udelay(1000); - - ath79_ehci_resources[0].start = AR934X_EHCI_BASE; diff --git a/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch index 75db84ceb6..5268ad44c9 100644 --- a/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch +++ b/target/linux/ar71xx/patches-3.3/463-spi-ath79-add-fast-flash-read.patch @@ -34,7 +34,7 @@ } static void ath79_spi_disable(struct ath79_spi *sp) -@@ -222,6 +229,110 @@ static u32 ath79_spi_txrx_mode0(struct s +@@ -229,6 +236,110 @@ static u32 ath79_spi_txrx_mode0(struct s return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); } @@ -145,7 +145,7 @@ static __devinit int ath79_spi_probe(struct platform_device *pdev) { struct spi_master *master; -@@ -244,6 +355,8 @@ static __devinit int ath79_spi_probe(str +@@ -251,6 +362,8 @@ static __devinit int ath79_spi_probe(str sp = spi_master_get_devdata(master); platform_set_drvdata(pdev, sp); @@ -154,7 +154,7 @@ master->setup = ath79_spi_setup; master->cleanup = ath79_spi_cleanup; master->bus_num = pdata->bus_num; -@@ -252,7 +365,7 @@ static __devinit int ath79_spi_probe(str +@@ -259,7 +372,7 @@ static __devinit int ath79_spi_probe(str sp->bitbang.master = spi_master_get(master); sp->bitbang.chipselect = ath79_spi_chipselect; sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; @@ -163,7 +163,7 @@ sp->bitbang.flags = SPI_CS_HIGH; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -@@ -277,7 +390,8 @@ static __devinit int ath79_spi_probe(str +@@ -284,7 +397,8 @@ static __devinit int ath79_spi_probe(str if (ret) goto err_clk_put; diff --git a/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch index 8ac50ea2a4..1ce8906333 100644 --- a/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch +++ b/target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch @@ -59,7 +59,7 @@ --- a/arch/mips/ath79/mach-db120.c +++ b/arch/mips/ath79/mach-db120.c -@@ -153,7 +153,7 @@ static void __init db120_setup(void) +@@ -134,7 +134,7 @@ static void __init db120_setup(void) ath79_register_spi(&db120_spi_data, db120_spi_info, ARRAY_SIZE(db120_spi_info)); ath79_register_usb(); diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch index 74b3c831f1..a5394add91 100644 --- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch @@ -76,7 +76,7 @@ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -285,7 +306,11 @@ +@@ -285,16 +306,50 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) @@ -88,16 +88,46 @@ #define AR933X_RESET_USB_HOST BIT(5) #define AR933X_RESET_USB_PHY BIT(4) #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) -@@ -323,6 +348,8 @@ - #define AR934X_RESET_MBOX BIT(1) - #define AR934X_RESET_I2S BIT(0) + ++#define AR934X_RESET_HOST BIT(31) ++#define AR934X_RESET_SLIC BIT(30) ++#define AR934X_RESET_HDMA BIT(29) ++#define AR934X_RESET_EXTERNAL BIT(28) ++#define AR934X_RESET_RTC BIT(27) ++#define AR934X_RESET_PCIE_EP_INT BIT(26) ++#define AR934X_RESET_CHKSUM_ACC BIT(25) ++#define AR934X_RESET_FULL_CHIP BIT(24) ++#define AR934X_RESET_GE1_MDIO BIT(23) ++#define AR934X_RESET_GE0_MDIO BIT(22) ++#define AR934X_RESET_CPU_NMI BIT(21) ++#define AR934X_RESET_CPU_COLD BIT(20) ++#define AR934X_RESET_HOST_RESET_INT BIT(19) ++#define AR934X_RESET_PCIE_EP BIT(18) ++#define AR934X_RESET_UART1 BIT(17) ++#define AR934X_RESET_DDR BIT(16) ++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define AR934X_RESET_NANDF BIT(14) ++#define AR934X_RESET_GE1_MAC BIT(13) ++#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) + #define AR934X_RESET_USB_PHY_ANALOG BIT(11) ++#define AR934X_RESET_HOST_DMA_INT BIT(10) ++#define AR934X_RESET_GE0_MAC BIT(9) ++#define AR934X_RESET_ETH_SWITCH BIT(8) ++#define AR934X_RESET_PCIE_PHY BIT(7) ++#define AR934X_RESET_PCIE BIT(6) + #define AR934X_RESET_USB_HOST BIT(5) + #define AR934X_RESET_USB_PHY BIT(4) + #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) ++#define AR934X_RESET_LUT BIT(2) ++#define AR934X_RESET_MBOX BIT(1) ++#define AR934X_RESET_I2S BIT(0) +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -427,6 +454,14 @@ +@@ -399,10 +454,138 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -110,9 +140,8 @@ +#define AR934X_GPIO_REG_FUNC 0x6c + #define AR71XX_GPIO_COUNT 16 - #define AR7240_GPIO_COUNT 18 - #define AR7241_GPIO_COUNT 20 -@@ -434,4 +469,124 @@ + #define AR724X_GPIO_COUNT 18 + #define AR913X_GPIO_COUNT 22 #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_COUNT 23 diff --git a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch index c0416ed6f0..01c3c9f1d5 100644 --- a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch +++ b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch @@ -7,9 +7,9 @@ - * Copyright (c) 2011 Gabor Juhos + * Copyright (c) 2011-2012 Gabor Juhos * - * All rights reserved. - * -@@ -38,16 +38,25 @@ + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -19,16 +19,25 @@ */ #include @@ -37,7 +37,7 @@ #define DB120_GPIO_LED_WLAN_5G 12 #define DB120_GPIO_LED_WLAN_2G 13 #define DB120_GPIO_LED_STATUS 14 -@@ -58,8 +67,10 @@ +@@ -39,8 +48,10 @@ #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) @@ -50,7 +50,7 @@ static struct gpio_led db120_leds_gpio[] __initdata = { { -@@ -82,6 +93,11 @@ static struct gpio_led db120_leds_gpio[] +@@ -63,6 +74,11 @@ static struct gpio_led db120_leds_gpio[] .gpio = DB120_GPIO_LED_WLAN_2G, .active_low = 1, }, @@ -62,7 +62,7 @@ }; static struct gpio_keys_button db120_gpio_keys[] __initdata = { -@@ -95,66 +111,90 @@ static struct gpio_keys_button db120_gpi +@@ -76,66 +92,90 @@ static struct gpio_keys_button db120_gpi }, }; diff --git a/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch index cc393a8e76..c47f99c05e 100644 --- a/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch +++ b/target/linux/ar71xx/patches-3.3/607-MIPS-ath79-ubnt-xm-fixes.patch @@ -42,8 +42,8 @@ }; -static struct ath79_spi_controller_data ubnt_xm_spi0_data = { -- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, -- .cs_line = 0, +- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, +- .cs_line = 0, -}; - -static struct spi_board_info ubnt_xm_spi_info[] = {