From: Nikolay Borisov Date: Tue, 20 Feb 2018 23:25:08 +0000 (-0800) Subject: memory-barriers: Fix description of data dependency barriers X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=51de78892b1294d1521c41226a5ef215a910c25f;p=openwrt%2Fstaging%2Fblogic.git memory-barriers: Fix description of data dependency barriers In the description of data dependency barriers the words 'before' is used erroneously. Since such barrier order dependent loads one after the other. So substitute 'before' with 'after'. Signed-off-by: Nikolay Borisov Signed-off-by: Paul E. McKenney Acked-by: Peter Zijlstra Cc: Linus Torvalds Cc: Thomas Gleixner Cc: akiyks@gmail.com Cc: boqun.feng@gmail.com Cc: dhowells@redhat.com Cc: j.alglave@ucl.ac.uk Cc: linux-arch@vger.kernel.org Cc: luc.maranget@inria.fr Cc: npiggin@gmail.com Cc: parri.andrea@gmail.com Cc: stern@rowland.harvard.edu Cc: will.deacon@arm.com Link: http://lkml.kernel.org/r/1519169112-20593-8-git-send-email-paulmck@linux.vnet.ibm.com Signed-off-by: Ingo Molnar --- diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index a37d3aff3e73..da6525bdc3f5 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -403,7 +403,7 @@ Memory barriers come in four basic varieties: where two loads are performed such that the second depends on the result of the first (eg: the first load retrieves the address to which the second load will be directed), a data dependency barrier would be required to - make sure that the target of the second load is updated before the address + make sure that the target of the second load is updated after the address obtained by the first load is accessed. A data dependency barrier is a partial ordering on interdependent loads