From: Rafał Miłecki Date: Wed, 10 May 2017 21:22:36 +0000 (+0200) Subject: bcm53xx: backport USB 3.0 PHY patch cleaning all writes X-Git-Tag: v18.06.0-rc1~2982 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=51abaf722ccdb2cc2e43e99616d5bacaae78fdea;p=openwrt%2Fstaging%2Fpepe2k.git bcm53xx: backport USB 3.0 PHY patch cleaning all writes It doesn't change any bevahior just cleanes up the code. Signed-off-by: Rafał Miłecki --- diff --git a/target/linux/bcm53xx/patches-4.4/071-0001-phy-bcm-ns-usb3-new-driver-for-USB-3.0-PHY-on-Norths.patch b/target/linux/bcm53xx/patches-4.4/071-0001-phy-bcm-ns-usb3-new-driver-for-USB-3.0-PHY-on-Norths.patch new file mode 100644 index 0000000000..ad34fc8484 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.4/071-0001-phy-bcm-ns-usb3-new-driver-for-USB-3.0-PHY-on-Norths.patch @@ -0,0 +1,361 @@ +From b8d7478ecfec51b3430f677da44e662d5ff12444 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 12 Aug 2016 00:28:03 +0200 +Subject: [PATCH] phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Northstar is a family of SoCs used in home routers. They have USB 2.0 +and 3.0 controllers with PHYs that need to be properly initialized. +This driver provides PHY init support in a generic way and can be bound +with XHCI controller driver. + +There aren't any public datasheets from Broadcom so we can't have nice +defines for all used bits. It means we just follow Broadcom's +initialization procedure using their magic values. We were quite lucky +actually that Broadcom put some comments in their SDK reference code +explaining what given writes are responsible for. + +Signed-off-by: Rafał Miłecki +Signed-off-by: Kishon Vijay Abraham I +--- + .../devicetree/bindings/phy/bcm-ns-usb3-phy.txt | 23 ++ + drivers/phy/Kconfig | 9 + + drivers/phy/Makefile | 1 + + drivers/phy/phy-bcm-ns-usb3.c | 274 +++++++++++++++++++++ + 4 files changed, 307 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt + create mode 100644 drivers/phy/phy-bcm-ns-usb3.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt +@@ -0,0 +1,23 @@ ++Driver for Broadcom Northstar USB 3.0 PHY ++ ++Required properties: ++ ++- compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy". ++- reg: register mappings for DMP (Device Management Plugin) and ChipCommon B ++ MMI. ++- reg-names: "dmp" and "ccb-mii" ++ ++Initialization of USB 3.0 PHY depends on Northstar version. There are currently ++three known series: Ax, Bx and Cx. ++Known A0: BCM4707 rev 0 ++Known B0: BCM4707 rev 4, BCM53573 rev 2 ++Known B1: BCM4707 rev 6 ++Known C0: BCM47094 rev 0 ++ ++Example: ++ usb3-phy { ++ compatible = "brcm,ns-ax-usb3-phy"; ++ reg = <0x18105000 0x1000>, <0x18003000 0x1000>; ++ reg-names = "dmp", "ccb-mii"; ++ #phy-cells = <0>; ++ }; +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -24,6 +24,15 @@ config PHY_BCM_NS_USB2 + Enable this to support Broadcom USB 2.0 PHY connected to the USB + controller on Northstar family. + ++config PHY_BCM_NS_USB3 ++ tristate "Broadcom Northstar USB 3.0 PHY Driver" ++ depends on ARCH_BCM_IPROC || COMPILE_TEST ++ depends on HAS_IOMEM && OF ++ select GENERIC_PHY ++ help ++ Enable this to support Broadcom USB 3.0 PHY connected to the USB ++ controller on Northstar family. ++ + config PHY_BERLIN_USB + tristate "Marvell Berlin USB PHY Driver" + depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -4,6 +4,7 @@ + + obj-$(CONFIG_GENERIC_PHY) += phy-core.o + obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o ++obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o + obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o + obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o + obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o +--- /dev/null ++++ b/drivers/phy/phy-bcm-ns-usb3.c +@@ -0,0 +1,274 @@ ++/* ++ * Broadcom Northstar USB 3.0 PHY Driver ++ * ++ * Copyright (C) 2016 Rafał Miłecki ++ * ++ * All magic values used for initialization (and related comments) were obtained ++ * from Broadcom's SDK: ++ * Copyright (c) Broadcom Corp, 2012 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */ ++ ++enum bcm_ns_family { ++ BCM_NS_UNKNOWN, ++ BCM_NS_AX, ++ BCM_NS_BX, ++}; ++ ++struct bcm_ns_usb3 { ++ struct device *dev; ++ enum bcm_ns_family family; ++ void __iomem *dmp; ++ void __iomem *ccb_mii; ++ struct phy *phy; ++}; ++ ++static const struct of_device_id bcm_ns_usb3_id_table[] = { ++ { ++ .compatible = "brcm,ns-ax-usb3-phy", ++ .data = (int *)BCM_NS_AX, ++ }, ++ { ++ .compatible = "brcm,ns-bx-usb3-phy", ++ .data = (int *)BCM_NS_BX, ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm_ns_usb3_id_table); ++ ++static int bcm_ns_usb3_wait_reg(struct bcm_ns_usb3 *usb3, void __iomem *addr, ++ u32 mask, u32 value, unsigned long timeout) ++{ ++ unsigned long deadline = jiffies + timeout; ++ u32 val; ++ ++ do { ++ val = readl(addr); ++ if ((val & mask) == value) ++ return 0; ++ cpu_relax(); ++ udelay(10); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ dev_err(usb3->dev, "Timeout waiting for register %p\n", addr); ++ ++ return -EBUSY; ++} ++ ++static inline int bcm_ns_usb3_mii_mng_wait_idle(struct bcm_ns_usb3 *usb3) ++{ ++ return bcm_ns_usb3_wait_reg(usb3, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL, ++ 0x0100, 0x0000, ++ usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); ++} ++ ++static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value) ++{ ++ int err; ++ ++ err = bcm_ns_usb3_mii_mng_wait_idle(usb3); ++ if (err < 0) { ++ dev_err(usb3->dev, "Couldn't write 0x%08x value\n", value); ++ return err; ++ } ++ ++ writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); ++ ++ return 0; ++} ++ ++static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) ++{ ++ int err; ++ ++ /* Enable MDIO. Setting MDCDIV as 26 */ ++ writel(0x0000009a, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL); ++ ++ /* Wait for MDIO? */ ++ udelay(2); ++ ++ /* USB3 PLL Block */ ++ err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); ++ if (err < 0) ++ return err; ++ ++ /* Assert Ana_Pllseq start */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000); ++ ++ /* Assert CML Divider ratio to 26 */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); ++ ++ /* Asserting PLL Reset */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000); ++ ++ /* Deaaserting PLL Reset */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcm_ns_usb3_mii_mng_wait_idle(usb3); ++ ++ /* Deasserting USB3 system reset */ ++ writel(0, usb3->dmp + BCMA_RESET_CTL); ++ ++ /* PLL frequency monitor enable */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000); ++ ++ /* PIPE Block */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060); ++ ++ /* CMPMAX & CMPMINTH setting */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d); ++ ++ /* DEGLITCH MIN & MAX setting */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302); ++ ++ /* TXPMD block */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); ++ ++ /* Enabling SSC */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcm_ns_usb3_mii_mng_wait_idle(usb3); ++ ++ return 0; ++} ++ ++static int bcm_ns_usb3_phy_init_ns_ax(struct bcm_ns_usb3 *usb3) ++{ ++ int err; ++ ++ /* Enable MDIO. Setting MDCDIV as 26 */ ++ writel(0x0000009a, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL); ++ ++ /* Wait for MDIO? */ ++ udelay(2); ++ ++ /* PLL30 block */ ++ err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); ++ if (err < 0) ++ return err; ++ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); ++ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0); ++ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c); ++ ++ /* Enable SSC */ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); ++ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3); ++ ++ bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcm_ns_usb3_mii_mng_wait_idle(usb3); ++ ++ /* Deasserting USB3 system reset */ ++ writel(0, usb3->dmp + BCMA_RESET_CTL); ++ ++ return 0; ++} ++ ++static int bcm_ns_usb3_phy_init(struct phy *phy) ++{ ++ struct bcm_ns_usb3 *usb3 = phy_get_drvdata(phy); ++ int err; ++ ++ /* Perform USB3 system soft reset */ ++ writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL); ++ ++ switch (usb3->family) { ++ case BCM_NS_AX: ++ err = bcm_ns_usb3_phy_init_ns_ax(usb3); ++ break; ++ case BCM_NS_BX: ++ err = bcm_ns_usb3_phy_init_ns_bx(usb3); ++ break; ++ default: ++ WARN_ON(1); ++ err = -ENOTSUPP; ++ } ++ ++ return err; ++} ++ ++static const struct phy_ops ops = { ++ .init = bcm_ns_usb3_phy_init, ++ .owner = THIS_MODULE, ++}; ++ ++static int bcm_ns_usb3_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *of_id; ++ struct bcm_ns_usb3 *usb3; ++ struct resource *res; ++ struct phy_provider *phy_provider; ++ ++ usb3 = devm_kzalloc(dev, sizeof(*usb3), GFP_KERNEL); ++ if (!usb3) ++ return -ENOMEM; ++ ++ usb3->dev = dev; ++ ++ of_id = of_match_device(bcm_ns_usb3_id_table, dev); ++ if (!of_id) ++ return -EINVAL; ++ usb3->family = (enum bcm_ns_family)of_id->data; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmp"); ++ usb3->dmp = devm_ioremap_resource(dev, res); ++ if (IS_ERR(usb3->dmp)) { ++ dev_err(dev, "Failed to map DMP regs\n"); ++ return PTR_ERR(usb3->dmp); ++ } ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ccb-mii"); ++ usb3->ccb_mii = devm_ioremap_resource(dev, res); ++ if (IS_ERR(usb3->ccb_mii)) { ++ dev_err(dev, "Failed to map ChipCommon B MII regs\n"); ++ return PTR_ERR(usb3->ccb_mii); ++ } ++ ++ usb3->phy = devm_phy_create(dev, NULL, &ops); ++ if (IS_ERR(usb3->phy)) { ++ dev_err(dev, "Failed to create PHY\n"); ++ return PTR_ERR(usb3->phy); ++ } ++ ++ phy_set_drvdata(usb3->phy, usb3); ++ platform_set_drvdata(pdev, usb3); ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (!IS_ERR(phy_provider)) ++ dev_info(dev, "Registered Broadcom Northstar USB 3.0 PHY driver\n"); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static struct platform_driver bcm_ns_usb3_driver = { ++ .probe = bcm_ns_usb3_probe, ++ .driver = { ++ .name = "bcm_ns_usb3", ++ .of_match_table = bcm_ns_usb3_id_table, ++ }, ++}; ++module_platform_driver(bcm_ns_usb3_driver); ++ ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/bcm53xx/patches-4.4/071-0002-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch b/target/linux/bcm53xx/patches-4.4/071-0002-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch new file mode 100644 index 0000000000..ddbec25863 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.4/071-0002-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch @@ -0,0 +1,177 @@ +From fff3364a637796611c06f59a6f2be61685d99bfe Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 2 Apr 2017 18:55:22 +0200 +Subject: [PATCH] phy: bcm-ns-usb3: split all writes into reg & val pairs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +So far all the PHY initialization was implemented using some totally +magic values. There was some pattern there but it wasn't clear what is +it about. + +Thanks to the patch submitted by Broadcom: +[PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC +and the upstream "iproc-mdio" driver we now know there is a MDIO bus +underneath with PHY(s) and their registers. + +It allows us to clean the driver a bit by making all these values less +magical. The next step is switching to using a proper MDIO layer. + +Signed-off-by: Rafał Miłecki +Acked-by: Jon Mason +Signed-off-by: Kishon Vijay Abraham I +--- + drivers/phy/phy-bcm-ns-usb3.c | 69 ++++++++++++++++++++++++++++++------------- + 1 file changed, 49 insertions(+), 20 deletions(-) + +--- a/drivers/phy/phy-bcm-ns-usb3.c ++++ b/drivers/phy/phy-bcm-ns-usb3.c +@@ -2,6 +2,7 @@ + * Broadcom Northstar USB 3.0 PHY Driver + * + * Copyright (C) 2016 Rafał Miłecki ++ * Copyright (C) 2016 Broadcom + * + * All magic values used for initialization (and related comments) were obtained + * from Broadcom's SDK: +@@ -23,6 +24,23 @@ + + #define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */ + ++#define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f ++#define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000 ++#define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040 ++#define BCM_NS_USB3_PHY_PIPE_BLOCK 0x8060 ++ ++/* Registers of PLL30 block */ ++#define BCM_NS_USB3_PLL_CONTROL 0x01 ++#define BCM_NS_USB3_PLLA_CONTROL0 0x0a ++#define BCM_NS_USB3_PLLA_CONTROL1 0x0b ++ ++/* Registers of TX PMD block */ ++#define BCM_NS_USB3_TX_PMD_CONTROL1 0x01 ++ ++/* Registers of PIPE block */ ++#define BCM_NS_USB3_LFPS_CMP 0x02 ++#define BCM_NS_USB3_LFPS_DEGLITCH 0x03 ++ + enum bcm_ns_family { + BCM_NS_UNKNOWN, + BCM_NS_AX, +@@ -76,8 +94,10 @@ static inline int bcm_ns_usb3_mii_mng_wa + usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); + } + +-static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value) ++static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, ++ u16 value) + { ++ u32 tmp = 0; + int err; + + err = bcm_ns_usb3_mii_mng_wait_idle(usb3); +@@ -86,7 +106,11 @@ static int bcm_ns_usb3_mii_mng_write32(s + return err; + } + +- writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); ++ /* TODO: Use a proper MDIO bus layer */ ++ tmp |= 0x58020000; /* Magic value for MDIO PHY write */ ++ tmp |= reg << 18; ++ tmp |= value; ++ writel(tmp, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); + + return 0; + } +@@ -102,21 +126,22 @@ static int bcm_ns_usb3_phy_init_ns_bx(st + udelay(2); + + /* USB3 PLL Block */ +- err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); ++ err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_PLL30_BLOCK); + if (err < 0) + return err; + + /* Assert Ana_Pllseq start */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000); + + /* Assert CML Divider ratio to 26 */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); + + /* Asserting PLL Reset */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0xc000); + + /* Deaaserting PLL Reset */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0x8000); + + /* Waiting MII Mgt interface idle */ + bcm_ns_usb3_mii_mng_wait_idle(usb3); +@@ -125,22 +150,24 @@ static int bcm_ns_usb3_phy_init_ns_bx(st + writel(0, usb3->dmp + BCMA_RESET_CTL); + + /* PLL frequency monitor enable */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x9000); + + /* PIPE Block */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_PIPE_BLOCK); + + /* CMPMAX & CMPMINTH setting */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_CMP, 0xf30d); + + /* DEGLITCH MIN & MAX setting */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_DEGLITCH, 0x6302); + + /* TXPMD block */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_TX_PMD_BLOCK); + + /* Enabling SSC */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003); + + /* Waiting MII Mgt interface idle */ + bcm_ns_usb3_mii_mng_wait_idle(usb3); +@@ -159,22 +186,24 @@ static int bcm_ns_usb3_phy_init_ns_ax(st + udelay(2); + + /* PLL30 block */ +- err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); ++ err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_PLL30_BLOCK); + if (err < 0) + return err; + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, 0x80e0); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c); ++ bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x009c); + + /* Enable SSC */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_TX_PMD_BLOCK); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3); ++ bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x21d3); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003); + + /* Waiting MII Mgt interface idle */ + bcm_ns_usb3_mii_mng_wait_idle(usb3); diff --git a/target/linux/bcm53xx/patches-4.4/071-phy-bcm-ns-usb3-new-driver-for-USB-3.0-PHY-on-Norths.patch b/target/linux/bcm53xx/patches-4.4/071-phy-bcm-ns-usb3-new-driver-for-USB-3.0-PHY-on-Norths.patch deleted file mode 100644 index ad34fc8484..0000000000 --- a/target/linux/bcm53xx/patches-4.4/071-phy-bcm-ns-usb3-new-driver-for-USB-3.0-PHY-on-Norths.patch +++ /dev/null @@ -1,361 +0,0 @@ -From b8d7478ecfec51b3430f677da44e662d5ff12444 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Aug 2016 00:28:03 +0200 -Subject: [PATCH] phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Northstar is a family of SoCs used in home routers. They have USB 2.0 -and 3.0 controllers with PHYs that need to be properly initialized. -This driver provides PHY init support in a generic way and can be bound -with XHCI controller driver. - -There aren't any public datasheets from Broadcom so we can't have nice -defines for all used bits. It means we just follow Broadcom's -initialization procedure using their magic values. We were quite lucky -actually that Broadcom put some comments in their SDK reference code -explaining what given writes are responsible for. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Kishon Vijay Abraham I ---- - .../devicetree/bindings/phy/bcm-ns-usb3-phy.txt | 23 ++ - drivers/phy/Kconfig | 9 + - drivers/phy/Makefile | 1 + - drivers/phy/phy-bcm-ns-usb3.c | 274 +++++++++++++++++++++ - 4 files changed, 307 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt - create mode 100644 drivers/phy/phy-bcm-ns-usb3.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt -@@ -0,0 +1,23 @@ -+Driver for Broadcom Northstar USB 3.0 PHY -+ -+Required properties: -+ -+- compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy". -+- reg: register mappings for DMP (Device Management Plugin) and ChipCommon B -+ MMI. -+- reg-names: "dmp" and "ccb-mii" -+ -+Initialization of USB 3.0 PHY depends on Northstar version. There are currently -+three known series: Ax, Bx and Cx. -+Known A0: BCM4707 rev 0 -+Known B0: BCM4707 rev 4, BCM53573 rev 2 -+Known B1: BCM4707 rev 6 -+Known C0: BCM47094 rev 0 -+ -+Example: -+ usb3-phy { -+ compatible = "brcm,ns-ax-usb3-phy"; -+ reg = <0x18105000 0x1000>, <0x18003000 0x1000>; -+ reg-names = "dmp", "ccb-mii"; -+ #phy-cells = <0>; -+ }; ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -24,6 +24,15 @@ config PHY_BCM_NS_USB2 - Enable this to support Broadcom USB 2.0 PHY connected to the USB - controller on Northstar family. - -+config PHY_BCM_NS_USB3 -+ tristate "Broadcom Northstar USB 3.0 PHY Driver" -+ depends on ARCH_BCM_IPROC || COMPILE_TEST -+ depends on HAS_IOMEM && OF -+ select GENERIC_PHY -+ help -+ Enable this to support Broadcom USB 3.0 PHY connected to the USB -+ controller on Northstar family. -+ - config PHY_BERLIN_USB - tristate "Marvell Berlin USB PHY Driver" - depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -4,6 +4,7 @@ - - obj-$(CONFIG_GENERIC_PHY) += phy-core.o - obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o -+obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o - obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o - obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o - obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o ---- /dev/null -+++ b/drivers/phy/phy-bcm-ns-usb3.c -@@ -0,0 +1,274 @@ -+/* -+ * Broadcom Northstar USB 3.0 PHY Driver -+ * -+ * Copyright (C) 2016 Rafał Miłecki -+ * -+ * All magic values used for initialization (and related comments) were obtained -+ * from Broadcom's SDK: -+ * Copyright (c) Broadcom Corp, 2012 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */ -+ -+enum bcm_ns_family { -+ BCM_NS_UNKNOWN, -+ BCM_NS_AX, -+ BCM_NS_BX, -+}; -+ -+struct bcm_ns_usb3 { -+ struct device *dev; -+ enum bcm_ns_family family; -+ void __iomem *dmp; -+ void __iomem *ccb_mii; -+ struct phy *phy; -+}; -+ -+static const struct of_device_id bcm_ns_usb3_id_table[] = { -+ { -+ .compatible = "brcm,ns-ax-usb3-phy", -+ .data = (int *)BCM_NS_AX, -+ }, -+ { -+ .compatible = "brcm,ns-bx-usb3-phy", -+ .data = (int *)BCM_NS_BX, -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm_ns_usb3_id_table); -+ -+static int bcm_ns_usb3_wait_reg(struct bcm_ns_usb3 *usb3, void __iomem *addr, -+ u32 mask, u32 value, unsigned long timeout) -+{ -+ unsigned long deadline = jiffies + timeout; -+ u32 val; -+ -+ do { -+ val = readl(addr); -+ if ((val & mask) == value) -+ return 0; -+ cpu_relax(); -+ udelay(10); -+ } while (!time_after_eq(jiffies, deadline)); -+ -+ dev_err(usb3->dev, "Timeout waiting for register %p\n", addr); -+ -+ return -EBUSY; -+} -+ -+static inline int bcm_ns_usb3_mii_mng_wait_idle(struct bcm_ns_usb3 *usb3) -+{ -+ return bcm_ns_usb3_wait_reg(usb3, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL, -+ 0x0100, 0x0000, -+ usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); -+} -+ -+static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value) -+{ -+ int err; -+ -+ err = bcm_ns_usb3_mii_mng_wait_idle(usb3); -+ if (err < 0) { -+ dev_err(usb3->dev, "Couldn't write 0x%08x value\n", value); -+ return err; -+ } -+ -+ writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); -+ -+ return 0; -+} -+ -+static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) -+{ -+ int err; -+ -+ /* Enable MDIO. Setting MDCDIV as 26 */ -+ writel(0x0000009a, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL); -+ -+ /* Wait for MDIO? */ -+ udelay(2); -+ -+ /* USB3 PLL Block */ -+ err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); -+ if (err < 0) -+ return err; -+ -+ /* Assert Ana_Pllseq start */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000); -+ -+ /* Assert CML Divider ratio to 26 */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); -+ -+ /* Asserting PLL Reset */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000); -+ -+ /* Deaaserting PLL Reset */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcm_ns_usb3_mii_mng_wait_idle(usb3); -+ -+ /* Deasserting USB3 system reset */ -+ writel(0, usb3->dmp + BCMA_RESET_CTL); -+ -+ /* PLL frequency monitor enable */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000); -+ -+ /* PIPE Block */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060); -+ -+ /* CMPMAX & CMPMINTH setting */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d); -+ -+ /* DEGLITCH MIN & MAX setting */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302); -+ -+ /* TXPMD block */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); -+ -+ /* Enabling SSC */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcm_ns_usb3_mii_mng_wait_idle(usb3); -+ -+ return 0; -+} -+ -+static int bcm_ns_usb3_phy_init_ns_ax(struct bcm_ns_usb3 *usb3) -+{ -+ int err; -+ -+ /* Enable MDIO. Setting MDCDIV as 26 */ -+ writel(0x0000009a, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL); -+ -+ /* Wait for MDIO? */ -+ udelay(2); -+ -+ /* PLL30 block */ -+ err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); -+ if (err < 0) -+ return err; -+ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); -+ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0); -+ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c); -+ -+ /* Enable SSC */ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); -+ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3); -+ -+ bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcm_ns_usb3_mii_mng_wait_idle(usb3); -+ -+ /* Deasserting USB3 system reset */ -+ writel(0, usb3->dmp + BCMA_RESET_CTL); -+ -+ return 0; -+} -+ -+static int bcm_ns_usb3_phy_init(struct phy *phy) -+{ -+ struct bcm_ns_usb3 *usb3 = phy_get_drvdata(phy); -+ int err; -+ -+ /* Perform USB3 system soft reset */ -+ writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL); -+ -+ switch (usb3->family) { -+ case BCM_NS_AX: -+ err = bcm_ns_usb3_phy_init_ns_ax(usb3); -+ break; -+ case BCM_NS_BX: -+ err = bcm_ns_usb3_phy_init_ns_bx(usb3); -+ break; -+ default: -+ WARN_ON(1); -+ err = -ENOTSUPP; -+ } -+ -+ return err; -+} -+ -+static const struct phy_ops ops = { -+ .init = bcm_ns_usb3_phy_init, -+ .owner = THIS_MODULE, -+}; -+ -+static int bcm_ns_usb3_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ const struct of_device_id *of_id; -+ struct bcm_ns_usb3 *usb3; -+ struct resource *res; -+ struct phy_provider *phy_provider; -+ -+ usb3 = devm_kzalloc(dev, sizeof(*usb3), GFP_KERNEL); -+ if (!usb3) -+ return -ENOMEM; -+ -+ usb3->dev = dev; -+ -+ of_id = of_match_device(bcm_ns_usb3_id_table, dev); -+ if (!of_id) -+ return -EINVAL; -+ usb3->family = (enum bcm_ns_family)of_id->data; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmp"); -+ usb3->dmp = devm_ioremap_resource(dev, res); -+ if (IS_ERR(usb3->dmp)) { -+ dev_err(dev, "Failed to map DMP regs\n"); -+ return PTR_ERR(usb3->dmp); -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ccb-mii"); -+ usb3->ccb_mii = devm_ioremap_resource(dev, res); -+ if (IS_ERR(usb3->ccb_mii)) { -+ dev_err(dev, "Failed to map ChipCommon B MII regs\n"); -+ return PTR_ERR(usb3->ccb_mii); -+ } -+ -+ usb3->phy = devm_phy_create(dev, NULL, &ops); -+ if (IS_ERR(usb3->phy)) { -+ dev_err(dev, "Failed to create PHY\n"); -+ return PTR_ERR(usb3->phy); -+ } -+ -+ phy_set_drvdata(usb3->phy, usb3); -+ platform_set_drvdata(pdev, usb3); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ if (!IS_ERR(phy_provider)) -+ dev_info(dev, "Registered Broadcom Northstar USB 3.0 PHY driver\n"); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static struct platform_driver bcm_ns_usb3_driver = { -+ .probe = bcm_ns_usb3_probe, -+ .driver = { -+ .name = "bcm_ns_usb3", -+ .of_match_table = bcm_ns_usb3_id_table, -+ }, -+}; -+module_platform_driver(bcm_ns_usb3_driver); -+ -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/bcm53xx/patches-4.9/070-0001-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch b/target/linux/bcm53xx/patches-4.9/070-0001-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch new file mode 100644 index 0000000000..ddbec25863 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.9/070-0001-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch @@ -0,0 +1,177 @@ +From fff3364a637796611c06f59a6f2be61685d99bfe Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 2 Apr 2017 18:55:22 +0200 +Subject: [PATCH] phy: bcm-ns-usb3: split all writes into reg & val pairs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +So far all the PHY initialization was implemented using some totally +magic values. There was some pattern there but it wasn't clear what is +it about. + +Thanks to the patch submitted by Broadcom: +[PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC +and the upstream "iproc-mdio" driver we now know there is a MDIO bus +underneath with PHY(s) and their registers. + +It allows us to clean the driver a bit by making all these values less +magical. The next step is switching to using a proper MDIO layer. + +Signed-off-by: Rafał Miłecki +Acked-by: Jon Mason +Signed-off-by: Kishon Vijay Abraham I +--- + drivers/phy/phy-bcm-ns-usb3.c | 69 ++++++++++++++++++++++++++++++------------- + 1 file changed, 49 insertions(+), 20 deletions(-) + +--- a/drivers/phy/phy-bcm-ns-usb3.c ++++ b/drivers/phy/phy-bcm-ns-usb3.c +@@ -2,6 +2,7 @@ + * Broadcom Northstar USB 3.0 PHY Driver + * + * Copyright (C) 2016 Rafał Miłecki ++ * Copyright (C) 2016 Broadcom + * + * All magic values used for initialization (and related comments) were obtained + * from Broadcom's SDK: +@@ -23,6 +24,23 @@ + + #define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */ + ++#define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f ++#define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000 ++#define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040 ++#define BCM_NS_USB3_PHY_PIPE_BLOCK 0x8060 ++ ++/* Registers of PLL30 block */ ++#define BCM_NS_USB3_PLL_CONTROL 0x01 ++#define BCM_NS_USB3_PLLA_CONTROL0 0x0a ++#define BCM_NS_USB3_PLLA_CONTROL1 0x0b ++ ++/* Registers of TX PMD block */ ++#define BCM_NS_USB3_TX_PMD_CONTROL1 0x01 ++ ++/* Registers of PIPE block */ ++#define BCM_NS_USB3_LFPS_CMP 0x02 ++#define BCM_NS_USB3_LFPS_DEGLITCH 0x03 ++ + enum bcm_ns_family { + BCM_NS_UNKNOWN, + BCM_NS_AX, +@@ -76,8 +94,10 @@ static inline int bcm_ns_usb3_mii_mng_wa + usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); + } + +-static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value) ++static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, ++ u16 value) + { ++ u32 tmp = 0; + int err; + + err = bcm_ns_usb3_mii_mng_wait_idle(usb3); +@@ -86,7 +106,11 @@ static int bcm_ns_usb3_mii_mng_write32(s + return err; + } + +- writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); ++ /* TODO: Use a proper MDIO bus layer */ ++ tmp |= 0x58020000; /* Magic value for MDIO PHY write */ ++ tmp |= reg << 18; ++ tmp |= value; ++ writel(tmp, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); + + return 0; + } +@@ -102,21 +126,22 @@ static int bcm_ns_usb3_phy_init_ns_bx(st + udelay(2); + + /* USB3 PLL Block */ +- err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); ++ err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_PLL30_BLOCK); + if (err < 0) + return err; + + /* Assert Ana_Pllseq start */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000); + + /* Assert CML Divider ratio to 26 */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); + + /* Asserting PLL Reset */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0xc000); + + /* Deaaserting PLL Reset */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0x8000); + + /* Waiting MII Mgt interface idle */ + bcm_ns_usb3_mii_mng_wait_idle(usb3); +@@ -125,22 +150,24 @@ static int bcm_ns_usb3_phy_init_ns_bx(st + writel(0, usb3->dmp + BCMA_RESET_CTL); + + /* PLL frequency monitor enable */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x9000); + + /* PIPE Block */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_PIPE_BLOCK); + + /* CMPMAX & CMPMINTH setting */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_CMP, 0xf30d); + + /* DEGLITCH MIN & MAX setting */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_DEGLITCH, 0x6302); + + /* TXPMD block */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_TX_PMD_BLOCK); + + /* Enabling SSC */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003); + + /* Waiting MII Mgt interface idle */ + bcm_ns_usb3_mii_mng_wait_idle(usb3); +@@ -159,22 +186,24 @@ static int bcm_ns_usb3_phy_init_ns_ax(st + udelay(2); + + /* PLL30 block */ +- err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); ++ err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_PLL30_BLOCK); + if (err < 0) + return err; + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, 0x80e0); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c); ++ bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x009c); + + /* Enable SSC */ +- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, ++ BCM_NS_USB3_PHY_TX_PMD_BLOCK); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3); ++ bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x21d3); + +- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); ++ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003); + + /* Waiting MII Mgt interface idle */ + bcm_ns_usb3_mii_mng_wait_idle(usb3);