From: John Crispin <john@openwrt.org>
Date: Wed, 23 Dec 2015 14:44:56 +0000 (+0000)
Subject: ar71xx: add support for QCA956x ethernet
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=502f91b22e83541d46de89aee39864d21edb607d;p=openwrt%2Fstaging%2Fkaloz.git

ar71xx: add support for QCA956x ethernet

Signed-off-by: Roman Yeryomin <roman@advem.lv>

SVN-Revision: 47982
---

diff --git a/target/linux/ar71xx/patches-4.1/622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch b/target/linux/ar71xx/patches-4.1/622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch
new file mode 100644
index 0000000000..6a6a2e4c4c
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.1/622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch
@@ -0,0 +1,166 @@
+--- a/arch/mips/ath79/dev-eth.c
++++ b/arch/mips/ath79/dev-eth.c
+@@ -198,7 +198,6 @@ void __init ath79_register_mdio(unsigned
+ 	case ATH79_SOC_AR9330:
+ 	case ATH79_SOC_AR9331:
+ 	case ATH79_SOC_QCA9533:
+-	case ATH79_SOC_QCA9561:
+ 	case ATH79_SOC_TP9343:
+ 		mdio_dev = &ath79_mdio1_device;
+ 		mdio_data = &ath79_mdio1_data;
+@@ -209,6 +208,7 @@ void __init ath79_register_mdio(unsigned
+ 	case ATH79_SOC_AR9344:
+ 	case ATH79_SOC_QCA9556:
+ 	case ATH79_SOC_QCA9558:
++	case ATH79_SOC_QCA956X:
+ 		if (id == 0) {
+ 			mdio_dev = &ath79_mdio0_device;
+ 			mdio_data = &ath79_mdio0_data;
+@@ -258,7 +258,6 @@ void __init ath79_register_mdio(unsigned
+ 		break;
+ 
+ 	case ATH79_SOC_QCA9533:
+-	case ATH79_SOC_QCA9561:
+ 	case ATH79_SOC_TP9343:
+ 		mdio_data->builtin_switch = 1;
+ 		break;
+@@ -268,6 +267,11 @@ void __init ath79_register_mdio(unsigned
+ 		mdio_data->is_ar934x = 1;
+ 		break;
+ 
++	case ATH79_SOC_QCA956X:
++		if (id == 1)
++			mdio_data->builtin_switch = 1;
++		break;
++
+ 	default:
+ 		break;
+ 	}
+@@ -387,6 +391,16 @@ static void qca955x_set_speed_sgmii(int
+ 	iounmap(base);
+ }
+ 
++static void qca956x_set_speed_sgmii(int speed)
++{
++	void __iomem *base;
++	u32 val = ath79_get_eth_pll(0, speed);
++
++	base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
++	__raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
++	iounmap(base);
++}
++
+ static void ath79_set_speed_dummy(int speed)
+ {
+ }
+@@ -517,6 +531,10 @@ struct ag71xx_switch_platform_data ath79
+ #define AR934X_PLL_VAL_100	0x00000101
+ #define AR934X_PLL_VAL_10	0x00001616
+ 
++#define QCA956X_PLL_VAL_1000	0x03000000
++#define QCA956X_PLL_VAL_100	0x00000101
++#define QCA956X_PLL_VAL_10	0x00001919
++
+ static void __init ath79_init_eth_pll_data(unsigned int id)
+ {
+ 	struct ath79_eth_pll_data *pll_data;
+@@ -575,13 +593,18 @@ static void __init ath79_init_eth_pll_da
+ 	case ATH79_SOC_QCA9533:
+ 	case ATH79_SOC_QCA9556:
+ 	case ATH79_SOC_QCA9558:
+-	case ATH79_SOC_QCA9561:
+ 	case ATH79_SOC_TP9343:
+ 		pll_10 = AR934X_PLL_VAL_10;
+ 		pll_100 = AR934X_PLL_VAL_100;
+ 		pll_1000 = AR934X_PLL_VAL_1000;
+ 		break;
+ 
++	case ATH79_SOC_QCA956X:
++		pll_10 = QCA956X_PLL_VAL_10;
++		pll_100 = QCA956X_PLL_VAL_100;
++		pll_1000 = QCA956X_PLL_VAL_1000;
++		break;
++
+ 	default:
+ 		BUG();
+ 	}
+@@ -656,6 +679,7 @@ static int __init ath79_setup_phy_if_mod
+ 
+ 		case ATH79_SOC_QCA9556:
+ 		case ATH79_SOC_QCA9558:
++		case ATH79_SOC_QCA956X:
+ 			switch (pdata->phy_if_mode) {
+ 			case PHY_INTERFACE_MODE_MII:
+ 			case PHY_INTERFACE_MODE_RGMII:
+@@ -666,11 +690,6 @@ static int __init ath79_setup_phy_if_mod
+ 			}
+ 			break;
+ 
+-		case ATH79_SOC_QCA9561:
+-			if (!pdata->phy_if_mode)
+-				pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
+-			break;
+-
+ 		default:
+ 			BUG();
+ 		}
+@@ -699,7 +718,7 @@ static int __init ath79_setup_phy_if_mod
+ 		case ATH79_SOC_AR7241:
+ 		case ATH79_SOC_AR9330:
+ 		case ATH79_SOC_AR9331:
+-		case ATH79_SOC_QCA9561:
++		case ATH79_SOC_QCA956X:
+ 		case ATH79_SOC_TP9343:
+ 			pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
+ 			break;
+@@ -1032,7 +1051,6 @@ void __init ath79_register_eth(unsigned
+ 			pdata->fifo_cfg3 = 0x01f00140;
+ 		break;
+ 
+-	case ATH79_SOC_QCA9561:
+ 	case ATH79_SOC_TP9343:
+ 		if (id == 0) {
+ 			pdata->reset_bit = AR933X_RESET_GE0_MAC |
+@@ -1100,6 +1118,34 @@ void __init ath79_register_eth(unsigned
+ 			pdata->fifo_cfg3 = 0x01f00140;
+ 		break;
+ 
++	case ATH79_SOC_QCA956X:
++		if (id == 0) {
++			pdata->reset_bit = QCA955X_RESET_GE0_MAC |
++					   QCA955X_RESET_GE0_MDIO;
++			if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
++				pdata->set_speed = qca956x_set_speed_sgmii;
++			else
++				/* FIXME */
++				pdata->set_speed = ath79_set_speed_dummy;
++		} else {
++			pdata->reset_bit = QCA955X_RESET_GE1_MAC |
++					   QCA955X_RESET_GE1_MDIO;
++			/* FIXME */
++			pdata->set_speed = ath79_set_speed_dummy;
++		}
++
++		pdata->ddr_flush = ath79_ddr_no_flush;
++		pdata->has_gbit = 1;
++		pdata->is_ar724x = 1;
++
++		if (!pdata->fifo_cfg1)
++			pdata->fifo_cfg1 = 0x0010ffff;
++		if (!pdata->fifo_cfg2)
++			pdata->fifo_cfg2 = 0x015500aa;
++		if (!pdata->fifo_cfg3)
++			pdata->fifo_cfg3 = 0x01f00140;
++		break;
++
+ 	default:
+ 		BUG();
+ 	}
+@@ -1140,7 +1186,6 @@ void __init ath79_register_eth(unsigned
+ 		case ATH79_SOC_AR9330:
+ 		case ATH79_SOC_AR9331:
+ 		case ATH79_SOC_QCA9533:
+-		case ATH79_SOC_QCA9561:
+ 		case ATH79_SOC_TP9343:
+ 			pdata->mii_bus_dev = &ath79_mdio1_device.dev;
+ 			break;