From: Sander Vanheule Date: Tue, 28 Jun 2022 19:15:00 +0000 (+0200) Subject: realtek: fix egress L2 learning on rtl839x X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4da0b5a786ca4817c0608881c957f5023b9eb72b;p=openwrt%2Fstaging%2Fstintel.git realtek: fix egress L2 learning on rtl839x The flag to enable L2 address learning on egress frames is in CPU header bit 40, with bit 0 being the leftmost bit of the header. This corresponds to BIT(7) in the third 16-bit value of the header. Correctly set L2LEARNING by fixing the off-by-one error. Fixes: 9eab76c84e31 ("realtek: Improve TX CPU-Tag usage") Tested-by: Luiz Angelo Daros de Luca Signed-off-by: Sander Vanheule (cherry picked from commit d6165ea75baea4f9039f3a378d55219c74b932a7) --- diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index aece1356e4..8c7813015a 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -127,7 +127,7 @@ static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio) h->cpu_tag[5] = BIT(dest_port) & 0xffff; } h->cpu_tag[2] |= BIT(4); // Enable destination port mask use - h->cpu_tag[2] |= BIT(8); // Enable L2 Learning + h->cpu_tag[2] |= BIT(7); // Enable L2 Learning // Set internal priority and AS_PRIO if (prio >= 0) h->cpu_tag[1] |= prio | BIT(3);