From: Robert Marko Date: Sun, 29 Oct 2023 10:00:50 +0000 (+0100) Subject: qualcommax: mark upstreamed patches as such X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4b7b3b97779ebada575bf310da56874f60a6554e;p=openwrt%2Fstaging%2Fldir.git qualcommax: mark upstreamed patches as such The GPLL fixes were merged upstream, so lets mark them as such. Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommax/patches-6.1/0131-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch b/target/linux/qualcommax/patches-6.1/0131-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch deleted file mode 100644 index a3e0c20f03..0000000000 --- a/target/linux/qualcommax/patches-6.1/0131-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 007ad475ba7f0d5d4d3e43a06e46a8a46d31c9d2 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:51 +0530 -Subject: [PATCH] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from - PLL clocks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based -on the request from dependent clocks. Doing so will result in the -unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL -clocks. - -Cc: stable@vger.kernel.org -Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") -Signed-off-by: Kathiravan Thirumoorthy ---- - drivers/clk/qcom/gcc-ipq8074.c | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq8074.c -+++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -76,7 +76,6 @@ static struct clk_fixed_factor gpll0_out - &gpll0_main.clkr.hw }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, -- .flags = CLK_SET_RATE_PARENT, - }, - }; - -@@ -122,7 +121,6 @@ static struct clk_alpha_pll_postdiv gpll - &gpll2_main.clkr.hw }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_ro_ops, -- .flags = CLK_SET_RATE_PARENT, - }, - }; - -@@ -155,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll - &gpll4_main.clkr.hw }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_ro_ops, -- .flags = CLK_SET_RATE_PARENT, - }, - }; - -@@ -189,7 +186,6 @@ static struct clk_alpha_pll_postdiv gpll - &gpll6_main.clkr.hw }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_ro_ops, -- .flags = CLK_SET_RATE_PARENT, - }, - }; - -@@ -202,7 +198,6 @@ static struct clk_fixed_factor gpll6_out - &gpll6_main.clkr.hw }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, -- .flags = CLK_SET_RATE_PARENT, - }, - }; - -@@ -267,7 +262,6 @@ static struct clk_alpha_pll_postdiv nss_ - &nss_crypto_pll_main.clkr.hw }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_ro_ops, -- .flags = CLK_SET_RATE_PARENT, - }, - }; - diff --git a/target/linux/qualcommax/patches-6.1/0132-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch b/target/linux/qualcommax/patches-6.1/0132-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch deleted file mode 100644 index ddd53f9d42..0000000000 --- a/target/linux/qualcommax/patches-6.1/0132-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch +++ /dev/null @@ -1,43 +0,0 @@ -From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:57 +0530 -Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock - provider - -While the kernel is booting up, APSS PLL will be running at 800MHz with -GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be -configured and select the rate based on the opp table and the source will -be changed to APSS_PLL_EARLY. - -Without this patch, CPU Freq driver reports that CPU is running at 24MHz -instead of the 800MHz. - -Reviewed-by: Konrad Dybcio -Tested-by: Robert Marko -Signed-off-by: Kathiravan Thirumoorthy ---- - drivers/clk/qcom/apss-ipq6018.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/clk/qcom/apss-ipq6018.c -+++ b/drivers/clk/qcom/apss-ipq6018.c -@@ -20,16 +20,19 @@ - - enum { - P_XO, -+ P_GPLL0, - P_APSS_PLL_EARLY, - }; - - static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { - { .fw_name = "xo" }, -+ { .fw_name = "gpll0" }, - { .fw_name = "pll" }, - }; - - static const struct parent_map parents_apcs_alias0_clk_src_map[] = { - { P_XO, 0 }, -+ { P_GPLL0, 4 }, - { P_APSS_PLL_EARLY, 5 }, - }; - diff --git a/target/linux/qualcommax/patches-6.1/0133-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch b/target/linux/qualcommax/patches-6.1/0133-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch deleted file mode 100644 index 693fb6cf2d..0000000000 --- a/target/linux/qualcommax/patches-6.1/0133-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001 -From: Kathiravan Thirumoorthy -Date: Thu, 14 Sep 2023 12:29:58 +0530 -Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock - provider for mailbox - -While the kernel is booting up, APSS PLL will be running at 800MHz with -GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be -configured to the rate based on the opp table and the source also will -be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, -with this inclusion, CPU Freq correctly reports that CPU is running at -800MHz rather than 24MHz. - -Signed-off-by: Kathiravan Thirumoorthy -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi -@@ -920,8 +920,8 @@ - apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq8074-apcs-apps-global"; - reg = <0x0b111000 0x1000>; -- clocks = <&a53pll>, <&xo>; -- clock-names = "pll", "xo"; -+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; -+ clock-names = "pll", "xo", "gpll0"; - - #clock-cells = <1>; - #mbox-cells = <1>; diff --git a/target/linux/qualcommax/patches-6.1/026-v6.7-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch b/target/linux/qualcommax/patches-6.1/026-v6.7-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch new file mode 100644 index 0000000000..a3e0c20f03 --- /dev/null +++ b/target/linux/qualcommax/patches-6.1/026-v6.7-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch @@ -0,0 +1,71 @@ +From 007ad475ba7f0d5d4d3e43a06e46a8a46d31c9d2 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:51 +0530 +Subject: [PATCH] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from + PLL clocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based +on the request from dependent clocks. Doing so will result in the +unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL +clocks. + +Cc: stable@vger.kernel.org +Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") +Signed-off-by: Kathiravan Thirumoorthy +--- + drivers/clk/qcom/gcc-ipq8074.c | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -76,7 +76,6 @@ static struct clk_fixed_factor gpll0_out + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, +- .flags = CLK_SET_RATE_PARENT, + }, + }; + +@@ -122,7 +121,6 @@ static struct clk_alpha_pll_postdiv gpll + &gpll2_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, +- .flags = CLK_SET_RATE_PARENT, + }, + }; + +@@ -155,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll + &gpll4_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, +- .flags = CLK_SET_RATE_PARENT, + }, + }; + +@@ -189,7 +186,6 @@ static struct clk_alpha_pll_postdiv gpll + &gpll6_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, +- .flags = CLK_SET_RATE_PARENT, + }, + }; + +@@ -202,7 +198,6 @@ static struct clk_fixed_factor gpll6_out + &gpll6_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, +- .flags = CLK_SET_RATE_PARENT, + }, + }; + +@@ -267,7 +262,6 @@ static struct clk_alpha_pll_postdiv nss_ + &nss_crypto_pll_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, +- .flags = CLK_SET_RATE_PARENT, + }, + }; + diff --git a/target/linux/qualcommax/patches-6.1/027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch b/target/linux/qualcommax/patches-6.1/027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch new file mode 100644 index 0000000000..ddd53f9d42 --- /dev/null +++ b/target/linux/qualcommax/patches-6.1/027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch @@ -0,0 +1,43 @@ +From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:57 +0530 +Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock + provider + +While the kernel is booting up, APSS PLL will be running at 800MHz with +GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be +configured and select the rate based on the opp table and the source will +be changed to APSS_PLL_EARLY. + +Without this patch, CPU Freq driver reports that CPU is running at 24MHz +instead of the 800MHz. + +Reviewed-by: Konrad Dybcio +Tested-by: Robert Marko +Signed-off-by: Kathiravan Thirumoorthy +--- + drivers/clk/qcom/apss-ipq6018.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/clk/qcom/apss-ipq6018.c ++++ b/drivers/clk/qcom/apss-ipq6018.c +@@ -20,16 +20,19 @@ + + enum { + P_XO, ++ P_GPLL0, + P_APSS_PLL_EARLY, + }; + + static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo" }, ++ { .fw_name = "gpll0" }, + { .fw_name = "pll" }, + }; + + static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, ++ { P_GPLL0, 4 }, + { P_APSS_PLL_EARLY, 5 }, + }; + diff --git a/target/linux/qualcommax/patches-6.1/028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch b/target/linux/qualcommax/patches-6.1/028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch new file mode 100644 index 0000000000..693fb6cf2d --- /dev/null +++ b/target/linux/qualcommax/patches-6.1/028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch @@ -0,0 +1,32 @@ +From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:58 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock + provider for mailbox + +While the kernel is booting up, APSS PLL will be running at 800MHz with +GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be +configured to the rate based on the opp table and the source also will +be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, +with this inclusion, CPU Freq correctly reports that CPU is running at +800MHz rather than 24MHz. + +Signed-off-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -920,8 +920,8 @@ + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x1000>; +- clocks = <&a53pll>, <&xo>; +- clock-names = "pll", "xo"; ++ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; ++ clock-names = "pll", "xo", "gpll0"; + + #clock-cells = <1>; + #mbox-cells = <1>;