From: Gabor Juhos <juhosg@openwrt.org>
Date: Tue, 9 Dec 2008 09:42:57 +0000 (+0000)
Subject: ag71xx driver: use same FIFO configuration for all SOC
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4b6e4d88a945e8d59b21b3c80d83a13dbed8e4a4;p=openwrt%2Fstaging%2Fnbd.git

ag71xx driver: use same FIFO configuration for all SOC

SVN-Revision: 13560
---

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index 36b6073aa3..7daa9f2066 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -38,7 +38,7 @@
 #define ETH_FCS_LEN	4
 
 #define AG71XX_DRV_NAME		"ag71xx"
-#define AG71XX_DRV_VERSION	"0.5.13"
+#define AG71XX_DRV_VERSION	"0.5.14"
 
 #define AG71XX_NAPI_WEIGHT	64
 #define AG71XX_OOM_REFILL	(1 + HZ/10)
@@ -227,7 +227,7 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG4_DV		BIT(1)	/* RX_DV Event */
 #define FIFO_CFG4_FC		BIT(2)	/* False Carrier */
 #define FIFO_CFG4_CE		BIT(3)	/* Code Error */
-#define FIFO_CFG4_CRC		BIT(4)	/* CRC error */
+#define FIFO_CFG4_CR		BIT(4)	/* CRC error */
 #define FIFO_CFG4_LM		BIT(5)	/* Length Mismatch */
 #define FIFO_CFG4_LO		BIT(6)	/* Length out of range */
 #define FIFO_CFG4_OK		BIT(7)	/* Packet is OK */
@@ -258,6 +258,8 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG5_VT		BIT(13)	/* VLAN tag detected */
 #define FIFO_CFG5_LE		BIT(14)	/* Long Event */
 #define FIFO_CFG5_FT		BIT(15)	/* Frame Truncated */
+#define FIFO_CFG5_16		BIT(16)	/* unknown */
+#define FIFO_CFG5_17		BIT(17)	/* unknown */
 #define FIFO_CFG5_SF		BIT(18)	/* Short Frame */
 #define FIFO_CFG5_BM		BIT(19)	/* Byte Mode */
 
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
index 01f9c03fee..58e3b11518 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
@@ -296,17 +296,6 @@ static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 }
 
-#define AR71XX_MAC_CFG1_INIT	(MAC_CFG1_RXE | MAC_CFG1_TXE | \
-				 MAC_CFG1_SRX | MAC_CFG1_STX)
-#define AR71XX_FIFO_CFG5_INIT	0x0007ffef
-
-#define AR91XX_MAC_CFG1_INIT	(MAC_CFG1_RXE | MAC_CFG1_TXE | \
-				 MAC_CFG1_SRX | MAC_CFG1_STX | \
-				 MAC_CFG1_TFC | MAC_CFG1_RFC)
-#define AR91XX_FIFO_CFG5_INIT	0x0007efef
-
-#define FIFO_CFG0_INIT	(FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
-
 static void ag71xx_dma_reset(struct ag71xx *ag)
 {
 	int i;
@@ -342,6 +331,25 @@ static void ag71xx_dma_reset(struct ag71xx *ag)
 	ag71xx_dump_dma_regs(ag);
 }
 
+#define MAC_CFG1_INIT	(MAC_CFG1_RXE | MAC_CFG1_TXE | \
+			 MAC_CFG1_SRX | MAC_CFG1_STX)
+
+#define FIFO_CFG0_INIT	(FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+
+#define FIFO_CFG4_INIT	(FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
+			 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
+			 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
+			 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
+			 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
+			 FIFO_CFG4_VT)
+
+#define FIFO_CFG5_INIT	(FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
+			 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
+			 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
+			 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
+			 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
+			 FIFO_CFG5_17 | FIFO_CFG5_SF)
+
 static void ag71xx_hw_init(struct ag71xx *ag)
 {
 	struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
@@ -355,8 +363,7 @@ static void ag71xx_hw_init(struct ag71xx *ag)
 	mdelay(100);
 
 	/* setup MAC configuration registers */
-	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
-		pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
+	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 	ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 		  MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 
@@ -370,10 +377,8 @@ static void ag71xx_hw_init(struct ag71xx *ag)
 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
-	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
-	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
-			pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
-					 : AR71XX_FIFO_CFG5_INIT);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
+	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 
 	ag71xx_dma_reset(ag);
 }