From: Vikram Kanigiri Date: Thu, 26 Feb 2015 15:25:58 +0000 (+0000) Subject: Use ARM CCI driver on FVP and Juno platforms X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4991ecdc50ff7b72e5d80b4cc8b6ef8c0fbe036e;p=project%2Fbcm63xx%2Fatf.git Use ARM CCI driver on FVP and Juno platforms This patch updates the FVP and Juno platform ports to use the common driver for ARM Cache Coherent Interconnects. Change-Id: Ib142f456b9b673600592616a2ec99e9b230d6542 --- diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 52916846..5e216737 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -61,6 +61,14 @@ #define MPIDR_AFFLVL1 1 #define MPIDR_AFFLVL2 2 #define MPIDR_AFFLVL3 3 +#define MPIDR_AFFLVL0_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL1_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL2_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL3_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) /* * The MPIDR_MAX_AFFLVL count starts from 0. Take care to * add one while using this macro to define array sizes. diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c index ddaacbaf..a8afb4e8 100644 --- a/plat/fvp/aarch64/fvp_common.c +++ b/plat/fvp/aarch64/fvp_common.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include #include @@ -295,6 +295,12 @@ uint64_t plat_get_syscnt_freq(void) return counter_base_frequency; } +/* Map of CCI masters with the slave interfaces they are connected */ +static const int cci_map[] = { + CCI400_CLUSTER0_SL_IFACE_IX, + CCI400_CLUSTER1_SL_IFACE_IX +}; + void fvp_cci_init(void) { /* @@ -302,19 +308,20 @@ void fvp_cci_init(void) */ if (plat_config.flags & CONFIG_HAS_CCI) cci_init(CCI400_BASE, - CCI400_SL_IFACE3_CLUSTER_IX, - CCI400_SL_IFACE4_CLUSTER_IX); + cci_map, + ARRAY_SIZE(cci_map)); } void fvp_cci_enable(void) { - /* - * Enable CCI-400 coherency for this cluster. No need - * for locks as no other cpu is active at the - * moment - */ if (plat_config.flags & CONFIG_HAS_CCI) - cci_enable_cluster_coherency(read_mpidr()); + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void fvp_cci_disable(void) +{ + if (plat_config.flags & CONFIG_HAS_CCI) + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); } void fvp_gic_init(void) diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h index e3442fce..a2f2da8c 100644 --- a/plat/fvp/fvp_def.h +++ b/plat/fvp/fvp_def.h @@ -236,8 +236,8 @@ * CCI-400 related constants ******************************************************************************/ #define CCI400_BASE 0x2c090000 -#define CCI400_SL_IFACE3_CLUSTER_IX 0 -#define CCI400_SL_IFACE4_CLUSTER_IX 1 +#define CCI400_CLUSTER0_SL_IFACE_IX 3 +#define CCI400_CLUSTER1_SL_IFACE_IX 4 /******************************************************************************* * GIC-400 & interrupt handling related constants diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c index c15d845d..3737ecff 100644 --- a/plat/fvp/fvp_pm.c +++ b/plat/fvp/fvp_pm.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include #include @@ -82,8 +82,7 @@ static void fvp_cluster_pwrdwn_common(void) uint64_t mpidr = read_mpidr_el1(); /* Disable coherency if this cluster is to be turned off */ - if (get_plat_config()->flags & CONFIG_HAS_CCI) - cci_disable_cluster_coherency(mpidr); + fvp_cci_disable(); /* Program the power controller to turn the cluster off */ fvp_pwrc_write_pcoffr(mpidr); diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h index 3949754b..4f60a161 100644 --- a/plat/fvp/fvp_private.h +++ b/plat/fvp/fvp_private.h @@ -138,6 +138,7 @@ int fvp_config_setup(void); void fvp_cci_init(void); void fvp_cci_enable(void); +void fvp_cci_disable(void); void fvp_gic_init(void); diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S index f050261f..9e5ef4d5 100644 --- a/plat/fvp/include/plat_macros.S +++ b/plat/fvp/include/plat_macros.S @@ -27,7 +27,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include #include #include #include "../fvp_def.h" diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk index bcee3286..7cf571e4 100644 --- a/plat/fvp/platform.mk +++ b/plat/fvp/platform.mk @@ -57,7 +57,7 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ plat/common/aarch64/plat_common.c \ plat/fvp/fvp_io_storage.c -BL1_SOURCES += drivers/arm/cci400/cci400.c \ +BL1_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ @@ -72,7 +72,7 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ plat/fvp/fvp_security.c \ plat/fvp/aarch64/fvp_common.c -BL31_SOURCES += drivers/arm/cci400/cci400.c \ +BL31_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c index 371323e7..6b6e1851 100644 --- a/plat/juno/aarch64/juno_common.c +++ b/plat/juno/aarch64/juno_common.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -136,6 +137,18 @@ const unsigned int irq_sec_array[] = { IRQ_SEC_SGI_7 }; +static const int cci_map[] = { + CCI400_CLUSTER0_SL_IFACE_IX, + CCI400_CLUSTER1_SL_IFACE_IX +}; + +void plat_cci_init(void) +{ + cci_init(CCI400_BASE, + cci_map, + ARRAY_SIZE(cci_map)); +} + /******************************************************************************* * Macro generating the code for the function setting up the pagetables as per * the platform memory map & initialize the mmu, for the given exception level diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c index 23e8592b..fd331bf6 100644 --- a/plat/juno/bl1_plat_setup.c +++ b/plat/juno/bl1_plat_setup.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include #include @@ -82,10 +82,8 @@ void bl1_early_platform_setup(void) * Enable CCI-400 for this cluster. No need for locks as no other cpu is * active at the moment */ - cci_init(CCI400_BASE, - CCI400_SL_IFACE3_CLUSTER_IX, - CCI400_SL_IFACE4_CLUSTER_IX); - cci_enable_cluster_coherency(read_mpidr()); + plat_cci_init(); + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = TZRAM_BASE; diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c index 1d337688..194d6205 100644 --- a/plat/juno/bl31_plat_setup.c +++ b/plat/juno/bl31_plat_setup.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include #include @@ -123,9 +123,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, * a warm boot. BL1 should have already enabled CCI coherency for this * cluster during cold boot. */ - cci_init(CCI400_BASE, - CCI400_SL_IFACE3_CLUSTER_IX, - CCI400_SL_IFACE4_CLUSTER_IX); + plat_cci_init(); /* * Check params passed from BL2 should not be NULL, diff --git a/plat/juno/include/plat_macros.S b/plat/juno/include/plat_macros.S index a9d2466b..ac1077b2 100644 --- a/plat/juno/include/plat_macros.S +++ b/plat/juno/include/plat_macros.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include #include #include "platform_def.h" #include "../juno_def.h" diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h index 62bdda3b..ab39f3ca 100644 --- a/plat/juno/juno_def.h +++ b/plat/juno/juno_def.h @@ -261,8 +261,8 @@ * CCI-400 related constants ******************************************************************************/ #define CCI400_BASE 0x2c090000 -#define CCI400_SL_IFACE3_CLUSTER_IX 1 -#define CCI400_SL_IFACE4_CLUSTER_IX 0 +#define CCI400_CLUSTER0_SL_IFACE_IX 4 +#define CCI400_CLUSTER1_SL_IFACE_IX 3 /******************************************************************************* * SCP <=> AP boot configuration diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h index 9a5944ca..afb1bfcf 100644 --- a/plat/juno/juno_private.h +++ b/plat/juno/juno_private.h @@ -154,6 +154,7 @@ unsigned long plat_get_ns_image_entrypoint(void); unsigned long platform_get_stack(unsigned long mpidr); uint64_t plat_get_syscnt_freq(void); void plat_gic_init(void); +void plat_cci_init(void); /* Declarations for plat_topology.c */ int plat_setup_topology(void); diff --git a/plat/juno/plat_pm.c b/plat/juno/plat_pm.c index 47338cfc..953e5f72 100644 --- a/plat/juno/plat_pm.c +++ b/plat/juno/plat_pm.c @@ -31,8 +31,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -159,8 +159,7 @@ void juno_affinst_on_finish(uint32_t afflvl, uint32_t state) * if this cluster was off. */ if (afflvl != MPIDR_AFFLVL0) - cci_enable_cluster_coherency(mpidr); - + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); /* Enable the gic cpu interface */ arm_gic_cpuif_setup(); @@ -187,7 +186,7 @@ static void juno_power_down_common(uint32_t afflvl) /* Cluster is to be turned off, so disable coherency */ if (afflvl > MPIDR_AFFLVL0) { - cci_disable_cluster_coherency(read_mpidr_el1()); + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); cluster_state = scpi_power_off; } diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk index 8beaecf0..9e44b235 100644 --- a/plat/juno/platform.mk +++ b/plat/juno/platform.mk @@ -56,7 +56,7 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ plat/common/plat_gic.c \ plat/juno/plat_io_storage.c -BL1_SOURCES += drivers/arm/cci400/cci400.c \ +BL1_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/aarch64/platform_up_stack.S \ @@ -75,7 +75,7 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ plat/juno/scp_bootloader.c \ plat/juno/scpi.c -BL31_SOURCES += drivers/arm/cci400/cci400.c \ +BL31_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \