From: Charlene Liu Date: Tue, 7 May 2019 20:12:02 +0000 (-0500) Subject: drm/amd/display: Add hubp_init entry to hubp vtable X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4850ce697f9892df083bd7b3ec7c715404dd4279;p=openwrt%2Fstaging%2Fblogic.git drm/amd/display: Add hubp_init entry to hubp vtable Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1 and DCN2. In addition, future HW will need to access the HUBPREQ_DEBUG and CUR_TTU_CNTL0 register for hubp_init. Add that here. Signed-off-by: Charlene Liu Reviewed-by: Jun Lei Acked-by: Leo Li Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c index 529bdc2f2975..82738f126517 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c @@ -675,9 +675,11 @@ static struct hubp_funcs dcn20_hubp_funcs = { .dmdata_status_done = hubp2_dmdata_status_done, .hubp_read_state = hubp1_read_state, .hubp_clear_underflow = hubp1_clear_underflow, - .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp1_init, }; + bool hubp2_construct( struct dcn20_hubp *hubp2, struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h index 9f56c1d2d188..f790ab9db6eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h @@ -62,6 +62,7 @@ SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\ SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\ SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\ + SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\ SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\ SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ SRI(VMID_SETTINGS_0, HUBPREQ, id) @@ -146,6 +147,7 @@ uint32_t FLIP_PARAMETERS_0;\ uint32_t FLIP_PARAMETERS_1;\ uint32_t FLIP_PARAMETERS_2;\ + uint32_t DCN_CUR1_TTU_CNTL0;\ uint32_t DCN_CUR1_TTU_CNTL1;\ uint32_t VMID_SETTINGS_0;\ uint32_t FLIP_PARAMETERS_3;\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 2ea72e965c1b..e7580e6e0fb6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -601,6 +601,8 @@ static void dcn20_init_hw(struct dc *dc) hubp->power_gated = false; pipe_ctx->stream_res.opp = NULL; + hubp->funcs->hubp_init(hubp); + //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; @@ -1224,7 +1226,7 @@ static void dcn20_program_all_pipe_in_tree( dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context); } -static void dcn20_pipe_control_lock_global( +void dcn20_pipe_control_lock_global( struct dc *dc, struct pipe_ctx *pipe, bool lock) @@ -1244,7 +1246,7 @@ static void dcn20_pipe_control_lock_global( } } -static void dcn20_pipe_control_lock( +void dcn20_pipe_control_lock( struct dc *dc, struct pipe_ctx *pipe, bool lock) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index e7a21fc9845b..fa98c96d0046 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -145,11 +145,11 @@ struct hubp_funcs { uint32_t dmdata_sw_size, const uint32_t *dmdata_sw_data); bool (*dmdata_status_done)(struct hubp *hubp); - void(*hubp_enable_tripleBuffer)( + void (*hubp_enable_tripleBuffer)( struct hubp *hubp, bool enable); - bool(*hubp_is_triplebuffer_enabled)( + bool (*hubp_is_triplebuffer_enabled)( struct hubp *hubp); void (*hubp_set_flip_control_surface_gsl)(