From: Enric Balletbò i Serra <eballetbo@gmail.com>
Date: Sun, 5 Aug 2012 00:55:56 +0000 (+0000)
Subject: OMAP3: fix DRAM size for IGEP-based boards.
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4833b0939ad1abba1c327be9d3a627509c916c39;p=project%2Fbcm63xx%2Fu-boot.git

OMAP3: fix DRAM size for IGEP-based boards.

The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the
LPDDR memory consist on two dies of 256MiB.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
---

diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index a4d099a5db..a8257a3005 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -77,19 +77,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 {
 	*mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-	*mcfg = MICRON_V_MCFG_200(512 << 20);
+	*mcfg = MICRON_V_MCFG_200(256 << 20);
 	*ctrla = MICRON_V_ACTIMA_200;
 	*ctrlb = MICRON_V_ACTIMB_200;
 	*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
 	if (get_cpu_family() == CPU_OMAP34XX) {
-		*mcfg = NUMONYX_V_MCFG_165(512 << 20);
+		*mcfg = NUMONYX_V_MCFG_165(256 << 20);
 		*ctrla = NUMONYX_V_ACTIMA_165;
 		*ctrlb = NUMONYX_V_ACTIMB_165;
 		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
 	} else {
-		*mcfg = NUMONYX_V_MCFG_200(512 << 20);
+		*mcfg = NUMONYX_V_MCFG_200(256 << 20);
 		*ctrla = NUMONYX_V_ACTIMA_200;
 		*ctrlb = NUMONYX_V_ACTIMB_200;
 		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 4f8b6452df..107cb7f8e0 100644
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -64,19 +64,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 {
 	*mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-	*mcfg = MICRON_V_MCFG_200(512 << 20);
+	*mcfg = MICRON_V_MCFG_200(256 << 20);
 	*ctrla = MICRON_V_ACTIMA_200;
 	*ctrlb = MICRON_V_ACTIMB_200;
 	*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
 	if (get_cpu_family() == CPU_OMAP34XX) {
-		*mcfg = NUMONYX_V_MCFG_165(512 << 20);
+		*mcfg = NUMONYX_V_MCFG_165(256 << 20);
 		*ctrla = NUMONYX_V_ACTIMA_165;
 		*ctrlb = NUMONYX_V_ACTIMB_165;
 		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
 	} else {
-		*mcfg = NUMONYX_V_MCFG_200(512 << 20);
+		*mcfg = NUMONYX_V_MCFG_200(256 << 20);
 		*ctrla = NUMONYX_V_ACTIMA_200;
 		*ctrlb = NUMONYX_V_ACTIMB_200;
 		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;