From: Florian Fainelli Date: Fri, 30 Nov 2012 10:53:55 +0000 (+0000) Subject: remove support for ubicom32 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=4801705d83e49f716eedd4014ec273c7617f11f3;p=openwrt%2Fstaging%2Fstintel.git remove support for ubicom32 Signed-off-by: Florian Fainelli SVN-Revision: 34432 --- diff --git a/scripts/config.sub b/scripts/config.sub index f4bdcd555e..df65a92201 100755 --- a/scripts/config.sub +++ b/scripts/config.sub @@ -298,7 +298,6 @@ case $basic_machine in | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ | spu | strongarm \ | tahoe | thumb | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ - | ubicom32 \ | v850 | v850e \ | we32k \ | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ @@ -395,7 +394,6 @@ case $basic_machine in | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ | tile-* | tilegx-* \ | tron-* \ - | ubicom32-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ diff --git a/toolchain/binutils/Config.in b/toolchain/binutils/Config.in index 90cfc346ea..414b1d905a 100644 --- a/toolchain/binutils/Config.in +++ b/toolchain/binutils/Config.in @@ -2,14 +2,13 @@ choice prompt "Binutils Version" if TOOLCHAINOPTS - default BINUTILS_VERSION_2_19_1 if ubicom32 + default BINUTILS_VERSION_2_19_1 default BINUTILS_VERSION_2_20_1 if avr32 default BINUTILS_VERSION_2_22 help Select the version of binutils you wish to use. config BINUTILS_VERSION_2_19_1 - depends ubicom32 bool "binutils 2.19.1" config BINUTILS_VERSION_2_20_1 @@ -17,17 +16,14 @@ choice bool "binutils 2.20.1" config BINUTILS_VERSION_2_21_1 - depends !ubicom32 depends !avr32 || (avr32 && BROKEN) bool "binutils 2.21.1" config BINUTILS_VERSION_2_22 - depends !ubicom32 || (ubicom32 && BROKEN) depends !avr32 || (avr32 && BROKEN) bool "binutils 2.22" config BINUTILS_VERSION_2_23_1 - depends !ubicom32 || (ubicom32 && BROKEN) depends !avr32 || (avr32 && BROKEN) bool "binutils 2.23.1" @@ -48,6 +44,5 @@ config BINUTILS_VERSION default "2.21.1" if BINUTILS_VERSION_2_21_1 default "2.22" if BINUTILS_VERSION_2_22 default "2.23.1" if BINUTILS_VERSION_2_23_1 - default "2.19.1" if ubicom32 default "2.20.1" if avr32 default "2.22" diff --git a/toolchain/binutils/patches/2.19.1/600-ubicom32_binutils_20090818.patch b/toolchain/binutils/patches/2.19.1/600-ubicom32_binutils_20090818.patch deleted file mode 100644 index aed373ddd4..0000000000 --- a/toolchain/binutils/patches/2.19.1/600-ubicom32_binutils_20090818.patch +++ /dev/null @@ -1,48949 +0,0 @@ ---- a/bfd/archures.c -+++ b/bfd/archures.c -@@ -375,6 +375,11 @@ DESCRIPTION - . bfd_arch_score, {* Sunplus score *} - . bfd_arch_openrisc, {* OpenRISC *} - . bfd_arch_mmix, {* Donald Knuth's educational processor. *} -+. bfd_arch_ubicom32, -+.#define bfd_mach_ubicom32 0 -+.#define bfd_mach_ubicom32dsp 1 -+.#define bfd_mach_ubicom32ver4 2 -+.#define bfd_mach_ubicom32posix 3 - . bfd_arch_xstormy16, - .#define bfd_mach_xstormy16 1 - . bfd_arch_msp430, {* Texas Instruments MSP430 architecture. *} -@@ -501,6 +506,7 @@ extern const bfd_arch_info_type bfd_tic3 - extern const bfd_arch_info_type bfd_tic4x_arch; - extern const bfd_arch_info_type bfd_tic54x_arch; - extern const bfd_arch_info_type bfd_tic80_arch; -+extern const bfd_arch_info_type bfd_ubicom32_arch; - extern const bfd_arch_info_type bfd_v850_arch; - extern const bfd_arch_info_type bfd_vax_arch; - extern const bfd_arch_info_type bfd_we32k_arch; -@@ -570,6 +576,7 @@ static const bfd_arch_info_type * const - &bfd_tic4x_arch, - &bfd_tic54x_arch, - &bfd_tic80_arch, -+ &bfd_ubicom32_arch, - &bfd_v850_arch, - &bfd_vax_arch, - &bfd_w65_arch, ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -1997,6 +1997,11 @@ enum bfd_architecture - bfd_arch_score, /* Sunplus score */ - bfd_arch_openrisc, /* OpenRISC */ - bfd_arch_mmix, /* Donald Knuth's educational processor. */ -+ bfd_arch_ubicom32, -+#define bfd_mach_ubicom32 0 -+#define bfd_mach_ubicom32dsp 1 -+#define bfd_mach_ubicom32ver4 2 -+#define bfd_mach_ubicom32posix 3 - bfd_arch_xstormy16, - #define bfd_mach_xstormy16 1 - bfd_arch_msp430, /* Texas Instruments MSP430 architecture. */ -@@ -3908,6 +3913,41 @@ instructions */ - BFD_RELOC_VPE4KMATH_DATA, - BFD_RELOC_VPE4KMATH_INSN, - -+/* Ubicom UBICOM32 Relocations. */ -+ BFD_RELOC_UBICOM32_21_PCREL, -+ BFD_RELOC_UBICOM32_24_PCREL, -+ BFD_RELOC_UBICOM32_HI24, -+ BFD_RELOC_UBICOM32_LO7_S, -+ BFD_RELOC_UBICOM32_LO7_2_S, -+ BFD_RELOC_UBICOM32_LO7_4_S, -+ BFD_RELOC_UBICOM32_LO7_D, -+ BFD_RELOC_UBICOM32_LO7_2_D, -+ BFD_RELOC_UBICOM32_LO7_4_D, -+ BFD_RELOC_UBICOM32_LO7_CALLI, -+ BFD_RELOC_UBICOM32_LO16_CALLI, -+ BFD_RELOC_UBICOM32_GOT_HI24, -+ BFD_RELOC_UBICOM32_GOT_LO7_S, -+ BFD_RELOC_UBICOM32_GOT_LO7_2_S, -+ BFD_RELOC_UBICOM32_GOT_LO7_4_S, -+ BFD_RELOC_UBICOM32_GOT_LO7_D, -+ BFD_RELOC_UBICOM32_GOT_LO7_2_D, -+ BFD_RELOC_UBICOM32_GOT_LO7_4_D, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D, -+ BFD_RELOC_UBICOM32_GOT_LO7_CALLI, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI, -+ BFD_RELOC_UBICOM32_FUNCDESC_VALUE, -+ BFD_RELOC_UBICOM32_FUNCDESC, -+ BFD_RELOC_UBICOM32_GOTOFFSET_LO, -+ BFD_RELOC_UBICOM32_GOTOFFSET_HI, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO, -+ BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI, -+ - /* These two relocations are used by the linker to determine which of - the entries in a C++ virtual function table are actually used. When - the --gc-sections option is given, the linker will zero out the entries ---- a/bfd/config.bfd -+++ b/bfd/config.bfd -@@ -1432,6 +1432,11 @@ case "${targ}" in - targ_underscore=yes - ;; - -+ ubicom32-*-*) -+ targ_defvec=bfd_elf32_ubicom32_vec -+ targ_selvecs=bfd_elf32_ubicom32fdpic_vec -+ ;; -+ - v850-*-*) - targ_defvec=bfd_elf32_v850_vec - ;; ---- a/bfd/configure -+++ b/bfd/configure -@@ -19743,6 +19743,8 @@ do - bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_us_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; -+ bfd_elf32_ubicom32_vec) tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;; -+ bfd_elf32_ubicom32fdpic_vec) tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;; - bfd_elf32_v850_vec) tb="$tb elf32-v850.lo elf32.lo $elf" ;; - bfd_elf32_vax_vec) tb="$tb elf32-vax.lo elf32.lo $elf" ;; - bfd_elf32_xstormy16_vec) tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;; ---- a/bfd/configure.in -+++ b/bfd/configure.in -@@ -736,6 +736,8 @@ do - bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;; - bfd_elf32_us_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; -+ bfd_elf32_ubicom32_vec) tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;; -+ bfd_elf32_ubicom32fdpic_vec) tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;; - bfd_elf32_v850_vec) tb="$tb elf32-v850.lo elf32.lo $elf" ;; - bfd_elf32_vax_vec) tb="$tb elf32-vax.lo elf32.lo $elf" ;; - bfd_elf32_xstormy16_vec) tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;; ---- /dev/null -+++ b/bfd/cpu-ubicom32.c -@@ -0,0 +1,126 @@ -+/* BFD support for the Ubicom32 processor. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ -+This file is part of BFD, the Binary File Descriptor library. -+ -+This program is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2 of the License, or -+(at your option) any later version. -+ -+This program is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with this program; if not, write to the Free Software -+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#include "bfd.h" -+#include "sysdep.h" -+#include "libbfd.h" -+ -+static const bfd_arch_info_type * -+ubicom32_arch_compatible (const bfd_arch_info_type *a, -+ const bfd_arch_info_type *b) -+{ -+ if (a->arch != b->arch) -+ return NULL; -+ -+ if (a->bits_per_word != b->bits_per_word) -+ return NULL; -+ -+ if (a->mach > b->mach) -+ return a; -+ -+ if (b->mach > a->mach) -+ return b; -+ -+ if (b->mach == bfd_mach_ubicom32ver4 && -+ strcmp("ubicom32uclinux", b->printable_name) == 0) { -+ return b; -+ } -+ -+ return a; -+} -+ -+const bfd_arch_info_type bfd_ubicom32_uclinux_arch = -+{ -+ 32, /* bits per word */ -+ 32, /* bits per address */ -+ 8, /* bits per byte */ -+ bfd_arch_ubicom32, /* architecture */ -+ bfd_mach_ubicom32ver4, /* machine */ -+ "ubicom32", /* architecture name */ -+ "ubicom32uclinux", /* printable name */ -+ 3, /* section align power */ -+ FALSE, /* the default ? */ -+ ubicom32_arch_compatible, /* architecture comparison fn */ -+ bfd_default_scan, /* string to architecture convert fn */ -+ NULL /* next in list */ -+}; -+ -+const bfd_arch_info_type bfd_ubicom32_posix_arch = -+{ -+ 32, /* bits per word */ -+ 32, /* bits per address */ -+ 8, /* bits per byte */ -+ bfd_arch_ubicom32, /* architecture */ -+ bfd_mach_ubicom32ver4, /* machine */ -+ "ubicom32", /* architecture name */ -+ "ubicom32posix", /* printable name */ -+ 3, /* section align power */ -+ FALSE, /* the default ? */ -+ bfd_default_compatible, /* architecture comparison fn */ -+ bfd_default_scan, /* string to architecture convert fn */ -+ &bfd_ubicom32_uclinux_arch, /* next in list */ -+}; -+ -+const bfd_arch_info_type bfd_ubicom32_ver4_arch = -+{ -+ 32, /* bits per word */ -+ 32, /* bits per address */ -+ 8, /* bits per byte */ -+ bfd_arch_ubicom32, /* architecture */ -+ bfd_mach_ubicom32ver4, /* machine */ -+ "ubicom32", /* architecture name */ -+ "ubicom32ver4", /* printable name */ -+ 3, /* section align power */ -+ FALSE, /* the default ? */ -+ ubicom32_arch_compatible, /* architecture comparison fn */ -+ bfd_default_scan, /* string to architecture convert fn */ -+ &bfd_ubicom32_posix_arch /* next in list */ -+}; -+ -+const bfd_arch_info_type bfd_ubicom32_nonext_arch = -+{ -+ 32, /* bits per word */ -+ 32, /* bits per address */ -+ 8, /* bits per byte */ -+ bfd_arch_ubicom32, /* architecture */ -+ bfd_mach_ubicom32dsp, /* machine */ -+ "ubicom32", /* architecture name */ -+ "ubicom32dsp", /* printable name */ -+ 3, /* section align power */ -+ FALSE, /* the default ? */ -+ bfd_default_compatible, /* architecture comparison fn */ -+ bfd_default_scan, /* string to architecture convert fn */ -+ & bfd_ubicom32_ver4_arch /* next in list */ -+}; -+ -+const bfd_arch_info_type bfd_ubicom32_arch = -+{ -+ 32, /* bits per word */ -+ 32, /* bits per address */ -+ 8, /* bits per byte */ -+ bfd_arch_ubicom32, /* architecture */ -+ bfd_mach_ubicom32, /* machine */ -+ "ubicom32", /* architecture name */ -+ "ubicom32", /* printable name */ -+ 3, /* section align power */ -+ TRUE, /* the default ? */ -+ bfd_default_compatible, /* architecture comparison fn */ -+ bfd_default_scan, /* string to architecture convert fn */ -+ & bfd_ubicom32_nonext_arch /* next in list */ -+}; ---- a/bfd/doc/archures.texi -+++ b/bfd/doc/archures.texi -@@ -303,6 +303,11 @@ enum bfd_architecture - bfd_arch_ip2k, /* Ubicom IP2K microcontrollers. */ - #define bfd_mach_ip2022 1 - #define bfd_mach_ip2022ext 2 -+ bfd_arch_ubicom32, -+#define bfd_mach_ubicom32 0 -+#define bfd_mach_ubicom32dsp 1 -+#define bfd_mach_ubicom32ver4 2 -+#define bfd_mach_ubicom32posix 3 - bfd_arch_iq2000, /* Vitesse IQ2000. */ - #define bfd_mach_iq2000 1 - #define bfd_mach_iq10 2 ---- /dev/null -+++ b/bfd/elf32-ubicom32.c -@@ -0,0 +1,5008 @@ -+/* Ubicom32 specific support for 32-bit ELF -+ Copyright 2000 Free Software Foundation, Inc. -+ -+This file is part of BFD, the Binary File Descriptor library. -+ -+This program is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2 of the License, or -+(at your option) any later version. -+ -+This program is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with this program; if not, write to the Free Software -+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#include -+#include "bfd.h" -+#include "sysdep.h" -+#include "libbfd.h" -+#include "elf-bfd.h" -+#include "elf/ubicom32.h" -+#include "elf/dwarf2.h" -+ -+/* Call offset = signed 24bit word offset -+ => 26bit signed byte offset. */ -+#define UBICOM32_CALL_MAX_POS_OFFS ((1 << 25) - 1) -+#define UBICOM32_CALL_MAX_NEG_OFFS (-(1 << 25)) -+ -+#define UNDEFINED_SYMBOL (~(bfd_vma)0) -+#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset) -+ -+#if 0 -+#define DPRINTF(fmt, ...) { printf("DBG %4d:" fmt, __LINE__, __VA_ARGS__); fflush(stdout); } -+#else -+#define DPRINTF(fmt, ...) {} -+#endif -+struct debugLineInfo { -+ unsigned int startOffset; -+ unsigned int length; -+ char *sectionName; -+ unsigned int startRelocIndex; -+ unsigned int endRelocIndex; -+ unsigned int discard; -+}; -+ -+struct debugLineInfoHeader { -+ unsigned int numEntries; -+ struct debugLineInfo linfo[1]; -+}; -+ -+/* we want RELA relocations, not REL */ -+#undef USE_REL -+#define USE_RELA -+ -+static bfd_reloc_status_type ubicom32_elf_generic_reloc -+ PARAMS ((bfd *abfd, arelent *reloc_entry, asymbol *symbol, PTR data, -+ asection *input_section, bfd *output_bfd, char **error_message)); -+static bfd_reloc_status_type ubicom32_elf_relocate_hi16 -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo16 -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_hi24 -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo7_s -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo7_2_s -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo7_4_s -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo7_d -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo7_2_d -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo7_4_d -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_pcrel24 -+ PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); -+static bfd_reloc_status_type ubicom32_elf_relocate_lo_calli -+ PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma, int)); -+ -+static void ubicom32_info_to_howto_rela -+ PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -+ -+static reloc_howto_type * ubicom32_reloc_type_lookup -+ PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -+ -+static bfd_vma symbol_value -+ PARAMS ((bfd *, Elf_Internal_Rela *)); -+static Elf_Internal_Shdr *file_symtab_hdr -+ PARAMS ((bfd *)); -+static Elf_Internal_Sym *file_isymbuf -+ PARAMS ((bfd *)); -+static Elf_Internal_Rela *section_relocs -+ PARAMS ((bfd *, asection *)); -+static bfd_byte *section_contents -+ PARAMS ((bfd *, asection *)); -+static bfd_boolean ubicom32_elf_relax_section -+ PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *)); -+static bfd_boolean ubicom32_elf_relax_calli -+ PARAMS ((bfd *, asection *, bfd_boolean *)); -+static bfd_boolean ubicom32_elf_relax_delete_bytes -+ PARAMS ((bfd *, asection *, bfd_vma, int)); -+static void adjust_sec_relocations -+ PARAMS ((bfd *, asection *, asection *, bfd_vma, int)); -+static void adjust_all_relocations -+ PARAMS ((bfd *, asection *, bfd_vma, int)); -+ -+static bfd_reloc_status_type ubicom32_final_link_relocate -+ PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, -+ Elf_Internal_Rela *, bfd_vma)); -+static bfd_boolean ubicom32_elf_relocate_section -+ PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, -+ bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, -+ asection **)); -+ -+static bfd_boolean ubicom32_elf_gc_sweep_hook -+ PARAMS ((bfd *, struct bfd_link_info *, asection *, const -+ Elf_Internal_Rela *)); -+static asection * ubicom32_elf_gc_mark_hook -+ PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, struct -+ elf_link_hash_entry *, Elf_Internal_Sym *)); -+static bfd_boolean ubicom32_elf_check_relocs -+ PARAMS ((bfd *, struct bfd_link_info *, asection *, -+ const Elf_Internal_Rela *)); -+extern bfd_boolean ubicom32_elf_discard_info -+ PARAMS ((bfd *, struct elf_reloc_cookie *, struct bfd_link_info *)); -+ -+static bfd_boolean ubicom32_elf_object_p PARAMS ((bfd *)); -+static bfd_boolean ubicom32_elf_set_private_flags PARAMS ((bfd *, flagword)); -+static bfd_boolean ubicom32_elf_copy_private_bfd_data PARAMS ((bfd *, bfd *)); -+static bfd_boolean ubicom32_elf_merge_private_bfd_data PARAMS ((bfd *, bfd *)); -+static bfd_boolean ubicom32_elf_print_private_bfd_data PARAMS ((bfd *, PTR)); -+ -+//static unsigned long read_unsigned_leb128 (bfd *, char *, unsigned int *); -+ -+//static long read_signed_leb128 (bfd *, char *, unsigned int *); -+ -+/* read dwarf information from a buffer */ -+ -+#define UBICOM32_HOWTO(t,rs,s,bs,pr,bp,name,sm,dm) \ -+ HOWTO(t, /* type */ \ -+ rs, /* rightshift */ \ -+ s, /* size (0 = byte, 1 = short, 2 = long) */ \ -+ bs, /* bitsize */ \ -+ pr, /* pc_relative */ \ -+ bp, /* bitpos */ \ -+ complain_overflow_bitfield, /* complain_on_overflow */ \ -+ ubicom32_elf_generic_reloc, /* special_function */ \ -+ name, /* name */ \ -+ FALSE, /* partial_inplace */ \ -+ sm, /* src_mask */ \ -+ dm, /* dst_mask */ \ -+ pr) /* pcrel_offset */ -+ -+/* Special Note: For addresses, we must always zero out the top byte of a -+ address because the harvard address space is represented as -+ a single virtual address space that uses the top byte to denote -+ whether the address belongs in the data or program space. This is -+ done to accomodate GDB which cannot handle program and data addresses -+ overlapping. */ -+ -+static reloc_howto_type ubicom32_elf_howto_table [] = -+{ -+ /* This reloc does nothing. */ -+ UBICOM32_HOWTO (R_UBICOM32_NONE, 0, 2, 32, FALSE, 0, "R_UBICOM32_NONE", 0, 0), -+ -+ /* A 16 bit absolute relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_16, 0, 1, 16, FALSE, 0, "R_UBICOM32_16", 0, 0xffff), -+ -+ /* A 32 bit absolute relocation. Must zero top byte of virtual address. */ -+ UBICOM32_HOWTO (R_UBICOM32_32, 0, 2, 32, FALSE, 0, "R_UBICOM32_32", 0, 0xffffffff), -+ -+ /* A 16 bit indirect relocation, low 16 bits of 32 */ -+ UBICOM32_HOWTO (R_UBICOM32_LO16, 0, 2, 16, FALSE, 0, "R_UBICOM32_LO16", 0x0, 0x0000ffff), -+ -+ /* A 16 bit indirect relocation, high 16 bits of 32 - must zero top byte of virtual address */ -+ UBICOM32_HOWTO (R_UBICOM32_HI16, 0, 2, 16, FALSE, 0, "R_UBICOM32_HI16", 0x0, 0x0000ffff), -+ -+ /* A 21 bit relative relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_21_PCREL, 2, 2, 21, TRUE, 0, "R_UBICOM32_21_PCREL", 0x0, 0x001fffff), -+ -+ /* A 24 bit relative relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_24_PCREL, 2, 2, 24, TRUE, 0, "R_UBICOM32_24_PCREL", 0x0, 0x071fffff), -+ -+ /* A 24 bit indirect relocation, bits 31:7 - assume top byte zero. */ -+ UBICOM32_HOWTO (R_UBICOM32_HI24, 7, 2, 24, FALSE, 0, "R_UBICOM32_HI24", 0x0, 0x0001ffff), -+ -+ /* A source operand low 7 bit indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_S, 0, 2, 7, FALSE, 0, "R_UBICOM32_LO7_S", 0x0, 0x0000031f), -+ -+ /* A source operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_2_S, 1, 2, 7, FALSE, 0, "R_UBICOM32_LO7_2_S", 0x0, 0x0000031f), -+ -+ /* A source operand low 7 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_4_S, 2, 2, 7, FALSE, 0, "R_UBICOM32_LO7_4_S", 0x0, 0x0000031f), -+ -+ /* A destination operand low 7 bit indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_D, 0, 2, 7, FALSE, 0, "R_UBICOM32_LO7_D", 0x0, 0x031f0000), -+ -+ /* A destination operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_2_D, 1, 2, 7, FALSE, 0, "R_UBICOM32_LO7_2_D", 0x0, 0x031f0000), -+ -+ /* A destination operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_4_D, 2, 2, 7, FALSE, 0, "R_UBICOM32_LO7_4_D", 0x0, 0x031f0000), -+ -+ /* A 32 bit absolute relocation in debug section. Must retain top byte of virtual address. */ -+ UBICOM32_HOWTO (R_UBICOM32_32_HARVARD, 0, 2, 32, FALSE, 0, "R_UBICOM32_32_HARVARD", 0, 0xffffffff), -+ -+ /* A calli offset operand low 7 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO7_CALLI, 2, 2, 7, FALSE, 0, "R_UBICOM32_LO7_CALLI", 0x0, 0x071f071f), -+ -+ /* A calli offset operand low 18 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_LO16_CALLI, 2, 2, 16, FALSE, 0, "R_UBICOM32_LO16_CALLI", 0x0, 0x071f071f), -+ -+ /* A 24 bit indirect relocation, bits 31:7 - assume top byte zero. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_HI24, 7, 2, 24, FALSE, 0, "R_UBICOM32_GOT_HI24", 0x0, 0x0001ffff), -+ -+ /* A source operand low 7 bit indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_S, 0, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_S", 0x0, 0x0000031f), -+ -+ /* A source operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_2_S, 1, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_2_S", 0x0, 0x0000031f), -+ -+ /* A source operand low 7 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_4_S, 2, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_4_S", 0x0, 0x0000031f), -+ -+ /* A destination operand low 7 bit indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_D, 0, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_D", 0x0, 0x031f0000), -+ -+ /* A destination operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_2_D, 1, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_2_D", 0x0, 0x031f0000), -+ -+ /* A destination operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_4_D, 2, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_4_D", 0x0, 0x031f0000), -+ -+ /* A 24 bit indirect relocation, bits 31:7 - assume top byte zero. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_HI24, 7, 2, 24, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_HI24", 0x0, 0x0001ffff), -+ -+ /* A source operand low 7 bit indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_S, 0, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_S", 0x0, 0x0000031f), -+ -+ /* A source operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_2_S, 1, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_2_S", 0x0, 0x0000031f), -+ -+ /* A source operand low 7 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_4_S, 2, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_4_S", 0x0, 0x0000031f), -+ -+ /* A destination operand low 7 bit indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_D, 0, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_D", 0x0, 0x031f0000), -+ -+ /* A destination operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_2_D, 1, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_2_D", 0x0, 0x031f0000), -+ -+ /* A destination operand low 7 bit .2 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_4_D, 2, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_4_D", 0x0, 0x031f0000), -+ -+ /* A calli offset operand low 7 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_CALLI, 2, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_CALLI", 0x0, 0x071f071f), -+ -+ /* A calli offset operand low 7 bit .4 insn indirect relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_CALLI, 2, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_CALLI", 0x0, 0x071f071f), -+ -+ /* A 32 bit absolute relocation. Must zero top byte of virtual address. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_VALUE, 0, 2, 32, FALSE, 0, "R_UBICOM32_FUNCDESC_VALUE", 0, 0xffffffff), -+ -+ /* A 32 bit absolute relocation. Must zero top byte of virtual address. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC, 0, 2, 32, FALSE, 0, "R_UBICOM32_FUNCDESC", 0, 0xffffffff), -+ -+ /* A 16 bit absolute relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOTOFFSET_LO, 0, 1, 16, FALSE, 0, "R_UBICOM32_GOTOFFSET_LO", 0, 0xffff), -+ -+ /* A 16 bit absolute relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_GOTOFFSET_HI, 0, 1, 16, FALSE, 0, "R_UBICOM32_GOTOFFSET_HI", 0, 0xffff), -+ -+ /* A 16 bit absolute relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOTOFFSET_LO, 0, 1, 16, FALSE, 0, "R_UBICOM32_FUNCDESC_GOTOFFSET_LO", 0, 0xffff), -+ -+ /* A 16 bit absolute relocation. */ -+ UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOTOFFSET_HI, 0, 1, 16, FALSE, 0, "R_UBICOM32_FUNCDESC_GOTOFFSET_HI", 0, 0xffff), -+}; -+ -+/* GNU extension to record C++ vtable hierarchy */ -+static reloc_howto_type ubicom32_elf_vtinherit_howto = -+ HOWTO (R_UBICOM32_GNU_VTINHERIT, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ NULL, /* special_function */ -+ "R_UBICOM32_GNU_VTINHERIT", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE); /* pcrel_offset */ -+ -+ /* GNU extension to record C++ vtable member usage */ -+static reloc_howto_type ubicom32_elf_vtentry_howto = -+ HOWTO (R_UBICOM32_GNU_VTENTRY, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ _bfd_elf_rel_vtable_reloc_fn, /* special_function */ -+ "R_UBICOM32_GNU_VTENTRY", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ FALSE); /* pcrel_offset */ -+ -+extern const bfd_target bfd_elf32_ubicom32fdpic_vec; -+#define IS_FDPIC(bfd) ((bfd)->xvec == &bfd_elf32_ubicom32fdpic_vec) -+ -+/* Relocation helpers */ -+bfd_reloc_status_type -+ubicom32_elf_generic_reloc (abfd, -+ reloc_entry, -+ symbol, -+ data, -+ input_section, -+ output_bfd, -+ error_message) -+ bfd *abfd ATTRIBUTE_UNUSED; -+ arelent *reloc_entry; -+ asymbol *symbol; -+ PTR data ATTRIBUTE_UNUSED; -+ asection *input_section; -+ bfd *output_bfd; -+ char **error_message ATTRIBUTE_UNUSED; -+{ -+ if (output_bfd != (bfd *) NULL -+ && (symbol->flags & BSF_SECTION_SYM) == 0 -+ && (! reloc_entry->howto->partial_inplace -+ || reloc_entry->addend == 0)) -+ { -+ reloc_entry->address += input_section->output_offset; -+ symbol = *reloc_entry->sym_ptr_ptr; -+ -+ if((symbol->flags & BSF_OBJECT) == 0) -+ { -+ reloc_entry->addend -= symbol->value; -+ } -+ return bfd_reloc_ok; -+ } -+ -+ return bfd_reloc_continue; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_hi16 (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value >>= 16; -+ value &= 0xffff; /* take off top byte of virtual address */ -+ insn = ((insn & ~0xFFFF) | value); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo16 (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0xFFFF; -+ insn = ((insn & ~0xFFFF) | value); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_hi24 (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ if (value & 0x80000000) { -+ fprintf (stderr,"@@@: You are trying load the address of something at %08lx\n This is >= 0x80000000 and the moveai instruction does not support it!\n",value); -+ } -+ value &= 0x7fffffff; /* zero off top bit of virtual address */ -+ value >>= 7; -+ insn = (insn & ~0x071FFFFF); -+ -+ insn |= (value & 0x1FFFFF); -+ insn |= (value & 0xe00000) << 3; -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo7_s (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma top; -+ bfd_vma bottom; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0x7f; -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ top = value >> 5; -+ bottom = value & 0x1f; -+ insn = ((insn & ~0x31f) | (top << 8) | bottom); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo7_2_s (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma top; -+ bfd_vma bottom; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0x7f; -+ value >>= 1; /* must shift by 1 because this is .2 insn */ -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ top = value >> 5; -+ bottom = value & 0x1f; -+ insn = ((insn & ~0x31f) | (top << 8) | bottom); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo7_4_s (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma top; -+ bfd_vma bottom; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0x7f; -+ value >>= 2; /* must shift by 1 because this is .4 insn */ -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ top = value >> 5; -+ bottom = value & 0x1f; -+ insn = ((insn & ~0x31f) | (top << 8) | bottom); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo7_d (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma top; -+ bfd_vma bottom; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0x7f; -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ top = value >> 5; -+ bottom = value & 0x1f; -+ insn = ((insn & ~0x031f0000) | (top << 24) | (bottom << 16)); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo7_2_d (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma top; -+ bfd_vma bottom; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0x7f; -+ value >>= 1; /* must shift by 1 because this is for a .2 insn */ -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ top = value >> 5; -+ bottom = value & 0x1f; -+ insn = ((insn & ~0x031f0000) | (top << 24) | (bottom << 16)); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo7_4_d (input_bfd, relhi, contents, value) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma top; -+ bfd_vma bottom; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= 0x7f; -+ value >>= 2; /* must shift by 2 because this is for a .4 insn */ -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ top = value >> 5; -+ bottom = value & 0x1f; -+ insn = ((insn & ~0x031f0000) | (top << 24) | (bottom << 16)); -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+/* Perform the relocation for call instructions */ -+static bfd_reloc_status_type -+ubicom32_elf_relocate_pcrel24 (input_bfd, input_section, rello, contents, value) -+ bfd *input_bfd; -+ asection *input_section; -+ Elf_Internal_Rela *rello; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ bfd_vma value_top; -+ bfd_vma value_bottom; -+ -+ /* Grab the instruction */ -+ insn = bfd_get_32 (input_bfd, contents + rello->r_offset); -+ -+ value -= input_section->output_section->vma + input_section->output_offset; -+ value -= rello->r_offset; -+ value += rello->r_addend; -+ -+ /* insn uses bottom 24 bits of relocation value times 4 */ -+ if (value & 0x03) -+ return bfd_reloc_dangerous; -+ -+ value = (value & 0x3ffffff) >> 2; -+ -+ if ((long) value > 0xffffff) -+ return bfd_reloc_overflow; -+ -+ value_top = (value >> 21) << 24; -+ value_bottom = value & 0x1fffff; -+ -+ insn = insn & 0xf8e00000; -+ insn = insn | value_top | value_bottom; -+ -+ bfd_put_32 (input_bfd, insn, contents + rello->r_offset); -+ -+ return bfd_reloc_ok; -+} -+ -+static bfd_reloc_status_type -+ubicom32_elf_relocate_gotoffset_lo (input_bfd, input_section, rello, contents, value) -+ bfd *input_bfd; -+ asection *input_section; -+ Elf_Internal_Rela *rello; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ -+ /* Grab the instruction */ -+ insn = bfd_get_32 (input_bfd, contents + rello->r_offset); -+ -+ /* Truncte to 16 and store. */ -+ value &= 0xffff; -+ -+ insn = (insn & 0xffff0000) | value; -+ -+ /* output it. */ -+ bfd_put_32 (input_bfd, insn, contents + rello->r_offset); -+} -+ -+static bfd_reloc_status_type -+ubicom32_elf_relocate_funcdesc_gotoffset_lo (input_bfd, input_section, rello, contents, value) -+ bfd *input_bfd; -+ asection *input_section; -+ Elf_Internal_Rela *rello; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ -+ /* Grab the instruction */ -+ insn = bfd_get_32 (input_bfd, contents + rello->r_offset); -+ -+ /* Truncte to 16 and store. */ -+ value &= 0xffff; -+ -+ insn = (insn & 0xffff0000) | value; -+ -+ /* output it. */ -+ bfd_put_32 (input_bfd, insn, contents + rello->r_offset); -+} -+ -+static bfd_reloc_status_type -+ubicom32_elf_relocate_funcdesc (input_bfd, input_section, rello, contents, value) -+ bfd *input_bfd; -+ asection *input_section; -+ Elf_Internal_Rela *rello; -+ bfd_byte *contents; -+ bfd_vma value; -+{ -+ bfd_vma insn; -+ -+ /* Grab the instruction */ -+ insn = bfd_get_32 (input_bfd, contents + rello->r_offset); -+ -+ /* Truncte to 16 and store. */ -+ value &= 0xffff; -+ -+ insn = (insn & 0xffff0000) | value; -+ -+ /* output it. */ -+ bfd_put_32 (input_bfd, insn, contents + rello->r_offset); -+} -+ -+bfd_reloc_status_type -+ubicom32_elf_relocate_lo_calli (input_bfd, relhi, contents, value, bits) -+ bfd *input_bfd; -+ Elf_Internal_Rela *relhi; -+ bfd_byte *contents; -+ bfd_vma value; -+ int bits; -+{ -+ bfd_vma insn; -+ -+ insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); -+ -+ value += relhi->r_addend; -+ value &= (1 << bits) - 1; -+ value >>= 2; /* must shift by 2 because this is .4 insn */ -+ -+ /* must split up value into top 2 bits and bottom 5 bits */ -+ insn &= ~0x071f071f; -+ insn |= (value & 0x1f) << 0; -+ value >>= 5; -+ insn |= (value & 0x07) << 8; -+ value >>= 3; -+ insn |= (value & 0x1f) << 16; -+ value >>= 5; -+ insn |= (value & 0x07) << 24; -+ -+ bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); -+ return bfd_reloc_ok; -+} -+ -+ -+/* Set the howto pointer for a UBICOM32 ELF reloc. */ -+ -+static void -+ubicom32_info_to_howto_rela (abfd, cache_ptr, dst) -+ bfd * abfd ATTRIBUTE_UNUSED; -+ arelent * cache_ptr; -+ Elf_Internal_Rela * dst; -+{ -+ unsigned int r_type; -+ -+ r_type = ELF32_R_TYPE (dst->r_info); -+ switch (r_type) -+ { -+ case R_UBICOM32_GNU_VTINHERIT: -+ cache_ptr->howto = &ubicom32_elf_vtinherit_howto; -+ break; -+ -+ case R_UBICOM32_GNU_VTENTRY: -+ cache_ptr->howto = &ubicom32_elf_vtentry_howto; -+ break; -+ -+ default: -+ cache_ptr->howto = &ubicom32_elf_howto_table[r_type]; -+ break; -+ } -+} -+ -+ -+static reloc_howto_type * -+ubicom32_reloc_type_lookup (abfd, code) -+ bfd * abfd ATTRIBUTE_UNUSED; -+ bfd_reloc_code_real_type code; -+{ -+ switch (code) -+ { -+ case BFD_RELOC_NONE: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_NONE]; -+ -+ case BFD_RELOC_16: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_16]; -+ -+ case BFD_RELOC_32: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_32]; -+ -+ case BFD_RELOC_LO16: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO16]; -+ -+ case BFD_RELOC_HI16: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_HI16]; -+ -+ case BFD_RELOC_UBICOM32_HI24: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_HI24]; -+ -+ case BFD_RELOC_UBICOM32_LO7_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_S]; -+ -+ case BFD_RELOC_UBICOM32_LO7_2_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_2_S]; -+ -+ case BFD_RELOC_UBICOM32_LO7_4_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_4_S]; -+ -+ case BFD_RELOC_UBICOM32_LO7_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_D]; -+ -+ case BFD_RELOC_UBICOM32_LO7_2_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_2_D]; -+ -+ case BFD_RELOC_UBICOM32_LO7_4_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_4_D]; -+ -+ case BFD_RELOC_UBICOM32_21_PCREL: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_21_PCREL]; -+ -+ case BFD_RELOC_UBICOM32_24_PCREL: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_24_PCREL]; -+ -+ case BFD_RELOC_UBICOM32_GOT_HI24: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_HI24]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_S]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_2_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_2_S]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_4_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_4_S]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_D]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_2_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_2_D]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_4_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_4_D]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_HI24]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_S]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_2_S]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_4_S]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_D]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_2_D]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_4_D]; -+ -+ case BFD_RELOC_UBICOM32_LO7_CALLI: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_CALLI]; -+ -+ case BFD_RELOC_UBICOM32_GOT_LO7_CALLI: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_CALLI]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_CALLI]; -+ -+ case BFD_RELOC_UBICOM32_LO16_CALLI: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO16_CALLI]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_VALUE: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_VALUE]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC]; -+ -+ case BFD_RELOC_UBICOM32_GOTOFFSET_LO: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOTOFFSET_LO]; -+ -+ case BFD_RELOC_UBICOM32_GOTOFFSET_HI: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOTOFFSET_HI]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOTOFFSET_LO]; -+ -+ case BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI: -+ return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOTOFFSET_HI]; -+ -+ case BFD_RELOC_VTABLE_INHERIT: -+ return &ubicom32_elf_vtinherit_howto; -+ -+ case BFD_RELOC_VTABLE_ENTRY: -+ return &ubicom32_elf_vtentry_howto; -+ -+ default: -+ /* Pacify gcc -Wall. */ -+ return NULL; -+ } -+ -+ return NULL; -+} -+ -+static reloc_howto_type * -+ubicom32_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ const char *r_name) -+{ -+ unsigned int i; -+ -+ for (i = 0; -+ i < (sizeof (ubicom32_elf_howto_table) -+ / sizeof (ubicom32_elf_howto_table[0])); -+ i++) -+ if (ubicom32_elf_howto_table[i].name != NULL -+ && strcasecmp (ubicom32_elf_howto_table[i].name, r_name) == 0) -+ return &ubicom32_elf_howto_table[i]; -+ -+ return NULL; -+} -+ -+/* Return the value of the symbol associated with the relocation IREL. */ -+ -+static bfd_vma -+symbol_value (abfd, irel) -+ bfd *abfd; -+ Elf_Internal_Rela *irel; -+{ -+ Elf_Internal_Shdr *symtab_hdr = file_symtab_hdr (abfd); -+ Elf_Internal_Sym *isymbuf = file_isymbuf (abfd); -+ -+ if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) -+ { -+ Elf_Internal_Sym *isym; -+ asection *sym_sec; -+ -+ isym = isymbuf + ELF32_R_SYM (irel->r_info); -+ if (isym->st_shndx == SHN_UNDEF) -+ sym_sec = bfd_und_section_ptr; -+ else if (isym->st_shndx == SHN_ABS) -+ sym_sec = bfd_abs_section_ptr; -+ else if (isym->st_shndx == SHN_COMMON) -+ sym_sec = bfd_com_section_ptr; -+ else -+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); -+ -+ return isym->st_value + BASEADDR (sym_sec); -+ } -+ else -+ { -+ unsigned long indx; -+ struct elf_link_hash_entry *h; -+ -+ indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; -+ h = elf_sym_hashes (abfd)[indx]; -+ BFD_ASSERT (h != NULL); -+ -+ if (h->root.type != bfd_link_hash_defined -+ && h->root.type != bfd_link_hash_defweak) -+ return UNDEFINED_SYMBOL; -+ -+ return (h->root.u.def.value + BASEADDR (h->root.u.def.section)); -+ } -+} -+ -+ -+static Elf_Internal_Shdr * -+file_symtab_hdr (abfd) -+ bfd *abfd; -+{ -+ return &elf_tdata (abfd)->symtab_hdr; -+} -+ -+static Elf_Internal_Sym * -+file_isymbuf (abfd) -+ bfd *abfd; -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ -+ symtab_hdr = file_symtab_hdr (abfd); -+ if (symtab_hdr->sh_info == 0) -+ return NULL; -+ -+ if (symtab_hdr->contents == NULL) -+ { -+ Elf_Internal_Sym * contents = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0, -+ NULL, NULL, NULL); -+ symtab_hdr->contents = (unsigned char *) contents; -+ } -+ -+ return (Elf_Internal_Sym *) symtab_hdr->contents; -+} -+ -+static Elf_Internal_Rela * -+section_relocs (abfd, sec) -+ bfd *abfd; -+ asection *sec; -+{ -+ if ((sec->flags & SEC_RELOC) == 0) -+ return NULL; -+ -+ if (sec->reloc_count == 0) -+ return NULL; -+ -+ if (elf_section_data (sec)->relocs == NULL) -+ elf_section_data (sec)->relocs = -+ _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, 1); -+ -+ return elf_section_data (sec)->relocs; -+} -+ -+static bfd_byte * -+section_contents (abfd, sec) -+ bfd *abfd; -+ asection *sec; -+{ -+ bfd_byte *contents; -+ -+ sec->rawsize = sec->rawsize ? sec->rawsize: sec->size; -+ -+ if (elf_section_data (sec)->this_hdr.contents) -+ return elf_section_data (sec)->this_hdr.contents; -+ -+ contents = (bfd_byte *) bfd_malloc (sec->rawsize); -+ if (contents == NULL) -+ return NULL; -+ -+ if (! bfd_get_section_contents (abfd, sec, contents, -+ (file_ptr) 0, sec->rawsize)) -+ { -+ free (contents); -+ return NULL; -+ } -+ -+ elf_section_data (sec)->this_hdr.contents = contents; -+ return contents; -+} -+ -+/* This function handles relaxing for the ubicom32. -+ -+ Principle: Start with the first page and remove page instructions that -+ are not require on this first page. By removing page instructions more -+ code will fit into this page - repeat until nothing more can be achieved -+ for this page. Move on to the next page. -+ -+ Processing the pages one at a time from the lowest page allows a removal -+ only policy to be used - pages can be removed but are never reinserted. */ -+ -+static bfd_boolean -+ubicom32_elf_relax_section (abfd, sec, link_info, again) -+ bfd *abfd; -+ asection *sec; -+ struct bfd_link_info *link_info; -+ bfd_boolean *again; -+{ -+ /* Assume nothing changes. */ -+ *again = FALSE; -+ -+ /* We don't have to do anything for a relocatable link, -+ if this section does not have relocs, or if this is -+ not a code section. */ -+ if (link_info->relocatable -+ || (sec->flags & SEC_RELOC) == 0 -+ || sec->reloc_count == 0 -+ || (sec->flags & SEC_CODE) == 0) -+ return TRUE; -+ -+ /* If this is the first time we have been called -+ for this section, initialise the cooked size. -+ if (sec->_cooked_size == 0) -+ sec->_cooked_size = sec->rawsize; -+ */ -+ -+ /* This is where all the relaxation actually get done. */ -+ if (!ubicom32_elf_relax_calli (abfd, sec, again)) -+ return FALSE; -+ -+ if (sec->rawsize != sec->size) -+ sec->size = sec->rawsize; -+ -+ /* Success! */ -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32_elf_relax_calli (abfd, sec, again) -+ bfd *abfd; -+ asection *sec; -+ bfd_boolean *again; -+{ -+ bfd_byte *contents = section_contents (abfd, sec); -+ Elf_Internal_Rela *irelbase = section_relocs (abfd, sec); -+ Elf_Internal_Rela *irelend = irelbase + sec->reloc_count; -+ Elf_Internal_Rela *irel_moveai = NULL; -+ Elf_Internal_Rela *irel; -+ unsigned long insn; -+ bfd_vma symval; -+ bfd_vma pc; -+ bfd_vma dest; -+ signed long offs; -+ -+ /* Walk thru the section looking for relaxation opertunities. */ -+ for (irel = irelbase; irel < irelend; irel++) -+ { -+ /* Remember last moveai instruction */ -+ if (ELF32_R_TYPE (irel->r_info) == (int) R_UBICOM32_HI24) -+ { -+ irel_moveai = irel; -+ continue; -+ } -+ -+ /* Ignore non calli instructions */ -+ if (ELF32_R_TYPE (irel->r_info) != (int) R_UBICOM32_LO7_CALLI) -+ continue; -+ -+ /* calli instruction => verify it is a calli instruction -+ using a5 with a 5 bit positive offset */ -+ insn = bfd_get_32 (abfd, (bfd_byte *)(contents + irel->r_offset)); -+ if ((insn & 0xffffffe0) != 0xf0a000a0) -+ continue; -+ symval = symbol_value (abfd, irel); -+ if (symval == UNDEFINED_SYMBOL) -+ continue; -+ dest = symval + irel->r_addend; -+ -+ /* Check proceeding instruction for a valid moveai */ -+ if (!irel_moveai) -+ continue; -+ if (irel_moveai->r_offset != (irel->r_offset - 4)) -+ continue; -+ insn = bfd_get_32 (abfd, (bfd_byte *)(contents + irel_moveai->r_offset)); -+ if ((insn & 0xf8e00000) != 0xe0a00000) -+ continue; -+ symval = symbol_value (abfd, irel_moveai); -+ if (symval == UNDEFINED_SYMBOL) -+ continue; -+ symval += irel_moveai->r_addend; -+ if (symval != dest) -+ continue; -+ -+ /* Check offset required */ -+ pc = BASEADDR (sec) + irel_moveai->r_offset; -+ offs = dest - pc; -+ if (offs > (UBICOM32_CALL_MAX_POS_OFFS + 4)) -+ continue; -+ if (offs < UBICOM32_CALL_MAX_NEG_OFFS) -+ continue; -+ -+ /* Replace calli with a call instruction */ -+ irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_UBICOM32_24_PCREL); -+ bfd_put_32 (abfd, 0xd8a00000, contents + irel->r_offset); -+ -+ /* Delete moveai instruction */ -+ irel_moveai->r_info = ELF32_R_INFO (ELF32_R_SYM (irel_moveai->r_info), R_UBICOM32_NONE); -+ if (!ubicom32_elf_relax_delete_bytes (abfd, sec, irel_moveai->r_offset, 4)) -+ return FALSE; -+ -+ /* Modified => will need to iterate relaxation again. */ -+ *again = TRUE; -+ } -+ -+ return TRUE; -+} -+ -+/* Delete some bytes from a section while relaxing. */ -+ -+static bfd_boolean -+ubicom32_elf_relax_delete_bytes (abfd, sec, addr, count) -+ bfd *abfd; -+ asection *sec; -+ bfd_vma addr; -+ int count; -+{ -+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -+ bfd_vma endaddr = sec->rawsize; -+ -+ /* Actually delete the bytes. */ -+ memmove (contents + addr, contents + addr + count, -+ endaddr - addr - count); -+ -+ sec->rawsize -= count; -+ -+ adjust_all_relocations (abfd, sec, addr + count, -count); -+ return TRUE; -+} -+ -+/* Adjust all the relocations entries after adding or inserting instructions. */ -+ -+static void -+adjust_sec_relocations (abfd, sec_to_process, addr_sec, addr, count) -+ bfd *abfd; -+ asection *sec_to_process; -+ asection *addr_sec; -+ bfd_vma addr; -+ int count; -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Sym *isymbuf, *isym; -+ Elf_Internal_Rela *irel, *irelend, *irelbase; -+ unsigned int addr_shndx; -+ -+ irelbase = section_relocs (abfd, sec_to_process); -+ if (irelbase == NULL) -+ return; -+ irelend = irelbase + sec_to_process->reloc_count; -+ -+ symtab_hdr = file_symtab_hdr (abfd); -+ isymbuf = file_isymbuf (abfd); -+ -+ addr_shndx = _bfd_elf_section_from_bfd_section (abfd, addr_sec); -+ -+ for (irel = irelbase; irel < irelend; irel++) -+ { -+ if (ELF32_R_TYPE (irel->r_info) != R_UBICOM32_NONE) -+ { -+ /* Get the value of the symbol referred to by the reloc. */ -+ if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) -+ { -+ asection *sym_sec; -+ bfd_vma xaddr, symval, relval; -+ -+ /* A local symbol. */ -+ isym = isymbuf + ELF32_R_SYM (irel->r_info); -+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); -+ xaddr = BASEADDR (addr_sec) + addr; -+ symval = BASEADDR (sym_sec) + isym->st_value; -+ relval = symval + irel->r_addend; -+ -+ if ((isym->st_shndx == addr_shndx) -+ && (xaddr > symval) -+ && (xaddr <= relval)) -+ irel->r_addend += count; -+ } -+ } -+ -+ /* Adjust irel base address for PC space relocations after a deleted instruction. */ -+ if (sec_to_process == addr_sec) -+ { -+ if (addr <= irel->r_offset) -+ irel->r_offset += count; -+ } -+ } -+} -+ -+static void -+adjust_all_relocations (abfd, sec, addr, count) -+ bfd *abfd; -+ asection *sec; -+ bfd_vma addr; -+ int count; -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Sym *isymbuf, *isym, *isymend; -+ struct elf_link_hash_entry **sym_hashes; -+ struct elf_link_hash_entry **end_hashes; -+ unsigned int symcount; -+ asection *section; -+ unsigned int shndx; -+ -+ symtab_hdr = file_symtab_hdr (abfd); -+ isymbuf = file_isymbuf (abfd); -+ -+ shndx = _bfd_elf_section_from_bfd_section (abfd, sec); -+ -+ /* Adjust all relocations that are affected. */ -+ for (section = abfd->sections; section != NULL; section = section->next) -+ adjust_sec_relocations (abfd, section, sec, addr, count); -+ -+ /* Adjust the local symbols defined in this section. */ -+ isymend = isymbuf + symtab_hdr->sh_info; -+ for (isym = isymbuf; isym < isymend; isym++) -+ { -+ if (isym->st_shndx == shndx -+ && addr <= isym->st_value) -+ isym->st_value += count; -+ } -+ -+ /* Now adjust the global symbols defined in this section. */ -+ symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) -+ - symtab_hdr->sh_info); -+ sym_hashes = elf_sym_hashes (abfd); -+ end_hashes = sym_hashes + symcount; -+ for (; sym_hashes < end_hashes; sym_hashes++) -+ { -+ struct elf_link_hash_entry *sym_hash = *sym_hashes; -+ -+ if ((sym_hash->root.type == bfd_link_hash_defined -+ || sym_hash->root.type == bfd_link_hash_defweak) -+ && sym_hash->root.u.def.section == sec) -+ { -+ if (addr <= sym_hash->root.u.def.value) -+ sym_hash->root.u.def.value += count; -+ } -+ } -+} -+ -+/* Perform a single relocation. By default we use the standard BFD -+ routines. */ -+ -+static bfd_reloc_status_type -+ubicom32_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation) -+ reloc_howto_type * howto; -+ bfd * input_bfd; -+ asection * input_section; -+ bfd_byte * contents; -+ Elf_Internal_Rela * rel; -+ bfd_vma relocation; -+{ -+ bfd_reloc_status_type r = bfd_reloc_ok; -+ -+ switch (howto->type) -+ { -+ default: -+ r = _bfd_final_link_relocate (howto, input_bfd, input_section, -+ contents, rel->r_offset, -+ relocation, rel->r_addend); -+ } -+ -+ return r; -+} -+ -+/* Relocate a UBICOM32 ELF section. -+ There is some attempt to make this function usable for many architectures, -+ both USE_REL and USE_RELA ['twould be nice if such a critter existed], -+ if only to serve as a learning tool. -+ -+ The RELOCATE_SECTION function is called by the new ELF backend linker -+ to handle the relocations for a section. -+ -+ The relocs are always passed as Rela structures; if the section -+ actually uses Rel structures, the r_addend field will always be -+ zero. -+ -+ This function is responsible for adjusting the section contents as -+ necessary, and (if using Rela relocs and generating a relocatable -+ output file) adjusting the reloc addend as necessary. -+ -+ This function does not have to worry about setting the reloc -+ address or the reloc symbol index. -+ -+ LOCAL_SYMS is a pointer to the swapped in local symbols. -+ -+ LOCAL_SECTIONS is an array giving the section in the input file -+ corresponding to the st_shndx field of each local symbol. -+ -+ The global hash table entry for the global symbols can be found -+ via elf_sym_hashes (input_bfd). -+ -+ When generating relocatable output, this function must handle -+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is -+ going to be the section symbol corresponding to the output -+ section, which means that the addend must be adjusted -+ accordingly. */ -+ -+static bfd_boolean -+ubicom32_elf_relocate_section (output_bfd, info, input_bfd, input_section, -+ contents, relocs, local_syms, local_sections) -+ bfd * output_bfd ATTRIBUTE_UNUSED; -+ struct bfd_link_info * info; -+ bfd * input_bfd; -+ asection * input_section; -+ bfd_byte * contents; -+ Elf_Internal_Rela * relocs; -+ Elf_Internal_Sym * local_syms; -+ asection ** local_sections; -+{ -+ Elf_Internal_Shdr * symtab_hdr; -+ struct elf_link_hash_entry ** sym_hashes; -+ Elf_Internal_Rela * rel; -+ Elf_Internal_Rela * relend; -+ struct debugLineInfoHeader *lh = NULL; -+ int cooked_size, discard_size; -+ bfd_byte *src, *dest, *content_end; -+ unsigned int i; -+ -+ symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (input_bfd); -+ relend = relocs + input_section->reloc_count; -+ -+ for (rel = relocs; rel < relend; rel ++) -+ { -+ reloc_howto_type * howto; -+ unsigned long r_symndx; -+ Elf_Internal_Sym * sym; -+ asection * sec; -+ struct elf_link_hash_entry * h; -+ bfd_vma relocation; -+ bfd_reloc_status_type r; -+ const char * name = NULL; -+ int r_type; -+ -+ r_type = ELF32_R_TYPE (rel->r_info); -+ -+ if ( r_type == R_UBICOM32_GNU_VTINHERIT -+ || r_type == R_UBICOM32_GNU_VTENTRY) -+ continue; -+ -+ r_symndx = ELF32_R_SYM (rel->r_info); -+ -+ if (info->relocatable) -+ { -+ /* This is a relocatable link. We don't have to change -+ anything, unless the reloc is against a section symbol, -+ in which case we have to adjust according to where the -+ section symbol winds up in the output section. */ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ sym = local_syms + r_symndx; -+ -+ if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) -+ { -+ sec = local_sections [r_symndx]; -+ rel->r_addend += sec->output_offset + sym->st_value; -+ } -+ } -+ -+ continue; -+ } -+ -+ /* This is a final link. */ -+ howto = ubicom32_elf_howto_table + ELF32_R_TYPE (rel->r_info); -+ h = NULL; -+ sym = NULL; -+ sec = NULL; -+ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ sym = local_syms + r_symndx; -+ sec = local_sections [r_symndx]; -+ relocation = (sec->output_section->vma -+ + sec->output_offset -+ + sym->st_value); -+ -+ name = bfd_elf_string_from_elf_section -+ (input_bfd, symtab_hdr->sh_link, sym->st_name); -+ name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; -+ } -+ else -+ { -+ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; -+ -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ name = h->root.root.string; -+ -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ { -+ sec = h->root.u.def.section; -+ relocation = (h->root.u.def.value -+ + sec->output_section->vma -+ + sec->output_offset); -+ } -+ else if (h->root.type == bfd_link_hash_undefweak) -+ { -+ relocation = 0; -+ } -+ else -+ { -+ if (! ((*info->callbacks->undefined_symbol) -+ (info, h->root.root.string, input_bfd, -+ input_section, rel->r_offset, -+ (!info->shared )))) -+ return FALSE; -+ relocation = 0; -+ } -+ } -+ -+ switch (r_type) -+ { -+ case R_UBICOM32_LO16: -+ r = ubicom32_elf_relocate_lo16 (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_HI16: -+ r = ubicom32_elf_relocate_hi16 (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_HI24: -+ r = ubicom32_elf_relocate_hi24 (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_S: -+ r = ubicom32_elf_relocate_lo7_s (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_2_S: -+ r = ubicom32_elf_relocate_lo7_2_s (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_4_S: -+ r = ubicom32_elf_relocate_lo7_4_s (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_D: -+ r = ubicom32_elf_relocate_lo7_d (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_2_D: -+ r = ubicom32_elf_relocate_lo7_2_d (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_4_D: -+ r = ubicom32_elf_relocate_lo7_4_d (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_24_PCREL: -+ r = ubicom32_elf_relocate_pcrel24 (input_bfd, input_section, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_CALLI: -+ r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 7); -+ break; -+ -+ case R_UBICOM32_LO16_CALLI: -+ r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 18); -+ break; -+ -+ case R_UBICOM32_32: -+ /* relocation &= ~(0xff << 24); */ -+ /* FALLTHROUGH */ -+ -+ default: -+ r = ubicom32_final_link_relocate (howto, input_bfd, input_section, -+ contents, rel, relocation); -+ break; -+ } -+ -+ if (r != bfd_reloc_ok) -+ { -+ const char * msg = (const char *) NULL; -+ -+ switch (r) -+ { -+ case bfd_reloc_overflow: -+ r = info->callbacks->reloc_overflow -+ (info, NULL, name, howto->name, (bfd_vma) 0, -+ input_bfd, input_section, rel->r_offset); -+ break; -+ -+ case bfd_reloc_undefined: -+ r = info->callbacks->undefined_symbol -+ (info, name, input_bfd, input_section, rel->r_offset, TRUE); -+ break; -+ -+ case bfd_reloc_outofrange: -+ msg = _("internal error: out of range error"); -+ break; -+ -+ case bfd_reloc_notsupported: -+ msg = _("internal error: unsupported relocation error"); -+ break; -+ -+ case bfd_reloc_dangerous: -+ msg = _("internal error: dangerous relocation"); -+ break; -+ -+ default: -+ msg = _("internal error: unknown error"); -+ break; -+ } -+ -+ if (msg) -+ r = info->callbacks->warning -+ (info, msg, name, input_bfd, input_section, rel->r_offset); -+ -+ if (! r) -+ return FALSE; -+ } -+ } -+ -+ /* -+ * now we have to collapse the .debug_line section if it has a -+ * sec_info section -+ */ -+ -+ if(strcmp(input_section->name, ".debug_line")) -+ return TRUE; -+ -+ /* this is a .debug_line section. See it has a sec_info entry */ -+ if(elf_section_data(input_section)->sec_info == NULL) -+ return TRUE; -+ -+ lh = (struct debugLineInfoHeader *) elf_section_data(input_section)->sec_info; -+ -+ if(lh->numEntries == 0) -+ return TRUE; -+ -+ dest = contents + lh->linfo[0].startOffset; -+ -+ cooked_size = input_section->rawsize; -+ content_end = contents + cooked_size; -+ discard_size = 0; -+ -+ for(i=0; i< lh->numEntries; i++) -+ { -+ if(lh->linfo[i].discard) -+ discard_size += lh->linfo[i].length; -+ else -+ { -+ src = contents + lh->linfo[i].startOffset; -+ (void) memcpy(dest, src, lh->linfo[i].length); -+ dest += lh->linfo[i].length; -+ } -+ } -+ -+ src = contents + lh->linfo[lh->numEntries-1].startOffset + lh->linfo[lh->numEntries-1].length; -+ if(src < content_end) -+ (void) memcpy(dest, src, content_end - src); -+ -+ i = bfd_get_32(input_bfd, contents); -+ i -= discard_size; -+ bfd_put_32(input_bfd, i, contents); -+ //input_section->rawsize -= discard_size; -+ return TRUE; -+} -+ -+ -+/* Update the got entry reference counts for the section being -+ removed. */ -+ -+static bfd_boolean -+ubicom32_elf_gc_sweep_hook (abfd, info, sec, relocs) -+ bfd * abfd ATTRIBUTE_UNUSED; -+ struct bfd_link_info * info ATTRIBUTE_UNUSED; -+ asection * sec ATTRIBUTE_UNUSED; -+ const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED; -+{ -+ return TRUE; -+} -+ -+/* Return the section that should be marked against GC for a given -+ relocation. */ -+ -+static asection * -+ubicom32_elf_gc_mark_hook (sec, info, rel, h, sym) -+ asection * sec; -+ struct bfd_link_info * info ATTRIBUTE_UNUSED; -+ Elf_Internal_Rela * rel; -+ struct elf_link_hash_entry * h; -+ Elf_Internal_Sym * sym; -+{ -+ if (h != NULL) -+ { -+ switch (ELF32_R_TYPE (rel->r_info)) -+ { -+ case R_UBICOM32_GNU_VTINHERIT: -+ case R_UBICOM32_GNU_VTENTRY: -+ break; -+ -+ default: -+ switch (h->root.type) -+ { -+ case bfd_link_hash_defined: -+ case bfd_link_hash_defweak: -+ return h->root.u.def.section; -+ -+ case bfd_link_hash_common: -+ return h->root.u.c.p->section; -+ -+ default: -+ break; -+ } -+ } -+ } -+ else -+ { -+ if (!(elf_bad_symtab (sec->owner) -+ && ELF_ST_BIND (sym->st_info) != STB_LOCAL) -+ && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE) -+ && sym->st_shndx != SHN_COMMON)) -+ { -+ return bfd_section_from_elf_index (sec->owner, sym->st_shndx); -+ } -+ } -+ -+ return NULL; -+} -+ -+/* Look through the relocs for a section during the first phase. -+ Since we don't do .gots or .plts, we just need to consider the -+ virtual table relocs for gc. */ -+ -+static bfd_boolean -+ubicom32_elf_check_relocs (abfd, info, sec, relocs) -+ bfd *abfd; -+ struct bfd_link_info *info; -+ asection *sec; -+ const Elf_Internal_Rela *relocs; -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; -+ Elf_Internal_Rela *rel; -+ Elf_Internal_Rela *rel_end; -+ Elf_Internal_Rela *my_rel = ( Elf_Internal_Rela*)relocs; -+ if (info->relocatable) -+ return TRUE; -+ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (abfd); -+ sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym); -+ if (!elf_bad_symtab (abfd)) -+ sym_hashes_end -= symtab_hdr->sh_info; -+ -+ rel_end = my_rel + sec->reloc_count; -+ for (rel = my_rel; rel < rel_end; rel++) -+ { -+ struct elf_link_hash_entry *h; -+ unsigned long r_symndx; -+ -+ r_symndx = ELF32_R_SYM (rel->r_info); -+ if (r_symndx < symtab_hdr->sh_info) -+ h = NULL; -+ else -+ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; -+ -+ switch (ELF32_R_TYPE (rel->r_info)) -+ { -+ /* This relocation describes the C++ object vtable hierarchy. -+ Reconstruct it for later use during GC. */ -+ case R_UBICOM32_GNU_VTINHERIT: -+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) -+ return FALSE; -+ break; -+ -+ /* This relocation describes which C++ vtable entries are actually -+ used. Record for later use during GC. */ -+ case R_UBICOM32_GNU_VTENTRY: -+ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) -+ return FALSE; -+ break; -+ -+ case R_UBICOM32_32: -+ /* For debug section, change to harvard relocations */ -+ if (memcmp (sec->name, ".debug", 6) == 0 -+ || memcmp (sec->name, ".stab", 5) == 0) -+ rel->r_info = ELF32_R_INFO (ELF32_R_SYM (rel->r_info), R_UBICOM32_32_HARVARD); -+ break; -+ } -+ } -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32_elf_object_p (abfd) -+ bfd *abfd; -+{ -+ flagword mach = elf_elfheader (abfd)->e_flags & 0xffff; -+ bfd_default_set_arch_mach (abfd, bfd_arch_ubicom32, mach); -+ return (((elf_elfheader (abfd)->e_flags & EF_UBICOM32_FDPIC) != 0) -+ == (IS_FDPIC (abfd))); -+} -+ -+ -+/* Function to set the ELF flag bits */ -+ -+static bfd_boolean -+ubicom32_elf_set_private_flags (abfd, flags) -+ bfd *abfd; -+ flagword flags; -+{ -+ elf_elfheader (abfd)->e_flags = flags; -+ elf_flags_init (abfd) = TRUE; -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32_elf_copy_private_bfd_data (ibfd, obfd) -+ bfd *ibfd; -+ bfd *obfd; -+{ -+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour -+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour) -+ return TRUE; -+ -+ BFD_ASSERT (!elf_flags_init (obfd) -+ || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags); -+ -+ elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; -+ elf_flags_init (obfd) = TRUE; -+ return TRUE; -+} -+ -+/* Merge backend specific data from an object file to the output -+ object file when linking. */ -+static bfd_boolean -+ubicom32_elf_merge_private_bfd_data (ibfd, obfd) -+ bfd *ibfd; -+ bfd *obfd; -+{ -+ flagword old_flags, new_flags; -+ bfd_boolean error = FALSE; -+ -+ new_flags = elf_elfheader (ibfd)->e_flags; -+ old_flags = elf_elfheader (obfd)->e_flags; -+ -+#ifdef DEBUG -+ (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s", -+ old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no", -+ bfd_get_filename (ibfd)); -+#endif -+ -+ if (!elf_flags_init (obfd)) /* First call, no flags set */ -+ { -+ elf_flags_init (obfd) = TRUE; -+ elf_elfheader (obfd)->e_flags = new_flags; -+ } -+ else -+ { -+ if (new_flags != old_flags) -+ { -+ /* Mismatched flags. */ -+ char *output_cpu_version = ((old_flags &0xffff) == 1) ? "V3" : (((old_flags &0xffff) == 2) ? "V4" : "unknown"); -+ char *input_cpu_version = ((new_flags &0xffff) == 1) ? "V3" : (((new_flags &0xffff) == 2) ? "V4" : "unknown"); -+ char *output_filename = bfd_get_filename (obfd); -+ char *input_filename = bfd_get_filename (ibfd); -+ char *output_pic = (old_flags & EF_UBICOM32_PIC_FLAGS) ? ((old_flags & EF_UBICOM32_PIC) ? "FPIC" : "FDPIC") : NULL; -+ char *input_pic = (new_flags & EF_UBICOM32_PIC_FLAGS) ? ((new_flags & EF_UBICOM32_PIC) ? "FPIC" : "FDPIC") : NULL; -+ -+ (*_bfd_error_handler) ("Linking mismatched file types. Output file = %s file type 0x%.8lx, input file = %s file type 0x%.8lx", -+ output_filename, old_flags, input_filename, new_flags); -+ -+ if (output_pic) -+ { -+ (*_bfd_error_handler)("Output file %s %s for cpu version %s", output_filename, output_pic, output_cpu_version); -+ } -+ else -+ { -+ (*_bfd_error_handler)("Output file %s for cpu version %s", output_filename, output_cpu_version); -+ } -+ -+ if (input_pic) -+ { -+ (*_bfd_error_handler)("Input file %s %s for cpu version %s", input_filename, input_pic, input_cpu_version); -+ } -+ else -+ { -+ (*_bfd_error_handler)("Input file %s for cpu version %s", input_filename, input_cpu_version); -+ } -+ -+ (*_bfd_error_handler) ("Link ABORTED."); -+ _exit(EXIT_FAILURE); -+ } -+ } -+ if (error) -+ bfd_set_error (bfd_error_bad_value); -+ -+ return !error; -+} -+ -+static bfd_boolean -+ubicom32_elf_print_private_bfd_data (abfd, ptr) -+ bfd *abfd; -+ PTR ptr; -+{ -+ FILE *file = (FILE *) ptr; -+ flagword flags; -+ -+ BFD_ASSERT (abfd != NULL && ptr != NULL); -+ -+ /* Print normal ELF private data. */ -+ _bfd_elf_print_private_bfd_data (abfd, ptr); -+ -+ flags = elf_elfheader (abfd)->e_flags; -+ fprintf (file, _("private flags = 0x%lx:"), (long)flags); -+ -+ fputc ('\n', file); -+ -+ return TRUE; -+} -+ -+bfd_boolean -+ubicom32_elf_discard_info(abfd, cookie, info) -+ bfd *abfd; -+ struct elf_reloc_cookie *cookie ATTRIBUTE_UNUSED; -+ struct bfd_link_info *info; -+ -+{ -+ unsigned int hasDebugLine=0; -+ unsigned needExclude = 0; -+ asection *o; -+ asection *sec= NULL; -+ bfd_byte *contents = NULL; -+ bfd_byte *contentsEnd; -+ Elf_Internal_Rela *irel, *irelend, *irelbase; -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Sym *isym; -+ Elf_Internal_Sym *isymbuf = NULL; -+ struct debugLineInfoHeader *lh = NULL; -+ unsigned int maxLineInfoEntries = 10; -+ unsigned int offset, contentLength; -+ unsigned char *ptr, *sequence_start; -+ unsigned int setupEntry=1; -+ unsigned int opcode_base, op_code; -+ unsigned int bytes_read; -+ -+ for (o = abfd->sections; o != NULL; o = o->next) -+ { -+ if(!hasDebugLine) -+ if(!strcmp(o->name, ".debug_line")) -+ { -+ hasDebugLine =1; -+ sec = o; -+ } -+ -+ /* Keep special sections. Keep .debug sections. */ -+ if (o->flags & SEC_EXCLUDE) -+ { -+ needExclude = 1; -+ } -+ } -+ -+ if(needExclude == 0 || hasDebugLine ==0) -+ return FALSE; -+ -+ /* -+ * you can be here only if we have .debug_line section and some -+ * section is being excudled -+ */ -+ -+ /* -+ * We need to extract .debug_line section contents and its -+ * relocation contents. -+ */ -+ -+ /* We don't have to do anything for a relocatable link, -+ if this section does not have relocs */ -+ if (info->relocatable -+ || (sec->flags & SEC_RELOC) == 0 -+ || sec->reloc_count == 0) -+ return FALSE; -+ -+ /* If this is the first time we have been called -+ for this section, initialise the cooked size. -+ if (sec->_cooked_size == 0) -+ sec->_cooked_size = sec->rawsize; -+ */ -+ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ -+ irelbase = _bfd_elf_link_read_relocs (abfd, sec, NULL, -+ (Elf_Internal_Rela *)NULL, -+ info->keep_memory); -+ -+ if(irelbase == NULL) -+ return FALSE; -+ -+ irelend = irelbase +sec->reloc_count; -+ -+ /* Get section contents cached copy if it exists. */ -+ if (contents == NULL) -+ { -+ contents = section_contents(abfd, sec); -+ } -+ -+ if (isymbuf == NULL && symtab_hdr->sh_info != 0) -+ { -+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; -+ if (isymbuf == NULL) -+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, -+ symtab_hdr->sh_info, 0, -+ NULL, NULL, NULL); -+ if (isymbuf == NULL) -+ return FALSE; -+ } -+ -+ /* allocate the line header and initialize it */ -+ lh = (struct debugLineInfoHeader *) -+ realloc( (void *)lh, sizeof (struct debugLineInfo)*maxLineInfoEntries + -+ sizeof(unsigned int)); -+ -+ lh->numEntries = 0; -+ -+ /* the first 4 bytes contains the length */ -+ contentLength = bfd_get_32 (abfd, (bfd_byte *)contents); -+ contentsEnd = contents + contentLength + 4; -+ -+ ptr = (unsigned char *)contents; -+ ptr +=6; -+ /* read the header length */ -+ offset = bfd_get_32(abfd, (bfd_byte *)ptr); -+ ptr += 4; -+ ptr += offset; -+ -+ /* extract the base opcode */ -+ opcode_base = (unsigned char)contents[14]; -+ sequence_start = NULL; -+ while(ptr < (unsigned char *) contentsEnd) -+ { -+ if(setupEntry) -+ { -+ if(lh->numEntries == maxLineInfoEntries) -+ { -+ /* need to do some reallocing. Bump up the entries by 10 */ -+ maxLineInfoEntries += 10; -+ lh = (struct debugLineInfoHeader *) -+ realloc( (void *)lh, -+ sizeof (struct debugLineInfo)*maxLineInfoEntries + -+ sizeof(unsigned int)); -+ } -+ -+ /* zero out the entry */ -+ memset((void *) &lh->linfo[lh->numEntries], -+ 0, -+ sizeof(struct debugLineInfo)); -+ lh->linfo[lh->numEntries].startOffset = (bfd_byte *)ptr - contents; -+ setupEntry = 0; -+ sequence_start = ptr; -+ } -+ -+ /* We need to run the state machine */ -+ op_code = bfd_get_8 (abfd, (bfd_byte *)ptr); -+ ptr += 1; -+ -+ if(op_code >= opcode_base) -+ continue; -+ -+ switch(op_code) -+ { -+ case DW_LNS_extended_op: -+ ptr += 1; /* ignore length */ -+ op_code = bfd_get_8 (abfd, (bfd_byte *)ptr); -+ ptr += 1; -+ switch (op_code) -+ { -+ case DW_LNE_end_sequence: -+ /* end of sequence. Time to record stuff */ -+ lh->linfo[lh->numEntries++].length = -+ (bfd_byte *)ptr - sequence_start; -+ setupEntry = 1; -+ break; -+ case DW_LNE_set_address: -+ ptr += 4; -+ break; -+ case DW_LNE_define_file: -+ { -+ ptr += (strlen((char *)ptr) + 1); -+ (void) read_unsigned_leb128(abfd, ptr, &bytes_read); -+ ptr += bytes_read; -+ (void) read_unsigned_leb128(abfd, ptr, &bytes_read); -+ ptr += bytes_read; -+ (void) read_unsigned_leb128(abfd, ptr, &bytes_read); -+ ptr += bytes_read; -+ break; -+ } -+ } -+ case DW_LNS_negate_stmt: -+ case DW_LNS_set_basic_block: -+ case DW_LNS_const_add_pc: -+ case DW_LNS_copy: -+ break; -+ case DW_LNS_advance_pc: -+ case DW_LNS_set_file: -+ case DW_LNS_set_column: -+ (void) read_unsigned_leb128 (abfd, ptr, &bytes_read); -+ ptr += bytes_read; -+ break; -+ case DW_LNS_advance_line: -+ (void) read_signed_leb128 (abfd, ptr, &bytes_read); -+ ptr += bytes_read; -+ break; -+ case DW_LNS_fixed_advance_pc: -+ ptr += 2; -+ break; -+ } -+ } -+ -+ /* -+ * now scan through the relocations and match the -+ * lineinfo to a section name -+ */ -+ for(irel = irelbase; irel< irelend; irel++) -+ { -+ bfd_vma offset; -+ asection *sym_sec; -+ int i; -+ -+ offset = irel->r_offset; -+ isym = isymbuf + ELF32_R_SYM (irel->r_info); -+ -+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); -+ -+ /* find which line section this rel entry belongs to */ -+ for(i=0; i< (int) lh->numEntries; i++) -+ { -+ if(lh->linfo[i].startOffset <= offset && -+ offset < lh->linfo[i].startOffset + lh->linfo[i].length) -+ break; -+ } -+ -+ if(lh->linfo[i].sectionName == NULL) -+ lh->linfo[i].sectionName = strdup(sym_sec->name); -+ } -+ -+ /* now scan through and find the exclude sections */ -+ for (o = abfd->sections; o != NULL; o = o->next) -+ { -+ if (o->flags & SEC_EXCLUDE) -+ { -+ /* go through the lh entries and mark as discard */ -+ int i; -+ for(i=0; i< (int) lh->numEntries; i++) -+ { -+ if(!strcmp(o->name, lh->linfo[i].sectionName)) -+ lh->linfo[i].discard = 1; -+ } -+ } -+ } -+ -+ elf_section_data(sec)->sec_info = (PTR)(lh); -+ -+ return TRUE; -+} -+ -+ -+/* An extension of the elf hash table data structure, containing some -+ additional Blackfin-specific data. */ -+struct ubicom32fdpic_elf_link_hash_table -+{ -+ struct elf_link_hash_table elf; -+ -+ /* A pointer to the .got section. */ -+ asection *sgot; -+ /* A pointer to the .rel.got section. */ -+ asection *sgotrel; -+ /* A pointer to the .rofixup section. */ -+ asection *sgotfixup; -+ /* A pointer to the .plt section. */ -+ asection *splt; -+ /* A pointer to the .rel.plt section. */ -+ asection *spltrel; -+ /* GOT base offset. */ -+ bfd_vma got0; -+ /* Location of the first non-lazy PLT entry, i.e., the number of -+ bytes taken by lazy PLT entries. */ -+ bfd_vma plt0; -+ /* A hash table holding information about which symbols were -+ referenced with which PIC-related relocations. */ -+ struct htab *relocs_info; -+}; -+ -+/* Get the Ubicom32 ELF linker hash table from a link_info structure. */ -+ -+#define ubicom32fdpic_hash_table(info) \ -+ ((struct ubicom32fdpic_elf_link_hash_table *) ((info)->hash)) -+ -+#define ubicom32fdpic_got_section(info) \ -+ (ubicom32fdpic_hash_table (info)->sgot) -+#define ubicom32fdpic_gotrel_section(info) \ -+ (ubicom32fdpic_hash_table (info)->sgotrel) -+#define ubicom32fdpic_gotfixup_section(info) \ -+ (ubicom32fdpic_hash_table (info)->sgotfixup) -+#define ubicom32fdpic_plt_section(info) \ -+ (ubicom32fdpic_hash_table (info)->splt) -+#define ubicom32fdpic_pltrel_section(info) \ -+ (ubicom32fdpic_hash_table (info)->spltrel) -+#define ubicom32fdpic_relocs_info(info) \ -+ (ubicom32fdpic_hash_table (info)->relocs_info) -+#define ubicom32fdpic_got_initial_offset(info) \ -+ (ubicom32fdpic_hash_table (info)->got0) -+#define ubicom32fdpic_plt_initial_offset(info) \ -+ (ubicom32fdpic_hash_table (info)->plt0) -+ -+/* The name of the dynamic interpreter. This is put in the .interp -+ section. */ -+ -+#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1" -+ -+#define DEFAULT_STACK_SIZE 0x20000 -+ -+/* This structure is used to collect the number of entries present in -+ each addressable range of the got. */ -+struct _ubicom32fdpic_dynamic_got_info -+{ -+ /* Several bits of information about the current link. */ -+ struct bfd_link_info *info; -+ /* Total size needed for GOT entries. */ -+ bfd_vma gotoffset_lo, gotoffset_hi; -+ /* Total size needed for function descriptor entries. */ -+ bfd_vma fd_gotoffset_lo, fd_gotoffset_hi; -+ /* Total size needed function descriptor entries referenced in PLT -+ entries, that would be profitable to place in offsets close to -+ the PIC register. */ -+ bfd_vma fdplt, privfdplt; -+ /* Total size needed by lazy PLT entries. */ -+ bfd_vma lzplt; -+ bfd_vma num_plts; -+ -+ /* Number of relocations carried over from input object files. */ -+ unsigned long relocs; -+ /* Number of fixups introduced by relocations in input object files. */ -+ unsigned long fixups; -+}; -+ -+/* This structure is used to assign offsets to got entries, function -+ descriptors, plt entries and lazy plt entries. */ -+struct ubicom32fdpic_dynamic_got_plt_info -+{ -+ /* Summary information collected with _bfinfdpic_count_got_plt_entries. */ -+ struct _ubicom32fdpic_dynamic_got_info g; -+ -+ bfd_signed_vma current_got; /* This will be used during got entry allocation */ -+ bfd_signed_vma current_fd; /* This will be used for function descriptro allocation. The numbers will go negative */ -+ bfd_signed_vma current_privfd; /* This will be used for function descriptro allocation. The numbers will go negative */ -+ bfd_vma current_plt; /* This is the offset to the PLT entry. We will need this to resolve the call entries. */ -+ bfd_vma current_plt_trampoline; /* This is the offset to the PLT trampoline entry. */ -+ bfd_vma total_fdplt; /* Total size of function descriptors. This is the memory above GOT pointer. */ -+ bfd_vma total_got; /* This is the total of got entries for got_lo and got_funcdesc_lo references. */ -+ bfd_vma total_lzplt; /* This is the total area for the PLT entries. This does not have the trampoline entry. */ -+ bfd_vma total_trampoline; /* This is the total area for the PLT trampoline entries. */ -+}; -+ -+/* Decide whether a reference to a symbol can be resolved locally or -+ not. If the symbol is protected, we want the local address, but -+ its function descriptor must be assigned by the dynamic linker. */ -+#define UBICOM32FDPIC_SYM_LOCAL(INFO, H) \ -+ (_bfd_elf_symbol_refs_local_p ((H), (INFO), 1) \ -+ || ! elf_hash_table (INFO)->dynamic_sections_created) -+#define UBICOM32FDPIC_FUNCDESC_LOCAL(INFO, H) \ -+ ((H)->dynindx == -1 || ! elf_hash_table (INFO)->dynamic_sections_created) -+ -+/* This structure collects information on what kind of GOT, PLT or -+ function descriptors are required by relocations that reference a -+ certain symbol. */ -+struct ubicom32fdpic_relocs_info -+{ -+ /* The index of the symbol, as stored in the relocation r_info, if -+ we have a local symbol; -1 otherwise. */ -+ long symndx; -+ union -+ { -+ /* The input bfd in which the symbol is defined, if it's a local -+ symbol. */ -+ bfd *abfd; -+ /* If symndx == -1, the hash table entry corresponding to a global -+ symbol (even if it turns out to bind locally, in which case it -+ should ideally be replaced with section's symndx + addend). */ -+ struct elf_link_hash_entry *h; -+ } d; -+ /* The addend of the relocation that references the symbol. */ -+ bfd_vma addend; -+ -+ /* The fields above are used to identify an entry. The fields below -+ contain information on how an entry is used and, later on, which -+ locations it was assigned. */ -+ /* The following 2 fields record whether the symbol+addend above was -+ ever referenced with a GOT relocation. The 17M4 suffix indicates a -+ GOT17M4 relocation; hilo is used for GOTLO/GOTHI pairs. */ -+ unsigned gotoffset_lo; -+ unsigned gotoffset_hi; -+ /* Whether a FUNCDESC relocation references symbol+addend. */ -+ unsigned fd; -+ /* Whether a FUNCDESC_GOT relocation references symbol+addend. */ -+ unsigned fd_gotoffset_lo; -+ unsigned fd_gotoffset_hi; -+ /* Whether symbol+addend is referenced with GOTOFF17M4, GOTOFFLO or -+ GOTOFFHI relocations. The addend doesn't really matter, since we -+ envision that this will only be used to check whether the symbol -+ is mapped to the same segment as the got. */ -+ unsigned gotoff; -+ /* Whether symbol+addend is referenced by a LABEL24 relocation. */ -+ unsigned call; -+ /* Whether symbol+addend is referenced by a 32 or FUNCDESC_VALUE -+ relocation. */ -+ unsigned sym; -+ /* Whether we need a PLT entry for a symbol. Should be implied by -+ something like: -+ (call && symndx == -1 && ! BFINFDPIC_SYM_LOCAL (info, d.h)) */ -+ unsigned plt:1; -+ /* Whether a function descriptor should be created in this link unit -+ for symbol+addend. Should be implied by something like: -+ (plt || fd_gotoffset_lo || fd_gotoffset_hi -+ || ((fd || fdgot17m4 || fdgothilo) -+ && (symndx != -1 || BFINFDPIC_FUNCDESC_LOCAL (info, d.h)))) */ -+ unsigned privfd:1; -+ /* Whether a lazy PLT entry is needed for this symbol+addend. -+ Should be implied by something like: -+ (privfd && symndx == -1 && ! BFINFDPIC_SYM_LOCAL (info, d.h) -+ && ! (info->flags & DF_BIND_NOW)) */ -+ unsigned lazyplt:1; -+ /* Whether we've already emitted GOT relocations and PLT entries as -+ needed for this symbol. */ -+ unsigned done:1; -+ -+ /* The number of R_byte4_data, R_BFIN_FUNCDESC and R_BFIN_FUNCDESC_VALUE -+ relocations referencing the symbol. */ -+ unsigned relocs32, relocsfd, relocsfdv; -+ -+ /* The number of .rofixups entries and dynamic relocations allocated -+ for this symbol, minus any that might have already been used. */ -+ unsigned fixups, dynrelocs; -+ -+ /* The offsets of the GOT entries assigned to symbol+addend, to the -+ function descriptor's address, and to a function descriptor, -+ respectively. Should be zero if unassigned. The offsets are -+ counted from the value that will be assigned to the PIC register, -+ not from the beginning of the .got section. */ -+ bfd_signed_vma got_entry, fdgot_entry, fd_entry; -+ /* The offsets of the PLT entries assigned to symbol+addend, -+ non-lazy and lazy, respectively. If unassigned, should be -+ (bfd_vma)-1. */ -+ bfd_vma plt_entry; -+ bfd_vma plt_trampoline_entry; -+ -+ /* plt_type is 1 for Sequence type 2 (0 - 255) it is 2 for > 255 */ -+ bfd_vma plt_type; -+ -+ /* rel_offset. Plt relocation offset need to be encoded into the plt entry. */ -+ bfd_vma rel_offset; -+ -+ /* bfd_vma lzplt_entry; not used in ubicom32 */ -+}; -+ -+/* Compute the total GOT size required by each symbol in each range. -+ Symbols may require up to 4 words in the GOT: an entry pointing to -+ the symbol, an entry pointing to its function descriptor, and a -+ private function descriptors taking two words. */ -+ -+#if 0 -+static bfd_vma plt_code[] = { -+ 0xc90f0000, //movei d15,#0 -+ 0x0123e30f, //lea.4 a3,(a0,d15) -+ 0x0124630f, //move.4 a4,(a0,d15) -+ 0x01206461, //move.4 a0,4(a3) -+ 0xf0800080, //calli a4,0(a4) -+}; -+#endif -+ -+static bfd_vma plt_trampoline[] = { -+ 0xc9280000, // movei mac_hi,#0 -+ 0x00002400, // ret (a0) -+}; -+ -+static bfd_vma plt_code_seq1[] = { -+ 0xc90fffe8, //movei d15,#-24 -+ 0x0123e30f, //lea.4 a3,(a0,d15) -+ 0x01206461, //move.4 a0,4(a3) -+ 0x00002460, //ret (a3) -+}; -+ -+static bfd_vma plt_code_seq2[] = { -+ 0x0123f71f, // pdec a3,4(a0) -+ 0x01206461, // move.4 a0,4(a3) -+ 0x00002460, // ret (a3) -+}; -+ -+#define NUM_PLT_CODE_WORDS (sizeof (plt_code) / sizeof (bfd_vma)) -+#define LZPLT_NORMAL_SIZE (sizeof(plt_code)) -+ -+#define NUM_PLT_CODE_WORDS_SEQ1 (sizeof (plt_code_seq1) / sizeof (bfd_vma)) -+#define LZPLT_SIZE_SEQ1 (sizeof(plt_code_seq1)) -+ -+#define NUM_PLT_CODE_WORDS_SEQ2 (sizeof (plt_code_seq2) / sizeof (bfd_vma)) -+#define LZPLT_SIZE_SEQ2 (sizeof(plt_code_seq2)) -+ -+#define NUM_PLT_TRAMPOLINE_WORDS (sizeof (plt_trampoline) / sizeof (bfd_vma)) -+#define PLT_TRAMPOLINE_SIZE (sizeof(plt_trampoline)) -+ -+//#define FUNCTION_DESCRIPTOR_SIZE 12 -+#define FUNCTION_DESCRIPTOR_SIZE 8 -+/* Decide whether a reference to a symbol can be resolved locally or -+ not. If the symbol is protected, we want the local address, but -+ its function descriptor must be assigned by the dynamic linker. */ -+#define UBICOM32FPIC_SYM_LOCAL(INFO, H) \ -+ (_bfd_elf_symbol_refs_local_p ((H), (INFO), 1) \ -+ || ! elf_hash_table (INFO)->dynamic_sections_created) -+#define UBICOM32FPIC_FUNCDESC_LOCAL(INFO, H) \ -+ ((H)->dynindx == -1 || ! elf_hash_table (INFO)->dynamic_sections_created) -+ -+ -+static int -+ubicom32fdpic_count_got_plt_entries (void **entryp, void *dinfo_) -+{ -+ struct ubicom32fdpic_relocs_info *entry = *entryp; -+ struct _ubicom32fdpic_dynamic_got_info *dinfo = dinfo_; -+ unsigned relocs = 0, fixups = 0; -+ -+ /* Allocate space for a GOT entry pointing to the symbol. */ -+ if (entry->gotoffset_lo) -+ { -+ dinfo->gotoffset_lo += 4; -+ entry->relocs32++; -+ } -+ -+ /* Allocate space for a GOT entry pointing to the function -+ descriptor. */ -+ if (entry->fd_gotoffset_lo) -+ { -+ dinfo->gotoffset_lo += 4; -+ entry->relocsfd++; -+ } -+ else if (entry->fd_gotoffset_hi) -+ { -+ dinfo->gotoffset_lo += 4; -+ entry->relocsfd++; -+ } -+ -+ /* Decide whether we need a PLT entry, a function descriptor in the -+ GOT, and a lazy PLT entry for this symbol. */ -+ entry->plt = entry->call -+ && entry->symndx == -1 && ! UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h) -+ && elf_hash_table (dinfo->info)->dynamic_sections_created; -+ entry->privfd = entry->plt -+ || ((entry->fd_gotoffset_lo || entry->fd_gotoffset_hi || entry->fd) -+ && (entry->symndx != -1 -+ || UBICOM32FPIC_FUNCDESC_LOCAL (dinfo->info, entry->d.h))); -+ entry->lazyplt = entry->privfd -+ && entry->symndx == -1 && ! UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h) -+ && ! (dinfo->info->flags & DF_BIND_NOW) -+ && elf_hash_table (dinfo->info)->dynamic_sections_created; -+ -+ /* Allocate space for a function descriptor. */ -+ if (entry->privfd && entry->plt) -+ { -+ dinfo->fdplt += FUNCTION_DESCRIPTOR_SIZE; -+ entry->relocsfdv++; -+ } -+ else if (entry->privfd) -+ { -+ /* privfd with plt = 0 */ -+ //printf("Privfd set with plt 0 gotoff_lo = %d fd_gotoffset_lo = %d entry = 0x%x\n", entry->gotoffset_lo, entry->fd_gotoffset_lo, entry); -+ //printf("symnxd = 0x%x sym_local = %d funcdesc_local = %d\n", entry->symndx, -+ // UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h), -+ // UBICOM32FPIC_FUNCDESC_LOCAL (dinfo->info, entry->d.h)); -+ //printf("Name = %s\n\n", entry->d.h->root.root.string); -+ dinfo->privfdplt += FUNCTION_DESCRIPTOR_SIZE; -+ entry->relocsfdv++; -+ } -+ -+ -+ if (entry->lazyplt) -+ { -+ //dinfo->lzplt += LZPLT_NORMAL_SIZE; -+ dinfo->num_plts++; -+ -+#if 0 -+ if (dinfo->num_plts > 256) -+ dinfo->lzplt += LZPLT_SIZE_SEQ1; -+ else -+ dinfo->lzplt += LZPLT_SIZE_SEQ2; -+ -+ DPRINTF("lzplt %d num_plt %d\n", dinfo->lzplt, dinfo->num_plts); -+#endif -+ } -+ -+ if (!dinfo->info->executable || dinfo->info->pie) -+ relocs = entry->relocs32 + entry->relocsfd + entry->relocsfdv; -+ else -+ { -+ if (entry->symndx != -1 || UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h)) -+ { -+ if (entry->symndx != -1 -+ || entry->d.h->root.type != bfd_link_hash_undefweak) -+ fixups += entry->relocs32 + 2 * entry->relocsfdv; -+ } -+ else -+ relocs += entry->relocs32 + entry->relocsfdv; -+ -+ if (entry->symndx != -1 -+ || UBICOM32FPIC_FUNCDESC_LOCAL (dinfo->info, entry->d.h)) -+ { -+ if (entry->symndx != -1 -+ || entry->d.h->root.type != bfd_link_hash_undefweak) -+ fixups += entry->relocsfd; -+ } -+ else -+ relocs += entry->relocsfd; -+ } -+ -+ entry->dynrelocs += relocs; -+ entry->fixups += fixups; -+ dinfo->relocs += relocs; -+ dinfo->fixups += fixups; -+ -+ return 1; -+} -+ -+/* Create a Ubicom32 ELF linker hash table. */ -+static struct bfd_link_hash_table * -+ubicom32fdpic_elf_link_hash_table_create (bfd *abfd) -+{ -+ struct ubicom32fdpic_elf_link_hash_table *ret; -+ bfd_size_type amt = sizeof (struct ubicom32fdpic_elf_link_hash_table); -+ -+ ret = bfd_zalloc (abfd, amt); -+ if (ret == NULL) -+ return NULL; -+ -+ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, -+ _bfd_elf_link_hash_newfunc, -+ sizeof (struct elf_link_hash_entry))) -+ { -+ free (ret); -+ return NULL; -+ } -+ -+ return &ret->elf.root; -+} -+ -+/* Compute a hash with the key fields of an ubicom32fdpic_relocs_info entry. */ -+static hashval_t -+ubicom32fdpic_relocs_info_hash (const void *entry_) -+{ -+ const struct ubicom32fdpic_relocs_info *entry = entry_; -+ -+ return (entry->symndx == -1 -+ ? (long) entry->d.h->root.root.hash -+ : entry->symndx + (long) entry->d.abfd->id * 257) + entry->addend; -+} -+ -+/* Test whether the key fields of two ubicom32fdpic_relocs_info entries are -+ identical. */ -+static int -+ubicom32fdpic_relocs_info_eq (const void *entry1, const void *entry2) -+{ -+ const struct ubicom32fdpic_relocs_info *e1 = entry1; -+ const struct ubicom32fdpic_relocs_info *e2 = entry2; -+ -+ return e1->symndx == e2->symndx && e1->addend == e2->addend -+ && (e1->symndx == -1 ? e1->d.h == e2->d.h : e1->d.abfd == e2->d.abfd); -+} -+ -+/* Find or create an entry in a hash table HT that matches the key -+ fields of the given ENTRY. If it's not found, memory for a new -+ entry is allocated in ABFD's obstack. */ -+static struct ubicom32fdpic_relocs_info * -+ubicom32fdpic_relocs_info_find (struct htab *ht, -+ bfd *abfd, -+ const struct ubicom32fdpic_relocs_info *entry, -+ enum insert_option insert) -+{ -+ struct ubicom32fdpic_relocs_info **loc = -+ (struct ubicom32fdpic_relocs_info **) htab_find_slot (ht, entry, insert); -+ -+ if (! loc) -+ return NULL; -+ -+ if (*loc) -+ return *loc; -+ -+ *loc = bfd_zalloc (abfd, sizeof (**loc)); -+ -+ if (! *loc) -+ return *loc; -+ -+ (*loc)->symndx = entry->symndx; -+ (*loc)->d = entry->d; -+ (*loc)->addend = entry->addend; -+ (*loc)->plt_entry = (bfd_vma)-1; -+ /* (*loc)->lzplt_entry = (bfd_vma)-1; */ -+ -+ return *loc; -+} -+ -+/* Obtain the address of the entry in HT associated with H's symbol + -+ addend, creating a new entry if none existed. ABFD is only used -+ for memory allocation purposes. */ -+inline static struct ubicom32fdpic_relocs_info * -+ubicom32fdpic_relocs_info_for_global (struct htab *ht, -+ bfd *abfd, -+ struct elf_link_hash_entry *h, -+ bfd_vma addend, -+ enum insert_option insert) -+{ -+ struct ubicom32fdpic_relocs_info entry; -+ -+ entry.symndx = -1; -+ entry.d.h = h; -+ entry.addend = addend; -+ -+ return ubicom32fdpic_relocs_info_find (ht, abfd, &entry, insert); -+} -+ -+/* Obtain the address of the entry in HT associated with the SYMNDXth -+ local symbol of the input bfd ABFD, plus the addend, creating a new -+ entry if none existed. */ -+inline static struct ubicom32fdpic_relocs_info * -+ubicom32fdpic_relocs_info_for_local (struct htab *ht, -+ bfd *abfd, -+ long symndx, -+ bfd_vma addend, -+ enum insert_option insert) -+{ -+ struct ubicom32fdpic_relocs_info entry; -+ -+ entry.symndx = symndx; -+ entry.d.abfd = abfd; -+ entry.addend = addend; -+ -+ return ubicom32fdpic_relocs_info_find (ht, abfd, &entry, insert); -+} -+ -+/* Merge fields set by check_relocs() of two entries that end up being -+ mapped to the same (presumably global) symbol. */ -+ -+inline static void -+ubicom32fdpic_pic_merge_early_relocs_info (struct ubicom32fdpic_relocs_info *e2, -+ struct ubicom32fdpic_relocs_info const *e1) -+{ -+ e2->gotoffset_lo |= e1->gotoffset_lo; -+ e2->gotoffset_hi |= e1->gotoffset_hi; -+ e2->fd_gotoffset_lo |= e1->fd_gotoffset_lo; -+ e2->fd_gotoffset_hi |= e1->fd_gotoffset_hi; -+ e2->fd |= e1->fd; -+ e2->gotoff |= e1->gotoff; -+ e2->call |= e1->call; -+ e2->sym |= e1->sym; -+} -+ -+/* Add a dynamic relocation to the SRELOC section. */ -+ -+inline static bfd_vma -+ubicom32fdpic_add_dyn_reloc (bfd *output_bfd, asection *sreloc, bfd_vma offset, -+ int reloc_type, long dynindx, bfd_vma addend, -+ struct ubicom32fdpic_relocs_info *entry) -+{ -+ Elf_Internal_Rela outrel; -+ bfd_vma reloc_offset; -+ -+ outrel.r_offset = offset; -+ outrel.r_info = ELF32_R_INFO (dynindx, reloc_type); -+ outrel.r_addend = addend; -+ -+ reloc_offset = sreloc->reloc_count * sizeof (Elf32_External_Rel); -+ BFD_ASSERT (reloc_offset < sreloc->size); -+ bfd_elf32_swap_reloc_out (output_bfd, &outrel, -+ sreloc->contents + reloc_offset); -+ sreloc->reloc_count++; -+ -+ /* If the entry's index is zero, this relocation was probably to a -+ linkonce section that got discarded. We reserved a dynamic -+ relocation, but it was for another entry than the one we got at -+ the time of emitting the relocation. Unfortunately there's no -+ simple way for us to catch this situation, since the relocation -+ is cleared right before calling relocate_section, at which point -+ we no longer know what the relocation used to point to. */ -+ if (entry->symndx) -+ { -+ BFD_ASSERT (entry->dynrelocs > 0); -+ entry->dynrelocs--; -+ } -+ -+ return reloc_offset; -+} -+ -+/* Add a fixup to the ROFIXUP section. */ -+ -+static bfd_vma -+ubicom32fdpic_add_rofixup (bfd *output_bfd, asection *rofixup, bfd_vma offset, -+ struct ubicom32fdpic_relocs_info *entry) -+{ -+ bfd_vma fixup_offset; -+ -+ if (rofixup->flags & SEC_EXCLUDE) -+ return -1; -+ -+ fixup_offset = rofixup->reloc_count * 4; -+ if (rofixup->contents) -+ { -+ BFD_ASSERT (fixup_offset < rofixup->size); -+ bfd_put_32 (output_bfd, offset, rofixup->contents + fixup_offset); -+ } -+ rofixup->reloc_count++; -+ -+ if (entry && entry->symndx) -+ { -+ /* See discussion about symndx == 0 in _ubicom32fdpic_add_dyn_reloc -+ above. */ -+ BFD_ASSERT (entry->fixups > 0); -+ entry->fixups--; -+ } -+ -+ return fixup_offset; -+} -+ -+/* Find the segment number in which OSEC, and output section, is -+ located. */ -+ -+static unsigned -+ubicom32fdpic_osec_to_segment (bfd *output_bfd, asection *osec) -+{ -+ Elf_Internal_Phdr *p = _bfd_elf_find_segment_containing_section (output_bfd, osec); -+ -+ return (p != NULL) ? p - elf_tdata (output_bfd)->phdr : -1; -+} -+ -+inline static bfd_boolean -+ubicom32fdpic_osec_readonly_p (bfd *output_bfd, asection *osec) -+{ -+ unsigned seg = ubicom32fdpic_osec_to_segment (output_bfd, osec); -+ -+ return ! (elf_tdata (output_bfd)->phdr[seg].p_flags & PF_W); -+} -+ -+#if 0 -+static bfd_vma plt_trampoline[] = { -+ 0x00002400, //ret (a0) -+}; -+#endif -+ -+/* Generate relocations for GOT entries, function descriptors, and -+ code for PLT and lazy PLT entries. */ -+ -+static bfd_boolean -+ubicom32fdpic_emit_got_relocs_plt_entries (struct ubicom32fdpic_relocs_info *entry, -+ bfd *output_bfd, -+ struct bfd_link_info *info, -+ asection *sec, -+ Elf_Internal_Sym *sym, -+ bfd_vma addend) -+ -+{ -+ bfd_vma fd_lazy_rel_offset = (bfd_vma)-1; -+ int dynindx = -1; -+ -+ if (entry->done) -+ return TRUE; -+ entry->done = 1; -+ -+ if (entry->got_entry || entry->fdgot_entry || entry->fd_entry) -+ { -+ DPRINTF(" emit %p got %d fdgot %d fd %d addend %d\n", entry, entry->got_entry, entry->fdgot_entry, entry->fd_entry, addend); -+ /* If the symbol is dynamic, consider it for dynamic -+ relocations, otherwise decay to section + offset. */ -+ if (entry->symndx == -1 && entry->d.h->dynindx != -1) -+ dynindx = entry->d.h->dynindx; -+ else -+ { -+ if (sec->output_section -+ && ! bfd_is_abs_section (sec->output_section) -+ && ! bfd_is_und_section (sec->output_section)) -+ dynindx = elf_section_data (sec->output_section)->dynindx; -+ else -+ dynindx = 0; -+ } -+ } -+ -+ /* Generate relocation for GOT entry pointing to the symbol. */ -+ if (entry->got_entry) -+ { -+ DPRINTF(" emit got entry %d:%p\n", entry->got_entry, entry); -+ -+ int idx = dynindx; -+ bfd_vma ad = addend; -+ -+ /* If the symbol is dynamic but binds locally, use -+ section+offset. */ -+ if (sec && (entry->symndx != -1 -+ || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h))) -+ { -+ if (entry->symndx == -1) -+ ad += entry->d.h->root.u.def.value; -+ else -+ ad += sym->st_value; -+ ad += sec->output_offset; -+ if (sec->output_section && elf_section_data (sec->output_section)) -+ idx = elf_section_data (sec->output_section)->dynindx; -+ else -+ idx = 0; -+ } -+ -+ /* If we're linking an executable at a fixed address, we can -+ omit the dynamic relocation as long as the symbol is local to -+ this module. */ -+ if (info->executable && !info->pie -+ && (entry->symndx != -1 -+ || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h))) -+ { -+ if (sec) -+ ad += sec->output_section->vma; -+ if (entry->symndx != -1 -+ || entry->d.h->root.type != bfd_link_hash_undefweak) -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section (info), -+ ubicom32fdpic_got_section (info)->output_section->vma -+ + ubicom32fdpic_got_section (info)->output_offset -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->got_entry, entry); -+ } -+ else -+ ubicom32fdpic_add_dyn_reloc (output_bfd, ubicom32fdpic_gotrel_section (info), -+ _bfd_elf_section_offset -+ (output_bfd, info, -+ ubicom32fdpic_got_section (info), -+ ubicom32fdpic_got_initial_offset (info) -+ + entry->got_entry) -+ + ubicom32fdpic_got_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_got_section (info)->output_offset, -+ R_UBICOM32_32, idx, ad, entry); -+ -+ bfd_put_32 (output_bfd, ad, -+ ubicom32fdpic_got_section (info)->contents -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->got_entry); -+ } -+ -+ /* Generate relocation for GOT entry pointing to a canonical -+ function descriptor. */ -+ if (entry->fdgot_entry) -+ { -+ DPRINTF(" emit got fdgot entry %d:%p\n", entry->fdgot_entry, entry); -+ -+ int reloc, idx; -+ bfd_vma ad = 0; -+ -+ if (! (entry->symndx == -1 -+ && entry->d.h->root.type == bfd_link_hash_undefweak -+ && UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h))) -+ { -+ /* If the symbol is dynamic and there may be dynamic symbol -+ resolution because we are, or are linked with, a shared -+ library, emit a FUNCDESC relocation such that the dynamic -+ linker will allocate the function descriptor. If the -+ symbol needs a non-local function descriptor but binds -+ locally (e.g., its visibility is protected, emit a -+ dynamic relocation decayed to section+offset. */ -+ if (entry->symndx == -1 -+ && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, entry->d.h) -+ && UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h) -+ && !(info->executable && !info->pie)) -+ { -+ reloc = R_UBICOM32_FUNCDESC; -+ idx = elf_section_data (entry->d.h->root.u.def.section -+ ->output_section)->dynindx; -+ ad = entry->d.h->root.u.def.section->output_offset -+ + entry->d.h->root.u.def.value; -+ } -+ else if (entry->symndx == -1 -+ && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, entry->d.h)) -+ { -+ reloc = R_UBICOM32_FUNCDESC; -+ idx = dynindx; -+ ad = addend; -+ if (ad) -+ return FALSE; -+ } -+ else -+ { -+ /* Otherwise, we know we have a private function descriptor, -+ so reference it directly. */ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ BFD_ASSERT (entry->privfd); -+ reloc = R_UBICOM32_32; -+ idx = elf_section_data (ubicom32fdpic_got_section (info) -+ ->output_section)->dynindx; -+ ad = ubicom32fdpic_got_section (info)->output_offset -+ + ubicom32fdpic_got_initial_offset (info) + entry->fd_entry; -+ } -+ -+ /* If there is room for dynamic symbol resolution, emit the -+ dynamic relocation. However, if we're linking an -+ executable at a fixed location, we won't have emitted a -+ dynamic symbol entry for the got section, so idx will be -+ zero, which means we can and should compute the address -+ of the private descriptor ourselves. */ -+ if (info->executable && !info->pie -+ && (entry->symndx != -1 -+ || UBICOM32FDPIC_FUNCDESC_LOCAL (info, entry->d.h))) -+ { -+ ad += ubicom32fdpic_got_section (info)->output_section->vma; -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section (info), -+ ubicom32fdpic_got_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_got_section (info) -+ ->output_offset -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fdgot_entry, entry); -+ } -+ else -+ ubicom32fdpic_add_dyn_reloc (output_bfd, -+ ubicom32fdpic_gotrel_section (info), -+ _bfd_elf_section_offset -+ (output_bfd, info, -+ ubicom32fdpic_got_section (info), -+ ubicom32fdpic_got_initial_offset (info) -+ + entry->fdgot_entry) -+ + ubicom32fdpic_got_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_got_section (info) -+ ->output_offset, -+ reloc, idx, ad, entry); -+ } -+ -+ bfd_put_32 (output_bfd, ad, -+ ubicom32fdpic_got_section (info)->contents -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fdgot_entry); -+ } -+ -+ /* Generate relocation to fill in a private function descriptor in -+ the GOT. */ -+ if (entry->fd_entry) -+ { -+ -+ int idx = dynindx; -+ bfd_vma ad = addend; -+ bfd_vma ofst; -+ long lowword, highword; -+ -+ /* If the symbol is dynamic but binds locally, use -+ section+offset. */ -+ if (sec && (entry->symndx != -1 -+ || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h))) -+ { -+ if (entry->symndx == -1) -+ ad += entry->d.h->root.u.def.value; -+ else -+ ad += sym->st_value; -+ ad += sec->output_offset; -+ if (sec->output_section && elf_section_data (sec->output_section)) -+ idx = elf_section_data (sec->output_section)->dynindx; -+ else -+ idx = 0; -+ } -+ -+ /* If we're linking an executable at a fixed address, we can -+ omit the dynamic relocation as long as the symbol is local to -+ this module. */ -+ if (info->executable && !info->pie -+ && (entry->symndx != -1 || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h))) -+ { -+ if (sec) -+ ad += sec->output_section->vma; -+ ofst = 0; -+ if (entry->symndx != -1 -+ || entry->d.h->root.type != bfd_link_hash_undefweak) -+ { -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section (info), -+ ubicom32fdpic_got_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_got_section (info) -+ ->output_offset -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fd_entry, entry); -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section (info), -+ ubicom32fdpic_got_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_got_section (info) -+ ->output_offset -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fd_entry + 4, entry); -+ } -+ } -+ else -+ { -+ ofst -+ = ubicom32fdpic_add_dyn_reloc (output_bfd, -+ entry->lazyplt -+ ? ubicom32fdpic_pltrel_section (info) -+ : ubicom32fdpic_gotrel_section (info), -+ _bfd_elf_section_offset -+ (output_bfd, info, -+ ubicom32fdpic_got_section (info), -+ ubicom32fdpic_got_initial_offset (info) -+ + entry->fd_entry) -+ + ubicom32fdpic_got_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_got_section (info) -+ ->output_offset, -+ R_UBICOM32_FUNCDESC_VALUE, idx, ad, entry); -+ } -+ -+ /* If we've omitted the dynamic relocation, just emit the fixed -+ addresses of the symbol and of the local GOT base offset. */ -+ if (info->executable && !info->pie && sec && sec->output_section) -+ { -+ lowword = ad; -+ highword = ubicom32fdpic_got_section (info)->output_section->vma -+ + ubicom32fdpic_got_section (info)->output_offset -+ + ubicom32fdpic_got_initial_offset (info); -+ } -+ else if (entry->lazyplt) -+ { -+ if (ad) -+ return FALSE; -+ -+ fd_lazy_rel_offset = ofst; -+ -+ /* A function descriptor used for lazy or local resolving is -+ initialized such that its high word contains the output -+ section index in which the PLT entries are located, and -+ the low word contains the address to the base of the PLT. -+ That location contains the PLT trampoline instruction ret 0(a0). -+ assigned to that section. */ -+ lowword = ubicom32fdpic_plt_section (info)->output_offset -+ + ubicom32fdpic_plt_section (info)->output_section->vma + entry->plt_trampoline_entry; -+ highword = ubicom32fdpic_osec_to_segment -+ (output_bfd, ubicom32fdpic_plt_section (info)->output_section); -+ } -+ else -+ { -+ /* A function descriptor for a local function gets the index -+ of the section. For a non-local function, it's -+ disregarded. */ -+ lowword = ad; -+ if (entry->symndx == -1 && entry->d.h->dynindx != -1 -+ && entry->d.h->dynindx == idx) -+ highword = 0; -+ else -+ highword = ubicom32fdpic_osec_to_segment -+ (output_bfd, sec->output_section); -+ } -+ -+ DPRINTF(" emit got fd_entry %d:%p lw 0x%x hw 0x%x fd_l_r_off 0x%x\n", entry->fd_entry, entry, lowword, highword, fd_lazy_rel_offset); -+ -+ -+ bfd_put_32 (output_bfd, lowword, -+ ubicom32fdpic_got_section (info)->contents -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fd_entry); -+ bfd_put_32 (output_bfd, highword, -+ ubicom32fdpic_got_section (info)->contents -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fd_entry + 4); -+ -+#if 0 -+ /* Load the fixup offset here. */ -+ bfd_put_32 (output_bfd, fd_lazy_rel_offset, -+ ubicom32fdpic_got_section (info)->contents -+ + ubicom32fdpic_got_initial_offset (info) -+ + entry->fd_entry + 8); -+#endif -+ -+ entry->rel_offset = fd_lazy_rel_offset; -+ } -+ -+ /* Generate code for the PLT entry. */ -+ if (entry->plt_entry != (bfd_vma) -1) -+ { -+ static output_trampoline_code = 1; -+ bfd_byte *plt_output_code = ubicom32fdpic_plt_section (info)->contents; -+ int i; -+ bfd_vma *plt_code; -+ -+ DPRINTF(" emit fd entry %x:%p plt=%2x code=%p\n", entry->fd_entry, entry, entry->plt_entry, plt_output_code); -+ -+#if 0 -+ if (output_trampoline_code) -+ { -+ /* output the trampoline code.*/ -+ bfd_put_32 (output_bfd, plt_trampoline[0], plt_output_code); -+ } -+#endif -+ -+ /* output the trampoline entry. */ -+ -+ plt_output_code += entry->plt_trampoline_entry; -+ plt_code = plt_trampoline; -+ plt_code[0] = (plt_code[0] & 0xFFFF0000) | (entry->rel_offset &0xffff); -+ bfd_put_32 (output_bfd, plt_code[0], plt_output_code); -+ bfd_put_32 (output_bfd, plt_code[1], plt_output_code + 4); -+ -+ -+ /* output the plt itself. */ -+ plt_output_code = ubicom32fdpic_plt_section (info)->contents; -+ plt_output_code += entry->plt_entry; -+ BFD_ASSERT (entry->fd_entry); -+ -+ if (entry->plt_type == 2) -+ { -+ bfd_vma data_lo = (entry->fd_entry >> 2) & 0xff; -+ -+ /* Output seqence 2. */ -+ plt_code = plt_code_seq2; -+ -+ /* Code the entry into the PDEC instruction. */ -+ plt_code[0] &= 0xFFFFF8E0; -+ plt_code[0] |= (data_lo & 0x1F); -+ plt_code[0] |= (data_lo & 0xE0) << 3; -+ -+ /* Write out the sequence. */ -+ for (i = 0; i < NUM_PLT_CODE_WORDS_SEQ2; i++) -+ { -+ bfd_put_32 (output_bfd, plt_code[i], plt_output_code); -+ plt_output_code += 4; -+ } -+ } -+ else if (entry->plt_type == 1) -+ { -+ /* Outupt sequence 1 */ -+ plt_code = plt_code_seq1; -+ -+ /* Code the entry into the movei instruction. */ -+ plt_code[0] = (plt_code[0] & 0xFFFF0000) | ((entry->fd_entry >> 2) & 0xFFFF); -+ -+ /* Write out the sequence. */ -+ for (i = 0; i < NUM_PLT_CODE_WORDS_SEQ1; i++) -+ { -+ bfd_put_32 (output_bfd, plt_code[i], plt_output_code); -+ plt_output_code += 4; -+ } -+ } -+ else -+ BFD_ASSERT(0); -+ -+#if 0 -+ /* We have to output 5 words. The very first movei has to be modified with whatever is in fd_entry. */ -+ plt_code[0] = (plt_code[0] & 0xFFFF0000) | ((entry->fd_entry >> 2) & 0xFFFF); -+ -+ for (i = 0; i < NUM_PLT_CODE_WORDS; i++) -+ { -+ bfd_put_32 (output_bfd, plt_code[i], plt_output_code); -+ plt_output_code += 4; -+ } -+#endif -+ } -+ -+ return TRUE; -+} -+ -+ -+/* Create a .got section, as well as its additional info field. This -+ is almost entirely copied from -+ elflink.c:_bfd_elf_create_got_section(). */ -+ -+static bfd_boolean -+ubicom32fdpic_elf_create_got_section (bfd *abfd, struct bfd_link_info *info) -+{ -+ flagword flags, pltflags; -+ asection *s; -+ struct elf_link_hash_entry *h; -+ const struct elf_backend_data *bed = get_elf_backend_data (abfd); -+ int ptralign; -+ int offset; -+ -+ /* This function may be called more than once. */ -+ s = bfd_get_section_by_name (abfd, ".got"); -+ if (s != NULL && (s->flags & SEC_LINKER_CREATED) != 0) -+ return TRUE; -+ -+ /* Machine specific: although pointers are 32-bits wide, we want the -+ GOT to be aligned to a 64-bit boundary, such that function -+ descriptors in it can be accessed with 64-bit loads and -+ stores. */ -+ ptralign = 3; -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED); -+ pltflags = flags; -+ -+ s = bfd_make_section_with_flags (abfd, ".got", flags); -+ if (s == NULL -+ || !bfd_set_section_alignment (abfd, s, ptralign)) -+ return FALSE; -+ -+ if (bed->want_got_plt) -+ { -+ s = bfd_make_section_with_flags (abfd, ".got.plt", flags); -+ if (s == NULL -+ || !bfd_set_section_alignment (abfd, s, ptralign)) -+ return FALSE; -+ } -+ -+ if (bed->want_got_sym) -+ { -+ /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got -+ (or .got.plt) section. We don't do this in the linker script -+ because we don't want to define the symbol if we are not creating -+ a global offset table. */ -+ h = _bfd_elf_define_linkage_sym (abfd, info, s, "_GLOBAL_OFFSET_TABLE_"); -+ elf_hash_table (info)->hgot = h; -+ if (h == NULL) -+ return FALSE; -+ -+ /* Machine-specific: we want the symbol for executables as -+ well. */ -+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return FALSE; -+ } -+ -+ /* The first bit of the global offset table is the header. */ -+ s->size += bed->got_header_size; -+ -+ /* This is the machine-specific part. Create and initialize section -+ data for the got. */ -+ if (IS_FDPIC (abfd)) -+ { -+ ubicom32fdpic_got_section (info) = s; -+ ubicom32fdpic_relocs_info (info) = htab_try_create (1, -+ ubicom32fdpic_relocs_info_hash, -+ ubicom32fdpic_relocs_info_eq, -+ (htab_del) NULL); -+ if (! ubicom32fdpic_relocs_info (info)) -+ return FALSE; -+ -+ s = bfd_make_section_with_flags (abfd, ".rel.got", -+ (flags | SEC_READONLY)); -+ if (s == NULL -+ || ! bfd_set_section_alignment (abfd, s, 2)) -+ return FALSE; -+ -+ ubicom32fdpic_gotrel_section (info) = s; -+ -+ /* Machine-specific. */ -+ s = bfd_make_section_with_flags (abfd, ".rofixup", -+ (flags | SEC_READONLY)); -+ if (s == NULL -+ || ! bfd_set_section_alignment (abfd, s, 2)) -+ return FALSE; -+ -+ ubicom32fdpic_gotfixup_section (info) = s; -+ offset = -2048; -+ flags = BSF_GLOBAL; -+ } -+ else -+ { -+ offset = 2048; -+ flags = BSF_GLOBAL | BSF_WEAK; -+ } -+ -+ return TRUE; -+} -+ -+/* Make sure the got and plt sections exist, and that our pointers in -+ the link hash table point to them. */ -+ -+static bfd_boolean -+ubicom32fdpic_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) -+{ flagword flags, pltflags; -+ asection *s; -+ const struct elf_backend_data *bed = get_elf_backend_data (abfd); -+ -+ /* We need to create .plt, .rel[a].plt, .got, .got.plt, .dynbss, and -+ .rel[a].bss sections. */ -+ DPRINTF(" ubicom32fdpic_elf_create_dynamic_sections %p %p\n", abfd, info); -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED); -+ -+ pltflags = flags; -+ pltflags |= SEC_CODE; -+ if (bed->plt_not_loaded) -+ pltflags &= ~ (SEC_CODE | SEC_LOAD | SEC_HAS_CONTENTS); -+ if (bed->plt_readonly) -+ pltflags |= SEC_READONLY; -+ -+ s = bfd_make_section_with_flags (abfd, ".plt", pltflags); -+ if (s == NULL -+ || ! bfd_set_section_alignment (abfd, s, bed->plt_alignment)) -+ return FALSE; -+ /* Blackfin-specific: remember it. */ -+ ubicom32fdpic_plt_section (info) = s; -+ -+ if (bed->want_plt_sym) -+ { -+ /* Define the symbol _PROCEDURE_LINKAGE_TABLE_ at the start of the -+ .plt section. */ -+ struct elf_link_hash_entry *h; -+ struct bfd_link_hash_entry *bh = NULL; -+ -+ if (! (_bfd_generic_link_add_one_symbol -+ (info, abfd, "_PROCEDURE_LINKAGE_TABLE_", BSF_GLOBAL, s, 0, NULL, -+ FALSE, get_elf_backend_data (abfd)->collect, &bh))) -+ return FALSE; -+ h = (struct elf_link_hash_entry *) bh; -+ h->def_regular = 1; -+ h->type = STT_OBJECT; -+ -+ if (! info->executable -+ && ! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return FALSE; -+ } -+ -+ /* Blackfin-specific: we want rel relocations for the plt. */ -+ s = bfd_make_section_with_flags (abfd, ".rel.plt", flags | SEC_READONLY); -+ if (s == NULL -+ || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) -+ return FALSE; -+ /* Blackfin-specific: remember it. */ -+ ubicom32fdpic_pltrel_section (info) = s; -+ -+ /* Blackfin-specific: we want to create the GOT in the Blackfin way. */ -+ if (! ubicom32fdpic_elf_create_got_section (abfd, info)) -+ return FALSE; -+ -+ /* Blackfin-specific: make sure we created everything we wanted. */ -+ BFD_ASSERT (ubicom32fdpic_got_section (info) && ubicom32fdpic_gotrel_section (info) -+ /* && ubicom32fdpic_gotfixup_section (info) */ -+ && ubicom32fdpic_plt_section (info) -+ && ubicom32fdpic_pltrel_section (info)); -+ -+ if (bed->want_dynbss) -+ { -+ /* The .dynbss section is a place to put symbols which are defined -+ by dynamic objects, are referenced by regular objects, and are -+ not functions. We must allocate space for them in the process -+ image and use a R_*_COPY reloc to tell the dynamic linker to -+ initialize them at run time. The linker script puts the .dynbss -+ section into the .bss section of the final image. */ -+ s = bfd_make_section_with_flags (abfd, ".dynbss", -+ SEC_ALLOC | SEC_LINKER_CREATED); -+ if (s == NULL) -+ return FALSE; -+ -+ /* The .rel[a].bss section holds copy relocs. This section is not -+ normally needed. We need to create it here, though, so that the -+ linker will map it to an output section. We can't just create it -+ only if we need it, because we will not know whether we need it -+ until we have seen all the input files, and the first time the -+ main linker code calls BFD after examining all the input files -+ (size_dynamic_sections) the input sections have already been -+ mapped to the output sections. If the section turns out not to -+ be needed, we can discard it later. We will never need this -+ section when generating a shared object, since they do not use -+ copy relocs. */ -+ if (! info->shared) -+ { -+ s = bfd_make_section_with_flags (abfd, -+ (bed->default_use_rela_p -+ ? ".rela.bss" : ".rel.bss"), -+ flags | SEC_READONLY); -+ if (s == NULL -+ || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) -+ return FALSE; -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* We need dynamic symbols for every section, since segments can -+ relocate independently. */ -+static bfd_boolean -+ubicom32fdpic_elf_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info -+ ATTRIBUTE_UNUSED, -+ asection *p ATTRIBUTE_UNUSED) -+{ -+ switch (elf_section_data (p)->this_hdr.sh_type) -+ { -+ case SHT_PROGBITS: -+ case SHT_NOBITS: -+ /* If sh_type is yet undecided, assume it could be -+ SHT_PROGBITS/SHT_NOBITS. */ -+ case SHT_NULL: -+ return FALSE; -+ -+ /* There shouldn't be section relative relocations -+ against any other section. */ -+ default: -+ return TRUE; -+ } -+} -+ -+/* Look through the relocs for a section during the first phase. -+ -+ Besides handling virtual table relocs for gc, we have to deal with -+ all sorts of PIC-related relocations. We describe below the -+ general plan on how to handle such relocations, even though we only -+ collect information at this point, storing them in hash tables for -+ perusal of later passes. -+ -+*/ -+static bfd_boolean -+ubicom32fdpic_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, -+ asection *sec, const Elf_Internal_Rela *relocs) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; -+ const Elf_Internal_Rela *rel; -+ const Elf_Internal_Rela *rel_end; -+ bfd *dynobj; -+ struct ubicom32fdpic_relocs_info *picrel; -+ -+ if (info->relocatable) -+ return TRUE; -+ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (abfd); -+ sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym); -+ if (!elf_bad_symtab (abfd)) -+ sym_hashes_end -= symtab_hdr->sh_info; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ rel_end = relocs + sec->reloc_count; -+ for (rel = relocs; rel < rel_end; rel++) -+ { -+ struct elf_link_hash_entry *h; -+ unsigned long r_symndx; -+ -+ r_symndx = ELF32_R_SYM (rel->r_info); -+ if (r_symndx < symtab_hdr->sh_info) -+ h = NULL; -+ else -+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; -+ -+ switch (ELF32_R_TYPE (rel->r_info)) -+ { -+ case R_UBICOM32_GOTOFFSET_HI: -+ case R_UBICOM32_GOTOFFSET_LO: -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_HI: -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ case R_UBICOM32_FUNCDESC: -+ case R_UBICOM32_FUNCDESC_VALUE: -+ if (! IS_FDPIC (abfd)) -+ goto bad_reloc; -+ /* Fall through. */ -+ case R_UBICOM32_24_PCREL: -+ case R_UBICOM32_32: -+ if (IS_FDPIC (abfd) && ! dynobj) -+ { -+ elf_hash_table (info)->dynobj = dynobj = abfd; -+ if (! ubicom32fdpic_elf_create_got_section (abfd, info)) -+ return FALSE; -+ } -+ if (! IS_FDPIC (abfd)) -+ { -+ picrel = NULL; -+ break; -+ } -+ if (h != NULL) -+ { -+ if (h->dynindx == -1) -+ switch (ELF_ST_VISIBILITY (h->other)) -+ { -+ case STV_INTERNAL: -+ case STV_HIDDEN: -+ break; -+ default: -+ bfd_elf_link_record_dynamic_symbol (info, h); -+ break; -+ } -+ picrel -+ = ubicom32fdpic_relocs_info_for_global (ubicom32fdpic_relocs_info (info), -+ abfd, h, -+ rel->r_addend, INSERT); -+ } -+ else -+ picrel = ubicom32fdpic_relocs_info_for_local (ubicom32fdpic_relocs_info (info), -+ abfd, r_symndx, -+ rel->r_addend, INSERT); -+ if (! picrel) -+ return FALSE; -+ break; -+ -+ default: -+ picrel = NULL; -+ break; -+ } -+ -+ switch (ELF32_R_TYPE (rel->r_info)) -+ { -+ case R_UBICOM32_24_PCREL: -+ if (IS_FDPIC (abfd)) -+ picrel->call++; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_VALUE: -+ picrel->relocsfdv++; -+ picrel->sym++; -+ break; -+ -+ case R_UBICOM32_32: -+ if (! IS_FDPIC (abfd)) -+ break; -+ -+ picrel->sym++; -+ if (bfd_get_section_flags (abfd, sec) & SEC_ALLOC) -+ picrel->relocs32++; -+ break; -+ -+ case R_UBICOM32_GOTOFFSET_HI: -+ picrel->gotoffset_hi++; -+ break; -+ -+ case R_UBICOM32_GOTOFFSET_LO: -+ picrel->gotoffset_lo++; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_HI: -+ picrel->fd_gotoffset_hi++; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ picrel->fd_gotoffset_lo++; -+ break; -+ -+ case R_UBICOM32_FUNCDESC: -+ picrel->fd++; -+ picrel->relocsfd++; -+ break; -+ -+ /* This relocation describes the C++ object vtable hierarchy. -+ Reconstruct it for later use during GC. */ -+ case R_UBICOM32_GNU_VTINHERIT: -+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) -+ return FALSE; -+ break; -+ -+ /* This relocation describes which C++ vtable entries are actually -+ used. Record for later use during GC. */ -+ case R_UBICOM32_GNU_VTENTRY: -+ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) -+ return FALSE; -+ break; -+ -+ case R_UBICOM32_21_PCREL: -+ case R_UBICOM32_HI24: -+ case R_UBICOM32_LO7_S: -+ break; -+ -+ default: -+ bad_reloc: -+ (*_bfd_error_handler) -+ (_("%B: unsupported (ubicom32) relocation type %i"), -+ abfd, ELF32_R_TYPE (rel->r_info)); -+ return FALSE; -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* Follow indirect and warning hash entries so that each got entry -+ points to the final symbol definition. P must point to a pointer -+ to the hash table we're traversing. Since this traversal may -+ modify the hash table, we set this pointer to NULL to indicate -+ we've made a potentially-destructive change to the hash table, so -+ the traversal must be restarted. */ -+static int -+ubicom32fdpic_resolve_final_relocs_info (void **entryp, void *p) -+{ -+ struct ubicom32fdpic_relocs_info *entry = *entryp; -+ htab_t *htab = p; -+ -+ if (entry->symndx == -1) -+ { -+ struct elf_link_hash_entry *h = entry->d.h; -+ struct ubicom32fdpic_relocs_info *oentry; -+ -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *)h->root.u.i.link; -+ -+ if (entry->d.h == h) -+ return 1; -+ -+ oentry = ubicom32fdpic_relocs_info_for_global (*htab, 0, h, entry->addend, -+ NO_INSERT); -+ -+ if (oentry) -+ { -+ /* Merge the two entries. */ -+ ubicom32fdpic_pic_merge_early_relocs_info (oentry, entry); -+ htab_clear_slot (*htab, entryp); -+ return 1; -+ } -+ -+ entry->d.h = h; -+ -+ /* If we can't find this entry with the new bfd hash, re-insert -+ it, and get the traversal restarted. */ -+ if (! htab_find (*htab, entry)) -+ { -+ htab_clear_slot (*htab, entryp); -+ entryp = htab_find_slot (*htab, entry, INSERT); -+ if (! *entryp) -+ *entryp = entry; -+ /* Abort the traversal, since the whole table may have -+ moved, and leave it up to the parent to restart the -+ process. */ -+ *(htab_t *)p = NULL; -+ return 0; -+ } -+ } -+ -+ return 1; -+} -+ -+/* Assign GOT offsets to private function descriptors used by PLT -+ entries (or referenced by 32-bit offsets), as well as PLT entries -+ and lazy PLT entries. */ -+static int -+ubicom32fdpic_assign_plt_entries (void **entryp, void *info_) -+{ -+ struct ubicom32fdpic_relocs_info *entry = *entryp; -+ struct ubicom32fdpic_dynamic_got_plt_info *dinfo = info_; -+ -+ if (entry->privfd && entry->fd_entry == 0) -+ { -+ // dinfo->current_fd -= FUNCTION_DESCRIPTOR_SIZE; -+ // entry->fd_entry = dinfo->current_fd; -+ DPRINTF(" late assign fd % 5d:%p \n", entry->fd_entry, entry); -+ } -+ -+ if (entry->plt) -+ { -+ /* We use the section's raw size to mark the location of the -+ next PLT entry. */ -+ entry->plt_entry = dinfo->current_plt; -+ entry->plt_trampoline_entry = dinfo->current_plt_trampoline; -+ dinfo->current_plt_trampoline += PLT_TRAMPOLINE_SIZE; -+ -+ if (entry->fd_entry >= (-512)) -+ { -+ /* This entry is going to be of type seq2 */ -+ dinfo->current_plt += LZPLT_SIZE_SEQ2; -+ entry->plt_type = 2; -+ } -+ else -+ { -+ /* This entry is going to be of type seq1 */ -+ dinfo->current_plt += LZPLT_SIZE_SEQ1; -+ entry->plt_type = 1; -+ } -+ DPRINTF(" assign plt % 4d for fd=% 4d:%p next %d plttype %d\n", entry->plt_entry, entry->fd_entry, entry, dinfo->current_plt, entry->plt_type); -+ -+ } -+ -+ return 1; -+} -+ -+/* Assign GOT offsets for every GOT entry and function descriptor. -+ Doing everything in a single pass is tricky. */ -+static int -+ubicom32fdpic_assign_got_entries (void **entryp, void *info_) -+{ -+ struct ubicom32fdpic_relocs_info *entry = *entryp; -+ struct ubicom32fdpic_dynamic_got_plt_info *dinfo = info_; -+ -+ if (entry->gotoffset_lo || entry->gotoffset_hi) -+ { -+ entry->got_entry = dinfo->current_got; -+ DPRINTF(" assign got % 5d:%p \n", entry->got_entry, entry); -+ dinfo->current_got += 4; -+ } -+ -+ if (entry->fd_gotoffset_lo || entry->fd_gotoffset_hi) -+ { -+ entry->fdgot_entry = dinfo->current_got; -+ DPRINTF(" assign fdgot % 5d:%p \n", entry->fdgot_entry, entry); -+ dinfo->current_got += 4; -+ } -+ -+ if (entry->plt) -+ { -+ dinfo->current_fd -= FUNCTION_DESCRIPTOR_SIZE; -+ entry->fd_entry = dinfo->current_fd; -+ -+ dinfo->total_trampoline += PLT_TRAMPOLINE_SIZE; -+ -+ if (entry->fd_entry >= (-512)) -+ { -+ /* This entry is going to be of type seq2 */ -+ dinfo->total_lzplt += LZPLT_SIZE_SEQ2; -+ entry->plt_type = 2; -+ } -+ else -+ { -+ /* This entry is going to be of type seq1 */ -+ dinfo->total_lzplt += LZPLT_SIZE_SEQ1; -+ entry->plt_type = 1; -+ } -+ -+ DPRINTF(" assign fd % 5d:%p \n", entry->fd_entry, entry); -+ } -+ else if (entry->privfd) -+ { -+ dinfo->current_privfd -= FUNCTION_DESCRIPTOR_SIZE; -+ entry->fd_entry = dinfo->current_privfd; -+ DPRINTF(" assign private fd % 5d:%p %p \n", entry->fd_entry, entry, entry->plt); -+ } -+ -+ return 1; -+} -+ -+/* Set the sizes of the dynamic sections. */ -+ -+static bfd_boolean -+ubicom32fdpic_elf_size_dynamic_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *s; -+ struct ubicom32fdpic_dynamic_got_plt_info gpinfo; -+ bfd_vma total_plt_size; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ BFD_ASSERT (dynobj != NULL); -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ /* Set the contents of the .interp section to the interpreter. */ -+ if (info->executable) -+ { -+ s = bfd_get_section_by_name (dynobj, ".interp"); -+ BFD_ASSERT (s != NULL); -+ s->size = sizeof ELF_DYNAMIC_INTERPRETER; -+ s->contents = (bfd_byte *) ELF_DYNAMIC_INTERPRETER; -+ } -+ } -+ -+ memset (&gpinfo, 0, sizeof (gpinfo)); -+ gpinfo.g.info = info; -+ -+ for (;;) -+ { -+ htab_t relocs = ubicom32fdpic_relocs_info (info); -+ -+ htab_traverse (relocs, ubicom32fdpic_resolve_final_relocs_info, &relocs); -+ -+ if (relocs == ubicom32fdpic_relocs_info (info)) -+ break; -+ } -+ -+ htab_traverse (ubicom32fdpic_relocs_info (info), ubicom32fdpic_count_got_plt_entries, -+ &gpinfo.g); -+ -+ /* At this point we know how many PLT entries we need. We know how many got entries we need and the total number of function descriptors in this link. */ -+ gpinfo.total_fdplt = gpinfo.g.fdplt + gpinfo.g.privfdplt; -+ gpinfo.total_got = gpinfo.g.gotoffset_lo; -+ gpinfo.total_lzplt = 0; -+ -+ gpinfo.current_got = 12; /* The first 12 bytes are reserved to get to resolver. */ -+ gpinfo.current_fd = 0; /* We will decrement this by FUNCTION_DESCRIPTOR_SIZE for each allocation. */ -+ gpinfo.current_privfd = -gpinfo.g.fdplt; /* We will decrement this by FUNCTION_DESCRIPTOR_SIZE for each allocation. */ -+ gpinfo.current_plt = 0; /* Initialize this to 0. The trampoline code is at the start of the plt section. -+ We will decrement this by LZPLT_NORMAL_SIZE each time we allocate. */ -+ gpinfo.current_plt_trampoline = 0; -+ -+ DPRINTF("Total plts = %d \n", gpinfo.g.num_plts); -+ -+ /* Now assign (most) GOT offsets. */ -+ htab_traverse (ubicom32fdpic_relocs_info (info), ubicom32fdpic_assign_got_entries, -+ &gpinfo); -+ -+ -+ ubicom32fdpic_got_section (info)->size = gpinfo.total_fdplt + gpinfo.total_got + 12; -+ -+ DPRINTF("GOT size = fd=%d, got=%d\n", gpinfo.total_fdplt, gpinfo.total_got); -+ -+ if (ubicom32fdpic_got_section (info)->size == 0) -+ ubicom32fdpic_got_section (info)->flags |= SEC_EXCLUDE; -+ else if (ubicom32fdpic_got_section (info)->size == 12 -+ && ! elf_hash_table (info)->dynamic_sections_created) -+ { -+ ubicom32fdpic_got_section (info)->flags |= SEC_EXCLUDE; -+ ubicom32fdpic_got_section (info)->size = 0; -+ } -+ else -+ { -+ DPRINTF(" Alloc GOT size = %d\n", ubicom32fdpic_got_section (info)->size); -+ ubicom32fdpic_got_section (info)->contents = -+ (bfd_byte *) bfd_zalloc (dynobj, -+ ubicom32fdpic_got_section (info)->size); -+ if (ubicom32fdpic_got_section (info)->contents == NULL) -+ return FALSE; -+ } -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ /* Subtract the number of lzplt entries, since those will generate -+ relocations in the pltrel section. */ -+ ubicom32fdpic_gotrel_section (info)->size = -+ (gpinfo.g.relocs - gpinfo.g.num_plts) -+ * get_elf_backend_data (output_bfd)->s->sizeof_rel; -+ else -+ BFD_ASSERT (gpinfo.g.relocs == 0); -+ if (ubicom32fdpic_gotrel_section (info)->size == 0) -+ ubicom32fdpic_gotrel_section (info)->flags |= SEC_EXCLUDE; -+ else -+ { -+ ubicom32fdpic_gotrel_section (info)->contents = -+ (bfd_byte *) bfd_zalloc (dynobj, -+ ubicom32fdpic_gotrel_section (info)->size); -+ if (ubicom32fdpic_gotrel_section (info)->contents == NULL) -+ return FALSE; -+ } -+ -+ ubicom32fdpic_gotfixup_section (info)->size = (gpinfo.g.fixups + 1) * 4; -+ if (ubicom32fdpic_gotfixup_section (info)->size == 0) -+ ubicom32fdpic_gotfixup_section (info)->flags |= SEC_EXCLUDE; -+ else -+ { -+ ubicom32fdpic_gotfixup_section (info)->contents = -+ (bfd_byte *) bfd_zalloc (dynobj, -+ ubicom32fdpic_gotfixup_section (info)->size); -+ if (ubicom32fdpic_gotfixup_section (info)->contents == NULL) -+ return FALSE; -+ } -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ ubicom32fdpic_pltrel_section (info)->size = -+ gpinfo.g.num_plts * get_elf_backend_data (output_bfd)->s->sizeof_rel; -+ if (ubicom32fdpic_pltrel_section (info)->size == 0) -+ ubicom32fdpic_pltrel_section (info)->flags |= SEC_EXCLUDE; -+ else -+ { -+ ubicom32fdpic_pltrel_section (info)->contents = -+ (bfd_byte *) bfd_zalloc (dynobj, -+ ubicom32fdpic_pltrel_section (info)->size); -+ if (ubicom32fdpic_pltrel_section (info)->contents == NULL) -+ return FALSE; -+ } -+ } -+ -+ /* The Pltsection is g.lzplt . The 4 is for the trampoline code. */ -+ total_plt_size = gpinfo.total_lzplt + gpinfo.total_trampoline; -+ gpinfo.current_plt_trampoline = gpinfo.total_lzplt; -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ DPRINTF(" PLT size = %d\n", (total_plt_size )); -+ ubicom32fdpic_plt_section (info)->size = (total_plt_size); -+ } -+ -+ /* Save information that we're going to need to generate GOT and PLT -+ entries. */ -+ ubicom32fdpic_got_initial_offset (info) = gpinfo.total_fdplt; -+ -+ if (get_elf_backend_data (output_bfd)->want_got_sym) -+ elf_hash_table (info)->hgot->root.u.def.value -+ += ubicom32fdpic_got_initial_offset (info); -+ -+ /* Allocate the PLT section contents. */ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ if (ubicom32fdpic_plt_section (info)->size == 4) -+ { -+ ubicom32fdpic_plt_section (info)->flags |= SEC_EXCLUDE; -+ ubicom32fdpic_plt_section (info)->size = 0; -+ } -+ else -+ { -+ DPRINTF(" Alloc PLT size = %d\n", (total_plt_size)); -+ ubicom32fdpic_plt_section (info)->contents = -+ (bfd_byte *) bfd_zalloc (dynobj, -+ ubicom32fdpic_plt_section (info)->size); -+ if (ubicom32fdpic_plt_section (info)->contents == NULL) -+ return FALSE; -+ } -+ } -+ -+ -+ htab_traverse (ubicom32fdpic_relocs_info (info), ubicom32fdpic_assign_plt_entries, -+ &gpinfo); -+ -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ if (ubicom32fdpic_got_section (info)->size) -+ if (!_bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0)) -+ return FALSE; -+ -+ if (ubicom32fdpic_pltrel_section (info)->size) -+ if (!_bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0) -+ || !_bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_REL) -+ || !_bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0)) -+ return FALSE; -+ -+ if (ubicom32fdpic_gotrel_section (info)->size) -+ if (!_bfd_elf_add_dynamic_entry (info, DT_REL, 0) -+ || !_bfd_elf_add_dynamic_entry (info, DT_RELSZ, 0) -+ || !_bfd_elf_add_dynamic_entry (info, DT_RELENT, -+ sizeof (Elf32_External_Rel))) -+ return FALSE; -+ } -+ -+ s = bfd_get_section_by_name (dynobj, ".rela.bss"); -+ if (s && s->size == 0) -+ s->flags |= SEC_EXCLUDE; -+ -+ s = bfd_get_section_by_name (dynobj, ".rel.plt"); -+ if (s && s->size == 0) -+ s->flags |= SEC_EXCLUDE; -+ -+ return TRUE; -+} -+ -+ -+/* Adjust a symbol defined by a dynamic object and referenced by a -+ regular object. */ -+ -+static bfd_boolean -+ubicom32fdpic_elf_adjust_dynamic_symbol -+(struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ struct elf_link_hash_entry *h ATTRIBUTE_UNUSED) -+{ -+ bfd * dynobj; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ -+ /* Make sure we know what is going on here. */ -+ BFD_ASSERT (dynobj != NULL -+ && (h->u.weakdef != NULL -+ || (h->def_dynamic -+ && h->ref_regular -+ && !h->def_regular))); -+ -+ /* If this is a weak symbol, and there is a real definition, the -+ processor independent code will have arranged for us to see the -+ real definition first, and we can just use the same value. */ -+ if (h->u.weakdef != NULL) -+ { -+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined -+ || h->u.weakdef->root.type == bfd_link_hash_defweak); -+ h->root.u.def.section = h->u.weakdef->root.u.def.section; -+ h->root.u.def.value = h->u.weakdef->root.u.def.value; -+ } -+ -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32fdpic_elf_always_size_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ if (!info->relocatable) -+ { -+ struct elf_link_hash_entry *h; -+ -+ /* Force a PT_GNU_STACK segment to be created. */ -+ if (! elf_tdata (output_bfd)->stack_flags) -+ elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X; -+ -+ /* Define __stacksize if it's not defined yet. */ -+ h = elf_link_hash_lookup (elf_hash_table (info), "__stacksize", -+ FALSE, FALSE, FALSE); -+ if (! h || h->root.type != bfd_link_hash_defined -+ || h->type != STT_OBJECT -+ || !h->def_regular) -+ { -+ struct bfd_link_hash_entry *bh = NULL; -+ -+ if (!(_bfd_generic_link_add_one_symbol -+ (info, output_bfd, "__stacksize", -+ BSF_GLOBAL, bfd_abs_section_ptr, DEFAULT_STACK_SIZE, -+ (const char *) NULL, FALSE, -+ get_elf_backend_data (output_bfd)->collect, &bh))) -+ return FALSE; -+ -+ h = (struct elf_link_hash_entry *) bh; -+ h->def_regular = 1; -+ h->type = STT_OBJECT; -+ } -+ } -+ -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32fdpic_elf_finish_dynamic_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *sdyn; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ -+ if (ubicom32fdpic_got_section (info)) -+ { -+ BFD_ASSERT (ubicom32fdpic_gotrel_section (info)->size -+ == (ubicom32fdpic_gotrel_section (info)->reloc_count -+ * sizeof (Elf32_External_Rel))); -+ -+ if (ubicom32fdpic_gotfixup_section (info)) -+ { -+ struct elf_link_hash_entry *hgot = elf_hash_table (info)->hgot; -+ bfd_vma got_value = hgot->root.u.def.value -+ + hgot->root.u.def.section->output_section->vma -+ + hgot->root.u.def.section->output_offset; -+ -+ ubicom32fdpic_add_rofixup (output_bfd, ubicom32fdpic_gotfixup_section (info), -+ got_value, 0); -+ -+ if (ubicom32fdpic_gotfixup_section (info)->size -+ != (ubicom32fdpic_gotfixup_section (info)->reloc_count * 4)) -+ { -+ (*_bfd_error_handler) -+ ("LINKER BUG: .rofixup section size mismatch Size %d, should be %d ", -+ ubicom32fdpic_gotfixup_section (info)->size, ubicom32fdpic_gotfixup_section (info)->reloc_count * 4); -+ return FALSE; -+ } -+ } -+ } -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ BFD_ASSERT (ubicom32fdpic_pltrel_section (info)->size -+ == (ubicom32fdpic_pltrel_section (info)->reloc_count -+ * sizeof (Elf32_External_Rel))); -+ } -+ -+ sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ Elf32_External_Dyn * dyncon; -+ Elf32_External_Dyn * dynconend; -+ -+ BFD_ASSERT (sdyn != NULL); -+ -+ dyncon = (Elf32_External_Dyn *) sdyn->contents; -+ dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); -+ -+ for (; dyncon < dynconend; dyncon++) -+ { -+ Elf_Internal_Dyn dyn; -+ -+ bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); -+ -+ switch (dyn.d_tag) -+ { -+ default: -+ break; -+ -+ case DT_PLTGOT: -+ dyn.d_un.d_ptr = ubicom32fdpic_got_section (info)->output_section->vma -+ + ubicom32fdpic_got_section (info)->output_offset -+ + ubicom32fdpic_got_initial_offset (info); -+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); -+ break; -+ -+ case DT_JMPREL: -+ dyn.d_un.d_ptr = ubicom32fdpic_pltrel_section (info) -+ ->output_section->vma -+ + ubicom32fdpic_pltrel_section (info)->output_offset; -+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); -+ break; -+ -+ case DT_PLTRELSZ: -+ dyn.d_un.d_val = ubicom32fdpic_pltrel_section (info)->size; -+ bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); -+ break; -+ } -+ } -+ } -+ -+ return TRUE; -+} -+ -+/* Perform any actions needed for dynamic symbols. */ -+static bfd_boolean -+ubicom32fdpic_elf_finish_dynamic_symbol -+(bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ struct elf_link_hash_entry *h ATTRIBUTE_UNUSED, -+ Elf_Internal_Sym *sym ATTRIBUTE_UNUSED) -+{ -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32fdpic_elf_modify_program_headers (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ struct elf_obj_tdata *tdata = elf_tdata (output_bfd); -+ struct elf_segment_map *m; -+ Elf_Internal_Phdr *p; -+ -+ if (! info) -+ return TRUE; -+ -+ for (p = tdata->phdr, m = tdata->segment_map; m != NULL; m = m->next, p++) -+ if (m->p_type == PT_GNU_STACK) -+ break; -+ -+ if (m) -+ { -+ struct elf_link_hash_entry *h; -+ -+ /* Obtain the pointer to the __stacksize symbol. */ -+ h = elf_link_hash_lookup (elf_hash_table (info), "__stacksize", -+ FALSE, FALSE, FALSE); -+ if (h) -+ { -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ BFD_ASSERT (h->root.type == bfd_link_hash_defined); -+ } -+ -+ /* Set the header p_memsz from the symbol value. We -+ intentionally ignore the symbol section. */ -+ if (h && h->root.type == bfd_link_hash_defined) -+ p->p_memsz = h->root.u.def.value; -+ else -+ p->p_memsz = DEFAULT_STACK_SIZE; -+ -+ p->p_align = 8; -+ } -+ -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32fdpic_elf_gc_sweep_hook (bfd *abfd, -+ struct bfd_link_info *info, -+ asection *sec, -+ const Elf_Internal_Rela *relocs) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; -+ const Elf_Internal_Rela *rel; -+ const Elf_Internal_Rela *rel_end; -+ struct ubicom32fdpic_relocs_info *picrel; -+ -+ BFD_ASSERT (IS_FDPIC (abfd)); -+ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (abfd); -+ sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym); -+ if (!elf_bad_symtab (abfd)) -+ sym_hashes_end -= symtab_hdr->sh_info; -+ -+ rel_end = relocs + sec->reloc_count; -+ for (rel = relocs; rel < rel_end; rel++) -+ { -+ struct elf_link_hash_entry *h; -+ unsigned long r_symndx; -+ -+ r_symndx = ELF32_R_SYM (rel->r_info); -+ if (r_symndx < symtab_hdr->sh_info) -+ h = NULL; -+ else -+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; -+ -+ if (h != NULL) -+ picrel = ubicom32fdpic_relocs_info_for_global (ubicom32fdpic_relocs_info (info), -+ abfd, h, -+ rel->r_addend, NO_INSERT); -+ else -+ picrel = ubicom32fdpic_relocs_info_for_local (ubicom32fdpic_relocs_info -+ (info), abfd, r_symndx, -+ rel->r_addend, NO_INSERT); -+ -+ if (!picrel) -+ continue; -+ -+ switch (ELF32_R_TYPE (rel->r_info)) -+ { -+ case R_UBICOM32_24_PCREL: -+ picrel->call--; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_VALUE: -+ picrel->relocsfdv--; -+ picrel->sym--; -+ break; -+ -+ case R_UBICOM32_GOTOFFSET_LO: -+ picrel->gotoffset_lo--; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ picrel->fd_gotoffset_lo--; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_HI: -+ picrel->fd_gotoffset_hi--; -+ break; -+ -+ case R_UBICOM32_FUNCDESC: -+ picrel->fd--; -+ picrel->relocsfd--; -+ break; -+ -+ case R_UBICOM32_32: -+ if (! IS_FDPIC (abfd)) -+ break; -+ -+ if (picrel->sym) -+ picrel->relocs32--;; -+ -+ picrel->sym--; -+ break; -+ -+ default: -+ break; -+ } -+ } -+ -+ return TRUE; -+} -+/* Decide whether to attempt to turn absptr or lsda encodings in -+ shared libraries into pcrel within the given input section. */ -+ -+static bfd_boolean -+ubicom32fdpic_elf_use_relative_eh_frame -+(bfd *input_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ asection *eh_frame_section ATTRIBUTE_UNUSED) -+{ -+ /* We can't use PC-relative encodings in FDPIC binaries, in general. */ -+ return FALSE; -+} -+ -+/* Adjust the contents of an eh_frame_hdr section before they're output. */ -+ -+static bfd_byte -+ubicom32fdpic_elf_encode_eh_address (bfd *abfd, -+ struct bfd_link_info *info, -+ asection *osec, bfd_vma offset, -+ asection *loc_sec, bfd_vma loc_offset, -+ bfd_vma *encoded) -+{ -+ struct elf_link_hash_entry *h; -+ -+ h = elf_hash_table (info)->hgot; -+ BFD_ASSERT (h && h->root.type == bfd_link_hash_defined); -+ -+ if (! h || (ubicom32fdpic_osec_to_segment (abfd, osec) -+ == ubicom32fdpic_osec_to_segment (abfd, loc_sec->output_section))) -+ return _bfd_elf_encode_eh_address (abfd, info, osec, offset, -+ loc_sec, loc_offset, encoded); -+ -+ BFD_ASSERT (ubicom32fdpic_osec_to_segment (abfd, osec) -+ == (ubicom32fdpic_osec_to_segment -+ (abfd, h->root.u.def.section->output_section))); -+ -+ *encoded = osec->vma + offset -+ - (h->root.u.def.value -+ + h->root.u.def.section->output_section->vma -+ + h->root.u.def.section->output_offset); -+ -+ return DW_EH_PE_datarel | DW_EH_PE_sdata4; -+} -+static bfd_boolean -+ubicom32fdpic_elf_copy_private_bfd_data (bfd *ibfd, bfd *obfd) -+{ -+ unsigned i; -+ -+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour -+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour) -+ return TRUE; -+ -+ if (! ubicom32_elf_copy_private_bfd_data (ibfd, obfd)) -+ return FALSE; -+ -+ if (! elf_tdata (ibfd) || ! elf_tdata (ibfd)->phdr -+ || ! elf_tdata (obfd) || ! elf_tdata (obfd)->phdr) -+ return TRUE; -+ -+ /* Copy the stack size. */ -+ for (i = 0; i < elf_elfheader (ibfd)->e_phnum; i++) -+ if (elf_tdata (ibfd)->phdr[i].p_type == PT_GNU_STACK) -+ { -+ Elf_Internal_Phdr *iphdr = &elf_tdata (ibfd)->phdr[i]; -+ -+ for (i = 0; i < elf_elfheader (obfd)->e_phnum; i++) -+ if (elf_tdata (obfd)->phdr[i].p_type == PT_GNU_STACK) -+ { -+ memcpy (&elf_tdata (obfd)->phdr[i], iphdr, sizeof (*iphdr)); -+ -+ /* Rewrite the phdrs, since we're only called after they -+ were first written. */ -+ if (bfd_seek (obfd, (bfd_signed_vma) get_elf_backend_data (obfd) -+ ->s->sizeof_ehdr, SEEK_SET) != 0 -+ || get_elf_backend_data (obfd)->s -+ ->write_out_phdrs (obfd, elf_tdata (obfd)->phdr, -+ elf_elfheader (obfd)->e_phnum) != 0) -+ return FALSE; -+ break; -+ } -+ -+ break; -+ } -+ -+ return TRUE; -+} -+ -+static bfd_boolean -+ubicom32fdpic_elf_relocate_section (bfd * output_bfd, -+ struct bfd_link_info *info, -+ bfd * input_bfd, -+ asection * input_section, -+ bfd_byte * contents, -+ Elf_Internal_Rela * relocs, -+ Elf_Internal_Sym * local_syms, -+ asection ** local_sections) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes; -+ Elf_Internal_Rela *rel; -+ Elf_Internal_Rela *relend; -+ unsigned isec_segment, got_segment, plt_segment, -+ check_segment[2]; -+ int silence_segment_error = !(info->shared || info->pie); -+ -+ if (info->relocatable) -+ return TRUE; -+ -+ symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (input_bfd); -+ relend = relocs + input_section->reloc_count; -+ -+ isec_segment = ubicom32fdpic_osec_to_segment (output_bfd, -+ input_section->output_section); -+ if (IS_FDPIC (output_bfd) && ubicom32fdpic_got_section (info)) -+ got_segment = ubicom32fdpic_osec_to_segment (output_bfd, -+ ubicom32fdpic_got_section (info) -+ ->output_section); -+ else -+ got_segment = -1; -+ if (IS_FDPIC (output_bfd) && elf_hash_table (info)->dynamic_sections_created) -+ plt_segment = ubicom32fdpic_osec_to_segment (output_bfd, -+ ubicom32fdpic_plt_section (info) -+ ->output_section); -+ else -+ plt_segment = -1; -+ -+ for (rel = relocs; rel < relend; rel ++) -+ { -+ reloc_howto_type *howto; -+ unsigned long r_symndx; -+ Elf_Internal_Sym *sym; -+ asection *sec; -+ struct elf_link_hash_entry *h; -+ bfd_vma relocation; -+ bfd_reloc_status_type r; -+ const char * name = NULL; -+ int r_type; -+ asection *osec; -+ struct ubicom32fdpic_relocs_info *picrel; -+ bfd_vma orig_addend = rel->r_addend; -+ -+ r_type = ELF32_R_TYPE (rel->r_info); -+ -+ if (r_type == R_UBICOM32_GNU_VTINHERIT -+ || r_type == R_UBICOM32_GNU_VTENTRY) -+ continue; -+ -+ /* This is a final link. */ -+ r_symndx = ELF32_R_SYM (rel->r_info); -+ -+ //howto = ubicom32_reloc_type_lookup (input_bfd, r_type); -+ howto = ubicom32_elf_howto_table + ELF32_R_TYPE (rel->r_info); -+ if (howto == NULL) -+ { -+ bfd_set_error (bfd_error_bad_value); -+ return FALSE; -+ } -+ -+ h = NULL; -+ sym = NULL; -+ sec = NULL; -+ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ sym = local_syms + r_symndx; -+ osec = sec = local_sections [r_symndx]; -+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); -+ -+ name = bfd_elf_string_from_elf_section -+ (input_bfd, symtab_hdr->sh_link, sym->st_name); -+ name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; -+ } -+ else -+ { -+ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; -+ -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ name = h->root.root.string; -+ -+ if ((h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ && ! UBICOM32FDPIC_SYM_LOCAL (info, h)) -+ { -+ sec = NULL; -+ relocation = 0; -+ } -+ else -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ { -+ sec = h->root.u.def.section; -+ relocation = (h->root.u.def.value -+ + sec->output_section->vma -+ + sec->output_offset); -+ } -+ else if (h->root.type == bfd_link_hash_undefweak) -+ { -+ relocation = 0; -+ } -+ else if (info->unresolved_syms_in_objects == RM_IGNORE -+ && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT) -+ relocation = 0; -+ else -+ { -+ if (! ((*info->callbacks->undefined_symbol) -+ (info, h->root.root.string, input_bfd, -+ input_section, rel->r_offset, -+ (info->unresolved_syms_in_objects == RM_GENERATE_ERROR -+ || ELF_ST_VISIBILITY (h->other))))) -+ return FALSE; -+ relocation = 0; -+ } -+ osec = sec; -+ } -+ -+ switch (r_type) -+ { -+ case R_UBICOM32_24_PCREL: -+ case R_UBICOM32_32: -+ if (! IS_FDPIC (output_bfd)) -+ goto non_fdpic; -+ -+ case R_UBICOM32_FUNCDESC_VALUE: -+ case R_UBICOM32_FUNCDESC: -+ case R_UBICOM32_GOTOFFSET_LO: -+ case R_UBICOM32_GOTOFFSET_HI: -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_HI: -+ if (h != NULL) -+ picrel = ubicom32fdpic_relocs_info_for_global (ubicom32fdpic_relocs_info -+ (info), input_bfd, h, -+ orig_addend, INSERT); -+ else -+ /* In order to find the entry we created before, we must -+ use the original addend, not the one that may have been -+ modified by _bfd_elf_rela_local_sym(). */ -+ picrel = ubicom32fdpic_relocs_info_for_local (ubicom32fdpic_relocs_info -+ (info), input_bfd, r_symndx, -+ orig_addend, INSERT); -+ if (! picrel) -+ return FALSE; -+ -+ if (!ubicom32fdpic_emit_got_relocs_plt_entries (picrel, output_bfd, info, -+ osec, sym, -+ rel->r_addend)) -+ { -+ (*_bfd_error_handler) -+ (_("%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend"), -+ input_bfd, input_section, rel->r_offset, name); -+ return FALSE; -+ -+ } -+ -+ break; -+ case R_UBICOM32_21_PCREL: -+ case R_UBICOM32_HI24: -+ case R_UBICOM32_LO7_S: -+ //printf("Seeing this stuff Don;t know what to do. r_type %d r_symndx %d %s %s\n", r_type, r_symndx, input_bfd->filename, input_section->name); -+ break; -+ -+ default: -+ non_fdpic: -+ picrel = NULL; -+ //printf("h = 0x%x %d\n", h, UBICOM32FDPIC_SYM_LOCAL (info, h)); -+ if (h && ! UBICOM32FDPIC_SYM_LOCAL (info, h)) -+ { -+ printf("h = 0x%x %d\n", h, UBICOM32FDPIC_SYM_LOCAL (info, h)); -+ printf("Seeing this stuff. r_type %d r_symndx %d %s %s\n", r_type, r_symndx, input_bfd->filename, input_section->name); -+ info->callbacks->warning -+ (info, _("relocation references symbol not defined in the module"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ break; -+ } -+ -+ switch (r_type) -+ { -+ case R_UBICOM32_21_PCREL: -+ case R_UBICOM32_HI24: -+ case R_UBICOM32_LO7_S: -+ //printf("Seeing this stuff. r_type %d r_symndx %d %s %s\n", r_type, r_symndx, input_bfd->filename, input_section->name); -+ check_segment[0] = check_segment[1] = got_segment; -+ break; -+ -+ case R_UBICOM32_24_PCREL: -+ check_segment[0] = isec_segment; -+ if (! IS_FDPIC (output_bfd)) -+ check_segment[1] = isec_segment; -+ else if (picrel->plt) -+ { -+ relocation = ubicom32fdpic_plt_section (info)->output_section->vma -+ + ubicom32fdpic_plt_section (info)->output_offset -+ + picrel->plt_entry; -+ -+ /* subtract rel->addend. This will get added back in the 23pcrel howto routine. */ -+ relocation -= rel->r_addend; -+ -+ check_segment[1] = plt_segment; -+ } -+ /* We don't want to warn on calls to undefined weak symbols, -+ as calls to them must be protected by non-NULL tests -+ anyway, and unprotected calls would invoke undefined -+ behavior. */ -+ else if (picrel->symndx == -1 -+ && picrel->d.h->root.type == bfd_link_hash_undefweak) -+ check_segment[1] = check_segment[0]; -+ else -+ check_segment[1] = sec -+ ? ubicom32fdpic_osec_to_segment (output_bfd, sec->output_section) -+ : (unsigned)-1; -+ break; -+ -+ case R_UBICOM32_GOTOFFSET_LO: -+ relocation = picrel->got_entry >> 2; -+ check_segment[0] = check_segment[1] = got_segment; -+ break; -+ -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ relocation = picrel->fdgot_entry >> 2; -+ check_segment[0] = check_segment[1] = got_segment; -+ break; -+ -+ case R_UBICOM32_FUNCDESC: -+ { -+ int dynindx; -+ bfd_vma addend = rel->r_addend; -+ -+ if (! (h && h->root.type == bfd_link_hash_undefweak -+ && UBICOM32FDPIC_SYM_LOCAL (info, h))) -+ { -+ /* If the symbol is dynamic and there may be dynamic -+ symbol resolution because we are or are linked with a -+ shared library, emit a FUNCDESC relocation such that -+ the dynamic linker will allocate the function -+ descriptor. If the symbol needs a non-local function -+ descriptor but binds locally (e.g., its visibility is -+ protected, emit a dynamic relocation decayed to -+ section+offset. */ -+ if (h && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, h) -+ && UBICOM32FDPIC_SYM_LOCAL (info, h) -+ && !(info->executable && !info->pie)) -+ { -+ dynindx = elf_section_data (h->root.u.def.section -+ ->output_section)->dynindx; -+ addend += h->root.u.def.section->output_offset -+ + h->root.u.def.value; -+ } -+ else if (h && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, h)) -+ { -+ if (addend) -+ { -+ info->callbacks->warning -+ (info, _("R_UBICOM32_FUNCDESC references dynamic symbol with nonzero addend"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ dynindx = h->dynindx; -+ } -+ else -+ { -+ /* Otherwise, we know we have a private function -+ descriptor, so reference it directly. */ -+ BFD_ASSERT (picrel->privfd); -+ r_type = R_UBICOM32_32; // was FUNCDESC but bfin uses 32 bit -+ dynindx = elf_section_data (ubicom32fdpic_got_section (info) -+ ->output_section)->dynindx; -+ addend = ubicom32fdpic_got_section (info)->output_offset -+ + ubicom32fdpic_got_initial_offset (info) -+ + picrel->fd_entry; -+ } -+ -+ /* If there is room for dynamic symbol resolution, emit -+ the dynamic relocation. However, if we're linking an -+ executable at a fixed location, we won't have emitted a -+ dynamic symbol entry for the got section, so idx will -+ be zero, which means we can and should compute the -+ address of the private descriptor ourselves. */ -+ if (info->executable && !info->pie -+ && (!h || UBICOM32FDPIC_FUNCDESC_LOCAL (info, h))) -+ { -+ addend += ubicom32fdpic_got_section (info)->output_section->vma; -+ if ((bfd_get_section_flags (output_bfd, -+ input_section->output_section) -+ & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD)) -+ { -+ if (ubicom32fdpic_osec_readonly_p (output_bfd, -+ input_section -+ ->output_section)) -+ { -+ info->callbacks->warning -+ (info, -+ _("cannot emit fixups in read-only section"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section -+ (info), -+ _bfd_elf_section_offset -+ (output_bfd, info, -+ input_section, rel->r_offset) -+ + input_section -+ ->output_section->vma -+ + input_section->output_offset, -+ picrel); -+ } -+ } -+ else if ((bfd_get_section_flags (output_bfd, -+ input_section->output_section) -+ & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD)) -+ { -+ bfd_vma offset; -+ -+ if (ubicom32fdpic_osec_readonly_p (output_bfd, -+ input_section -+ ->output_section)) -+ { -+ info->callbacks->warning -+ (info, -+ _("cannot emit dynamic relocations in read-only section"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ offset = _bfd_elf_section_offset (output_bfd, info, -+ input_section, rel->r_offset); -+ /* Only output a reloc for a not deleted entry. */ -+ if (offset >= (bfd_vma) -2) -+ ubicom32fdpic_add_dyn_reloc (output_bfd, -+ ubicom32fdpic_gotrel_section (info), -+ 0, -+ R_UBICOM32_NONE, -+ dynindx, addend, picrel); -+ else -+ ubicom32fdpic_add_dyn_reloc (output_bfd, -+ ubicom32fdpic_gotrel_section (info), -+ offset + input_section -+ ->output_section->vma -+ + input_section->output_offset, -+ r_type, -+ dynindx, addend, picrel); -+ } -+ else -+ addend += ubicom32fdpic_got_section (info)->output_section->vma; -+ } -+ -+ /* We want the addend in-place because dynamic -+ relocations are REL. Setting relocation to it should -+ arrange for it to be installed. */ -+ relocation = addend - rel->r_addend; -+ } -+ check_segment[0] = check_segment[1] = got_segment; -+ break; -+ -+ case R_UBICOM32_32: -+ if (! IS_FDPIC (output_bfd)) -+ { -+ check_segment[0] = check_segment[1] = -1; -+ break; -+ } -+ /* Fall through. */ -+ case R_UBICOM32_FUNCDESC_VALUE: -+ { -+ int dynindx; -+ bfd_vma addend = rel->r_addend; -+ bfd_vma offset; -+ offset = _bfd_elf_section_offset (output_bfd, info, -+ input_section, rel->r_offset); -+ -+ /* If the symbol is dynamic but binds locally, use -+ section+offset. */ -+ if (h && ! UBICOM32FDPIC_SYM_LOCAL (info, h)) -+ { -+ if (addend && r_type == R_UBICOM32_FUNCDESC_VALUE) -+ { -+ info->callbacks->warning -+ (info, _("R_UBICOM32_FUNCDESC_VALUE references dynamic symbol with nonzero addend"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ dynindx = h->dynindx; -+ } -+ else -+ { -+ if (h) -+ addend += h->root.u.def.value; -+ else -+ addend += sym->st_value; -+ if (osec) -+ addend += osec->output_offset; -+ if (osec && osec->output_section -+ && ! bfd_is_abs_section (osec->output_section) -+ && ! bfd_is_und_section (osec->output_section)) -+ dynindx = elf_section_data (osec->output_section)->dynindx; -+ else -+ dynindx = 0; -+ } -+ -+ /* If we're linking an executable at a fixed address, we -+ can omit the dynamic relocation as long as the symbol -+ is defined in the current link unit (which is implied -+ by its output section not being NULL). */ -+ if (info->executable && !info->pie -+ && (!h || UBICOM32FDPIC_SYM_LOCAL (info, h))) -+ { -+ if (osec) -+ addend += osec->output_section->vma; -+ if (IS_FDPIC (input_bfd) -+ && (bfd_get_section_flags (output_bfd, -+ input_section->output_section) -+ & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD)) -+ { -+ if (ubicom32fdpic_osec_readonly_p (output_bfd, -+ input_section -+ ->output_section)) -+ { -+ info->callbacks->warning -+ (info, -+ _("cannot emit fixups in read-only section"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ if (!h || h->root.type != bfd_link_hash_undefweak) -+ { -+ /* Only output a reloc for a not deleted entry. */ -+ if (offset >= (bfd_vma)-2) -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section -+ (info), -1, picrel); -+ else -+ ubicom32fdpic_add_rofixup (output_bfd, -+ ubicom32fdpic_gotfixup_section -+ (info), -+ offset + input_section -+ ->output_section->vma -+ + input_section->output_offset, -+ picrel); -+ -+ if (r_type == R_UBICOM32_FUNCDESC_VALUE) -+ { -+ if (offset >= (bfd_vma)-2) -+ ubicom32fdpic_add_rofixup -+ (output_bfd, -+ ubicom32fdpic_gotfixup_section (info), -+ -1, picrel); -+ else -+ ubicom32fdpic_add_rofixup -+ (output_bfd, -+ ubicom32fdpic_gotfixup_section (info), -+ offset + input_section->output_section->vma -+ + input_section->output_offset + 4, picrel); -+ } -+ } -+ } -+ } -+ else -+ { -+ if ((bfd_get_section_flags (output_bfd, -+ input_section->output_section) -+ & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD)) -+ { -+ if (ubicom32fdpic_osec_readonly_p (output_bfd, -+ input_section -+ ->output_section)) -+ { -+ info->callbacks->warning -+ (info, -+ _("cannot emit dynamic relocations in read-only section"), -+ name, input_bfd, input_section, rel->r_offset); -+ return FALSE; -+ } -+ /* Only output a reloc for a not deleted entry. */ -+ if (offset >= (bfd_vma)-2) -+ ubicom32fdpic_add_dyn_reloc (output_bfd, -+ ubicom32fdpic_gotrel_section (info), -+ 0, R_UBICOM32_NONE, dynindx, addend, picrel); -+ else -+ ubicom32fdpic_add_dyn_reloc (output_bfd, -+ ubicom32fdpic_gotrel_section (info), -+ offset -+ + input_section -+ ->output_section->vma -+ + input_section->output_offset, -+ r_type, dynindx, addend, picrel); -+ } -+ else if (osec) -+ addend += osec->output_section->vma; -+ /* We want the addend in-place because dynamic -+ relocations are REL. Setting relocation to it -+ should arrange for it to be installed. */ -+ relocation = addend - rel->r_addend; -+ } -+ -+ if (r_type == R_UBICOM32_FUNCDESC_VALUE && offset < (bfd_vma)-2) -+ { -+ /* If we've omitted the dynamic relocation, just emit -+ the fixed addresses of the symbol and of the local -+ GOT base offset. */ -+ if (info->executable && !info->pie -+ && (!h || UBICOM32FDPIC_SYM_LOCAL (info, h))) -+ bfd_put_32 (output_bfd, -+ ubicom32fdpic_got_section (info)->output_section->vma -+ + ubicom32fdpic_got_section (info)->output_offset -+ + ubicom32fdpic_got_initial_offset (info), -+ contents + rel->r_offset + 4); -+ else -+ /* A function descriptor used for lazy or local -+ resolving is initialized such that its high word -+ contains the output section index in which the -+ PLT entries are located, and the low word -+ contains the offset of the lazy PLT entry entry -+ point into that section. */ -+ bfd_put_32 (output_bfd, -+ h && ! UBICOM32FDPIC_SYM_LOCAL (info, h) -+ ? 0 -+ : ubicom32fdpic_osec_to_segment (output_bfd, -+ sec -+ ->output_section), -+ contents + rel->r_offset + 4); -+ } -+ } -+ check_segment[0] = check_segment[1] = got_segment; -+ break; -+ -+ default: -+ check_segment[0] = isec_segment; -+ check_segment[1] = sec -+ ? ubicom32fdpic_osec_to_segment (output_bfd, sec->output_section) -+ : (unsigned)-1; -+ break; -+ } -+ -+ if (check_segment[0] != check_segment[1] && IS_FDPIC (output_bfd)) -+ { -+#if 1 /* If you take this out, remove the #error from fdpic-static-6.d -+ in the ld testsuite. */ -+ /* This helps catch problems in GCC while we can't do more -+ than static linking. The idea is to test whether the -+ input file basename is crt0.o only once. */ -+ if (silence_segment_error == 1) -+ silence_segment_error = -+ (strlen (input_bfd->filename) == 6 -+ && strcmp (input_bfd->filename, "crt0.o") == 0) -+ || (strlen (input_bfd->filename) > 6 -+ && strcmp (input_bfd->filename -+ + strlen (input_bfd->filename) - 7, -+ "/crt0.o") == 0) -+ ? -1 : 0; -+#endif -+ if (!silence_segment_error -+ /* We don't want duplicate errors for undefined -+ symbols. */ -+ && !(picrel && picrel->symndx == -1 -+ && picrel->d.h->root.type == bfd_link_hash_undefined)) -+ info->callbacks->warning -+ (info, -+ (info->shared || info->pie) -+ ? _("relocations between different segments are not supported") -+ : _("warning: relocation references a different segment"), -+ name, input_bfd, input_section, rel->r_offset); -+ if (!silence_segment_error && (info->shared || info->pie)) -+ return FALSE; -+ elf_elfheader (output_bfd)->e_flags |= 0x80000000; -+ } -+ -+ switch (r_type) -+ { -+ case R_UBICOM32_LO16: -+ r = ubicom32_elf_relocate_lo16 (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_HI16: -+ r = ubicom32_elf_relocate_hi16 (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_HI24: -+ r = ubicom32_elf_relocate_hi24 (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_S: -+ r = ubicom32_elf_relocate_lo7_s (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_2_S: -+ r = ubicom32_elf_relocate_lo7_2_s (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_4_S: -+ r = ubicom32_elf_relocate_lo7_4_s (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_D: -+ r = ubicom32_elf_relocate_lo7_d (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_2_D: -+ r = ubicom32_elf_relocate_lo7_2_d (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_4_D: -+ r = ubicom32_elf_relocate_lo7_4_d (input_bfd, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_24_PCREL: -+ r = ubicom32_elf_relocate_pcrel24 (input_bfd, input_section, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_LO7_CALLI: -+ r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 7); -+ break; -+ -+ case R_UBICOM32_LO16_CALLI: -+ r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 18); -+ break; -+ -+ case R_UBICOM32_GOTOFFSET_LO: -+ r = ubicom32_elf_relocate_gotoffset_lo(input_bfd, input_section, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_FUNCDESC_GOTOFFSET_LO: -+ r = ubicom32_elf_relocate_funcdesc_gotoffset_lo(input_bfd, input_section, rel, contents, relocation); -+ break; -+ -+ case R_UBICOM32_32: -+ case R_UBICOM32_FUNCDESC: -+ /* relocation &= ~(0xff << 24); */ -+ /* FALLTHROUGH */ -+ -+ default: -+ r = ubicom32_final_link_relocate (howto, input_bfd, input_section, -+ contents, rel, relocation); -+ break; -+ } -+ } -+ -+ return TRUE; -+} -+ -+#define elf_info_to_howto ubicom32_info_to_howto_rela -+#define elf_info_to_howto_rel NULL -+ -+#define bfd_elf32_bfd_reloc_type_lookup ubicom32_reloc_type_lookup -+#define bfd_elf32_bfd_reloc_name_lookup ubicom32_reloc_name_lookup -+#define bfd_elf32_bfd_relax_section ubicom32_elf_relax_section -+ -+#define elf_backend_relocate_section ubicom32_elf_relocate_section -+#define elf_backend_gc_mark_hook ubicom32_elf_gc_mark_hook -+#define elf_backend_gc_sweep_hook ubicom32_elf_gc_sweep_hook -+#define elf_backend_check_relocs ubicom32_elf_check_relocs -+#define elf_backend_object_p ubicom32_elf_object_p -+ -+#define elf_backend_discard_info ubicom32_elf_discard_info -+ -+#define elf_backend_can_gc_sections 1 -+ -+#define bfd_elf32_bfd_set_private_flags ubicom32_elf_set_private_flags -+#define bfd_elf32_bfd_copy_private_bfd_data ubicom32_elf_copy_private_bfd_data -+#define bfd_elf32_bfd_merge_private_bfd_data ubicom32_elf_merge_private_bfd_data -+#define bfd_elf32_bfd_print_private_bfd_data ubicom32_elf_print_private_bfd_data -+ -+#define bfd_elf32_bfd_extcode_relax NULL -+ -+#define TARGET_BIG_SYM bfd_elf32_ubicom32_vec -+#define TARGET_BIG_NAME "elf32-ubicom32" -+ -+#define ELF_ARCH bfd_arch_ubicom32 -+#define ELF_MACHINE_CODE EM_UBICOM32 -+#define ELF_MAXPAGESIZE 0x1000 -+ -+#include "elf32-target.h" -+ -+#undef TARGET_BIG_SYM -+#define TARGET_BIG_SYM bfd_elf32_ubicom32fdpic_vec -+#undef TARGET_BIG_NAME -+#define TARGET_BIG_NAME "elf32-ubicom32fdpic" -+#undef elf32_bed -+#define elf32_bed elf32_ubicom32fdpic_bed -+ -+#undef elf_backend_relocate_section -+#define elf_backend_relocate_section ubicom32fdpic_elf_relocate_section -+ -+#undef elf_backend_check_relocs -+#define elf_backend_check_relocs ubicom32fdpic_elf_check_relocs -+ -+#undef elf_backend_gc_sweep_hook -+#define elf_backend_gc_sweep_hook ubicom32fdpic_elf_gc_sweep_hook -+#undef bfd_elf32_bfd_link_hash_table_create -+#define bfd_elf32_bfd_link_hash_table_create \ -+ ubicom32fdpic_elf_link_hash_table_create -+#undef elf_backend_always_size_sections -+#define elf_backend_always_size_sections \ -+ ubicom32fdpic_elf_always_size_sections -+#undef elf_backend_modify_program_headers -+#define elf_backend_modify_program_headers \ -+ ubicom32fdpic_elf_modify_program_headers -+#undef bfd_elf32_bfd_copy_private_bfd_data -+#define bfd_elf32_bfd_copy_private_bfd_data \ -+ ubicom32fdpic_elf_copy_private_bfd_data -+ -+#undef elf_backend_create_dynamic_sections -+#define elf_backend_create_dynamic_sections \ -+ ubicom32fdpic_elf_create_dynamic_sections -+#undef elf_backend_adjust_dynamic_symbol -+#define elf_backend_adjust_dynamic_symbol \ -+ ubicom32fdpic_elf_adjust_dynamic_symbol -+#undef elf_backend_size_dynamic_sections -+#define elf_backend_size_dynamic_sections \ -+ ubicom32fdpic_elf_size_dynamic_sections -+#undef elf_backend_finish_dynamic_symbol -+#define elf_backend_finish_dynamic_symbol \ -+ ubicom32fdpic_elf_finish_dynamic_symbol -+#undef elf_backend_finish_dynamic_sections -+#define elf_backend_finish_dynamic_sections \ -+ ubicom32fdpic_elf_finish_dynamic_sections -+ -+#undef elf_backend_can_make_relative_eh_frame -+#define elf_backend_can_make_relative_eh_frame \ -+ ubicom32fdpic_elf_use_relative_eh_frame -+#undef elf_backend_can_make_lsda_relative_eh_frame -+#define elf_backend_can_make_lsda_relative_eh_frame \ -+ ubicom32fdpic_elf_use_relative_eh_frame -+#undef elf_backend_encode_eh_address -+#define elf_backend_encode_eh_address \ -+ ubicom32fdpic_elf_encode_eh_address -+ -+#undef elf_backend_may_use_rel_p -+#define elf_backend_may_use_rel_p 1 -+#undef elf_backend_may_use_rela_p -+#define elf_backend_may_use_rela_p 1 -+/* We use REL for dynamic relocations only. */ -+#undef elf_backend_default_use_rela_p -+#define elf_backend_default_use_rela_p 1 -+ -+#undef elf_backend_omit_section_dynsym -+#define elf_backend_omit_section_dynsym ubicom32fdpic_elf_link_omit_section_dynsym -+ -+#undef elf_backend_can_refcount -+#define elf_backend_can_refcount 1 -+ -+#undef elf_backend_want_got_plt -+#define elf_backend_want_got_plt 0 -+ -+#undef elf_backend_plt_readonly -+#define elf_backend_plt_readonly 1 -+ -+#undef elf_backend_want_plt_sym -+#define elf_backend_want_plt_sym 1 -+ -+#undef elf_backend_got_header_size -+#define elf_backend_got_header_size 12 -+ -+#undef elf_backend_rela_normal -+#define elf_backend_rela_normal 1 -+ -+#include "elf32-target.h" ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -1689,6 +1689,39 @@ static const char *const bfd_reloc_code_ - "BFD_RELOC_IP2K_FR_OFFSET", - "BFD_RELOC_VPE4KMATH_DATA", - "BFD_RELOC_VPE4KMATH_INSN", -+ "BFD_RELOC_UBICOM32_21_PCREL", -+ "BFD_RELOC_UBICOM32_24_PCREL", -+ "BFD_RELOC_UBICOM32_HI24", -+ "BFD_RELOC_UBICOM32_LO7_S", -+ "BFD_RELOC_UBICOM32_LO7_2_S", -+ "BFD_RELOC_UBICOM32_LO7_4_S", -+ "BFD_RELOC_UBICOM32_LO7_D", -+ "BFD_RELOC_UBICOM32_LO7_2_D", -+ "BFD_RELOC_UBICOM32_LO7_4_D", -+ "BFD_RELOC_UBICOM32_LO7_CALLI", -+ "BFD_RELOC_UBICOM32_LO16_CALLI", -+ "BFD_RELOC_UBICOM32_GOT_HI24", -+ "BFD_RELOC_UBICOM32_GOT_LO7_S", -+ "BFD_RELOC_UBICOM32_GOT_LO7_2_S", -+ "BFD_RELOC_UBICOM32_GOT_LO7_4_S", -+ "BFD_RELOC_UBICOM32_GOT_LO7_D", -+ "BFD_RELOC_UBICOM32_GOT_LO7_2_D", -+ "BFD_RELOC_UBICOM32_GOT_LO7_4_D", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D", -+ "BFD_RELOC_UBICOM32_GOT_LO7_CALLI", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI", -+ "BFD_RELOC_UBICOM32_FUNCDESC_VALUE", -+ "BFD_RELOC_UBICOM32_FUNCDESC", -+ "BFD_RELOC_UBICOM32_GOTOFFSET_LO", -+ "BFD_RELOC_UBICOM32_GOTOFFSET_HI", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO", -+ "BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI", - "BFD_RELOC_VTABLE_INHERIT", - "BFD_RELOC_VTABLE_ENTRY", - "BFD_RELOC_IA64_IMM14", ---- a/bfd/Makefile.am -+++ b/bfd/Makefile.am -@@ -114,6 +114,7 @@ ALL_MACHINES = \ - cpu-tic4x.lo \ - cpu-tic54x.lo \ - cpu-tic80.lo \ -+ cpu-ubicom32.lo \ - cpu-v850.lo \ - cpu-vax.lo \ - cpu-we32k.lo \ -@@ -180,6 +181,7 @@ ALL_MACHINES_CFILES = \ - cpu-tic4x.c \ - cpu-tic54x.c \ - cpu-tic80.c \ -+ cpu-ubicom32.c \ - cpu-v850.c \ - cpu-vax.c \ - cpu-we32k.c \ -@@ -292,6 +294,7 @@ BFD32_BACKENDS = \ - elfxx-sparc.lo \ - elf32-sparc.lo \ - elf32-spu.lo \ -+ elf32-ubicom32.lo \ - elf32-v850.lo \ - elf32-vax.lo \ - elf32-xstormy16.lo \ -@@ -473,6 +476,7 @@ BFD32_BACKENDS_CFILES = \ - elfxx-sparc.c \ - elf32-sparc.c \ - elf32-spu.c \ -+ elf32-ubicom32.c \ - elf32-v850.c \ - elf32-vax.c \ - elf32-xstormy16.c \ -@@ -1131,6 +1135,7 @@ cpu-tic30.lo: cpu-tic30.c $(INCDIR)/file - cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h - cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h - cpu-tic80.lo: cpu-tic80.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h -+cpu-ubicom32.lo: cpu-ubicom32.c $(INCDIR)/filenames.h - cpu-v850.lo: cpu-v850.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ - $(INCDIR)/safe-ctype.h - cpu-vax.lo: cpu-vax.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h -@@ -1556,6 +1561,10 @@ elf32-spu.lo: elf32-spu.c $(INCDIR)/file - $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/spu.h \ - $(INCDIR)/elf/reloc-macros.h elf32-spu.h elf32-target.h -+elf32-ubicom32.lo: elf32-ubicom32.c $(INCDIR)/filenames.h elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/reloc-macros.h \ -+ elf32-target.h - elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/v850.h \ ---- a/bfd/Makefile.in -+++ b/bfd/Makefile.in -@@ -367,6 +367,7 @@ ALL_MACHINES = \ - cpu-tic4x.lo \ - cpu-tic54x.lo \ - cpu-tic80.lo \ -+ cpu-ubicom32.lo \ - cpu-v850.lo \ - cpu-vax.lo \ - cpu-we32k.lo \ -@@ -433,6 +434,7 @@ ALL_MACHINES_CFILES = \ - cpu-tic4x.c \ - cpu-tic54x.c \ - cpu-tic80.c \ -+ cpu-ubicom32.c \ - cpu-v850.c \ - cpu-vax.c \ - cpu-we32k.c \ -@@ -546,6 +548,7 @@ BFD32_BACKENDS = \ - elfxx-sparc.lo \ - elf32-sparc.lo \ - elf32-spu.lo \ -+ elf32-ubicom32.lo \ - elf32-v850.lo \ - elf32-vax.lo \ - elf32-xstormy16.lo \ -@@ -727,6 +730,7 @@ BFD32_BACKENDS_CFILES = \ - elfxx-sparc.c \ - elf32-sparc.c \ - elf32-spu.c \ -+ elf32-ubicom32.c \ - elf32-v850.c \ - elf32-vax.c \ - elf32-xstormy16.c \ -@@ -1715,6 +1719,7 @@ cpu-tic30.lo: cpu-tic30.c $(INCDIR)/file - cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h - cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h - cpu-tic80.lo: cpu-tic80.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h -+cpu-ubicom32.lo: cpu-ubicom32.c $(INCDIR)/filenames.h - cpu-v850.lo: cpu-v850.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ - $(INCDIR)/safe-ctype.h - cpu-vax.lo: cpu-vax.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h -@@ -2140,6 +2145,10 @@ elf32-spu.lo: elf32-spu.c $(INCDIR)/file - $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/spu.h \ - $(INCDIR)/elf/reloc-macros.h elf32-spu.h elf32-target.h -+elf32-ubicom32.lo: elf32-ubicom32.c $(INCDIR)/filenames.h elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/reloc-macros.h \ -+ elf32-target.h - elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/v850.h \ ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -4227,6 +4227,75 @@ ENUMDOC - Scenix VPE4K coprocessor - data/insn-space addressing - - ENUM -+ BFD_RELOC_UBICOM32_21_PCREL -+ENUMX -+ BFD_RELOC_UBICOM32_24_PCREL -+ENUMX -+ BFD_RELOC_UBICOM32_HI24 -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_S -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_2_S -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_4_S -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_D -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_2_D -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_4_D -+ENUMX -+ BFD_RELOC_UBICOM32_LO7_CALLI -+ENUMX -+ BFD_RELOC_UBICOM32_LO16_CALLI -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_HI24 -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_S -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_2_S -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_4_S -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_D -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_2_D -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_4_D -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24 -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D -+ENUMX -+ BFD_RELOC_UBICOM32_GOT_LO7_CALLI -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_VALUE -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC -+ENUMX -+ BFD_RELOC_UBICOM32_GOTOFFSET_LO -+ENUMX -+ BFD_RELOC_UBICOM32_GOTOFFSET_HI -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO -+ENUMX -+ BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI -+ENUMDOC -+ Ubicom UBICOM32 Relocations. -+ -+ENUM - BFD_RELOC_VTABLE_INHERIT - ENUMX - BFD_RELOC_VTABLE_ENTRY ---- a/bfd/targets.c -+++ b/bfd/targets.c -@@ -663,6 +663,8 @@ extern const bfd_target bfd_elf32_spu_ve - extern const bfd_target bfd_elf32_tradbigmips_vec; - extern const bfd_target bfd_elf32_tradlittlemips_vec; - extern const bfd_target bfd_elf32_us_cris_vec; -+extern const bfd_target bfd_elf32_ubicom32_vec; -+extern const bfd_target bfd_elf32_ubicom32fdpic_vec; - extern const bfd_target bfd_elf32_v850_vec; - extern const bfd_target bfd_elf32_vax_vec; - extern const bfd_target bfd_elf32_xc16x_vec; -@@ -1001,6 +1003,7 @@ static const bfd_target * const _bfd_tar - &bfd_elf32_tradbigmips_vec, - &bfd_elf32_tradlittlemips_vec, - &bfd_elf32_us_cris_vec, -+ &bfd_elf32_ubicom32_vec, - &bfd_elf32_v850_vec, - &bfd_elf32_vax_vec, - &bfd_elf32_xc16x_vec, ---- a/binutils/Makefile.am -+++ b/binutils/Makefile.am -@@ -584,7 +584,7 @@ readelf.o: readelf.c config.h sysdep.h $ - $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/frv.h \ - $(INCDIR)/elf/hppa.h $(INCDIR)/elf/i386.h $(INCDIR)/elf/i370.h \ - $(INCDIR)/elf/i860.h $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h \ -- $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \ -+ $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \ - $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/m68hc11.h \ - $(INCDIR)/elf/mcore.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/mips.h \ - $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h $(INCDIR)/elf/mn10300.h \ ---- a/binutils/Makefile.in -+++ b/binutils/Makefile.in -@@ -1338,7 +1338,7 @@ readelf.o: readelf.c config.h sysdep.h $ - $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/frv.h \ - $(INCDIR)/elf/hppa.h $(INCDIR)/elf/i386.h $(INCDIR)/elf/i370.h \ - $(INCDIR)/elf/i860.h $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h \ -- $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \ -+ $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \ - $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/m68hc11.h \ - $(INCDIR)/elf/mcore.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/mips.h \ - $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h $(INCDIR)/elf/mn10300.h \ ---- a/binutils/readelf.c -+++ b/binutils/readelf.c -@@ -152,6 +152,7 @@ - #include "elf/sh.h" - #include "elf/sparc.h" - #include "elf/spu.h" -+#include "elf/ubicom32.h" - #include "elf/v850.h" - #include "elf/vax.h" - #include "elf/x86-64.h" -@@ -612,6 +613,7 @@ guess_is_rela (unsigned int e_machine) - case EM_SPARC32PLUS: - case EM_SPARCV9: - case EM_SPU: -+ case EM_UBICOM32: - case EM_V850: - case EM_CYGNUS_V850: - case EM_VAX: -@@ -1159,6 +1161,10 @@ dump_relocations (FILE *file, - rtype = elf_crx_reloc_type (type); - break; - -+ case EM_UBICOM32: -+ rtype = elf_ubicom32_reloc_type (type); -+ break; -+ - case EM_VAX: - rtype = elf_vax_reloc_type (type); - break; -@@ -1812,6 +1818,7 @@ get_machine_name (unsigned e_machine) - case EM_DLX: return "OpenDLX"; - case EM_IP2K_OLD: - case EM_IP2K: return "Ubicom IP2xxx 8-bit microcontrollers"; -+ case EM_UBICOM32: return "Ubicom32 32-bit microcontrollers"; - case EM_IQ2000: return "Vitesse IQ2000"; - case EM_XTENSA_OLD: - case EM_XTENSA: return "Tensilica Xtensa Processor"; ---- a/configure -+++ b/configure -@@ -2666,6 +2666,12 @@ case "${target}" in - xtensa*-*-*) - noconfigdirs="$noconfigdirs ${libgcj}" - ;; -+ ubicom32-*-*linux*) -+ noconfigdirs="$noconfigdirs target-libffi target-newlib" -+ ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi target-newlib" -+ ;; - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}" - ;; ---- a/configure.ac -+++ b/configure.ac -@@ -915,6 +915,12 @@ case "${target}" in - xtensa*-*-*) - noconfigdirs="$noconfigdirs ${libgcj}" - ;; -+ ubicom32-*-*linux*) -+ noconfigdirs="$noconfigdirs target-libffi target-newlib" -+ ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}" - ;; ---- /dev/null -+++ b/gas/config/tc-ubicom32.c -@@ -0,0 +1,609 @@ -+/* tc-ubicom32.c -- Assembler for the Ubicom32 -+ Copyright (C) 2000, 2002 Free Software Foundation. -+ -+ This file is part of GAS, the GNU Assembler. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to -+ the Free Software Foundation, 59 Temple Place - Suite 330, -+ Boston, MA 02111-1307, USA. */ -+ -+#include -+#include -+ -+#include "as.h" -+#include "dwarf2dbg.h" -+#include "subsegs.h" -+#include "symcat.h" -+#include "opcodes/ubicom32-desc.h" -+#include "opcodes/ubicom32-opc.h" -+#include "cgen.h" -+#include "elf/common.h" -+#include "elf/ubicom32.h" -+#include "libbfd.h" -+ -+extern void gas_cgen_md_operand (expressionS *); -+ -+/* Structure to hold all of the different components describing -+ an individual instruction. */ -+typedef struct -+{ -+ const CGEN_INSN * insn; -+ const CGEN_INSN * orig_insn; -+ CGEN_FIELDS fields; -+#if CGEN_INT_INSN_P -+ CGEN_INSN_INT buffer [1]; -+#define INSN_VALUE(buf) (*(buf)) -+#else -+ unsigned char buffer [CGEN_MAX_INSN_SIZE]; -+#define INSN_VALUE(buf) (buf) -+#endif -+ char * addr; -+ fragS * frag; -+ int num_fixups; -+ fixS * fixups [GAS_CGEN_MAX_FIXUPS]; -+ int indices [MAX_OPERAND_INSTANCES]; -+} -+ubicom32_insn; -+ -+const char comment_chars[] = ";"; -+const char line_comment_chars[] = "#"; -+const char line_separator_chars[] = ""; -+const char EXP_CHARS[] = "eE"; -+const char FLT_CHARS[] = "dD"; -+ -+/* Ubicom32 specific function to handle FD-PIC pointer initializations. */ -+ -+static void -+ubicom32_pic_ptr (int nbytes) -+{ -+ expressionS exp; -+ char *p; -+ -+ if (nbytes != 4) -+ abort (); -+ -+#ifdef md_flush_pending_output -+ md_flush_pending_output (); -+#endif -+ -+ if (is_it_end_of_statement ()) -+ { -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+#ifdef md_cons_align -+ md_cons_align (nbytes); -+#endif -+ -+ do -+ { -+ bfd_reloc_code_real_type reloc_type = BFD_RELOC_UBICOM32_FUNCDESC; -+ -+ if (strncasecmp (input_line_pointer, "%funcdesc(", strlen("%funcdesc(")) == 0) -+ { -+ input_line_pointer += strlen("%funcdesc("); -+ expression (&exp); -+ if (*input_line_pointer == ')') -+ input_line_pointer++; -+ else -+ as_bad (_("missing ')'")); -+ } -+ else -+ as_bad ("missing funcdesc in picptr"); -+ -+ p = frag_more (4); -+ memset (p, 0, 4); -+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0, -+ reloc_type); -+ } -+ while (*input_line_pointer++ == ','); -+ -+ input_line_pointer--; /* Put terminator back into stream. */ -+ demand_empty_rest_of_line (); -+} -+ -+/* The target specific pseudo-ops which we support. */ -+const pseudo_typeS md_pseudo_table[] = -+{ -+ { "file", (void (*)(int))dwarf2_directive_file, 0 }, -+ { "loc", dwarf2_directive_loc, 0 }, -+ { "picptr", ubicom32_pic_ptr, 4 }, -+ { "word", cons, 4 }, -+ { NULL, NULL, 0 } -+}; -+ -+/* A table of the register symbols */ -+#if 0 -+static symbolS *ubicom32_register_table[40]; /* 32 data & 8 address */ -+#endif -+ -+ -+#define OPTION_CPU_IP3035 (OPTION_MD_BASE) -+#define OPTION_CPU_UBICOM32DSP (OPTION_MD_BASE+1) -+#define OPTION_CPU_UBICOM32VER4 (OPTION_MD_BASE+2) -+#define OPTION_CPU_UBICOM32VER3FDPIC (OPTION_MD_BASE+3) -+#define OPTION_CPU_UBICOM32VER4FDPIC (OPTION_MD_BASE+4) -+#define OPTION_CPU_UBICOM32_FDPIC (OPTION_MD_BASE+5) -+ -+struct option md_longopts[] = -+{ -+ { "mubicom32v1", no_argument, NULL, OPTION_CPU_IP3035 }, -+ { "mubicom32v2", no_argument, NULL, OPTION_CPU_UBICOM32DSP }, -+ { "mubicom32v3", no_argument, NULL, OPTION_CPU_UBICOM32DSP }, -+ { "mubicom32v4", no_argument, NULL, OPTION_CPU_UBICOM32VER4 }, -+ { "mubicom32v3fdpic", no_argument, NULL, OPTION_CPU_UBICOM32VER3FDPIC }, -+ { "mubicom32v4fdpic", no_argument, NULL, OPTION_CPU_UBICOM32VER4FDPIC }, -+ { "mfdpic", no_argument, NULL, OPTION_CPU_UBICOM32_FDPIC }, -+ { NULL, no_argument, NULL, 0 }, -+}; -+size_t md_longopts_size = sizeof (md_longopts); -+ -+const char * md_shortopts = ""; -+ -+/* Mach selected from command line. */ -+int ubicom32_mach = 0; -+unsigned ubicom32_mach_bitmask = 0; -+ -+int -+md_parse_option (c, arg) -+ int c ATTRIBUTE_UNUSED; -+ char * arg ATTRIBUTE_UNUSED; -+{ -+ int pic_state = ubicom32_mach & 0xffff0000; -+ switch (c) -+ { -+ case OPTION_CPU_IP3035: -+ ubicom32_mach = bfd_mach_ubicom32; -+ ubicom32_mach_bitmask = 1 << MACH_IP3035; -+ break; -+ -+ case OPTION_CPU_UBICOM32DSP: -+ ubicom32_mach = bfd_mach_ubicom32dsp; -+ ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY); -+ break; -+ -+ case OPTION_CPU_UBICOM32VER4: -+ ubicom32_mach = bfd_mach_ubicom32ver4; -+ ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY) | (1 << MACH_UBICOM32_VER4); -+ break; -+ -+ case OPTION_CPU_UBICOM32VER3FDPIC: -+ ubicom32_mach = bfd_mach_ubicom32dsp | EF_UBICOM32_FDPIC; -+ ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY); -+ break; -+ -+ case OPTION_CPU_UBICOM32VER4FDPIC: -+ ubicom32_mach = bfd_mach_ubicom32ver4 | EF_UBICOM32_FDPIC; -+ ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY) | (1 << MACH_UBICOM32_VER4); -+ break; -+ -+ case OPTION_CPU_UBICOM32_FDPIC: -+ ubicom32_mach |= EF_UBICOM32_FDPIC; -+ break; -+ -+ default: -+ return 0; -+ } -+ ubicom32_mach |= pic_state; -+ -+ return 1; -+} -+ -+ -+void -+md_show_usage (stream) -+ FILE * stream; -+{ -+ fprintf (stream, _("UBICOM32 specific command line options:\n")); -+ fprintf (stream, _(" -mubicom32v1 restrict to IP3023 insns \n")); -+ fprintf (stream, _(" -mubicom32v3 permit DSP extended insn\n")); -+ fprintf (stream, _(" -mubicom32v4 permit DSP extended insn and additional .1 instructions.\n")); -+ fprintf (stream, _(" -mfdpic This in addition to the v3 or v4 flags will produce a FDPIC .o.\n")); -+ -+} -+ -+ -+void -+md_begin () -+{ -+ /* Initialize the `cgen' interface. */ -+ if(ubicom32_mach_bitmask == 0) { -+ /* md_parse_option has not been called */ -+ ubicom32_mach_bitmask = 1<signed_overflow_ok_p=1; -+ -+ /* need a way to detect when we have multiple increments to same An register */ -+ insn.fields.f_s1_i4_1 = 0; -+ insn.fields.f_s1_i4_2 = 0; -+ insn.fields.f_s1_i4_4 = 0; -+ insn.fields.f_d_i4_1 = 0; -+ insn.fields.f_d_i4_2 = 0; -+ insn.fields.f_d_i4_4 = 0; -+ insn.fields.f_s1_direct = 0; -+ insn.fields.f_d_direct = 0; -+ -+ memset(&insn.fields, 0, sizeof(insn.fields)); -+ insn.insn = ubicom32_cgen_assemble_insn -+ (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); -+ -+ if (!insn.insn) -+ { -+ as_bad ("%s", errmsg); -+ return; -+ } -+ -+ if (insn.fields.f_s1_An == insn.fields.f_d_An) -+ { -+ if ((insn.fields.f_s1_i4_1 != 0 && insn.fields.f_d_i4_1 != 0) || -+ (insn.fields.f_s1_i4_2 != 0 && insn.fields.f_d_i4_2 != 0) || -+ (insn.fields.f_s1_i4_4 != 0 && insn.fields.f_d_i4_4 != 0)) -+ { -+ /* user has tried to increment the same An register in both the s1 -+ and d operands which is illegal */ -+ static char errbuf[255]; -+ char *first_part; -+ first_part = _("s1 and d operands update same An register"); -+ if (strlen (str) > 50) -+ sprintf (errbuf, "%s `%.50s...'", first_part, str); -+ else -+ sprintf (errbuf, "%s `%.50s'", first_part, str); -+ -+ as_bad ("%s", errbuf); -+ return; -+ } -+ } -+ -+ if(insn.fields.f_d_direct && -+ insn.fields.f_d_An == 0 && -+ insn.fields.f_d_imm7_4 == 0 && -+ insn.fields.f_d_imm7_2 == 0 && -+ insn.fields.f_d_imm7_1 == 0 && -+ insn.fields.f_d_i4_1 == 0 && -+ insn.fields.f_d_i4_2 == 0 && -+ insn.fields.f_d_i4_4 == 0) -+ { -+ if (insn.fields.f_d_direct >= A0_ADDRESS && -+ insn.fields.f_d_direct <= A7_ADDRESS) -+ { -+ long d_direct = (insn.fields.f_d_direct - A0_ADDRESS) >> 2; -+ if (d_direct == insn.fields.f_s1_An && -+ (insn.fields.f_s1_i4_1 != 0 || -+ insn.fields.f_s1_i4_2 != 0 || -+ insn.fields.f_s1_i4_4 != 0)) -+ { -+ /* user has tried to increment an An register that is also the destination register */ -+ static char errbuf[255]; -+ char *first_part; -+ first_part = _("s1 and d operands update same An register"); -+ if (strlen (str) > 50) -+ sprintf (errbuf, "%s `%.50s...'", first_part, str); -+ else -+ sprintf (errbuf, "%s `%.50s'", first_part, str); -+ -+ as_bad ("%s", errbuf); -+ return; -+ } -+ } -+ } -+ -+ /* Doesn't really matter what we pass for RELAX_P here. */ -+ gas_cgen_finish_insn (insn.insn, insn.buffer, -+ CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); -+ -+} -+ -+/* The syntax in the manual says constants begin with '#'. -+ We just ignore it. */ -+ -+void -+md_operand (expressionP) -+ expressionS * expressionP; -+{ -+ /* In case of a syntax error, escape back to try next syntax combo. */ -+ if (expressionP->X_op == O_absent) -+ gas_cgen_md_operand (expressionP); -+} -+ -+valueT -+md_section_align (segment, size) -+ segT segment; -+ valueT size; -+{ -+ int align = bfd_get_section_alignment (stdoutput, segment); -+ return ((size + (1 << align) - 1) & (-1 << align)); -+} -+ -+ -+/* Be sure to use our register symbols. */ -+symbolS * -+md_undefined_symbol (char * name ATTRIBUTE_UNUSED) -+{ -+#if 0 -+ char c; -+ unsigned int u; -+ -+ if (sscanf(name, "%c%u", &c, &u) == 2) -+ { -+ if (c == 'd' && u < 32) -+ return ubicom32_register_table[u]; -+ if (c == 'a' && u < 8) -+ return ubicom32_register_table[u + 32]; -+ } -+#endif -+ return (0); -+} -+ -+/* Interface to relax_segment. */ -+ -+/* Return an initial guess of the length by which a fragment must grow to -+ hold a branch to reach its destination. -+ Also updates fr_type/fr_subtype as necessary. -+ -+ Called just before doing relaxation. -+ Any symbol that is now undefined will not become defined. -+ The guess for fr_var is ACTUALLY the growth beyond fr_fix. -+ Whatever we do to grow fr_fix or fr_var contributes to our returned value. -+ Although it may not be explicit in the frag, pretend fr_var starts with a -+ 0 value. */ -+ -+int -+md_estimate_size_before_relax (fragP, segment) -+ fragS * fragP; -+ segT segment ATTRIBUTE_UNUSED; -+{ -+ int old_fr_fix = fragP->fr_fix; -+ -+ /* The only thing we have to handle here are symbols outside of the -+ current segment. They may be undefined or in a different segment in -+ which case linker scripts may place them anywhere. -+ However, we can't finish the fragment here and emit the reloc as insn -+ alignment requirements may move the insn about. */ -+ -+ return (fragP->fr_var + fragP->fr_fix - old_fr_fix); -+} -+ -+/* *fragP has been relaxed to its final size, and now needs to have -+ the bytes inside it modified to conform to the new size. -+ -+ Called after relaxation is finished. -+ fragP->fr_type == rs_machine_dependent. -+ fragP->fr_subtype is the subtype of what the address relaxed to. */ -+ -+void -+md_convert_frag (abfd, sec, fragP) -+ bfd * abfd ATTRIBUTE_UNUSED; -+ segT sec ATTRIBUTE_UNUSED; -+ fragS * fragP ATTRIBUTE_UNUSED; -+{ -+} -+ -+ -+/* Functions concerning relocs. */ -+ -+long -+md_pcrel_from_section (fixS *fixP ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED) -+{ -+ /* Leave it for the linker to figure out so relaxation can work*/ -+ return 0; -+} -+ -+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. -+ Returns BFD_RELOC_NONE if no reloc type can be found. -+ *FIXP may be modified if desired. */ -+ -+bfd_reloc_code_real_type -+md_cgen_lookup_reloc (insn, operand, fixP) -+ const CGEN_INSN * insn ATTRIBUTE_UNUSED; -+ const CGEN_OPERAND * operand; -+ fixS * fixP; -+{ -+ switch (operand->type) -+ { -+ case UBICOM32_OPERAND_IMM16_2: -+ case UBICOM32_OPERAND_IMM24: -+ case UBICOM32_OPERAND_S1_IMM7_1: -+ case UBICOM32_OPERAND_S1_IMM7_2: -+ case UBICOM32_OPERAND_S1_IMM7_4: -+ case UBICOM32_OPERAND_D_IMM7_1: -+ case UBICOM32_OPERAND_D_IMM7_2: -+ case UBICOM32_OPERAND_D_IMM7_4: -+ case UBICOM32_OPERAND_OFFSET16: -+ /* The relocation type should be recorded in opinfo */ -+ if (fixP->fx_cgen.opinfo != 0) -+ return fixP->fx_cgen.opinfo; -+ -+ case UBICOM32_OPERAND_OFFSET21: -+ fixP->fx_pcrel = TRUE; -+ return BFD_RELOC_UBICOM32_21_PCREL; -+ -+ case UBICOM32_OPERAND_OFFSET24: -+ fixP->fx_pcrel = TRUE; -+ return BFD_RELOC_UBICOM32_24_PCREL; -+ -+ default: -+ /* Pacify gcc -Wall. */ -+ return BFD_RELOC_NONE; -+ } -+} -+ -+/* See whether we need to force a relocation into the output file. */ -+ -+int -+ubicom32_force_relocation (fix) -+ fixS * fix; -+{ -+ if (fix->fx_r_type == BFD_RELOC_UNUSED) -+ return 0; -+ -+ /* Force all relocations so linker relaxation can work. */ -+ return 1; -+} -+ -+/* Write a value out to the object file, using the appropriate endianness. */ -+ -+void -+md_number_to_chars (buf, val, n) -+ char * buf; -+ valueT val; -+ int n; -+{ -+ number_to_chars_bigendian (buf, val, n); -+} -+ -+/* Turn a string in input_line_pointer into a floating point constant of type -+ type, and store the appropriate bytes in *litP. The number of LITTLENUMS -+ emitted is stored in *sizeP . An error message is returned, or NULL on OK. -+*/ -+ -+/* Equal to MAX_PRECISION in atof-ieee.c */ -+#define MAX_LITTLENUMS 6 -+ -+char * -+md_atof (int type, -+ char * litP, -+ int * sizeP) -+{ -+ int prec; -+ LITTLENUM_TYPE words [MAX_LITTLENUMS]; -+ LITTLENUM_TYPE *wordP; -+ char * t; -+ //char * atof_ieee (void); -+ -+ switch (type) -+ { -+ case 'f': -+ case 'F': -+ case 's': -+ case 'S': -+ prec = 2; -+ break; -+ -+ case 'd': -+ case 'D': -+ case 'r': -+ case 'R': -+ prec = 4; -+ break; -+ -+ /* FIXME: Some targets allow other format chars for bigger sizes here. */ -+ -+ default: -+ * sizeP = 0; -+ return _("Bad call to md_atof()"); -+ } -+ -+ t = atof_ieee (input_line_pointer, type, words); -+ if (t) -+ input_line_pointer = t; -+ * sizeP = prec * sizeof (LITTLENUM_TYPE); -+ -+ /* This loops outputs the LITTLENUMs in REVERSE order; in accord with -+ the ubicom32 endianness. */ -+ for (wordP = words; prec--;) -+ { -+ md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE)); -+ litP += sizeof (LITTLENUM_TYPE); -+ } -+ -+ return 0; -+} -+ -+bfd_boolean -+ubicom32_fix_adjustable (fixP) -+ fixS * fixP; -+{ -+ bfd_reloc_code_real_type reloc_type; -+ -+ if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) -+ { -+ const CGEN_INSN *insn = NULL; -+ int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; -+ const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); -+ reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); -+ } -+ else -+ reloc_type = fixP->fx_r_type; -+ -+ if (fixP->fx_addsy == NULL) -+ return 1; -+ -+ if (!S_IS_LOCAL (fixP->fx_addsy)) -+ /* Let the linker resolve all symbols not within the local function -+ so the linker can relax correctly. */ -+ return 0; -+ -+ if (S_IS_WEAK (fixP->fx_addsy)) -+ return 0; -+ -+ /* We need the symbol name for the VTABLE entries */ -+ if ( reloc_type == BFD_RELOC_VTABLE_INHERIT -+ || reloc_type == BFD_RELOC_VTABLE_ENTRY) -+ return 0; -+ -+ return 1; -+} ---- /dev/null -+++ b/gas/config/tc-ubicom32.h -@@ -0,0 +1,74 @@ -+/* tc-ubicom32.h -- Header file for tc-ubicom32.c. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ -+ This file is part of GAS, the GNU Assembler. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to -+ the Free Software Foundation, 59 Temple Place - Suite 330, -+ Boston, MA 02111-1307, USA. */ -+ -+#define TC_UBICOM32 -+ -+#if 0 -+#ifndef BFD_ASSEMBLER -+/* leading space so will compile with cc */ -+ #error UBICOM32 support requires BFD_ASSEMBLER -+#endif -+#endif -+ -+#define LISTING_HEADER "IP3xxx GAS " -+ -+/* The target BFD architecture. */ -+#define TARGET_ARCH bfd_arch_ubicom32 -+ -+#define TARGET_FORMAT "elf32-ubicom32" -+ -+#define TARGET_BYTES_BIG_ENDIAN 1 -+ -+/* Permit temporary numeric labels. */ -+#define LOCAL_LABELS_FB 1 -+ -+/* .-foo gets turned into PC relative relocs. */ -+#define DIFF_EXPR_OK -+ -+/* UBICOM32 uses '(' and ')' as punctuation in addressing mode syntax. */ -+#define RELAX_PAREN_GROUPING -+ -+/* We don't need to handle .word strangely. */ -+#define WORKING_DOT_WORD -+ -+#define MD_APPLY_FIX3 -+#define md_apply_fix gas_cgen_md_apply_fix -+ -+/* special characters for hex and bin literals */ -+#define LITERAL_PREFIXDOLLAR_HEX -+#define LITERAL_PREFIXPERCENT_BIN -+#define DOUBLESLASH_LINE_COMMENTS -+ -+/* call md_pcrel_from_section, not md_pcrel_from */ -+long md_pcrel_from_section PARAMS ((struct fix *, segT)); -+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) -+ -+#define obj_fix_adjustable(fixP) ubicom32_fix_adjustable (fixP) -+extern bfd_boolean ubicom32_fix_adjustable PARAMS ((struct fix *)); -+ -+/* Permit temporary numeric labels. */ -+#define LOCAL_LABELS_FB 1 -+ -+#define TC_HANDLES_FX_DONE -+ -+#define tc_gen_reloc gas_cgen_tc_gen_reloc -+ -+#define TC_FORCE_RELOCATION(fixp) ubicom32_force_relocation(fixp) -+extern int ubicom32_force_relocation PARAMS ((struct fix *)); ---- a/gas/configure -+++ b/gas/configure -@@ -11188,7 +11188,7 @@ _ACEOF - fi - ;; - -- fr30 | ip2k | iq2000 | m32r | openrisc) -+ fr30 | ubicom32 | ip2k | iq2000 | m32r | openrisc) - using_cgen=yes - ;; - ---- a/gas/configure.in -+++ b/gas/configure.in -@@ -307,7 +307,7 @@ changequote([,])dnl - fi - ;; - -- fr30 | ip2k | iq2000 | m32r | openrisc) -+ fr30 | ubicom32 | ip2k | iq2000 | m32r | openrisc) - using_cgen=yes - ;; - ---- a/gas/configure.tgt -+++ b/gas/configure.tgt -@@ -81,6 +81,7 @@ case ${cpu} in - strongarm*be) cpu_type=arm endian=big ;; - strongarm*b) cpu_type=arm endian=big ;; - strongarm*) cpu_type=arm endian=little ;; -+ ubicom32) cpu_type=ubicom32 endian=big ;; - v850*) cpu_type=v850 ;; - x86_64*) cpu_type=i386 arch=x86_64;; - xscale*be|xscale*b) cpu_type=arm endian=big ;; -@@ -384,6 +385,8 @@ case ${generic_target} in - tic4x-*-* | c4x-*-*) fmt=coff bfd_gas=yes ;; - tic54x-*-* | c54x*-*-*) fmt=coff bfd_gas=yes need_libm=yes;; - -+ ubicom32-*-*) fmt=elf ;; -+ - v850-*-*) fmt=elf ;; - v850e-*-*) fmt=elf ;; - v850ea-*-*) fmt=elf ;; ---- a/gas/Makefile.am -+++ b/gas/Makefile.am -@@ -92,6 +92,7 @@ CPU_TYPES = \ - tic30 \ - tic4x \ - tic54x \ -+ ubicom32 \ - v850 \ - vax \ - xc16x \ -@@ -287,6 +288,7 @@ TARGET_CPU_CFILES = \ - config/tc-tic30.c \ - config/tc-tic4x.c \ - config/tc-tic54x.c \ -+ config/tc-ubicom32.c \ - config/tc-vax.c \ - config/tc-v850.c \ - config/tc-xstormy16.c \ -@@ -1415,6 +1417,14 @@ DEPTC_tic54x_coff = $(srcdir)/config/obj - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \ - sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \ - $(INCDIR)/opcode/tic54x.h -+DEPTC_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \ -+ subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ubicom32-desc.h \ -+ $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/ubicom32-opc.h \ -+ cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ubicom32.h \ -+ $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h - DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \ - $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \ -@@ -1791,6 +1801,11 @@ DEPOBJ_tic54x_coff = $(srcdir)/config/ob - $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ - subsegs.h -+DEPOBJ_ubicomm32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \ -+ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ -+ $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h - DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \ - $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \ -@@ -2106,6 +2121,11 @@ DEP_tic4x_coff = $(srcdir)/config/obj-co - DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \ - $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h -+DEP_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \ -+ $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \ -+ $(BFDDIR)/libcoff.h - DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \ - $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \ ---- a/gas/Makefile.in -+++ b/gas/Makefile.in -@@ -341,6 +341,7 @@ CPU_TYPES = \ - tic30 \ - tic4x \ - tic54x \ -+ ubicom32 \ - v850 \ - vax \ - xc16x \ -@@ -534,6 +535,7 @@ TARGET_CPU_CFILES = \ - config/tc-tic30.c \ - config/tc-tic4x.c \ - config/tc-tic54x.c \ -+ config/tc-ubicom32.c \ - config/tc-vax.c \ - config/tc-v850.c \ - config/tc-xstormy16.c \ -@@ -594,6 +596,7 @@ TARGET_CPU_HFILES = \ - config/tc-tic30.h \ - config/tc-tic4x.h \ - config/tc-tic54x.h \ -+ config/tc-ubicom32.h \ - config/tc-vax.h \ - config/tc-v850.h \ - config/tc-xstormy16.h \ -@@ -1244,6 +1247,13 @@ DEPTC_tic54x_coff = $(srcdir)/config/obj - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \ - sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \ - $(INCDIR)/opcode/tic54x.h -+DEPTC_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \ -+ subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ubicom32-desc.h \ -+ $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(srcdir)/../opcodes/ubicom32-opc.h cgen.h $(INCDIR)/elf/ubicom32.h \ -+ $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h - - DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \ -@@ -1700,6 +1710,11 @@ DEPOBJ_tic54x_coff = $(srcdir)/config/ob - $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ - subsegs.h -+DEPOBJ_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \ -+ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ -+ struc-symbol.h $(INCDIR)/aout/aout64.h - - DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \ -@@ -2096,6 +2111,11 @@ DEP_tic54x_coff = $(srcdir)/config/obj-c - $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h - -+DEP_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ -+ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ -+ $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \ -+ $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \ -+ $(BFDDIR)/libcoff.h - DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \ - $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \ ---- a/include/dis-asm.h -+++ b/include/dis-asm.h -@@ -275,6 +275,7 @@ extern int print_insn_tic30 (bfd_vma, d - extern int print_insn_tic4x (bfd_vma, disassemble_info *); - extern int print_insn_tic54x (bfd_vma, disassemble_info *); - extern int print_insn_tic80 (bfd_vma, disassemble_info *); -+extern int print_insn_ubicom32 (bfd_vma, disassemble_info *); - extern int print_insn_v850 (bfd_vma, disassemble_info *); - extern int print_insn_vax (bfd_vma, disassemble_info *); - extern int print_insn_w65 (bfd_vma, disassemble_info *); ---- /dev/null -+++ b/include/dis-asm_ubicom32.h -@@ -0,0 +1,339 @@ -+/* Interface between the opcode library and its callers. -+ -+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 -+ Free Software Foundation, Inc. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2, or (at your option) -+ any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, -+ Boston, MA 02110-1301, USA. -+ -+ Written by Cygnus Support, 1993. -+ -+ The opcode library (libopcodes.a) provides instruction decoders for -+ a large variety of instruction sets, callable with an identical -+ interface, for making instruction-processing programs more independent -+ of the instruction set being processed. */ -+ -+#ifndef DIS_ASM_H -+#define DIS_ASM_H -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include -+#include "bfd.h" -+ -+typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2; -+ -+enum dis_insn_type { -+ dis_noninsn, /* Not a valid instruction */ -+ dis_nonbranch, /* Not a branch instruction */ -+ dis_branch, /* Unconditional branch */ -+ dis_condbranch, /* Conditional branch */ -+ dis_jsr, /* Jump to subroutine */ -+ dis_condjsr, /* Conditional jump to subroutine */ -+ dis_dref, /* Data reference instruction */ -+ dis_dref2 /* Two data references in instruction */ -+}; -+ -+/* This struct is passed into the instruction decoding routine, -+ and is passed back out into each callback. The various fields are used -+ for conveying information from your main routine into your callbacks, -+ for passing information into the instruction decoders (such as the -+ addresses of the callback functions), or for passing information -+ back from the instruction decoders to their callers. -+ -+ It must be initialized before it is first passed; this can be done -+ by hand, or using one of the initialization macros below. */ -+ -+typedef struct disassemble_info { -+ fprintf_ftype fprintf_func; -+ void *stream; -+ void *application_data; -+ -+ /* Target description. We could replace this with a pointer to the bfd, -+ but that would require one. There currently isn't any such requirement -+ so to avoid introducing one we record these explicitly. */ -+ /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ -+ enum bfd_flavour flavour; -+ /* The bfd_arch value. */ -+ enum bfd_architecture arch; -+ /* The bfd_mach value. */ -+ unsigned long mach; -+ /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ -+ enum bfd_endian endian; -+ /* An arch/mach-specific bitmask of selected instruction subsets, mainly -+ for processors with run-time-switchable instruction sets. The default, -+ zero, means that there is no constraint. CGEN-based opcodes ports -+ may use ISA_foo masks. */ -+ void *insn_sets; -+ -+ /* Some targets need information about the current section to accurately -+ display insns. If this is NULL, the target disassembler function -+ will have to make its best guess. */ -+ asection *section; -+ -+ /* An array of pointers to symbols either at the location being disassembled -+ or at the start of the function being disassembled. The array is sorted -+ so that the first symbol is intended to be the one used. The others are -+ present for any misc. purposes. This is not set reliably, but if it is -+ not NULL, it is correct. */ -+ asymbol **symbols; -+ /* Number of symbols in array. */ -+ int num_symbols; -+ -+ /* For use by the disassembler. -+ The top 16 bits are reserved for public use (and are documented here). -+ The bottom 16 bits are for the internal use of the disassembler. */ -+ unsigned long flags; -+#define INSN_HAS_RELOC 0x80000000 -+ void *private_data; -+ -+ /* Function used to get bytes to disassemble. MEMADDR is the -+ address of the stuff to be disassembled, MYADDR is the address to -+ put the bytes in, and LENGTH is the number of bytes to read. -+ INFO is a pointer to this struct. -+ Returns an errno value or 0 for success. */ -+ int (*read_memory_func) -+ (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, -+ struct disassemble_info *info); -+ -+ /* Function which should be called if we get an error that we can't -+ recover from. STATUS is the errno value from read_memory_func and -+ MEMADDR is the address that we were trying to read. INFO is a -+ pointer to this struct. */ -+ void (*memory_error_func) -+ (int status, bfd_vma memaddr, struct disassemble_info *info); -+ -+ /* Function called to print ADDR. */ -+ void (*print_address_func) -+ (bfd_vma addr, struct disassemble_info *info); -+ -+ /* Function called to determine if there is a symbol at the given ADDR. -+ If there is, the function returns 1, otherwise it returns 0. -+ This is used by ports which support an overlay manager where -+ the overlay number is held in the top part of an address. In -+ some circumstances we want to include the overlay number in the -+ address, (normally because there is a symbol associated with -+ that address), but sometimes we want to mask out the overlay bits. */ -+ int (* symbol_at_address_func) -+ (bfd_vma addr, struct disassemble_info * info); -+ -+ /* Function called to check if a SYMBOL is can be displayed to the user. -+ This is used by some ports that want to hide special symbols when -+ displaying debugging outout. */ -+ bfd_boolean (* symbol_is_valid) -+ (asymbol *, struct disassemble_info * info); -+ -+ /* These are for buffer_read_memory. */ -+ bfd_byte *buffer; -+ bfd_vma buffer_vma; -+ unsigned int buffer_length; -+ -+ /* This variable may be set by the instruction decoder. It suggests -+ the number of bytes objdump should display on a single line. If -+ the instruction decoder sets this, it should always set it to -+ the same value in order to get reasonable looking output. */ -+ int bytes_per_line; -+ -+ /* The next two variables control the way objdump displays the raw data. */ -+ /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ -+ /* output will look like this: -+ 00: 00000000 00000000 -+ with the chunks displayed according to "display_endian". */ -+ int bytes_per_chunk; -+ enum bfd_endian display_endian; -+ -+ /* Number of octets per incremented target address -+ Normally one, but some DSPs have byte sizes of 16 or 32 bits. */ -+ unsigned int octets_per_byte; -+ -+ /* The number of zeroes we want to see at the end of a section before we -+ start skipping them. */ -+ unsigned int skip_zeroes; -+ -+ /* The number of zeroes to skip at the end of a section. If the number -+ of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES, -+ they will be disassembled. If there are fewer than -+ SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic -+ attempt to avoid disassembling zeroes inserted by section -+ alignment. */ -+ unsigned int skip_zeroes_at_end; -+ -+ /* Whether the disassembler always needs the relocations. */ -+ bfd_boolean disassembler_needs_relocs; -+ -+ /* Results from instruction decoders. Not all decoders yet support -+ this information. This info is set each time an instruction is -+ decoded, and is only valid for the last such instruction. -+ -+ To determine whether this decoder supports this information, set -+ insn_info_valid to 0, decode an instruction, then check it. */ -+ -+ char insn_info_valid; /* Branch info has been set. */ -+ char branch_delay_insns; /* How many sequential insn's will run before -+ a branch takes effect. (0 = normal) */ -+ char data_size; /* Size of data reference in insn, in bytes */ -+ enum dis_insn_type insn_type; /* Type of instruction */ -+ bfd_vma target; /* Target address of branch or dref, if known; -+ zero if unknown. */ -+ bfd_vma target2; /* Second target address for dref2 */ -+ -+ /* Command line options specific to the target disassembler. */ -+ char * disassembler_options; -+ -+} disassemble_info; -+ -+ -+/* Standard disassemblers. Disassemble one instruction at the given -+ target address. Return number of octets processed. */ -+typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); -+ -+extern int print_insn_big_mips (bfd_vma, disassemble_info *); -+extern int print_insn_little_mips (bfd_vma, disassemble_info *); -+extern int print_insn_i386 (bfd_vma, disassemble_info *); -+extern int print_insn_i386_att (bfd_vma, disassemble_info *); -+extern int print_insn_i386_intel (bfd_vma, disassemble_info *); -+extern int print_insn_ia64 (bfd_vma, disassemble_info *); -+extern int print_insn_i370 (bfd_vma, disassemble_info *); -+extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); -+extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); -+extern int print_insn_m68k (bfd_vma, disassemble_info *); -+extern int print_insn_z80 (bfd_vma, disassemble_info *); -+extern int print_insn_z8001 (bfd_vma, disassemble_info *); -+extern int print_insn_z8002 (bfd_vma, disassemble_info *); -+extern int print_insn_h8300 (bfd_vma, disassemble_info *); -+extern int print_insn_h8300h (bfd_vma, disassemble_info *); -+extern int print_insn_h8300s (bfd_vma, disassemble_info *); -+extern int print_insn_h8500 (bfd_vma, disassemble_info *); -+extern int print_insn_alpha (bfd_vma, disassemble_info *); -+extern int print_insn_big_arm (bfd_vma, disassemble_info *); -+extern int print_insn_little_arm (bfd_vma, disassemble_info *); -+extern int print_insn_sparc (bfd_vma, disassemble_info *); -+extern int print_insn_avr (bfd_vma, disassemble_info *); -+extern int print_insn_bfin (bfd_vma, disassemble_info *); -+extern int print_insn_d10v (bfd_vma, disassemble_info *); -+extern int print_insn_d30v (bfd_vma, disassemble_info *); -+extern int print_insn_dlx (bfd_vma, disassemble_info *); -+extern int print_insn_fr30 (bfd_vma, disassemble_info *); -+extern int print_insn_hppa (bfd_vma, disassemble_info *); -+extern int print_insn_i860 (bfd_vma, disassemble_info *); -+extern int print_insn_i960 (bfd_vma, disassemble_info *); -+extern int print_insn_m32r (bfd_vma, disassemble_info *); -+extern int print_insn_m88k (bfd_vma, disassemble_info *); -+extern int print_insn_maxq_little (bfd_vma, disassemble_info *); -+extern int print_insn_maxq_big (bfd_vma, disassemble_info *); -+extern int print_insn_mcore (bfd_vma, disassemble_info *); -+extern int print_insn_mmix (bfd_vma, disassemble_info *); -+extern int print_insn_mn10200 (bfd_vma, disassemble_info *); -+extern int print_insn_mn10300 (bfd_vma, disassemble_info *); -+extern int print_insn_mt (bfd_vma, disassemble_info *); -+extern int print_insn_msp430 (bfd_vma, disassemble_info *); -+extern int print_insn_ns32k (bfd_vma, disassemble_info *); -+extern int print_insn_crx (bfd_vma, disassemble_info *); -+extern int print_insn_openrisc (bfd_vma, disassemble_info *); -+extern int print_insn_big_or32 (bfd_vma, disassemble_info *); -+extern int print_insn_little_or32 (bfd_vma, disassemble_info *); -+extern int print_insn_pdp11 (bfd_vma, disassemble_info *); -+extern int print_insn_pj (bfd_vma, disassemble_info *); -+extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); -+extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); -+extern int print_insn_rs6000 (bfd_vma, disassemble_info *); -+extern int print_insn_s390 (bfd_vma, disassemble_info *); -+extern int print_insn_sh (bfd_vma, disassemble_info *); -+extern int print_insn_tic30 (bfd_vma, disassemble_info *); -+extern int print_insn_tic4x (bfd_vma, disassemble_info *); -+extern int print_insn_tic54x (bfd_vma, disassemble_info *); -+extern int print_insn_tic80 (bfd_vma, disassemble_info *); -+extern int print_insn_ubicom32 (bfd_vma, disassemble_info *); -+extern int print_insn_v850 (bfd_vma, disassemble_info *); -+extern int print_insn_vax (bfd_vma, disassemble_info *); -+extern int print_insn_w65 (bfd_vma, disassemble_info *); -+extern int print_insn_xstormy16 (bfd_vma, disassemble_info *); -+extern int print_insn_xtensa (bfd_vma, disassemble_info *); -+extern int print_insn_sh64 (bfd_vma, disassemble_info *); -+extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); -+extern int print_insn_frv (bfd_vma, disassemble_info *); -+extern int print_insn_iq2000 (bfd_vma, disassemble_info *); -+extern int print_insn_xc16x (bfd_vma, disassemble_info *); -+extern int print_insn_m32c (bfd_vma, disassemble_info *); -+ -+extern disassembler_ftype arc_get_disassembler (void *); -+extern disassembler_ftype cris_get_disassembler (bfd *); -+ -+extern void print_mips_disassembler_options (FILE *); -+extern void print_ppc_disassembler_options (FILE *); -+extern void print_arm_disassembler_options (FILE *); -+extern void parse_arm_disassembler_option (char *); -+extern int get_arm_regname_num_options (void); -+extern int set_arm_regname_option (int); -+extern int get_arm_regnames (int, const char **, const char **, const char *const **); -+extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); -+ -+/* Fetch the disassembler for a given BFD, if that support is available. */ -+extern disassembler_ftype disassembler (bfd *); -+ -+/* Amend the disassemble_info structure as necessary for the target architecture. -+ Should only be called after initialising the info->arch field. */ -+extern void disassemble_init_for_target (struct disassemble_info * info); -+ -+/* Document any target specific options available from the disassembler. */ -+extern void disassembler_usage (FILE *); -+ -+ -+/* This block of definitions is for particular callers who read instructions -+ into a buffer before calling the instruction decoder. */ -+ -+/* Here is a function which callers may wish to use for read_memory_func. -+ It gets bytes from a buffer. */ -+extern int buffer_read_memory -+ (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *); -+ -+/* This function goes with buffer_read_memory. -+ It prints a message using info->fprintf_func and info->stream. */ -+extern void perror_memory (int, bfd_vma, struct disassemble_info *); -+ -+ -+/* Just print the address in hex. This is included for completeness even -+ though both GDB and objdump provide their own (to print symbolic -+ addresses). */ -+extern void generic_print_address -+ (bfd_vma, struct disassemble_info *); -+ -+/* Always true. */ -+extern int generic_symbol_at_address -+ (bfd_vma, struct disassemble_info *); -+ -+/* Also always true. */ -+extern bfd_boolean generic_symbol_is_valid -+ (asymbol *, struct disassemble_info *); -+ -+/* Method to initialize a disassemble_info struct. This should be -+ called by all applications creating such a struct. */ -+extern void init_disassemble_info (struct disassemble_info *info, void *stream, -+ fprintf_ftype fprintf_func); -+ -+/* For compatibility with existing code. */ -+#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \ -+ init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) -+#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \ -+ init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) -+ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* ! defined (DIS_ASM_H) */ ---- a/include/elf/common.h -+++ b/include/elf/common.h -@@ -318,6 +318,9 @@ - - #define EM_XSTORMY16 0xad45 - -+#define EM_UBICOM32 0xde3d /* Ubicom32; no ABI */ -+#define EM_UBICOM32MATH 0xde3e /* Ubicom32 co-processor; no ABI */ -+ - /* mn10200 and mn10300 backend magic numbers. - Written in the absense of an ABI. */ - #define EM_CYGNUS_MN10300 0xbeef ---- /dev/null -+++ b/include/elf/ubicom32.h -@@ -0,0 +1,79 @@ -+/* ubicom32 ELF support for BFD. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ -+This file is part of BFD, the Binary File Descriptor library. -+ -+This program is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2 of the License, or -+(at your option) any later version. -+ -+This program is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with this program; if not, write to the Free Software Foundation, Inc., -+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifndef _ELF_UBICOM32_H -+#define _ELF_UBICOM32_H -+ -+#include "elf/reloc-macros.h" -+ -+/* Relocations. */ -+START_RELOC_NUMBERS (elf_ubicom32_reloc_type) -+ RELOC_NUMBER (R_UBICOM32_NONE, 0) -+ RELOC_NUMBER (R_UBICOM32_16, 1) -+ RELOC_NUMBER (R_UBICOM32_32, 2) -+ RELOC_NUMBER (R_UBICOM32_LO16, 3) -+ RELOC_NUMBER (R_UBICOM32_HI16, 4) -+ RELOC_NUMBER (R_UBICOM32_21_PCREL, 5) -+ RELOC_NUMBER (R_UBICOM32_24_PCREL, 6) -+ RELOC_NUMBER (R_UBICOM32_HI24, 7) -+ RELOC_NUMBER (R_UBICOM32_LO7_S, 8) -+ RELOC_NUMBER (R_UBICOM32_LO7_2_S, 9) -+ RELOC_NUMBER (R_UBICOM32_LO7_4_S, 10) -+ RELOC_NUMBER (R_UBICOM32_LO7_D, 11) -+ RELOC_NUMBER (R_UBICOM32_LO7_2_D, 12) -+ RELOC_NUMBER (R_UBICOM32_LO7_4_D, 13) -+ RELOC_NUMBER (R_UBICOM32_32_HARVARD, 14) -+ RELOC_NUMBER (R_UBICOM32_LO7_CALLI, 15) -+ RELOC_NUMBER (R_UBICOM32_LO16_CALLI, 16) -+ RELOC_NUMBER (R_UBICOM32_GOT_HI24, 17) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_S, 18) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_2_S, 19) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_4_S, 20) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_D, 21) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_2_D, 22) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_4_D, 23) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_HI24, 24) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_S, 25) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_2_S, 26) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_4_S, 27) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_D, 28) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_2_D, 29) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_4_D, 30) -+ RELOC_NUMBER (R_UBICOM32_GOT_LO7_CALLI, 31) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_CALLI, 32) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_VALUE, 33) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC, 34) -+ RELOC_NUMBER (R_UBICOM32_GOTOFFSET_LO, 35) -+ RELOC_NUMBER (R_UBICOM32_GOTOFFSET_HI, 36) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOTOFFSET_LO, 37) -+ RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOTOFFSET_HI, 38) -+ RELOC_NUMBER (R_UBICOM32_GNU_VTINHERIT, 200) -+ RELOC_NUMBER (R_UBICOM32_GNU_VTENTRY, 201) -+END_RELOC_NUMBERS(R_UBICOM32_max) -+ -+ -+/* -+ * Processor specific flags for the ELF header e_flags field. -+ */ -+#define EF_UBICOM32_PIC 0x80000000 /* -fpic */ -+#define EF_UBICOM32_FDPIC 0x40000000 /* -mfdpic */ -+ -+#define EF_UBICOM32_PIC_FLAGS (EF_UBICOM32_PIC | EF_UBICOM32_FDPIC) -+ -+#endif /* _ELF_IP_H */ ---- a/ld/configure.tgt -+++ b/ld/configure.tgt -@@ -607,6 +607,15 @@ tic4x-*-* | c4x-*-*) targ_emul=tic4xc - tic54x-*-* | c54x*-*-*) targ_emul=tic54xcoff ;; - tic80-*-*) targ_emul=tic80coff - ;; -+ubicom32-*-linux-*) targ_emul=elf32ubicom32 -+ targ_extra_emuls=elf32ubicom32fdpic -+ targ_extra_libpath=$targ_extra_emuls -+ ;; -+ubicom32-*-*) targ_emul=elf32ubicom32 -+ targ_extra_emuls=elf32ubicom32fdpic -+ targ_extra_libpath=$targ_extra_emuls -+ ;; -+ - v850-*-*) targ_emul=v850 ;; - v850e-*-*) targ_emul=v850 ;; - v850ea-*-*) targ_emul=v850 ---- /dev/null -+++ b/ld/emulparams/elf32ubicom32fdpic.sh -@@ -0,0 +1,28 @@ -+MACHINE= -+SCRIPT_NAME=elf -+OUTPUT_FORMAT="elf32-ubicom32fdpic" -+TEXT_START_ADDR=0x000000 -+MAXPAGESIZE=0x1000 -+TARGET_PAGE_SIZE=0x1000 -+NONPAGED_TEXT_START_ADDR=${TEXT_START_ADDR} -+ARCH=ubicom32 -+TEMPLATE_NAME=elf32 -+ENTRY=_start -+EMBEDDED=yes -+GENERATE_SHLIB_SCRIPT=yes -+EMBEDDED= # This gets us program headers mapped as part of the text segment. -+OTHER_GOT_SYMBOLS= -+OTHER_READONLY_SECTIONS=" -+ .rofixup : { -+ ${RELOCATING+__ROFIXUP_LIST__ = .;} -+ *(.rofixup) -+ ${RELOCATING+__ROFIXUP_END__ = .;} -+ } -+" -+ELFSIZE=32 -+WRITABLE_RODATA="" -+DATA_START_SYMBOLS= -+CTOR_START='___ctors = .;' -+CTOR_END='___ctors_end = .;' -+DTOR_START='___dtors = .;' -+DTOR_END='___dtors_end = .;' ---- /dev/null -+++ b/ld/emulparams/elf32ubicom32.sh -@@ -0,0 +1,23 @@ -+MACHINE= -+SCRIPT_NAME=elf -+OUTPUT_FORMAT="elf32-ubicom32" -+DATA_ADDR=0x100000 -+EXT_DATA_START_ADDR=0x100000 -+EXT_DATA_SIZE=0x10000 -+TEXT_START_ADDR=0x40000000 -+EXT_PROGRAM_START_ADDR=0x40000000 -+EXT_PROGRAM_SIZE=0x80000 -+FLASHRAM_START_ADDR=0x20000000 -+COPROCESSOR_MEMORY=0x400000 -+COPROCESSOR_MEM_SIZE=0x100000 -+ARCH=ubicom32 -+TEMPLATE_NAME=elf32 -+ENTRY=_start -+EMBEDDED=yes -+ELFSIZE=32 -+MAXPAGESIZE=256 -+DATA_START_SYMBOLS= -+CTOR_START='___ctors = .;' -+CTOR_END='___ctors_end = .;' -+DTOR_START='___dtors = .;' -+DTOR_END='___dtors_end = .;' ---- a/ld/Makefile.am -+++ b/ld/Makefile.am -@@ -198,6 +198,8 @@ ALL_EMULATIONS = \ - eelf32ppcsim.o \ - eelf32ppcwindiss.o \ - eelf32ppcvxworks.o \ -+ eelf32ubicom32.o \ -+ eelf32ubicom32fdpic.o \ - eelf32vax.o \ - eelf32xc16x.o \ - eelf32xc16xl.o \ -@@ -927,6 +929,14 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64 - eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \ - $(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf32i370 "$(tdir_elf32i370)" -+eelf32ubicom32.c: $(srcdir)/emulparams/elf32ubicom32.sh \ -+ $(ELF_DEPS) \ -+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ubicom32 "$(tdir_ubicom32)" -+eelf32ubicom32fdpic.c: $(srcdir)/emulparams/elf32ubicom32fdpic.sh \ -+ $(ELF_DEPS) \ -+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ubicom32fdpic "$(tdir_ubicom32fdpic)" - eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \ - $(ELF_DEPS) $(srcdir)/scripttempl/ip2k.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf32ip2k "$(tdir_ip2k)" ---- a/ld/Makefile.in -+++ b/ld/Makefile.in -@@ -449,6 +449,8 @@ ALL_EMULATIONS = \ - eelf32ppcsim.o \ - eelf32ppcwindiss.o \ - eelf32ppcvxworks.o \ -+ eelf32ubicom32.o \ -+ eelf32ubicom32fdpic.o \ - eelf32vax.o \ - eelf32xc16x.o \ - eelf32xc16xl.o \ -@@ -1759,6 +1761,14 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64 - eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \ - $(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf32i370 "$(tdir_elf32i370)" -+eelf32ubicom32.c: $(srcdir)/emulparams/elf32ubicom32.sh \ -+ $(ELF_DEPS) \ -+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ubicom32 "$(tdir_ubicom32)" -+eelf32ubicom32fdpic.c: $(srcdir)/emulparams/elf32ubicom32fdpic.sh \ -+ $(ELF_DEPS) \ -+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ubicom32fdpic "$(tdir_ubicom32fdpic)" - eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \ - $(ELF_DEPS) $(srcdir)/scripttempl/ip2k.sc ${GEN_DEPENDS} - ${GENSCRIPTS} elf32ip2k "$(tdir_ip2k)" ---- /dev/null -+++ b/ld/scripttempl/ubicom32.sc -@@ -0,0 +1,395 @@ -+# -+# Unusual variables checked by this code: -+# EXT_DATA_START_ADDR - virtual address start of extended data storage -+# EXT_DATA_SIZE - size of extended data storage -+# EXT_PROGRAM_START_ADDR - virtual address start of extended prog storage -+# EXT_PROGRAM_SIZE - size of extended program storage -+# FLASHRAM1_START_ADDR - virtual address start of flash ram 1 storage -+# FLASHRAM2_START_ADDR - virtual address start of flash ram 2 storage -+# FLASHRAM3_START_ADDR - virtual address start of flash ram 3 storage -+# FLASHRAM4_START_ADDR - virtual address start of flash ram 4 storage -+# FLASHRAM5_START_ADDR - virtual address start of flash ram 5 storage -+# FLASHRAM6_START_ADDR - virtual address start of flash ram 6 storage -+# FLASHRAM7_START_ADDR - virtual address start of flash ram 7 storage -+# FLASHRAM8_START_ADDR - virtual address start of flash ram 8 storage -+# PROGRAM_SRAM_START_ADDR - virtual address start of program sram storage -+# NOP - two byte opcode for no-op (defaults to 0) -+# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start -+# INITIAL_READONLY_SECTIONS - at start of text segment -+# OTHER_READONLY_SECTIONS - other than .text .init .rodata ... -+# (e.g., .PARISC.milli) -+# OTHER_TEXT_SECTIONS - these get put in .text when relocating -+# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ... -+# (e.g., .PARISC.global) -+# OTHER_BSS_SECTIONS - other than .bss .sbss ... -+# OTHER_SECTIONS - at the end -+# EXECUTABLE_SYMBOLS - symbols that must be defined for an -+# executable (e.g., _DYNAMIC_LINK) -+# TEXT_START_SYMBOLS - symbols that appear at the start of the -+# .text section. -+# DATA_START_SYMBOLS - symbols that appear at the start of the -+# .data section. -+# OTHER_GOT_SYMBOLS - symbols defined just before .got. -+# OTHER_GOT_SECTIONS - sections just after .got and .sdata. -+# OTHER_BSS_SYMBOLS - symbols that appear at the start of the -+# .bss section besides __bss_start. -+# DATA_PLT - .plt should be in data segment, not text segment. -+# BSS_PLT - .plt should be in bss segment -+# TEXT_DYNAMIC - .dynamic in text segment, not data segment. -+# EMBEDDED - whether this is for an embedded system. -+# SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set -+# start address of shared library. -+# INPUT_FILES - INPUT command of files to always include -+# WRITABLE_RODATA - if set, the .rodata section should be writable -+# INIT_START, INIT_END - statements just before and just after -+# combination of .init sections. -+# FINI_START, FINI_END - statements just before and just after -+# combination of .fini sections. -+# -+# When adding sections, do note that the names of some sections are used -+# when specifying the start address of the next. -+# -+ -+test -z "$ENTRY" && ENTRY=_start -+test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT} -+test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT} -+if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi -+test -z "${ELFSIZE}" && ELFSIZE=32 -+test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8" -+test "$LD_FLAG" = "N" && DATA_ADDR=. -+INTERP=".interp ${RELOCATING-0} : { *(.interp) } ${RELOCATING+ > datamem}" -+PLT=".plt ${RELOCATING-0} : { *(.plt) } ${RELOCATING+ > datamem}" -+DYNAMIC=".dynamic ${RELOCATING-0} : { *(.dynamic) } ${RELOCATING+ > datamem}" -+RODATA=".rodata ${RELOCATING-0} : { *(.rodata) ${RELOCATING+*(.rodata.*)} ${RELOCATING+*(.gnu.linkonce.r*)} } ${RELOCATING+ > datamem}" -+SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2) } ${RELOCATING+ > datamem}" -+SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2) } ${RELOCATING+ >datamem}" -+CTOR=".ctors ${CONSTRUCTING-0} : -+ { -+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} -+ ${CONSTRUCTING+${CTOR_START}} -+ LONG (-1) -+ /* gcc uses crtbegin.o to find the start of -+ the constructors, so we make sure it is -+ first. Because this is a wildcard, it -+ doesn't matter if the user does not -+ actually link against crtbegin.o; the -+ linker won't look for a file to match a -+ wildcard. The wildcard also means that it -+ doesn't matter which directory crtbegin.o -+ is in. */ -+ -+ KEEP (*crtbegin.o(.ctors)) -+ -+ /* We don't want to include the .ctor section from -+ from the crtend.o file until after the sorted ctors. -+ The .ctor section from the crtend file contains the -+ end of ctors marker and it must be last */ -+ -+ KEEP (*(EXCLUDE_FILE (*crtend.o $OTHER_EXCLUDE_FILES) .ctors)) -+ KEEP (*(SORT(.ctors.*))) -+ KEEP (*(.ctors)) -+ LONG (0) -+ ${CONSTRUCTING+${CTOR_END}} -+ } ${RELOCATING+ > datamem}" -+ -+DTOR=" .dtors ${CONSTRUCTING-0} : -+ { -+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} -+ ${CONSTRUCTING+${DTOR_START}} -+ LONG (-1) -+ KEEP (*crtbegin.o(.dtors)) -+ KEEP (*(EXCLUDE_FILE (*crtend.o $OTHER_EXCLUDE_FILES) .dtors)) -+ KEEP (*(SORT(.dtors.*))) -+ KEEP (*(.dtors)) -+ LONG (0) -+ ${CONSTRUCTING+${DTOR_END}} -+ } ${RELOCATING+ > datamem}" -+ -+# if this is for an embedded system, don't add SIZEOF_HEADERS. -+if [ -z "$EMBEDDED" ]; then -+ test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS" -+else -+ test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}" -+fi -+ -+cat < flashram} -+ .copro ${RELOCATING-0} : {*(.copro) } ${RELOCATING+ > copromem} -+ -+ ${CREATE_SHLIB-${RELOCATING+. = ${TEXT_BASE_ADDRESS};}} -+ ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}} -+ .text ${RELOCATING-0} : -+ { -+ ${RELOCATING+${TEXT_START_SYMBOLS}} -+ *(.text) -+ ${RELOCATING+*(.text.*)} -+ *(.stub) -+ /* .gnu.warning sections are handled specially by elf32.em. */ -+ *(.gnu.warning) -+ ${RELOCATING+*(.gnu.linkonce.t*)} -+ ${RELOCATING+${OTHER_TEXT_SECTIONS}} -+ } ${RELOCATING+ > progmem} =${NOP-0} -+ -+ .rel.text ${RELOCATING-0} : -+ { -+ *(.rel.text) -+ ${RELOCATING+*(.rel.text.*)} -+ ${RELOCATING+*(.rel.gnu.linkonce.t*)} -+ } ${RELOCATING+ > progmem} -+ -+ .rela.text ${RELOCATING-0} : -+ { -+ *(.rela.text) -+ ${RELOCATING+*(.rela.text.*)} -+ ${RELOCATING+*(.rela.gnu.linkonce.t*)} -+ } ${RELOCATING+ > progmem} -+ -+ ${RELOCATING+PROVIDE (__etext = .);} -+ ${RELOCATING+PROVIDE (_etext = .);} -+ ${RELOCATING+PROVIDE (etext = .);} -+ -+ /* Adjust the address for the data segment. We want to adjust up to -+ the same address within the page on the next page up. */ -+ ${CREATE_SHLIB-${RELOCATING+. = ${DATA_ADDR-ALIGN(${MAXPAGESIZE}) + (. & (${MAXPAGESIZE} - 1))};}} -+ ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-ALIGN(${MAXPAGESIZE}) + (. & (${MAXPAGESIZE} - 1))};}} -+ -+ /* Skip first word to ensure first data element can't end up having address -+ 0 in code (NULL pointer) */ -+ . = . + 4; -+ .data ${RELOCATING-0} : -+ { -+ ${RELOCATING+${DATA_START_SYMBOLS}} -+ *(.data) -+ ${RELOCATING+*(.data.*)} -+ ${RELOCATING+*(.gnu.linkonce.d*)} -+ ${CONSTRUCTING+SORT(CONSTRUCTORS)} -+ } ${RELOCATING+ > datamem} -+ .data1 ${RELOCATING-0} : { *(.data1) } ${RELOCATING+ > datamem} -+ .eh_frame ${RELOCATING-0} : -+ { -+ ${RELOCATING+PROVIDE (___eh_frame_begin = .);} -+ *(.eh_frame) -+ LONG (0); -+ ${RELOCATING+PROVIDE (___eh_frame_end = .);} -+ } ${RELOCATING+ > datamem} -+ .gcc_except_table : { *(.gcc_except_table) } ${RELOCATING+ > datamem} -+ -+ /* Read-only sections, placed in data space: */ -+ ${CREATE_SHLIB-${INTERP}} -+ ${INITIAL_READONLY_SECTIONS} -+ ${TEXT_DYNAMIC+${DYNAMIC}} -+ .hash ${RELOCATING-0} : { *(.hash) } ${RELOCATING+ > datamem} -+ .dynsym ${RELOCATING-0} : { *(.dynsym) } ${RELOCATING+ > datamem} -+ .dynstr ${RELOCATING-0} : { *(.dynstr) } ${RELOCATING+ > datamem} -+ .gnu.version ${RELOCATING-0} : { *(.gnu.version) } ${RELOCATING+ > datamem} -+ .gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) } ${RELOCATING+ > datamem} -+ .gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) } ${RELOCATING+ > datamem} -+ -+ .rel.init ${RELOCATING-0} : { *(.rel.init) } ${RELOCATING+ > datamem} -+ .rela.init ${RELOCATING-0} : { *(.rela.init) } ${RELOCATING+ > datamem} -+ .rel.fini ${RELOCATING-0} : { *(.rel.fini) } ${RELOCATING+ > datamem} -+ .rela.fini ${RELOCATING-0} : { *(.rela.fini) } ${RELOCATING+ > datamem} -+ .rel.rodata ${RELOCATING-0} : -+ { -+ *(.rel.rodata) -+ ${RELOCATING+*(.rel.rodata.*)} -+ ${RELOCATING+*(.rel.gnu.linkonce.r*)} -+ } ${RELOCATING+ > datamem} -+ .rela.rodata ${RELOCATING-0} : -+ { -+ *(.rela.rodata) -+ ${RELOCATING+*(.rela.rodata.*)} -+ ${RELOCATING+*(.rela.gnu.linkonce.r*)} -+ } ${RELOCATING+ > datamem} -+ ${OTHER_READONLY_RELOC_SECTIONS} -+ .rel.data ${RELOCATING-0} : -+ { -+ *(.rel.data) -+ ${RELOCATING+*(.rel.data.*)} -+ ${RELOCATING+*(.rel.gnu.linkonce.d*)} -+ } ${RELOCATING+ > datamem} -+ .rela.data ${RELOCATING-0} : -+ { -+ *(.rela.data) -+ ${RELOCATING+*(.rela.data.*)} -+ ${RELOCATING+*(.rela.gnu.linkonce.d*)} -+ } ${RELOCATING+ > datamem} -+ .rel.ctors ${RELOCATING-0} : { *(.rel.ctors) } ${RELOCATING+ > datamem} -+ .rela.ctors ${RELOCATING-0} : { *(.rela.ctors) } ${RELOCATING+ > datamem} -+ .rel.dtors ${RELOCATING-0} : { *(.rel.dtors) } ${RELOCATING+ > datamem} -+ .rela.dtors ${RELOCATING-0} : { *(.rela.dtors) } ${RELOCATING+ > datamem} -+ .rel.got ${RELOCATING-0} : { *(.rel.got) } ${RELOCATING+ > datamem} -+ .rela.got ${RELOCATING-0} : { *(.rela.got) } ${RELOCATING+ > datamem} -+ ${OTHER_GOT_RELOC_SECTIONS} -+ .rel.sdata ${RELOCATING-0} : -+ { -+ *(.rel.sdata) -+ ${RELOCATING+*(.rel.sdata.*)} -+ ${RELOCATING+*(.rel.gnu.linkonce.s*)} -+ } ${RELOCATING+ > datamem} -+ .rela.sdata ${RELOCATING-0} : -+ { -+ *(.rela.sdata) -+ ${RELOCATING+*(.rela.sdata.*)} -+ ${RELOCATING+*(.rela.gnu.linkonce.s*)} -+ } ${RELOCATING+ > datamem} -+ .rel.sbss ${RELOCATING-0} : { *(.rel.sbss) } ${RELOCATING+ > datamem} -+ .rela.sbss ${RELOCATING-0} : { *(.rela.sbss) } ${RELOCATING+ > datamem} -+ .rel.sdata2 ${RELOCATING-0} : { *(.rel.sdata2) } ${RELOCATING+ > datamem} -+ .rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2) } ${RELOCATING+ > datamem} -+ .rel.sbss2 ${RELOCATING-0} : { *(.rel.sbss2) } ${RELOCATING+ > datamem} -+ .rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2) } ${RELOCATING+ > datamem} -+ .rel.bss ${RELOCATING-0} : { *(.rel.bss) } ${RELOCATING+ > datamem} -+ .rela.bss ${RELOCATING-0} : { *(.rela.bss) } ${RELOCATING+ > datamem} -+ .rel.plt ${RELOCATING-0} : { *(.rel.plt) } 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-+ { -+ *(.dynbss) -+ *(.bss) -+ ${RELOCATING+*(.bss.*)} -+ *(COMMON) -+ /* Align here to ensure that the .bss section occupies space up to -+ _end. Align after .bss to ensure correct alignment even if the -+ .bss section disappears because there are no input sections. */ -+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} -+ } ${RELOCATING+ > datamem} -+ ${RELOCATING+${OTHER_BSS_SECTIONS}} -+ ${RELOCATING+. = ALIGN(${ALIGNMENT});} -+ ${RELOCATING+_end = .;} -+ ${RELOCATING+${OTHER_BSS_END_SYMBOLS}} -+ ${RELOCATING+PROVIDE (end = .);} -+ -+ /* Stabs debugging sections. */ -+ .stab 0 : { *(.stab) } -+ .stabstr 0 : { *(.stabstr) } -+ .stab.excl 0 : { *(.stab.excl) } -+ .stab.exclstr 0 : { *(.stab.exclstr) } -+ .stab.index 0 : { *(.stab.index) } -+ .stab.indexstr 0 : { *(.stab.indexstr) } -+ -+ .comment 0 : { *(.comment) } -+ -+ /* DWARF debug sections. -+ Symbols in the DWARF debugging sections are relative to the beginning -+ of the section so we begin them at 0. */ -+ -+ /* DWARF 1 */ -+ .debug 0 : { *(.debug) } -+ .line 0 : { *(.line) } -+ -+ /* GNU DWARF 1 extensions */ -+ .debug_srcinfo 0 : { *(.debug_srcinfo) } -+ .debug_sfnames 0 : { *(.debug_sfnames) } -+ -+ /* DWARF 1.1 and DWARF 2 */ -+ .debug_aranges 0 : { *(.debug_aranges) } -+ .debug_pubnames 0 : { *(.debug_pubnames) } -+ -+ /* DWARF 2 */ -+ .debug_info 0 : { *(.debug_info) } -+ .debug_abbrev 0 : { *(.debug_abbrev) } -+ .debug_line 0 : { *(.debug_line) } -+ .debug_frame 0 : { *(.debug_frame) } -+ .debug_str 0 : { *(.debug_str) } -+ .debug_loc 0 : { *(.debug_loc) } -+ .debug_macinfo 0 : { *(.debug_macinfo) } -+ -+ /* SGI/MIPS DWARF 2 extensions */ -+ .debug_weaknames 0 : { *(.debug_weaknames) } -+ .debug_funcnames 0 : { *(.debug_funcnames) } -+ .debug_typenames 0 : { *(.debug_typenames) } -+ .debug_varnames 0 : { *(.debug_varnames) } -+ -+ ${RELOCATING+${OTHER_RELOCATING_SECTIONS}} -+ -+ /* These must appear regardless of ${RELOCATING}. */ -+ ${OTHER_SECTIONS} -+} -+EOF ---- a/opcodes/configure -+++ b/opcodes/configure -@@ -11885,6 +11885,7 @@ if test x${all_targets} = xfalse ; then - bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; - bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; -+ bfd_ubicom32_arch) ta="$ta ubicom32-asm.lo ubicom32-desc.lo ubicom32-dis.lo ubicom32-ibld.lo ubicom32-opc.lo" using_cgen=yes ;; - bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; ---- a/opcodes/configure.in -+++ b/opcodes/configure.in -@@ -245,6 +245,7 @@ if test x${all_targets} = xfalse ; then - bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; - bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; -+ bfd_ubicom32_arch) ta="$ta ubicom32-asm.lo ubicom32-desc.lo ubicom32-dis.lo ubicom32-ibld.lo ubicom32-opc.lo" using_cgen=yes ;; - bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; ---- a/opcodes/disassemble.c -+++ b/opcodes/disassemble.c -@@ -77,6 +77,7 @@ - #define ARCH_tic4x - #define ARCH_tic54x - #define ARCH_tic80 -+#define ARCH_ubicom32 - #define ARCH_v850 - #define ARCH_vax - #define ARCH_w65 -@@ -386,6 +387,11 @@ disassembler (abfd) - disassemble = print_insn_tic80; - break; - #endif -+#ifdef ARCH_ubicom32 -+ case bfd_arch_ubicom32: -+ disassemble = print_insn_ubicom32; -+ break; -+#endif - #ifdef ARCH_v850 - case bfd_arch_v850: - disassemble = print_insn_v850; ---- a/opcodes/Makefile.am -+++ b/opcodes/Makefile.am -@@ -50,6 +50,7 @@ HFILES = \ - sh-opc.h \ - sh64-opc.h \ - sysdep.h \ -+ ubicom32-desc.h ubicom32-opc.h \ - w65-opc.h \ - xc16x-desc.h xc16x-opc.h \ - xstormy16-desc.h xstormy16-opc.h \ -@@ -191,6 +192,11 @@ CFILES = \ - tic54x-opc.c \ - tic80-dis.c \ - tic80-opc.c \ -+ ubicom32-asm.c \ -+ ubicom32-desc.c \ -+ ubicom32-dis.c \ -+ ubicom32-ibld.c \ -+ ubicom32-opc.c \ - v850-dis.c \ - v850-opc.c \ - vax-dis.c \ -@@ -333,6 +339,11 @@ ALL_MACHINES = \ - tic54x-opc.lo \ - tic80-dis.lo \ - tic80-opc.lo \ -+ ubicom32-asm.lo \ -+ ubicom32-desc.lo \ -+ ubicom32-dis.lo \ -+ ubicom32-ibld.lo \ -+ ubicom32-opc.lo \ - v850-dis.lo \ - v850-opc.lo \ - vax-dis.lo \ -@@ -421,7 +432,7 @@ uninstall_libopcodes: - rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h - - CLEANFILES = \ -- stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ -+ stamp-ubicom32 stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ - stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ - libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 - -@@ -438,10 +449,11 @@ CGENDEPS = \ - $(CGENDIR)/opc-opinst.scm \ - cgen-asm.in cgen-dis.in cgen-ibld.in - --CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 -+CGEN_CPUS = fr30 frv ip2k ubicom32 m32c m32r mep mt openrisc xc16x xstormy16 - - if CGEN_MAINT - IP2K_DEPS = stamp-ip2k -+UBICOM32_DEPS = stamp-ubicom32 - M32C_DEPS = stamp-m32c - M32R_DEPS = stamp-m32r - FR30_DEPS = stamp-fr30 -@@ -454,6 +466,7 @@ XC16X_DEPS = stamp-xc16x - XSTORMY16_DEPS = stamp-xstormy16 - else - IP2K_DEPS = -+UBICOM32_DEPS = - M32C_DEPS = - M32R_DEPS = - FR30_DEPS = -@@ -482,6 +495,10 @@ run-cgen-all: - .PHONY: run-cgen-all - - # For now, require developers to configure with --enable-cgen-maint. -+$(srcdir)/ubicom32-desc.h $(srcdir)/ubicom32-desc.c $(srcdir)/ubicom32-opc.h $(srcdir)/ubicom32-opc.c $(srcdir)/ubicom32-ibld.c $(srcdir)/ubicom32-asm.c $(srcdir)/ubicom32-dis.c: $(UBICOM32_DEPS) -+# @true -+stamp-ubicom32: $(CGENDEPS) $(CPUDIR)/ubicom32.cpu $(CPUDIR)/ubicom32.opc -+ $(MAKE) run-cgen arch=ubicom32 prefix=ubicom32 options= extrafiles= - $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) - @true - stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc -@@ -823,6 +840,34 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/anside - ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c \ - ia64-opc-d.c - ia64-asmtab.lo: ia64-asmtab.c -+ubicom32-asm.lo: ubicom32-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ -+ $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h -+ubicom32-desc.lo: ubicom32-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ -+ $(INCDIR)/xregex.h $(INCDIR)/xregex2.h -+ubicom32-dis.lo: ubicom32-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ -+ $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ opintl.h -+ubicom32-ibld.lo: ubicom32-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ -+ $(BFD_H) $(INCDIR)/symcat.h ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h \ -+ $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ -+ ubicom32-opc.h opintl.h $(INCDIR)/safe-ctype.h -+ubicom32-opc.lo: ubicom32-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h - ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \ - $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \ ---- a/opcodes/Makefile.in -+++ b/opcodes/Makefile.in -@@ -278,6 +278,7 @@ HFILES = \ - sh-opc.h \ - sh64-opc.h \ - sysdep.h \ -+ ubicom32-desc.h ubicom32-opc.h \ - w65-opc.h \ - xc16x-desc.h xc16x-opc.h \ - xstormy16-desc.h xstormy16-opc.h \ -@@ -420,6 +421,11 @@ CFILES = \ - tic54x-opc.c \ - tic80-dis.c \ - tic80-opc.c \ -+ ubicom32-asm.c \ -+ ubicom32-desc.c \ -+ ubicom32-dis.c \ -+ ubicom32-ibld.c \ -+ ubicom32-opc.c \ - v850-dis.c \ - v850-opc.c \ - vax-dis.c \ -@@ -562,6 +568,11 @@ ALL_MACHINES = \ - tic54x-opc.lo \ - tic80-dis.lo \ - tic80-opc.lo \ -+ ubicom32-asm.lo \ -+ ubicom32-desc.lo \ -+ ubicom32-dis.lo \ -+ ubicom32-ibld.lo \ -+ ubicom32-opc.lo \ - v850-dis.lo \ - v850-opc.lo \ - vax-dis.lo \ -@@ -604,7 +615,7 @@ libopcodes_la_LDFLAGS = -release `cat .. - noinst_LIBRARIES = libopcodes.a - POTFILES = $(HFILES) $(CFILES) - CLEANFILES = \ -- stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ -+ stamp-ip2k stamp-ubicom32 stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ - stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ - libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 - -@@ -619,9 +630,11 @@ CGENDEPS = \ - $(CGENDIR)/opc-opinst.scm \ - cgen-asm.in cgen-dis.in cgen-ibld.in - --CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 -+CGEN_CPUS = fr30 frv ip2k ubicom32 m32c m32r mep mt openrisc xc16x xstormy16 - @CGEN_MAINT_FALSE@IP2K_DEPS = - @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k -+@CGEN_MAINT_FALSE@UBICOM32_DEPS = -+@CGEN_MAINT_TRUE@UBICOM32_DEPS = stamp-ubicom32 - @CGEN_MAINT_FALSE@M32C_DEPS = - @CGEN_MAINT_TRUE@M32C_DEPS = stamp-m32c - @CGEN_MAINT_FALSE@M32R_DEPS = -@@ -1035,6 +1048,11 @@ run-cgen-all: - .PHONY: run-cgen-all - - # For now, require developers to configure with --enable-cgen-maint. -+$(srcdir)/ubicom32-desc.h $(srcdir)/ubicom32-desc.c $(srcdir)/ubicom32-opc.h $(srcdir)/ubicom32-opc.c $(srcdir)/ubicom32-ibld.c $(srcdir)/ubicom32-asm.c $(srcdir)/ubicom32-dis.c: $(UBICOM32_DEPS) -+# @true -+stamp-ubicom32: $(CGENDEPS) $(CPUDIR)/ubicom32.cpu $(CPUDIR)/ubicom32.opc -+ $(MAKE) run-cgen arch=ubicom32 prefix=ubicom32 \ -+ archfile=$(CPUDIR)/ubicom32.cpu opcfile=$(CPUDIR)/ubicom32.opc options= extrafiles= - $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) - @true - stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc -@@ -1375,6 +1393,34 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/anside - ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c \ - ia64-opc-d.c - ia64-asmtab.lo: ia64-asmtab.c -+ubicom32-asm.lo: ubicom32-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ -+ $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h -+ubicom32-desc.lo: ubicom32-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ -+ $(INCDIR)/xregex.h $(INCDIR)/xregex2.h -+ubicom32-dis.lo: ubicom32-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ -+ $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ opintl.h -+ubicom32-ibld.lo: ubicom32-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ -+ $(BFD_H) $(INCDIR)/symcat.h ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h \ -+ $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ -+ ubicom32-opc.h opintl.h $(INCDIR)/safe-ctype.h -+ubicom32-opc.lo: ubicom32-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ -+ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ -+ ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ -+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \ -+ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h - ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \ - $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \ ---- /dev/null -+++ b/opcodes/ubicom32-asm.c -@@ -0,0 +1,1863 @@ -+/* Assembler interface for targets using CGEN. -*- C -*- -+ CGEN: Cpu tools GENerator -+ -+ THIS FILE IS MACHINE GENERATED WITH CGEN. -+ - the resultant file is machine generated, cgen-asm.in isn't -+ -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007 -+ Free Software Foundation, Inc. -+ -+ This file is part of libopcodes. -+ -+ This library is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -+ -+ -+/* ??? Eventually more and more of this stuff can go to cpu-independent files. -+ Keep that in mind. */ -+ -+#include "sysdep.h" -+#include -+#include "ansidecl.h" -+#include "bfd.h" -+#include "symcat.h" -+#include "ubicom32-desc.h" -+#include "ubicom32-opc.h" -+#include "opintl.h" -+#include "xregex.h" -+#include "libiberty.h" -+#include "safe-ctype.h" -+ -+#undef min -+#define min(a,b) ((a) < (b) ? (a) : (b)) -+#undef max -+#define max(a,b) ((a) > (b) ? (a) : (b)) -+ -+static const char * parse_insn_normal -+ (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); -+ -+/* -- assembler routines inserted here. */ -+ -+/* -- asm.c */ -+ -+/* Directly addressable registers on the UBICOM32. -+ */ -+ -+#define RW 0 /* read/write */ -+#define RO 1 /* read-only */ -+#define WO 2 /* write-only */ -+ -+struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mercury[] = { -+ { 0x0, "d0", RW, }, /* data registers */ -+ /* d1, d2 and d3 are later */ -+ { 0x10, "d4", RW, }, -+ { 0x14, "d5", RW, }, -+ { 0x18, "d6", RW, }, -+ { 0x1c, "d7", RW, }, -+ { 0x20, "d8", RW, }, -+ { 0x24, "d9", RW, }, -+ { 0x28, "d10", RW, }, -+ { 0x2c, "d11", RW, }, -+ { 0x30, "d12", RW, }, -+ { 0x34, "d13", RW, }, -+ { 0x38, "d14", RW, }, -+ { 0x3c, "d15", RW, }, -+ { 0x4, "d1", RW, }, /* put them here where they work */ -+ { 0x8, "d2", RW, }, -+ { 0xc, "d3", RW, }, -+ { A0_ADDRESS, "a0", RW, }, /* address registers */ -+ { A1_ADDRESS, "a1", RW, }, -+ { A2_ADDRESS, "a2", RW, }, -+ { A3_ADDRESS, "a3", RW, }, -+ { A4_ADDRESS, "a4", RW, }, -+ { A5_ADDRESS, "a5", RW, }, -+ { A6_ADDRESS, "a6", RW, }, -+ { A7_ADDRESS, "sp", RW, }, /* sp is a7; first so we use it */ -+ { A7_ADDRESS, "a7", RW, }, -+ { 0xa0, "mac_hi", RW, }, -+ { 0xa4, "mac_lo", RW, }, -+ { 0xa8, "mac_rc16", RW, }, -+ { 0xac, "source3", RW, }, -+ { 0xac, "source_3", RW, }, -+ { 0xb0, "context_cnt", RO,}, -+ { 0xb0, "inst_cnt", RO,}, -+ { 0xb4, "csr", RW, }, -+ { 0xb8, "rosr", RO, }, -+ { 0xbc, "iread_data", RW, }, -+ { 0xc0, "int_mask0", RW, }, -+ { 0xc4, "int_mask1", RW, }, -+ /* 0xc8 - 0xcf reserved for future interrupt masks */ -+ { 0xd0, "pc", RW, }, -+ /* 0xd4 - ff reserved */ -+ { 0x100, "chip_id", RO, }, -+ { 0x104, "int_stat0", RO, }, -+ { 0x108, "int_stat1", RO, }, -+ /* 0x10c - 0x113 reserved for future interrupt masks */ -+ { 0x114, "int_set0", WO, }, -+ { 0x118, "int_set1", WO, }, -+ /* 0x11c - 0x123 reserved for future interrupt set */ -+ { 0x124, "int_clr0", WO, }, -+ { 0x128, "int_clr1", WO, }, -+ /* 0x13c - 0x133 reserved for future interrupt clear */ -+ { 0x134, "global_ctrl", RW, }, -+ { 0x13c, "mt_active_set", WO, }, -+ { 0x140, "mt_active_clr", WO, }, -+ { 0x138, "mt_active", RO, }, -+ { 0x148, "mt_dbg_active_set", WO, }, -+ { 0x144, "mt_dbg_active", RO, }, -+ { 0x14C, "mt_en", RW, }, -+ { 0x150, "mt_hpri", RW, }, -+ { 0x150, "mt_pri", RW, }, -+ { 0x154, "mt_hrt", RW, }, -+ { 0x154, "mt_sched", RW, }, -+ { 0x15C, "mt_break_clr", WO, }, -+ { 0x158, "mt_break", RO, }, -+ { 0x160, "mt_single_step", RW, }, -+ { 0x164, "mt_min_delay_en", RW, }, -+ { 0x164, "mt_min_del_en", RW, }, -+ -+ { 0x16c, "perr_addr", RO, }, -+ { 0x178, "dcapt_tnum", RO, }, -+ { 0x174, "dcapt_pc", RO, }, -+ { 0x170, "dcapt", RW, }, -+ /* 0x17c - 0x1ff reserved */ -+ { 0x17c, "mt_dbg_active_clr", WO, }, -+ { 0x180, "scratchpad0", RW, }, -+ { 0x184, "scratchpad1", RW, }, -+ { 0x188, "scratchpad2", RW, }, -+ { 0x18c, "scratchpad3", RW, }, -+ -+ { 0x0, 0, RW, }, -+}; -+ -+struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mars[] = { -+ { 0x0, "d0", RW, }, /* data registers */ -+ /* d1, d2 and d3 are later */ -+ { 0x10, "d4", RW, }, -+ { 0x14, "d5", RW, }, -+ { 0x18, "d6", RW, }, -+ { 0x1c, "d7", RW, }, -+ { 0x20, "d8", RW, }, -+ { 0x24, "d9", RW, }, -+ { 0x28, "d10", RW, }, -+ { 0x2c, "d11", RW, }, -+ { 0x30, "d12", RW, }, -+ { 0x34, "d13", RW, }, -+ { 0x38, "d14", RW, }, -+ { 0x3c, "d15", RW, }, -+ { 0x4, "d1", RW, }, /* put them here where they work */ -+ { 0x8, "d2", RW, }, -+ { 0xc, "d3", RW, }, -+ { A0_ADDRESS, "a0", RW, }, /* address registers */ -+ { A1_ADDRESS, "a1", RW, }, -+ { A2_ADDRESS, "a2", RW, }, -+ { A3_ADDRESS, "a3", RW, }, -+ { A4_ADDRESS, "a4", RW, }, -+ { A5_ADDRESS, "a5", RW, }, -+ { A6_ADDRESS, "a6", RW, }, -+ { A7_ADDRESS, "sp", RW, }, /* sp is a7; first so we use it */ -+ { A7_ADDRESS, "a7", RW, }, -+ { 0xa0, "mac_hi", RW, }, -+ { 0xa0, "acc0_hi", RW, }, /* mac_hi and mac_lo are also known as acc0_hi and acc0_lo */ -+ { 0xa4, "mac_lo", RW, }, -+ { 0xa4, "acc0_lo", RW, }, -+ { 0xa8, "mac_rc16", RW, }, -+ { 0xac, "source3", RW, }, -+ { 0xac, "source_3", RW, }, -+ { 0xb0, "context_cnt", RO,}, -+ { 0xb0, "inst_cnt", RO,}, -+ { 0xb4, "csr", RW, }, -+ { 0xb8, "rosr", RO, }, -+ { 0xbc, "iread_data", RW, }, -+ { 0xc0, "int_mask0", RW, }, -+ { 0xc4, "int_mask1", RW, }, -+ /* 0xc8 - 0xcf reserved for future interrupt masks */ -+ { 0xd0, "pc", RW, }, -+ { 0xd4, "trap_cause", RW, }, -+ { 0xd8, "acc1_hi", RW, }, /* Defines for acc1 */ -+ { 0xdc, "acc1_lo", RW, }, -+ { 0xe0, "previous_pc", RO, }, -+ -+ /* 0xe4 - ff reserved */ -+ { 0x100, "chip_id", RO, }, -+ { 0x104, "int_stat0", RO, }, -+ { 0x108, "int_stat1", RO, }, -+ /* 0x10c - 0x113 reserved for future interrupt masks */ -+ { 0x114, "int_set0", WO, }, -+ { 0x118, "int_set1", WO, }, -+ /* 0x11c - 0x123 reserved for future interrupt set */ -+ { 0x124, "int_clr0", WO, }, -+ { 0x128, "int_clr1", WO, }, -+ /* 0x130 - 0x133 reserved for future interrupt clear */ -+ { 0x134, "global_ctrl", RW, }, -+ { 0x13c, "mt_active_set", WO, }, -+ { 0x140, "mt_active_clr", WO, }, -+ { 0x138, "mt_active", RO, }, -+ { 0x148, "mt_dbg_active_set", WO, }, -+ { 0x144, "mt_dbg_active", RO, }, -+ { 0x14C, "mt_en", RW, }, -+ { 0x150, "mt_hpri", RW, }, -+ { 0x150, "mt_pri", RW, }, -+ { 0x154, "mt_hrt", RW, }, -+ { 0x154, "mt_sched", RW, }, -+ { 0x15C, "mt_break_clr", WO, }, -+ { 0x158, "mt_break", RO, }, -+ { 0x160, "mt_single_step", RW, }, -+ { 0x164, "mt_min_delay_en", RW, }, -+ { 0x164, "mt_min_del_en", RW, }, -+ { 0x168, "mt_break_set", WO, }, -+ /* 0x16c - 0x16f reserved */ -+ { 0x170, "dcapt", RW, }, -+ /* 0x174 - 0x17b reserved */ -+ { 0x17c, "mt_dbg_active_clr", WO, }, -+ { 0x180, "scratchpad0", RW, }, -+ { 0x184, "scratchpad1", RW, }, -+ { 0x188, "scratchpad2", RW, }, -+ { 0x18c, "scratchpad3", RW, }, -+ -+ /* 0x190 - 0x19f Reserved */ -+ { 0x1a0, "chip_cfg", RW, }, -+ { 0x1a4, "mt_i_blocked", RO, }, -+ { 0x1a8, "mt_d_blocked", RO, }, -+ { 0x1ac, "mt_i_blocked_set", WO}, -+ { 0x1b0, "mt_d_blocked_set", WO}, -+ { 0x1b4, "mt_blocked_clr", WO}, -+ { 0x1b8, "mt_trap_en", RW, }, -+ { 0x1bc, "mt_trap", RO, }, -+ { 0x1c0, "mt_trap_set", WO, }, -+ { 0x1c4, "mt_trap_clr", WO, }, -+ /* 0x1c8-0x1FF Reserved */ -+ { 0x200, "i_range0_hi", RW}, -+ { 0x204, "i_range1_hi", RW}, -+ { 0x208, "i_range2_hi", RW}, -+ { 0x20c, "i_range3_hi", RW}, -+ -+ /* 0x210-0x21f Reserved */ -+ { 0x220, "i_range0_lo", RW}, -+ { 0x224, "i_range1_lo", RW}, -+ { 0x228, "i_range2_lo", RW}, -+ { 0x22c, "i_range3_lo", RW}, -+ -+ /* 0x230-0x23f Reserved */ -+ { 0x240, "i_range0_en", RW}, -+ { 0x244, "i_range1_en", RW}, -+ { 0x248, "i_range2_en", RW}, -+ { 0x24c, "i_range3_en", RW}, -+ -+ /* 0x250-0x25f Reserved */ -+ { 0x260, "d_range0_hi", RW}, -+ { 0x264, "d_range1_hi", RW}, -+ { 0x268, "d_range2_hi", RW}, -+ { 0x26c, "d_range3_hi", RW}, -+ { 0x270, "d_range4_hi", RW}, -+ -+ /* 0x274-0x27f Reserved */ -+ { 0x280, "d_range0_lo", RW}, -+ { 0x284, "d_range1_lo", RW}, -+ { 0x288, "d_range2_lo", RW}, -+ { 0x28c, "d_range3_lo", RW}, -+ { 0x290, "d_range4_lo", RW}, -+ -+ /* 0x294-0x29f Reserved */ -+ { 0x2a0, "d_range0_en", RW}, -+ { 0x2a4, "d_range1_en", RW}, -+ { 0x2a8, "d_range2_en", RW}, -+ { 0x2ac, "d_range3_en", RW}, -+ { 0x2b0, "d_range4_en", RW}, -+ -+ /* 0x2b4-0x3ff Reserved */ -+ -+ { 0x0, 0, RW, }, -+}; -+ -+/* t_is_set will be 1 if .t is set for the madd.2 and msub.2 instructions */ -+static unsigned char t_is_set =0; -+ -+static const char * -+parse_t_is_set_for_addsub ( -+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ const char **strp, -+ CGEN_KEYWORD *keyword_table, -+ long *valuep) -+{ -+ const char *errmsg; -+ -+ t_is_set = 0; -+ -+ errmsg = cgen_parse_keyword (cd, strp, keyword_table, valuep); -+ if (errmsg) -+ { -+ t_is_set = 0; -+ -+ return errmsg; -+ } -+ -+ if((int)*valuep) -+ t_is_set = 1; -+ -+ return NULL; -+} -+ -+char myerrmsg[128]; -+ -+/* -+ * If accumulator is selected for madd.2 and msub.2 instructions then -+ * the T bit should not be selected. Flag an assembler error in those -+ * cases. -+ */ -+static const char * -+parse_acc_for_addsub (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ const char **strp, -+ CGEN_KEYWORD *keyword_table, -+ long *valuep) -+{ -+ const char *errmsg; -+ -+ errmsg = cgen_parse_keyword (cd, strp, keyword_table, valuep); -+ if (errmsg) -+ { -+ t_is_set = 0; -+ -+ return errmsg; -+ } -+ -+ -+ if(t_is_set) -+ { -+ /* This is erroneous. */ -+ sprintf(myerrmsg, "Extenstion \".t\" is illegal when using acc%d as Source 2 register.", (int)*valuep); -+ t_is_set=0; -+ return (myerrmsg); -+ } -+ -+ t_is_set=0; -+ return NULL; -+} -+ -+/* -+ * For dsp madd/msub cases if S2 is a data register then t_is_set flag should be set to zero. -+ */ -+static const char * -+parse_dr_for_addsub (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ const char **strp, -+ CGEN_KEYWORD *keyword_table, -+ long *valuep) -+{ -+ const char *errmsg; -+ -+ errmsg = cgen_parse_keyword (cd, strp, keyword_table, valuep); -+ if (errmsg) -+ { -+ t_is_set = 0; -+ -+ return errmsg; -+ } -+ t_is_set=0; -+ return NULL; -+} -+ -+static const char * -+parse_bit5 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ const char *errmsg; -+ char mode = 0; -+ long count = 0; -+ unsigned long value; -+ -+ if (strncmp (*strp, "%bit", 4) == 0) -+ { -+ *strp += 4; -+ mode = 1; -+ } -+ else if (strncmp (*strp, "%msbbit", 7) == 0) -+ { -+ *strp += 7; -+ mode = 2; -+ } -+ else if (strncmp (*strp, "%lsbbit", 7) == 0) -+ { -+ *strp += 7; -+ mode = 3; -+ } -+ -+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -+ if (errmsg) { -+ return errmsg; -+ } -+ -+ if (mode) { -+ value = (unsigned long) *valuep; -+ if (value == 0) { -+ errmsg = _("Attempt to find bit index of 0"); -+ return errmsg; -+ } -+ -+ if (mode == 1) { -+ count = 31; -+ while ((value & 0x80000000) == 0) { -+ count--; -+ value <<= 1; -+ } -+ if ((value & 0x7FFFFFFF) != 0) { -+ errmsg = _("More than one bit set in bitmask"); -+ return errmsg; -+ } -+ } else if (mode == 2) { -+ count = 31; -+ while ((value & 0x80000000) == 0) { -+ count--; -+ value <<= 1; -+ } -+ } else if (mode == 3) { -+ count = 0; -+ while ((value & 0x00000001) == 0) { -+ count++; -+ value >>= 1; -+ } -+ } -+ -+ *valuep = count; -+ } -+ -+ return errmsg; -+} -+ -+/* -+ * For dsp madd/msub cases if S2 is a #bit5 then t_is_set flag should be set to zero. -+ */ -+static const char * -+parse_bit5_for_addsub (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ const char *errmsg; -+ -+ errmsg = parse_bit5(cd, strp, opindex, valuep); -+ if (errmsg) -+ { -+ t_is_set = 0; -+ -+ return errmsg; -+ } -+ t_is_set=0; -+ return NULL; -+} -+ -+/* Parse signed 4 bit immediate value, being careful (hacky) to avoid -+ eating a `++' that might be present */ -+static const char * -+parse_imm4 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep, -+ int size) -+{ -+ const char *errmsg; -+ char *plusplus; -+ long value; -+ -+ plusplus = strstr(*strp, "++"); -+ if (plusplus) -+ *plusplus = 0; -+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); -+ if (plusplus) -+ *plusplus = '+'; -+ -+ if (errmsg == NULL) -+ { -+ if ((size == 2 && (value % 2)) || -+ (size == 4 && (value % 4))) -+ errmsg = _("unaligned increment"); -+ else if ((size == 1 && (value < -8 || value > 7)) || -+ (size == 2 && (value < -16 || value > 15)) || -+ (size == 4 && (value < -32 || value > 31))) -+ errmsg = _("out of bounds increment"); -+ else -+ *valuep = value; -+ } -+ return errmsg; -+} -+ -+/* as above, for single byte addresses */ -+static const char * -+parse_imm4_1 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ return parse_imm4 (cd, strp, opindex, valuep, 1); -+} -+ -+/* as above, for half-word addresses */ -+static const char * -+parse_imm4_2 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ return parse_imm4 (cd, strp, opindex, valuep, 2); -+} -+ -+/* as above, for word addresses */ -+static const char * -+parse_imm4_4 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ return parse_imm4 (cd, strp, opindex, valuep, 4); -+} -+ -+/* Parse a direct address. This can be either `$xx' or a Register -+ Mnemonic. -+ */ -+static const char * -+parse_direct_addr (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep, -+ int isdest) -+{ -+ const char *errmsg = NULL; -+ bfd_vma value; -+ struct ubicom32_cgen_data_space_map *cur; -+ size_t len; -+ -+ if(cd->machs & (1<name; cur++) -+ if (strncasecmp(cur->name, *strp, (len = strlen(cur->name))) == 0 && -+ !ISALNUM((*strp)[len]) && (*strp)[len] != '_' ) -+ { -+ *strp += len; -+ /* fail if specifying a read-only register as a destination */ -+ if (isdest && cur->type == RO) -+ return _("attempt to write to read-only register"); -+ -+ /* fail if specifying a write-only register as a source */ -+ if ((isdest==0) && cur->type == WO) -+ return _("attempt to read a write-only register"); -+ value = cur->address; -+ errmsg = NULL; -+ break; -+ } -+ -+ /* Not found: try parsing it as a literal */ -+ if (cur->name == NULL) -+ { -+ char *plusplus; -+ if (**strp == '(') -+ { -+ return _("parentheses are reserved for indirect addressing"); -+ } -+ -+ if (strncasecmp(*strp, "%f", 2) == 0) -+ { -+ *valuep = 0; -+ return NULL; -+ } -+ -+ /* we want to avoid parsing a negative post-increment expression as a numeric -+ expression because the parser assumes zeroes exist between the pluses and -+ issues an extraneous warning message. */ -+ plusplus = strstr(*strp, "++"); -+ if (plusplus) -+ *plusplus = 0; -+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); -+ if (plusplus) -+ *plusplus = '+'; -+ -+ if (errmsg) -+ return errmsg; -+ } -+ -+ value &= 0x3ff; -+ *valuep = value; -+ return errmsg; -+} -+ -+static const char * -+parse_d_direct_addr (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ return parse_direct_addr (cd, strp, opindex, valuep, 1); -+} -+ -+static const char * -+parse_s1_direct_addr (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ long *valuep) -+{ -+ return parse_direct_addr (cd, strp, opindex, valuep, 0); -+} -+ -+/* support for source-1 and destination operand 7-bit immediates for indirect addressing */ -+static const char *imm7_1_rangemsg = "7-bit byte immediate value out of range"; -+static const char *imm7_2_rangemsg = "7-bit halfword immediate value out of range"; -+static const char *imm7_4_rangemsg = "7-bit word immediate value out of range"; -+static const char *imm7_pdec_rangemsg = "Pdec offset out of range. Allowed range is >=4 and <=512."; -+static const char *imm7_2_maskmsg = "7-bit halfword immediate not a multiple of 2"; -+static const char *imm7_4_maskmsg = "7-bit word immediate not a multiple of 4"; -+ -+/* Parse 7-bit immediates, allow %lo() operator */ -+static const char * -+parse_imm7_basic (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep, -+ const char *rangemsg, -+ const char *maskmsg, -+ bfd_vma max, -+ int mask, -+ int reloc) -+{ -+ const char *errmsg; -+ enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; -+ bfd_vma value; -+ int newreloc; -+ -+ /* in this case we want low 7-bits to accompany the 24-bit immediate of a moveai instruction */ -+ if (strncasecmp (*strp, "%lo(", 4) == 0) -+ { -+ *strp += 4; -+ errmsg = cgen_parse_address (cd, strp, opindex, reloc, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0x7f; /* always want 7 bits, regardless of imm7 type */ -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%got_lo(", strlen("%got_lo(")) == 0) -+ { -+ *strp += strlen("%got_lo("); -+ -+ /* Switch the relocation to the GOT relocation. */ -+ switch(reloc) -+ { -+ case BFD_RELOC_UBICOM32_LO7_S: -+ reloc = BFD_RELOC_UBICOM32_GOT_LO7_S; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_2_S: -+ reloc = BFD_RELOC_UBICOM32_GOT_LO7_2_S; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_4_S: -+ reloc = BFD_RELOC_UBICOM32_GOT_LO7_4_S; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_D: -+ reloc = BFD_RELOC_UBICOM32_GOT_LO7_D; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_2_D: -+ reloc = BFD_RELOC_UBICOM32_GOT_LO7_2_D; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_4_D: -+ reloc = BFD_RELOC_UBICOM32_GOT_LO7_4_D; -+ break; -+ } -+ errmsg = cgen_parse_address (cd, strp, opindex, reloc, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0x7f; /* always want 7 bits, regardless of imm7 type */ -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%funcdesc_got_lo(", strlen("%funcdesc_got_lo(")) == 0) -+ { -+ *strp += strlen("%funcdesc_got_lo("); -+ -+ /* Switch the relocation to the GOT relocation. */ -+ switch(reloc) -+ { -+ case BFD_RELOC_UBICOM32_LO7_S: -+ reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_2_S: -+ reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_4_S: -+ reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_D: -+ reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_2_D: -+ reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D; -+ break; -+ case BFD_RELOC_UBICOM32_LO7_4_D: -+ reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D; -+ break; -+ } -+ errmsg = cgen_parse_address (cd, strp, opindex, reloc, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0x7f; /* always want 7 bits, regardless of imm7 type */ -+ *valuep = value; -+ return errmsg; -+ } -+ else -+ { -+ if (**strp == '(') -+ { -+ return _("parentheses are reserved for indirect addressing"); -+ } -+ -+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); -+ } -+ -+ if (errmsg == NULL) -+ { -+ if (value > max) -+ return rangemsg; -+ if (value & mask) -+ return maskmsg; -+ } -+ -+ *valuep = value & max; -+ return errmsg; -+} -+ -+/* Parse 7-bit immediates, allow %lo() operator */ -+static const char * -+parse_imm7_pdec (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep, -+ const char *rangemsg, -+ const char *maskmsg, -+ int reloc) -+{ -+ const char *errmsg; -+ enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; -+ bfd_vma value; -+ -+ /* in this case we want low 7-bits to accompany the 24-bit immediate of a moveai instruction */ -+ if (strncasecmp (*strp, "%lo(", 4) == 0) -+ { -+ *strp += 4; -+ errmsg = cgen_parse_address (cd, strp, opindex, reloc, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0x7f; /* always want 7 bits, regardless of imm7 type */ -+ *valuep = value; -+ return errmsg; -+ } -+ else -+ { -+ if (**strp == '(') -+ { -+ return _("parentheses are reserved for indirect addressing"); -+ } -+ -+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); -+ } -+ -+ if (errmsg == NULL) -+ { -+ if (((long)value > 512) || ((long)value < 4)) -+ return rangemsg; -+ if (value & 0x3) -+ return maskmsg; -+ } -+ -+ *valuep = value; -+ return errmsg; -+} -+ -+/* single byte imm7 */ -+static const char * -+parse_imm7_1_s (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ return parse_imm7_basic (cd, strp, opindex, valuep, _(imm7_1_rangemsg), -+ NULL, 0x7f, 0, BFD_RELOC_UBICOM32_LO7_S); -+} -+ -+/* halfword imm7 */ -+static const char * -+parse_imm7_2_s (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ return parse_imm7_basic (cd, strp, opindex, valuep, -+ _(imm7_2_rangemsg), -+ _(imm7_2_maskmsg), -+ 0xfe, 0x1, BFD_RELOC_UBICOM32_LO7_2_S); -+} -+ -+/* word imm7 */ -+static const char * -+parse_imm7_4_s (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ return parse_imm7_basic (cd, strp, opindex, valuep, -+ _(imm7_4_rangemsg), -+ _(imm7_4_maskmsg), -+ 0x1fc, 0x3, BFD_RELOC_UBICOM32_LO7_4_S); -+} -+ -+/* word imm7 */ -+static const char * -+parse_pdec_imm7_4_s (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ unsigned long value; -+ const char *errmsg = parse_imm7_pdec (cd, strp, opindex, &value, -+ _(imm7_pdec_rangemsg), -+ _(imm7_4_maskmsg), -+ BFD_RELOC_UBICOM32_LO7_4_S); -+ -+ if(errmsg == NULL) -+ { -+ /* at this point we have a valid value. Take the 2's comp and truncate to 7 bits */ -+ if(value == 0) -+ return _("Offset for PDEC source cannot be 0"); -+ -+ value = ~value; -+ value ++; -+ value &= 0x1fc; -+ *valuep = value; -+ } -+ -+ return errmsg; -+} -+ -+/* single byte dest imm7 */ -+static const char * -+parse_imm7_1_d (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ return parse_imm7_basic (cd, strp, opindex, valuep, _(imm7_1_rangemsg), -+ NULL, 0x7f, 0, BFD_RELOC_UBICOM32_LO7_D); -+} -+ -+/* halfword dest imm7 */ -+static const char * -+parse_imm7_2_d (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ return parse_imm7_basic (cd, strp, opindex, valuep, -+ _(imm7_2_rangemsg), -+ _(imm7_2_maskmsg), -+ 0xfe, 0x1, BFD_RELOC_UBICOM32_LO7_2_D); -+} -+ -+/* word dest imm7 */ -+static const char * -+parse_imm7_4_d (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ return parse_imm7_basic (cd, strp, opindex, valuep, -+ _(imm7_4_rangemsg), -+ _(imm7_4_maskmsg), -+ 0x1fc, 0x3, BFD_RELOC_UBICOM32_LO7_4_D); -+} -+ -+/* Parse 16-bit immediate, allow %hi() or %lo() operators */ -+static const char * -+parse_imm16 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ const char *errmsg; -+ enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; -+ bfd_vma value; -+ -+ if (strncasecmp (*strp, "%hi(", 4) == 0) -+ { -+ *strp += 4; -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value >>= 16; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%got_hi(", strlen("%got_hi(")) == 0) -+ { -+ *strp += strlen("%got_hi("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOTOFFSET_HI, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value >>= 16; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%got_funcdesc_hi(", strlen("%got_funcdesc_hi(")) == 0) -+ { -+ *strp += strlen("%got_funcdesc_hi("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value >>= 16; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%lo(", 4) == 0) -+ { -+ *strp += 4; -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0xffff; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%got_lo(", strlen("%got_lo(")) == 0) -+ { -+ *strp += strlen("%got_lo("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOTOFFSET_LO, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0xffff; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%got_funcdesc_lo(", strlen("%got_funcdesc_lo(")) == 0) -+ { -+ *strp += strlen("%got_funcdesc_lo("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value &= 0xffff; -+ *valuep = value; -+ return errmsg; -+ } -+ else -+ { -+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); -+ } -+ -+ if (errmsg == NULL -+ && ((long)value > 65535 || (long)value < -32768)) -+ return _("16-bit immediate value out of range"); -+ -+ *valuep = value & 0xffff; -+ return errmsg; -+} -+ -+/* Parse 24-bit immediate for moveai instruction and allow %hi() operator */ -+static const char * -+parse_imm24 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ const char *errmsg; -+ enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; -+ bfd_vma value; -+ -+ if (strncasecmp (*strp, "%hi(", 4) == 0) -+ { -+ *strp += 4; -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_HI24, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value >>= 7; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%got_hi(", strlen("%got_hi(")) == 0) -+ { -+ *strp += strlen("%got_hi("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOT_HI24, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value >>= 7; -+ *valuep = value; -+ return errmsg; -+ } -+ else if (strncasecmp (*strp, "%funcdesc_got_hi(", strlen("%funcdesc_got_hi(")) == 0) -+ { -+ *strp += strlen("%funcdesc_got_hi("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24, -+ &result_type, &value); -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ if (errmsg == NULL -+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ value >>= 7; -+ *valuep = value; -+ return errmsg; -+ } -+ else -+ { -+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); -+ } -+ -+ if (errmsg == NULL -+ && ((long)value > 16777215 || (long)value < 0)) -+ return _("24-bit immediate value out of range"); -+ -+ *valuep = value; -+ return errmsg; -+} -+ -+static const char * -+parse_offset21 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ int reloc ATTRIBUTE_UNUSED, -+ enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, -+ unsigned long *valuep) -+{ -+ const char *errmsg; -+ enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; -+ bfd_vma value; -+ -+ if (**strp == '#') -+ { -+ ++*strp; -+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); -+ } -+ else -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_21_PCREL, -+ &result_type, &value); -+ -+ if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ { -+ /* we treat jmp #constant as being jump to pc + constant * 4 */ -+ if ((long)value > 1048575 || (long)value < -1048576) -+ return _("21-bit relative offset out of range"); -+ } -+ -+ *valuep = value & 0x7fffff; /* address is actually 23 bits before shift */ -+ return errmsg; -+} -+ -+static const char * -+parse_offset16 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ const char *errmsg; -+ enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; -+ bfd_vma value; -+ -+ /* in this case we want low 7-bits to accompany the 24-bit immediate of a moveai instruction */ -+ if (strncasecmp (*strp, "%lo(", 4) == 0) -+ { -+ *strp += 4; -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_LO7_CALLI, -+ &result_type, &value); -+ if (errmsg != NULL) -+ return errmsg; -+ -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ -+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ *valuep = value & 0x7c; -+ -+ return NULL; -+ } -+ -+ if (strncasecmp (*strp, "%got_lo(", strlen("%got_lo(")) == 0) -+ { -+ *strp += strlen("%got_lo("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOT_LO7_CALLI, -+ &result_type, &value); -+ if (errmsg != NULL) -+ return errmsg; -+ -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ -+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ *valuep = value & 0x7c; -+ -+ return NULL; -+ } -+ -+ if (strncasecmp (*strp, "%funcdesc_got_lo(", strlen("%funcdesc_got_lo(")) == 0) -+ { -+ *strp += strlen("%funcdesc_got_lo("); -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI, -+ &result_type, &value); -+ if (errmsg != NULL) -+ return errmsg; -+ -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ -+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ *valuep = value & 0x7c; -+ -+ return NULL; -+ } -+ -+ if (strncasecmp (*strp, "%lo18(", 6) == 0) -+ { -+ *strp += 6; -+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_LO16_CALLI, -+ &result_type, &value); -+ if (errmsg != NULL) -+ return errmsg; -+ -+ if (**strp != ')') -+ return _("missing `)'"); -+ ++*strp; -+ -+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) -+ *valuep = value & 0x0003fffc; -+ -+ return NULL; -+ } -+ -+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); -+ if (errmsg != NULL) -+ return errmsg; -+ -+ /* ensure calli constant within limits and is multiple of 4 */ -+ if (value & 0x3) -+ return _("calli offset must be multiple of 4"); -+ -+ if ((long)value > 131071 || (long)value < -131072) -+ return _("16-bit calli offset out of range"); -+ -+ *valuep = value & 0x0003fffc; /* address is actually 18 bits before shift */ -+ return NULL; -+} -+ -+static const char * -+parse_imm8 (CGEN_CPU_DESC cd, -+ const char **strp, -+ int opindex, -+ unsigned long *valuep) -+{ -+ const char *errmsg; -+ bfd_vma value; -+ int no_sign = 0; -+ -+ if (**strp == '0' && TOUPPER(*(*strp+1)) == 'X') -+ no_sign = 1; -+ -+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); -+ -+ if (errmsg == NULL) -+ { -+ if ((no_sign && ((long)value > 255)) || -+ (!no_sign && (((long)value > 127) || ((long)value < -128)))) -+ return _("8-bit immediate value out of range"); -+ } -+ -+ *valuep = value & 0xff; -+ return errmsg; -+} -+ -+/* -- dis.c */ -+ -+const char * ubicom32_cgen_parse_operand -+ (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); -+ -+/* Main entry point for operand parsing. -+ -+ This function is basically just a big switch statement. Earlier versions -+ used tables to look up the function to use, but -+ - if the table contains both assembler and disassembler functions then -+ the disassembler contains much of the assembler and vice-versa, -+ - there's a lot of inlining possibilities as things grow, -+ - using a switch statement avoids the function call overhead. -+ -+ This function could be moved into `parse_insn_normal', but keeping it -+ separate makes clear the interface between `parse_insn_normal' and each of -+ the handlers. */ -+ -+const char * -+ubicom32_cgen_parse_operand (CGEN_CPU_DESC cd, -+ int opindex, -+ const char ** strp, -+ CGEN_FIELDS * fields) -+{ -+ const char * errmsg = NULL; -+ /* Used by scalar operands that still need to be parsed. */ -+ long junk ATTRIBUTE_UNUSED; -+ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_Am); -+ break; -+ case UBICOM32_OPERAND_AN : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_An); -+ break; -+ case UBICOM32_OPERAND_C : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_C, & fields->f_C); -+ break; -+ case UBICOM32_OPERAND_DN : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_Dn); -+ break; -+ case UBICOM32_OPERAND_P : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_P, & fields->f_P); -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_ACC1HI, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_ACC1LO, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ errmsg = parse_bit5 (cd, strp, UBICOM32_OPERAND_BIT5, (unsigned long *) (& fields->f_bit5)); -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ errmsg = parse_bit5_for_addsub (cd, strp, UBICOM32_OPERAND_BIT5_ADDSUB, (unsigned long *) (& fields->f_bit5)); -+ break; -+ case UBICOM32_OPERAND_CC : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_cc, & fields->f_cond); -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_d_An); -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ errmsg = parse_d_direct_addr (cd, strp, UBICOM32_OPERAND_D_DIRECT_ADDR, (unsigned long *) (& fields->f_d_direct)); -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ errmsg = parse_imm4_1 (cd, strp, UBICOM32_OPERAND_D_I4_1, (long *) (& fields->f_d_i4_1)); -+ break; -+ case UBICOM32_OPERAND_D_I4_2 : -+ errmsg = parse_imm4_2 (cd, strp, UBICOM32_OPERAND_D_I4_2, (long *) (& fields->f_d_i4_2)); -+ break; -+ case UBICOM32_OPERAND_D_I4_4 : -+ errmsg = parse_imm4_4 (cd, strp, UBICOM32_OPERAND_D_I4_4, (long *) (& fields->f_d_i4_4)); -+ break; -+ case UBICOM32_OPERAND_D_IMM7_1 : -+ errmsg = parse_imm7_1_d (cd, strp, UBICOM32_OPERAND_D_IMM7_1, (unsigned long *) (& fields->f_d_imm7_1)); -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ errmsg = parse_imm7_2_d (cd, strp, UBICOM32_OPERAND_D_IMM7_2, (unsigned long *) (& fields->f_d_imm7_2)); -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ errmsg = parse_imm7_4_d (cd, strp, UBICOM32_OPERAND_D_IMM7_4, (unsigned long *) (& fields->f_d_imm7_4)); -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ errmsg = parse_imm8 (cd, strp, UBICOM32_OPERAND_D_IMM8, (long *) (& fields->f_d_imm8)); -+ break; -+ case UBICOM32_OPERAND_D_R : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_d_r); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ errmsg = parse_acc_for_addsub (cd, strp, & ubicom32_cgen_opval_acc_names, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_acc_names, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ errmsg = parse_dr_for_addsub (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_DSP_S2_SEL, (unsigned long *) (& fields->f_dsp_S2_sel)); -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_DSP_C, & fields->f_dsp_C); -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_DSP_Dest_A, & fields->f_dsp_destA); -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_DSP_T, & fields->f_dsp_T); -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ errmsg = parse_t_is_set_for_addsub (cd, strp, & ubicom32_cgen_opval_h_DSP_T_addsub, & fields->f_dsp_T); -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ errmsg = cgen_parse_signed_integer (cd, strp, UBICOM32_OPERAND_IMM16_1, (long *) (& fields->f_imm16_1)); -+ break; -+ case UBICOM32_OPERAND_IMM16_2 : -+ errmsg = parse_imm16 (cd, strp, UBICOM32_OPERAND_IMM16_2, (long *) (& fields->f_imm16_2)); -+ break; -+ case UBICOM32_OPERAND_IMM24 : -+ errmsg = parse_imm24 (cd, strp, UBICOM32_OPERAND_IMM24, (unsigned long *) (& fields->f_imm24)); -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_INTERRUPT, (unsigned long *) (& fields->f_int)); -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_IREAD, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_IRQ_0, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_IRQ_1, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_MACHI, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_MACLO, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ errmsg = parse_offset16 (cd, strp, UBICOM32_OPERAND_OFFSET16, (long *) (& fields->f_o16)); -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ { -+ bfd_vma value = 0; -+ errmsg = parse_offset21 (cd, strp, UBICOM32_OPERAND_OFFSET21, 0, NULL, & value); -+ fields->f_o21 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_OFFSET24 : -+ { -+ bfd_vma value = 0; -+ errmsg = cgen_parse_address (cd, strp, UBICOM32_OPERAND_OFFSET24, 0, NULL, & value); -+ fields->f_o24 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_OPC1, (unsigned long *) (& fields->f_op1)); -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_OPC2, (unsigned long *) (& fields->f_op2)); -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ errmsg = parse_pdec_imm7_4_s (cd, strp, UBICOM32_OPERAND_PDEC_S1_IMM7_4, (unsigned long *) (& fields->f_s1_imm7_4)); -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_s1_An); -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ errmsg = parse_s1_direct_addr (cd, strp, UBICOM32_OPERAND_S1_DIRECT_ADDR, (unsigned long *) (& fields->f_s1_direct)); -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ errmsg = parse_imm4_1 (cd, strp, UBICOM32_OPERAND_S1_I4_1, (long *) (& fields->f_s1_i4_1)); -+ break; -+ case UBICOM32_OPERAND_S1_I4_2 : -+ errmsg = parse_imm4_2 (cd, strp, UBICOM32_OPERAND_S1_I4_2, (long *) (& fields->f_s1_i4_2)); -+ break; -+ case UBICOM32_OPERAND_S1_I4_4 : -+ errmsg = parse_imm4_4 (cd, strp, UBICOM32_OPERAND_S1_I4_4, (long *) (& fields->f_s1_i4_4)); -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_1 : -+ errmsg = parse_imm7_1_s (cd, strp, UBICOM32_OPERAND_S1_IMM7_1, (unsigned long *) (& fields->f_s1_imm7_1)); -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ errmsg = parse_imm7_2_s (cd, strp, UBICOM32_OPERAND_S1_IMM7_2, (unsigned long *) (& fields->f_s1_imm7_2)); -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ errmsg = parse_imm7_4_s (cd, strp, UBICOM32_OPERAND_S1_IMM7_4, (unsigned long *) (& fields->f_s1_imm7_4)); -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ errmsg = parse_imm8 (cd, strp, UBICOM32_OPERAND_S1_IMM8, (long *) (& fields->f_s1_imm8)); -+ break; -+ case UBICOM32_OPERAND_S1_R : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_s1_r); -+ break; -+ case UBICOM32_OPERAND_S2 : -+ errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_s2); -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_SRC3, (unsigned long *) (& junk)); -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_BIT26, (unsigned long *) (& fields->f_bit26)); -+ break; -+ case UBICOM32_OPERAND_X_D : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_D, (unsigned long *) (& fields->f_d)); -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_DN, (unsigned long *) (& fields->f_Dn)); -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_OP2, (unsigned long *) (& fields->f_op2)); -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_S1, (unsigned long *) (& fields->f_s1)); -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); -+ abort (); -+ } -+ -+ return errmsg; -+} -+ -+cgen_parse_fn * const ubicom32_cgen_parse_handlers[] = -+{ -+ parse_insn_normal, -+}; -+ -+void -+ubicom32_cgen_init_asm (CGEN_CPU_DESC cd) -+{ -+ ubicom32_cgen_init_opcode_table (cd); -+ ubicom32_cgen_init_ibld_table (cd); -+ cd->parse_handlers = & ubicom32_cgen_parse_handlers[0]; -+ cd->parse_operand = ubicom32_cgen_parse_operand; -+#ifdef CGEN_ASM_INIT_HOOK -+CGEN_ASM_INIT_HOOK -+#endif -+} -+ -+ -+ -+/* Regex construction routine. -+ -+ This translates an opcode syntax string into a regex string, -+ by replacing any non-character syntax element (such as an -+ opcode) with the pattern '.*' -+ -+ It then compiles the regex and stores it in the opcode, for -+ later use by ubicom32_cgen_assemble_insn -+ -+ Returns NULL for success, an error message for failure. */ -+ -+char * -+ubicom32_cgen_build_insn_regex (CGEN_INSN *insn) -+{ -+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); -+ const char *mnem = CGEN_INSN_MNEMONIC (insn); -+ char rxbuf[CGEN_MAX_RX_ELEMENTS]; -+ char *rx = rxbuf; -+ const CGEN_SYNTAX_CHAR_TYPE *syn; -+ int reg_err; -+ -+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); -+ -+ /* Mnemonics come first in the syntax string. */ -+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) -+ return _("missing mnemonic in syntax string"); -+ ++syn; -+ -+ /* Generate a case sensitive regular expression that emulates case -+ insensitive matching in the "C" locale. We cannot generate a case -+ insensitive regular expression because in Turkish locales, 'i' and 'I' -+ are not equal modulo case conversion. */ -+ -+ /* Copy the literal mnemonic out of the insn. */ -+ for (; *mnem; mnem++) -+ { -+ char c = *mnem; -+ -+ if (ISALPHA (c)) -+ { -+ *rx++ = '['; -+ *rx++ = TOLOWER (c); -+ *rx++ = TOUPPER (c); -+ *rx++ = ']'; -+ } -+ else -+ *rx++ = c; -+ } -+ -+ /* Copy any remaining literals from the syntax string into the rx. */ -+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) -+ { -+ if (CGEN_SYNTAX_CHAR_P (* syn)) -+ { -+ char c = CGEN_SYNTAX_CHAR (* syn); -+ -+ switch (c) -+ { -+ /* Escape any regex metacharacters in the syntax. */ -+ case '.': case '[': case '\\': -+ case '*': case '^': case '$': -+ -+#ifdef CGEN_ESCAPE_EXTENDED_REGEX -+ case '?': case '{': case '}': -+ case '(': case ')': case '*': -+ case '|': case '+': case ']': -+#endif -+ *rx++ = '\\'; -+ *rx++ = c; -+ break; -+ -+ default: -+ if (ISALPHA (c)) -+ { -+ *rx++ = '['; -+ *rx++ = TOLOWER (c); -+ *rx++ = TOUPPER (c); -+ *rx++ = ']'; -+ } -+ else -+ *rx++ = c; -+ break; -+ } -+ } -+ else -+ { -+ /* Replace non-syntax fields with globs. */ -+ *rx++ = '.'; -+ *rx++ = '*'; -+ } -+ } -+ -+ /* Trailing whitespace ok. */ -+ * rx++ = '['; -+ * rx++ = ' '; -+ * rx++ = '\t'; -+ * rx++ = ']'; -+ * rx++ = '*'; -+ -+ /* But anchor it after that. */ -+ * rx++ = '$'; -+ * rx = '\0'; -+ -+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); -+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); -+ -+ if (reg_err == 0) -+ return NULL; -+ else -+ { -+ static char msg[80]; -+ -+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); -+ regfree ((regex_t *) CGEN_INSN_RX (insn)); -+ free (CGEN_INSN_RX (insn)); -+ (CGEN_INSN_RX (insn)) = NULL; -+ return msg; -+ } -+} -+ -+ -+/* Default insn parser. -+ -+ The syntax string is scanned and operands are parsed and stored in FIELDS. -+ Relocs are queued as we go via other callbacks. -+ -+ ??? Note that this is currently an all-or-nothing parser. If we fail to -+ parse the instruction, we return 0 and the caller will start over from -+ the beginning. Backtracking will be necessary in parsing subexpressions, -+ but that can be handled there. Not handling backtracking here may get -+ expensive in the case of the m68k. Deal with later. -+ -+ Returns NULL for success, an error message for failure. */ -+ -+static const char * -+parse_insn_normal (CGEN_CPU_DESC cd, -+ const CGEN_INSN *insn, -+ const char **strp, -+ CGEN_FIELDS *fields) -+{ -+ /* ??? Runtime added insns not handled yet. */ -+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); -+ const char *str = *strp; -+ const char *errmsg; -+ const char *p; -+ const CGEN_SYNTAX_CHAR_TYPE * syn; -+#ifdef CGEN_MNEMONIC_OPERANDS -+ /* FIXME: wip */ -+ int past_opcode_p; -+#endif -+ -+ /* For now we assume the mnemonic is first (there are no leading operands). -+ We can parse it without needing to set up operand parsing. -+ GAS's input scrubber will ensure mnemonics are lowercase, but we may -+ not be called from GAS. */ -+ p = CGEN_INSN_MNEMONIC (insn); -+ while (*p && TOLOWER (*p) == TOLOWER (*str)) -+ ++p, ++str; -+ -+ if (* p) -+ return _("unrecognized instruction"); -+ -+#ifndef CGEN_MNEMONIC_OPERANDS -+ if (* str && ! ISSPACE (* str)) -+ return _("unrecognized instruction"); -+#endif -+ -+ CGEN_INIT_PARSE (cd); -+ cgen_init_parse_operand (cd); -+#ifdef CGEN_MNEMONIC_OPERANDS -+ past_opcode_p = 0; -+#endif -+ -+ /* We don't check for (*str != '\0') here because we want to parse -+ any trailing fake arguments in the syntax string. */ -+ syn = CGEN_SYNTAX_STRING (syntax); -+ -+ /* Mnemonics come first for now, ensure valid string. */ -+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) -+ abort (); -+ -+ ++syn; -+ -+ while (* syn != 0) -+ { -+ /* Non operand chars must match exactly. */ -+ if (CGEN_SYNTAX_CHAR_P (* syn)) -+ { -+ /* FIXME: While we allow for non-GAS callers above, we assume the -+ first char after the mnemonic part is a space. */ -+ /* FIXME: We also take inappropriate advantage of the fact that -+ GAS's input scrubber will remove extraneous blanks. */ -+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) -+ { -+#ifdef CGEN_MNEMONIC_OPERANDS -+ if (CGEN_SYNTAX_CHAR(* syn) == ' ') -+ past_opcode_p = 1; -+#endif -+ ++ syn; -+ ++ str; -+ } -+ else if (*str) -+ { -+ /* Syntax char didn't match. Can't be this insn. */ -+ static char msg [80]; -+ -+ /* xgettext:c-format */ -+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"), -+ CGEN_SYNTAX_CHAR(*syn), *str); -+ return msg; -+ } -+ else -+ { -+ /* Ran out of input. */ -+ static char msg [80]; -+ -+ /* xgettext:c-format */ -+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), -+ CGEN_SYNTAX_CHAR(*syn)); -+ return msg; -+ } -+ continue; -+ } -+ -+ /* We have an operand of some sort. */ -+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), -+ &str, fields); -+ if (errmsg) -+ return errmsg; -+ -+ /* Done with this operand, continue with next one. */ -+ ++ syn; -+ } -+ -+ /* If we're at the end of the syntax string, we're done. */ -+ if (* syn == 0) -+ { -+ /* FIXME: For the moment we assume a valid `str' can only contain -+ blanks now. IE: We needn't try again with a longer version of -+ the insn and it is assumed that longer versions of insns appear -+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ -+ while (ISSPACE (* str)) -+ ++ str; -+ -+ if (* str != '\0') -+ return _("junk at end of line"); /* FIXME: would like to include `str' */ -+ -+ return NULL; -+ } -+ -+ /* We couldn't parse it. */ -+ return _("unrecognized instruction"); -+} -+ -+/* Main entry point. -+ This routine is called for each instruction to be assembled. -+ STR points to the insn to be assembled. -+ We assume all necessary tables have been initialized. -+ The assembled instruction, less any fixups, is stored in BUF. -+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value -+ still needs to be converted to target byte order, otherwise BUF is an array -+ of bytes in target byte order. -+ The result is a pointer to the insn's entry in the opcode table, -+ or NULL if an error occured (an error message will have already been -+ printed). -+ -+ Note that when processing (non-alias) macro-insns, -+ this function recurses. -+ -+ ??? It's possible to make this cpu-independent. -+ One would have to deal with a few minor things. -+ At this point in time doing so would be more of a curiosity than useful -+ [for example this file isn't _that_ big], but keeping the possibility in -+ mind helps keep the design clean. */ -+ -+const CGEN_INSN * -+ubicom32_cgen_assemble_insn (CGEN_CPU_DESC cd, -+ const char *str, -+ CGEN_FIELDS *fields, -+ CGEN_INSN_BYTES_PTR buf, -+ char **errmsg) -+{ -+ const char *start; -+ CGEN_INSN_LIST *ilist; -+ const char *parse_errmsg = NULL; -+ const char *insert_errmsg = NULL; -+ int recognized_mnemonic = 0; -+ -+ /* Skip leading white space. */ -+ while (ISSPACE (* str)) -+ ++ str; -+ -+ /* The instructions are stored in hashed lists. -+ Get the first in the list. */ -+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str); -+ -+ /* Keep looking until we find a match. */ -+ start = str; -+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) -+ { -+ const CGEN_INSN *insn = ilist->insn; -+ recognized_mnemonic = 1; -+ -+#ifdef CGEN_VALIDATE_INSN_SUPPORTED -+ /* Not usually needed as unsupported opcodes -+ shouldn't be in the hash lists. */ -+ /* Is this insn supported by the selected cpu? */ -+ if (! ubicom32_cgen_insn_supported (cd, insn)) -+ continue; -+#endif -+ /* If the RELAXED attribute is set, this is an insn that shouldn't be -+ chosen immediately. Instead, it is used during assembler/linker -+ relaxation if possible. */ -+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) -+ continue; -+ -+ str = start; -+ -+ /* Skip this insn if str doesn't look right lexically. */ -+ if (CGEN_INSN_RX (insn) != NULL && -+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) -+ continue; -+ -+ /* Allow parse/insert handlers to obtain length of insn. */ -+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); -+ -+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); -+ if (parse_errmsg != NULL) -+ continue; -+ -+ /* ??? 0 is passed for `pc'. */ -+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, -+ (bfd_vma) 0); -+ if (insert_errmsg != NULL) -+ continue; -+ -+ /* It is up to the caller to actually output the insn and any -+ queued relocs. */ -+ return insn; -+ } -+ -+ { -+ static char errbuf[150]; -+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS -+ const char *tmp_errmsg; -+ -+ /* If requesting verbose error messages, use insert_errmsg. -+ Failing that, use parse_errmsg. */ -+ tmp_errmsg = (insert_errmsg ? insert_errmsg : -+ parse_errmsg ? parse_errmsg : -+ recognized_mnemonic ? -+ _("unrecognized form of instruction") : -+ _("unrecognized instruction")); -+ -+ if (strlen (start) > 50) -+ /* xgettext:c-format */ -+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); -+ else -+ /* xgettext:c-format */ -+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); -+#else -+ if (strlen (start) > 50) -+ /* xgettext:c-format */ -+ sprintf (errbuf, _("bad instruction `%.50s...'"), start); -+ else -+ /* xgettext:c-format */ -+ sprintf (errbuf, _("bad instruction `%.50s'"), start); -+#endif -+ -+ *errmsg = errbuf; -+ return NULL; -+ } -+} ---- /dev/null -+++ b/opcodes/ubicom32-desc.c -@@ -0,0 +1,15137 @@ -+/* CPU data for ubicom32. -+ -+THIS FILE IS MACHINE GENERATED WITH CGEN. -+ -+Copyright 1996-2007 Free Software Foundation, Inc. -+ -+This file is part of the GNU Binutils and/or GDB, the GNU debugger. -+ -+ This file is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -+ -+*/ -+ -+#include "sysdep.h" -+#include -+#include -+#include "ansidecl.h" -+#include "bfd.h" -+#include "symcat.h" -+#include "ubicom32-desc.h" -+#include "ubicom32-opc.h" -+#include "opintl.h" -+#include "libiberty.h" -+#include "xregex.h" -+ -+/* Attributes. */ -+ -+static const CGEN_ATTR_ENTRY bool_attr[] = -+{ -+ { "#f", 0 }, -+ { "#t", 1 }, -+ { 0, 0 } -+}; -+ -+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = -+{ -+ { "base", MACH_BASE }, -+ { "ip3035", MACH_IP3035 }, -+ { "ubicom32dsp", MACH_UBICOM32DSP }, -+ { "ip3023compatibility", MACH_IP3023COMPATIBILITY }, -+ { "ubicom32_ver4", MACH_UBICOM32_VER4 }, -+ { "max", MACH_MAX }, -+ { 0, 0 } -+}; -+ -+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = -+{ -+ { "ubicom32", ISA_UBICOM32 }, -+ { "max", ISA_MAX }, -+ { 0, 0 } -+}; -+ -+const CGEN_ATTR_TABLE ubicom32_cgen_ifield_attr_table[] = -+{ -+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, -+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, -+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, -+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, -+ { "RESERVED", &bool_attr[0], &bool_attr[0] }, -+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, -+ { "SIGNED", &bool_attr[0], &bool_attr[0] }, -+ { 0, 0, 0 } -+}; -+ -+const CGEN_ATTR_TABLE ubicom32_cgen_hardware_attr_table[] = -+{ -+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, -+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, -+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, -+ { "PC", &bool_attr[0], &bool_attr[0] }, -+ { "PROFILE", &bool_attr[0], &bool_attr[0] }, -+ { 0, 0, 0 } -+}; -+ -+const CGEN_ATTR_TABLE ubicom32_cgen_operand_attr_table[] = -+{ -+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, -+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, -+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, -+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, -+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, -+ { "SIGNED", &bool_attr[0], &bool_attr[0] }, -+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, -+ { "RELAX", &bool_attr[0], &bool_attr[0] }, -+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, -+ { 0, 0, 0 } -+}; -+ -+const CGEN_ATTR_TABLE ubicom32_cgen_insn_attr_table[] = -+{ -+ { "MACH", & MACH_attr[0], & MACH_attr[0] }, -+ { "ALIAS", &bool_attr[0], &bool_attr[0] }, -+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, -+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, -+ { "COND-CTI", &bool_attr[0], &bool_attr[0] }, -+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, -+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, -+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, -+ { "RELAXED", &bool_attr[0], &bool_attr[0] }, -+ { "NO-DIS", &bool_attr[0], &bool_attr[0] }, -+ { "PBB", &bool_attr[0], &bool_attr[0] }, -+ { 0, 0, 0 } -+}; -+ -+/* Instruction set variants. */ -+ -+static const CGEN_ISA ubicom32_cgen_isa_table[] = { -+ { "ubicom32", 32, 32, 32, 32 }, -+ { 0, 0, 0, 0, 0 } -+}; -+ -+/* Machine variants. */ -+ -+static const CGEN_MACH ubicom32_cgen_mach_table[] = { -+ { "ip3035", "ubicom32", MACH_IP3035, 0 }, -+ { "ubicom32dsp", "ubicom32dsp", MACH_UBICOM32DSP, 0 }, -+ { "ip3023compatibility", "ubicom32dsp", MACH_IP3023COMPATIBILITY, 0 }, -+ { "ubicom32_ver4", "ubicom32ver4", MACH_UBICOM32_VER4, 0 }, -+ { 0, 0, 0, 0 } -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_data_names_entries[] = -+{ -+ { "d0", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d1", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d2", 2, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d3", 3, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d4", 4, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d5", 5, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d6", 6, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d7", 7, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d8", 8, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d9", 9, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d10", 10, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d11", 11, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d12", 12, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d13", 13, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d14", 14, {0, {{{0, 0}}}}, 0, 0 }, -+ { "d15", 15, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_data_names = -+{ -+ & ubicom32_cgen_opval_data_names_entries[0], -+ 16, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_addr_names_entries[] = -+{ -+ { "sp", 7, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a2", 2, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a3", 3, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a4", 4, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a5", 5, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a6", 6, {0, {{{0, 0}}}}, 0, 0 }, -+ { "a7", 7, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_addr_names = -+{ -+ & ubicom32_cgen_opval_addr_names_entries[0], -+ 9, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_acc_names_entries[] = -+{ -+ { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_acc_names = -+{ -+ & ubicom32_cgen_opval_acc_names_entries[0], -+ 2, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_spad_names_entries[] = -+{ -+ { "scratchpad0", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "scratchpad1", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "scratchpad2", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "scratchpad3", 0, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_spad_names = -+{ -+ & ubicom32_cgen_opval_spad_names_entries[0], -+ 4, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_cc_entries[] = -+{ -+ { "f", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "lo", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { "cc", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { "hs", 2, {0, {{{0, 0}}}}, 0, 0 }, -+ { "cs", 2, {0, {{{0, 0}}}}, 0, 0 }, -+ { "eq", 3, {0, {{{0, 0}}}}, 0, 0 }, -+ { "ge", 4, {0, {{{0, 0}}}}, 0, 0 }, -+ { "gt", 5, {0, {{{0, 0}}}}, 0, 0 }, -+ { "hi", 6, {0, {{{0, 0}}}}, 0, 0 }, -+ { "le", 7, {0, {{{0, 0}}}}, 0, 0 }, -+ { "ls", 8, {0, {{{0, 0}}}}, 0, 0 }, -+ { "lt", 9, {0, {{{0, 0}}}}, 0, 0 }, -+ { "mi", 10, {0, {{{0, 0}}}}, 0, 0 }, -+ { "ne", 11, {0, {{{0, 0}}}}, 0, 0 }, -+ { "pl", 12, {0, {{{0, 0}}}}, 0, 0 }, -+ { "t", 13, {0, {{{0, 0}}}}, 0, 0 }, -+ { "vc", 14, {0, {{{0, 0}}}}, 0, 0 }, -+ { "vs", 15, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_cc = -+{ -+ & ubicom32_cgen_opval_h_cc_entries[0], -+ 18, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_C_entries[] = -+{ -+ { "", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { ".s", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { ".w", 1, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_C = -+{ -+ & ubicom32_cgen_opval_h_C_entries[0], -+ 3, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_P_entries[] = -+{ -+ { ".t", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { ".f", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "", 1, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_P = -+{ -+ & ubicom32_cgen_opval_h_P_entries[0], -+ 3, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_C_entries[] = -+{ -+ { ".c", 1, {0, {{{0, 0}}}}, 0, 0 }, -+ { "", 0, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_C = -+{ -+ & ubicom32_cgen_opval_h_DSP_C_entries[0], -+ 2, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_Dest_A_entries[] = -+{ -+ { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_Dest_A = -+{ -+ & ubicom32_cgen_opval_h_DSP_Dest_A_entries[0], -+ 2, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_T_entries[] = -+{ -+ { "", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { ".t", 1, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T = -+{ -+ & ubicom32_cgen_opval_h_DSP_T_entries[0], -+ 2, -+ 0, 0, 0, 0, "" -+}; -+ -+static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_T_addsub_entries[] = -+{ -+ { "", 0, {0, {{{0, 0}}}}, 0, 0 }, -+ { ".t", 1, {0, {{{0, 0}}}}, 0, 0 } -+}; -+ -+CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T_addsub = -+{ -+ & ubicom32_cgen_opval_h_DSP_T_addsub_entries[0], -+ 2, -+ 0, 0, 0, 0, "" -+}; -+ -+ -+/* The hardware table. */ -+ -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define A(a) (1 << CGEN_HW_##a) -+#else -+#define A(a) (1 << CGEN_HW_/**/a) -+#endif -+ -+const CGEN_HW_ENTRY ubicom32_cgen_hw_table[] = -+{ -+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) -+ { -+ if (strcmp (name, table->bfd_name) == 0) -+ return table; -+ ++table; -+ } -+ abort (); -+} -+ -+/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table. */ -+ -+static void -+build_hw_table (CGEN_CPU_TABLE *cd) -+{ -+ int i; -+ int machs = cd->machs; -+ const CGEN_HW_ENTRY *init = & ubicom32_cgen_hw_table[0]; -+ /* MAX_HW is only an upper bound on the number of selected entries. -+ However each entry is indexed by it's enum so there can be holes in -+ the table. */ -+ const CGEN_HW_ENTRY **selected = -+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); -+ -+ cd->hw_table.init_entries = init; -+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); -+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); -+ /* ??? For now we just use machs to determine which ones we want. */ -+ for (i = 0; init[i].name != NULL; ++i) -+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) -+ & machs) -+ selected[init[i].type] = &init[i]; -+ cd->hw_table.entries = selected; -+ cd->hw_table.num_entries = MAX_HW; -+} -+ -+/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table. */ -+ -+static void -+build_ifield_table (CGEN_CPU_TABLE *cd) -+{ -+ cd->ifld_table = & ubicom32_cgen_ifld_table[0]; -+} -+ -+/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table. */ -+ -+static void -+build_operand_table (CGEN_CPU_TABLE *cd) -+{ -+ int i; -+ int machs = cd->machs; -+ const CGEN_OPERAND *init = & ubicom32_cgen_operand_table[0]; -+ /* MAX_OPERANDS is only an upper bound on the number of selected entries. -+ However each entry is indexed by it's enum so there can be holes in -+ the table. */ -+ const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); -+ -+ cd->operand_table.init_entries = init; -+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND); -+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); -+ /* ??? For now we just use mach to determine which ones we want. */ -+ for (i = 0; init[i].name != NULL; ++i) -+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) -+ & machs) -+ selected[init[i].type] = &init[i]; -+ cd->operand_table.entries = selected; -+ cd->operand_table.num_entries = MAX_OPERANDS; -+} -+ -+/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table. -+ ??? This could leave out insns not supported by the specified mach/isa, -+ but that would cause errors like "foo only supported by bar" to become -+ "unknown insn", so for now we include all insns and require the app to -+ do the checking later. -+ ??? On the other hand, parsing of such insns may require their hardware or -+ operand elements to be in the table [which they mightn't be]. */ -+ -+static void -+build_insn_table (CGEN_CPU_TABLE *cd) -+{ -+ int i; -+ const CGEN_IBASE *ib = & ubicom32_cgen_insn_table[0]; -+ CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); -+ -+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); -+ for (i = 0; i < MAX_INSNS; ++i) -+ insns[i].base = &ib[i]; -+ cd->insn_table.init_entries = insns; -+ cd->insn_table.entry_size = sizeof (CGEN_IBASE); -+ cd->insn_table.num_init_entries = MAX_INSNS; -+} -+ -+/* Subroutine of ubicom32_cgen_cpu_open to rebuild the tables. */ -+ -+static void -+ubicom32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) -+{ -+ int i; -+ CGEN_BITSET *isas = cd->isas; -+ unsigned int machs = cd->machs; -+ -+ cd->int_insn_p = CGEN_INT_INSN_P; -+ -+ /* Data derived from the isa spec. */ -+#define UNSET (CGEN_SIZE_UNKNOWN + 1) -+ cd->default_insn_bitsize = UNSET; -+ cd->base_insn_bitsize = UNSET; -+ cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ -+ cd->max_insn_bitsize = 0; -+ for (i = 0; i < MAX_ISAS; ++i) -+ if (cgen_bitset_contains (isas, i)) -+ { -+ const CGEN_ISA *isa = & ubicom32_cgen_isa_table[i]; -+ -+ /* Default insn sizes of all selected isas must be -+ equal or we set the result to 0, meaning "unknown". */ -+ if (cd->default_insn_bitsize == UNSET) -+ cd->default_insn_bitsize = isa->default_insn_bitsize; -+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize) -+ ; /* This is ok. */ -+ else -+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; -+ -+ /* Base insn sizes of all selected isas must be equal -+ or we set the result to 0, meaning "unknown". */ -+ if (cd->base_insn_bitsize == UNSET) -+ cd->base_insn_bitsize = isa->base_insn_bitsize; -+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize) -+ ; /* This is ok. */ -+ else -+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; -+ -+ /* Set min,max insn sizes. */ -+ if (isa->min_insn_bitsize < cd->min_insn_bitsize) -+ cd->min_insn_bitsize = isa->min_insn_bitsize; -+ if (isa->max_insn_bitsize > cd->max_insn_bitsize) -+ cd->max_insn_bitsize = isa->max_insn_bitsize; -+ } -+ -+ /* Data derived from the mach spec. */ -+ for (i = 0; i < MAX_MACHS; ++i) -+ if (((1 << i) & machs) != 0) -+ { -+ const CGEN_MACH *mach = & ubicom32_cgen_mach_table[i]; -+ -+ if (mach->insn_chunk_bitsize != 0) -+ { -+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) -+ { -+ fprintf (stderr, "ubicom32_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", -+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); -+ abort (); -+ } -+ -+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; -+ } -+ } -+ -+ /* Determine which hw elements are used by MACH. */ -+ build_hw_table (cd); -+ -+ /* Build the ifield table. */ -+ build_ifield_table (cd); -+ -+ /* Determine which operands are used by MACH/ISA. */ -+ build_operand_table (cd); -+ -+ /* Build the instruction table. */ -+ build_insn_table (cd); -+} -+ -+/* Initialize a cpu table and return a descriptor. -+ It's much like opening a file, and must be the first function called. -+ The arguments are a set of (type/value) pairs, terminated with -+ CGEN_CPU_OPEN_END. -+ -+ Currently supported values: -+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr -+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr -+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name -+ CGEN_CPU_OPEN_ENDIAN: specify endian choice -+ CGEN_CPU_OPEN_END: terminates arguments -+ -+ ??? Simultaneous multiple isas might not make sense, but it's not (yet) -+ precluded. -+ -+ ??? We only support ISO C stdargs here, not K&R. -+ Laziness, plus experiment to see if anything requires K&R - eventually -+ K&R will no longer be supported - e.g. GDB is currently trying this. */ -+ -+CGEN_CPU_DESC -+ubicom32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) -+{ -+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); -+ static int init_p; -+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ -+ unsigned int machs = 0; /* 0 = "unspecified" */ -+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; -+ va_list ap; -+ -+ if (! init_p) -+ { -+ init_tables (); -+ init_p = 1; -+ } -+ -+ memset (cd, 0, sizeof (*cd)); -+ -+ va_start (ap, arg_type); -+ while (arg_type != CGEN_CPU_OPEN_END) -+ { -+ switch (arg_type) -+ { -+ case CGEN_CPU_OPEN_ISAS : -+ isas = va_arg (ap, CGEN_BITSET *); -+ break; -+ case CGEN_CPU_OPEN_MACHS : -+ machs = va_arg (ap, unsigned int); -+ break; -+ case CGEN_CPU_OPEN_BFDMACH : -+ { -+ const char *name = va_arg (ap, const char *); -+ const CGEN_MACH *mach = -+ lookup_mach_via_bfd_name (ubicom32_cgen_mach_table, name); -+ -+ machs |= 1 << mach->num; -+ break; -+ } -+ case CGEN_CPU_OPEN_ENDIAN : -+ endian = va_arg (ap, enum cgen_endian); -+ break; -+ default : -+ fprintf (stderr, "ubicom32_cgen_cpu_open: unsupported argument `%d'\n", -+ arg_type); -+ abort (); /* ??? return NULL? */ -+ } -+ arg_type = va_arg (ap, enum cgen_cpu_open_arg); -+ } -+ va_end (ap); -+ -+ /* Mach unspecified means "all". */ -+ if (machs == 0) -+ machs = (1 << MAX_MACHS) - 1; -+ /* Base mach is always selected. */ -+ machs |= 1; -+ if (endian == CGEN_ENDIAN_UNKNOWN) -+ { -+ /* ??? If target has only one, could have a default. */ -+ fprintf (stderr, "ubicom32_cgen_cpu_open: no endianness specified\n"); -+ abort (); -+ } -+ -+ cd->isas = cgen_bitset_copy (isas); -+ cd->machs = machs; -+ cd->endian = endian; -+ /* FIXME: for the sparc case we can determine insn-endianness statically. -+ The worry here is where both data and insn endian can be independently -+ chosen, in which case this function will need another argument. -+ Actually, will want to allow for more arguments in the future anyway. */ -+ cd->insn_endian = endian; -+ -+ /* Table (re)builder. */ -+ cd->rebuild_tables = ubicom32_cgen_rebuild_tables; -+ ubicom32_cgen_rebuild_tables (cd); -+ -+ /* Default to not allowing signed overflow. */ -+ cd->signed_overflow_ok_p = 0; -+ -+ return (CGEN_CPU_DESC) cd; -+} -+ -+/* Cover fn to ubicom32_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. -+ MACH_NAME is the bfd name of the mach. */ -+ -+CGEN_CPU_DESC -+ubicom32_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) -+{ -+ return ubicom32_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, -+ CGEN_CPU_OPEN_ENDIAN, endian, -+ CGEN_CPU_OPEN_END); -+} -+ -+/* Close a cpu table. -+ ??? This can live in a machine independent file, but there's currently -+ no place to put this file (there's no libcgen). libopcodes is the wrong -+ place as some simulator ports use this but they don't use libopcodes. */ -+ -+void -+ubicom32_cgen_cpu_close (CGEN_CPU_DESC cd) -+{ -+ unsigned int i; -+ const CGEN_INSN *insns; -+ -+ if (cd->macro_insn_table.init_entries) -+ { -+ insns = cd->macro_insn_table.init_entries; -+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) -+ if (CGEN_INSN_RX ((insns))) -+ regfree (CGEN_INSN_RX (insns)); -+ } -+ -+ if (cd->insn_table.init_entries) -+ { -+ insns = cd->insn_table.init_entries; -+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) -+ if (CGEN_INSN_RX (insns)) -+ regfree (CGEN_INSN_RX (insns)); -+ } -+ -+ if (cd->macro_insn_table.init_entries) -+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries); -+ -+ if (cd->insn_table.init_entries) -+ free ((CGEN_INSN *) cd->insn_table.init_entries); -+ -+ if (cd->hw_table.entries) -+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries); -+ -+ if (cd->operand_table.entries) -+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries); -+ -+ free (cd); -+} -+ ---- /dev/null -+++ b/opcodes/ubicom32-desc.h -@@ -0,0 +1,369 @@ -+/* CPU data header for ubicom32. -+ -+THIS FILE IS MACHINE GENERATED WITH CGEN. -+ -+Copyright 1996-2007 Free Software Foundation, Inc. -+ -+This file is part of the GNU Binutils and/or GDB, the GNU debugger. -+ -+ This file is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -+ -+*/ -+ -+#ifndef UBICOM32_CPU_H -+#define UBICOM32_CPU_H -+ -+#include "opcode/cgen-bitset.h" -+ -+#define CGEN_ARCH ubicom32 -+ -+/* Given symbol S, return ubicom32_cgen_. */ -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define CGEN_SYM(s) ubicom32##_cgen_##s -+#else -+#define CGEN_SYM(s) ubicom32/**/_cgen_/**/s -+#endif -+ -+ -+/* Selected cpu families. */ -+#define HAVE_CPU_UBICOM32BF -+ -+#define CGEN_INSN_LSB0_P 1 -+ -+/* Minimum size of any insn (in bytes). */ -+#define CGEN_MIN_INSN_SIZE 4 -+ -+/* Maximum size of any insn (in bytes). */ -+#define CGEN_MAX_INSN_SIZE 4 -+ -+#define CGEN_INT_INSN_P 1 -+ -+/* Maximum number of syntax elements in an instruction. */ -+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 27 -+ -+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. -+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands -+ we can't hash on everything up to the space. */ -+#define CGEN_MNEMONIC_OPERANDS -+ -+/* Maximum number of fields in an instruction. */ -+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 15 -+ -+/* Enums. */ -+ -+/* Enum declaration for insn format enums. */ -+typedef enum insn_op1 { -+ OP_X0, OP_UNUSED_01, OP_X2, OP_UNUSED_03 -+ , OP_BSET, OP_BCLR, OP_DSP, OP_UNUSED_07 -+ , OP_AND_2, OP_AND_4, OP_OR_2, OP_OR_4 -+ , OP_XOR_2, OP_XOR_4, OP_ADD_2, OP_ADD_4 -+ , OP_ADDC, OP_SUB_2, OP_SUB_4, OP_SUBC -+ , OP_PXBLEND, OP_PXVI, OP_PXADDS, OP_UNUSED_17 -+ , OP_CMPI, OP_MOVEI, OP_JMP, OP_CALL -+ , OP_MOVEAI, OP_UNUSED_1D, OP_CALLI, OP_UNUSED_1F -+} INSN_OP1; -+ -+/* Enum declaration for insn x0 opcode ext enums. */ -+typedef enum insn_op2 { -+ OPX0_UNUSED_00, OPX0_SUSPEND, OPX0_UNUSED_02, OPX0_UNUSED_03 -+ , OPX0_RET, OPX0_IERASE, OPX0_IREAD, OPX0_BKPT -+ , OPX0_UNUSED_08, OPX0_UNUSED_09, OPX0_NOT_4, OPX0_NOT_2 -+ , OPX0_MOVE_4, OPX0_MOVE_2, OPX0_MOVEA, OPX0_MOVE_1 -+ , OPX0_IWRITE, OPX0_UNUSED_11, OPX0_SETCSR, OPX0_UNUSED_13 -+ , OPX0_UNUSED_14, OPX0_EXT_2, OPX0_UNUSED_16, OPX0_EXT_1 -+ , OPX0_SWAPB_2, OPX0_SWAPB_4, OPX0_PXCNV, OPX0_PXCNV_T -+ , OPX0_LEA_4, OPX0_LEA_2, OPX0_PDEC, OPX0_LEA_1 -+} INSN_OP2; -+ -+/* Enum declaration for insn x2 opcode ext enums. */ -+typedef enum insn_opext { -+ OPX2_PXHI, OPX2_MULS, OPX2_PXHI_S, OPX2_MULU -+ , OPX2_UNUSED_04, OPX2_MULF, OPX2_BTST, OPX2_UNUSED_07 -+ , OPX2_CRCGEN, OPX2_MAC, OPX2_LSL_1, OPX2_LSR_1 -+ , OPX2_ASR_1, OPX2_UNUSED_0D, OPX2_UNUSED_0E, OPX2_UNUSED_0F -+ , OPX2_LSL_4, OPX2_LSL_2, OPX2_LSR_4, OPX2_LSR_2 -+ , OPX2_ASR_4, OPX2_ASR_2, OPX2_BFEXTU, OPX2_UNUSED_17 -+ , OPX2_BFRVRS, OPX2_UNUSED_19, OPX2_SHFTD, OPX2_UNUSED_1B -+ , OPX2_MERGE, OPX2_UNUSED_1D, OPX2_SHMRG_2, OPX2_SHMRG_1 -+} INSN_OPEXT; -+ -+/* Enum declaration for insn dsp opcode ext enums. */ -+typedef enum insn_dsp_subop { -+ OPDSP_MULS, OPDSP_MACS, OPDSP_MULU, OPDSP_MACU -+ , OPDSP_MULF, OPDSP_MACF, OPDSP_UNUSED_06, OPDSP_MACUS -+ , OPDSP_MULS_4, OPDSP_MSUF, OPDSP_MULU_4, OPDSP_UNUSED_0B -+ , OPDSP_UNUSED_0C, OPDSP_UNUSED_0D, OPDSP_UNUSED_0E, OPDSP_UNUSED_0F -+ , OPDSP_MADD_4, OPDSP_MADD_2, OPDSP_MSUB_4, OPDSP_MSUB_2 -+ , OPDSP_UNUSED_14, OPDSP_UNUSED_15, OPDSP_UNUSED_16, OPDSP_UNUSED_17 -+ , OPDSP_UNUSED_18, OPDSP_UNUSED_19, OPDSP_UNUSED_1A, OPDSP_UNUSED_1B -+ , OPDSP_UNUSED_1C, OPDSP_UNUSED_1D, OPDSP_UNUSED_1E, OPDSP_UNUSED_1F -+} INSN_DSP_SUBOP; -+ -+/* Enum declaration for . */ -+typedef enum data_names { -+ H_DR_D0, H_DR_D1, H_DR_D2, H_DR_D3 -+ , H_DR_D4, H_DR_D5, H_DR_D6, H_DR_D7 -+ , H_DR_D8, H_DR_D9, H_DR_D10, H_DR_D11 -+ , H_DR_D12, H_DR_D13, H_DR_D14, H_DR_D15 -+} DATA_NAMES; -+ -+/* Enum declaration for . */ -+typedef enum addr_names { -+ H_AR_SP = 7, H_AR_A0 = 0, H_AR_A1 = 1, H_AR_A2 = 2 -+ , H_AR_A3 = 3, H_AR_A4 = 4, H_AR_A5 = 5, H_AR_A6 = 6 -+ , H_AR_A7 = 7 -+} ADDR_NAMES; -+ -+/* Enum declaration for . */ -+typedef enum acc_names { -+ ACC_LOS_ACC0, ACC_LOS_ACC1 -+} ACC_NAMES; -+ -+/* Enum declaration for . */ -+typedef enum spad_names { -+ H_SP_SCRATCHPAD0 = 0, H_SP_SCRATCHPAD1 = 0, H_SP_SCRATCHPAD2 = 0, H_SP_SCRATCHPAD3 = 0 -+} SPAD_NAMES; -+ -+/* Attributes. */ -+ -+/* Enum declaration for machine type selection. */ -+typedef enum mach_attr { -+ MACH_BASE, MACH_IP3035, MACH_UBICOM32DSP, MACH_IP3023COMPATIBILITY -+ , MACH_UBICOM32_VER4, MACH_MAX -+} MACH_ATTR; -+ -+/* Enum declaration for instruction set selection. */ -+typedef enum isa_attr { -+ ISA_UBICOM32, ISA_MAX -+} ISA_ATTR; -+ -+/* Number of architecture variants. */ -+#define MAX_ISAS 1 -+#define MAX_MACHS ((int) MACH_MAX) -+ -+/* Ifield support. */ -+ -+/* Ifield attribute indices. */ -+ -+/* Enum declaration for cgen_ifld attrs. */ -+typedef enum cgen_ifld_attr { -+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED -+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 -+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS -+} CGEN_IFLD_ATTR; -+ -+/* Number of non-boolean elements in cgen_ifld_attr. */ -+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) -+ -+/* cgen_ifld attribute accessor macros. */ -+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) -+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) -+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) -+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) -+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) -+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) -+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) -+ -+/* Enum declaration for ubicom32 ifield types. */ -+typedef enum ifield_type { -+ UBICOM32_F_NIL, UBICOM32_F_ANYOF, UBICOM32_F_D, UBICOM32_F_D_BIT10 -+ , UBICOM32_F_D_TYPE, UBICOM32_F_D_R, UBICOM32_F_D_M, UBICOM32_F_D_I4_1 -+ , UBICOM32_F_D_I4_2, UBICOM32_F_D_I4_4, UBICOM32_F_D_AN, UBICOM32_F_D_DIRECT -+ , UBICOM32_F_D_IMM8, UBICOM32_F_D_IMM7_T, UBICOM32_F_D_IMM7_B, UBICOM32_F_D_IMM7_1 -+ , UBICOM32_F_D_IMM7_2, UBICOM32_F_D_IMM7_4, UBICOM32_F_S1, UBICOM32_F_S1_BIT10 -+ , UBICOM32_F_S1_TYPE, UBICOM32_F_S1_R, UBICOM32_F_S1_M, UBICOM32_F_S1_I4_1 -+ , UBICOM32_F_S1_I4_2, UBICOM32_F_S1_I4_4, UBICOM32_F_S1_AN, UBICOM32_F_S1_DIRECT -+ , UBICOM32_F_S1_IMM8, UBICOM32_F_S1_IMM7_T, UBICOM32_F_S1_IMM7_B, UBICOM32_F_S1_IMM7_1 -+ , UBICOM32_F_S1_IMM7_2, UBICOM32_F_S1_IMM7_4, UBICOM32_F_OP1, UBICOM32_F_OP2 -+ , UBICOM32_F_BIT26, UBICOM32_F_OPEXT, UBICOM32_F_COND, UBICOM32_F_IMM16_1 -+ , UBICOM32_F_IMM16_2, UBICOM32_F_O21, UBICOM32_F_O23_21, UBICOM32_F_O20_0 -+ , UBICOM32_F_O24, UBICOM32_F_IMM23_21, UBICOM32_F_IMM24, UBICOM32_F_O15_13 -+ , UBICOM32_F_O12_8, UBICOM32_F_O7_5, UBICOM32_F_O4_0, UBICOM32_F_O16 -+ , UBICOM32_F_AN, UBICOM32_F_AM, UBICOM32_F_DN, UBICOM32_F_BIT5 -+ , UBICOM32_F_P, UBICOM32_F_C, UBICOM32_F_INT, UBICOM32_F_DSP_C -+ , UBICOM32_F_DSP_T, UBICOM32_F_DSP_S2_SEL, UBICOM32_F_DSP_R, UBICOM32_F_DSP_DESTA -+ , UBICOM32_F_DSP_B15, UBICOM32_F_DSP_S2, UBICOM32_F_DSP_J, UBICOM32_F_S2 -+ , UBICOM32_F_B15, UBICOM32_F_MAX -+} IFIELD_TYPE; -+ -+#define MAX_IFLD ((int) UBICOM32_F_MAX) -+ -+/* Hardware attribute indices. */ -+ -+/* Enum declaration for cgen_hw attrs. */ -+typedef enum cgen_hw_attr { -+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE -+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS -+} CGEN_HW_ATTR; -+ -+/* Number of non-boolean elements in cgen_hw_attr. */ -+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) -+ -+/* cgen_hw attribute accessor macros. */ -+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) -+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) -+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) -+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) -+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) -+ -+/* Enum declaration for ubicom32 hardware types. */ -+typedef enum cgen_hw_type { -+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR -+ , HW_H_IADDR, HW_H_GLOBAL_CONTROL, HW_H_MT_BREAK, HW_H_MT_ACTIVE -+ , HW_H_MT_ENABLE, HW_H_MT_PRIORITY, HW_H_MT_SCHEDULE, HW_H_IRQ_STATUS_0 -+ , HW_H_IRQ_STATUS_1, HW_H_DR, HW_H_S1_DR, HW_H_AR -+ , HW_H_AR_INC, HW_H_AR_INC_FLAG, HW_H_MAC_HI, HW_H_MAC_LO -+ , HW_H_SRC_3, HW_H_CSR, HW_H_IREAD, HW_H_ACC1_HI -+ , HW_H_ACC1_LO, HW_H_PC, HW_H_NBIT_16, HW_H_ZBIT_16 -+ , HW_H_VBIT_16, HW_H_CBIT_16, HW_H_NBIT_32, HW_H_ZBIT_32 -+ , HW_H_VBIT_32, HW_H_CBIT_32, HW_H_CC, HW_H_C -+ , HW_H_P, HW_H_DSP_C, HW_H_DSP_DEST_A, HW_H_DSP_T -+ , HW_H_DSP_T_ADDSUB, HW_H_DSP_S2_ACC_REG_MUL, HW_H_DSP_S2_ACC_REG_ADDSUB, HW_H_SP -+ , HW_MAX -+} CGEN_HW_TYPE; -+ -+#define MAX_HW ((int) HW_MAX) -+ -+/* Operand attribute indices. */ -+ -+/* Enum declaration for cgen_operand attrs. */ -+typedef enum cgen_operand_attr { -+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT -+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY -+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS -+} CGEN_OPERAND_ATTR; -+ -+/* Number of non-boolean elements in cgen_operand_attr. */ -+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) -+ -+/* cgen_operand attribute accessor macros. */ -+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) -+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) -+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) -+ -+/* Enum declaration for ubicom32 operand types. */ -+typedef enum cgen_operand_type { -+ UBICOM32_OPERAND_PC, UBICOM32_OPERAND_S2, UBICOM32_OPERAND_SRC3, UBICOM32_OPERAND_OFFSET24 -+ , UBICOM32_OPERAND_AN, UBICOM32_OPERAND_CC, UBICOM32_OPERAND_C, UBICOM32_OPERAND_P -+ , UBICOM32_OPERAND_AM, UBICOM32_OPERAND_DN, UBICOM32_OPERAND_INTERRUPT, UBICOM32_OPERAND_IMM16_1 -+ , UBICOM32_OPERAND_X_OP2, UBICOM32_OPERAND_X_BIT26, UBICOM32_OPERAND_X_S1, UBICOM32_OPERAND_X_D -+ , UBICOM32_OPERAND_X_DN, UBICOM32_OPERAND_MACHI, UBICOM32_OPERAND_MACLO, UBICOM32_OPERAND_ACC1HI -+ , UBICOM32_OPERAND_ACC1LO, UBICOM32_OPERAND_IRQ_0, UBICOM32_OPERAND_IRQ_1, UBICOM32_OPERAND_IREAD -+ , UBICOM32_OPERAND_OPC1, UBICOM32_OPERAND_OPC2, UBICOM32_OPERAND_AN_INC, UBICOM32_OPERAND_DSP_C -+ , UBICOM32_OPERAND_DSP_T, UBICOM32_OPERAND_DSP_DESTA, UBICOM32_OPERAND_DSP_S2_SEL, UBICOM32_OPERAND_DSP_S2_DATA_REG -+ , UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL, UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB, UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB, UBICOM32_OPERAND_DSP_T_ADDSUB -+ , UBICOM32_OPERAND_BIT5, UBICOM32_OPERAND_BIT5_ADDSUB, UBICOM32_OPERAND_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_OPERAND_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_OPERAND_DSP_SRC2_DATA_REG, UBICOM32_OPERAND_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_OPERAND_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_OPERAND_DSP_IMM_BIT5 -+ , UBICOM32_OPERAND_DSP_IMM_BIT5_ADDSUB, UBICOM32_OPERAND_DSP_IMM_BIT5_ADDSUB2, UBICOM32_OPERAND_IMM_BIT5, UBICOM32_OPERAND_DYN_REG -+ , UBICOM32_OPERAND_OP3, UBICOM32_OPERAND_DSP_SRC2_MUL, UBICOM32_OPERAND_DSP_COMPATIBILITY_SRC2_MUL, UBICOM32_OPERAND_DSP_SRC2_ADDSUB -+ , UBICOM32_OPERAND_DSP_SRC2_ADDSUB2, UBICOM32_OPERAND_OFFSET21, UBICOM32_OPERAND_OFFSET16, UBICOM32_OPERAND_IMM24 -+ , UBICOM32_OPERAND_NBIT_16, UBICOM32_OPERAND_VBIT_16, UBICOM32_OPERAND_ZBIT_16, UBICOM32_OPERAND_CBIT_16 -+ , UBICOM32_OPERAND_NBIT_32, UBICOM32_OPERAND_VBIT_32, UBICOM32_OPERAND_ZBIT_32, UBICOM32_OPERAND_CBIT_32 -+ , UBICOM32_OPERAND_S1_IMM7_1, UBICOM32_OPERAND_S1_IMM7_2, UBICOM32_OPERAND_S1_IMM7_4, UBICOM32_OPERAND_PDEC_S1_IMM7_4 -+ , UBICOM32_OPERAND_S1_IMM8, UBICOM32_OPERAND_S1_AN, UBICOM32_OPERAND_S1_R, UBICOM32_OPERAND_S1_AN_INC -+ , UBICOM32_OPERAND_S1_I4_1, UBICOM32_OPERAND_S1_I4_2, UBICOM32_OPERAND_S1_I4_4, UBICOM32_OPERAND_S1_INDIRECT_1 -+ , UBICOM32_OPERAND_S1_INDIRECT_2, UBICOM32_OPERAND_S1_INDIRECT_4, UBICOM32_OPERAND_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_OPERAND_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_OPERAND_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_OPERAND_S1_INDIRECT_WITH_INDEX_1, UBICOM32_OPERAND_S1_INDIRECT_WITH_INDEX_2, UBICOM32_OPERAND_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_OPERAND_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_OPERAND_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_OPERAND_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_OPERAND_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_OPERAND_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_OPERAND_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_OPERAND_S1_DIRECT_ADDR, UBICOM32_OPERAND_S1_DIRECT -+ , UBICOM32_OPERAND_S1_IMMEDIATE, UBICOM32_OPERAND_S1_1, UBICOM32_OPERAND_S1_2, UBICOM32_OPERAND_S1_4 -+ , UBICOM32_OPERAND_S1_EA_INDIRECT, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_OPERAND_S1_EA_IMMEDIATE, UBICOM32_OPERAND_S1_EA_DIRECT, UBICOM32_OPERAND_S1_EA_1 -+ , UBICOM32_OPERAND_S1_EA_2, UBICOM32_OPERAND_S1_EA_4, UBICOM32_OPERAND_S1_PEA, UBICOM32_OPERAND_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_OPERAND_PDEC_PEA_S1, UBICOM32_OPERAND_D_IMM7_1, UBICOM32_OPERAND_D_IMM7_2, UBICOM32_OPERAND_D_IMM7_4 -+ , UBICOM32_OPERAND_D_IMM8, UBICOM32_OPERAND_D_AN, UBICOM32_OPERAND_D_R, UBICOM32_OPERAND_D_AN_INC -+ , UBICOM32_OPERAND_D_I4_1, UBICOM32_OPERAND_D_I4_2, UBICOM32_OPERAND_D_I4_4, UBICOM32_OPERAND_D_INDIRECT_1 -+ , UBICOM32_OPERAND_D_INDIRECT_2, UBICOM32_OPERAND_D_INDIRECT_4, UBICOM32_OPERAND_D_INDIRECT_WITH_OFFSET_1, UBICOM32_OPERAND_D_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_OPERAND_D_INDIRECT_WITH_OFFSET_4, UBICOM32_OPERAND_D_INDIRECT_WITH_INDEX_1, UBICOM32_OPERAND_D_INDIRECT_WITH_INDEX_2, UBICOM32_OPERAND_D_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_OPERAND_D_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_OPERAND_D_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_OPERAND_D_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_OPERAND_D_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_OPERAND_D_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_OPERAND_D_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_OPERAND_D_DIRECT_ADDR, UBICOM32_OPERAND_D_DIRECT -+ , UBICOM32_OPERAND_D_IMMEDIATE_1, UBICOM32_OPERAND_D_IMMEDIATE_2, UBICOM32_OPERAND_D_IMMEDIATE_4, UBICOM32_OPERAND_D_1 -+ , UBICOM32_OPERAND_D_2, UBICOM32_OPERAND_D_4, UBICOM32_OPERAND_D_PEA_INDIRECT, UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_OFFSET -+ , UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_POST_INCREMENT, UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_PRE_INCREMENT, UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_INDEX, UBICOM32_OPERAND_D_PEA -+ , UBICOM32_OPERAND_IMM16_2, UBICOM32_OPERAND_MAX -+} CGEN_OPERAND_TYPE; -+ -+/* Number of operands types. */ -+#define MAX_OPERANDS 157 -+ -+/* Maximum number of operands referenced by any insn. */ -+#define MAX_OPERAND_INSTANCES 8 -+ -+/* Insn attribute indices. */ -+ -+/* Enum declaration for cgen_insn attrs. */ -+typedef enum cgen_insn_attr { -+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI -+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED -+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 -+ , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS -+} CGEN_INSN_ATTR; -+ -+/* Number of non-boolean elements in cgen_insn_attr. */ -+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) -+ -+/* cgen_insn attribute accessor macros. */ -+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) -+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) -+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) -+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) -+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) -+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) -+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) -+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) -+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) -+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) -+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) -+ -+/* cgen.h uses things we just defined. */ -+#include "opcode/cgen.h" -+ -+extern const struct cgen_ifld ubicom32_cgen_ifld_table[]; -+ -+/* Attributes. */ -+extern const CGEN_ATTR_TABLE ubicom32_cgen_hardware_attr_table[]; -+extern const CGEN_ATTR_TABLE ubicom32_cgen_ifield_attr_table[]; -+extern const CGEN_ATTR_TABLE ubicom32_cgen_operand_attr_table[]; -+extern const CGEN_ATTR_TABLE ubicom32_cgen_insn_attr_table[]; -+ -+/* Hardware decls. */ -+ -+extern CGEN_KEYWORD ubicom32_cgen_opval_data_names; -+extern CGEN_KEYWORD ubicom32_cgen_opval_data_names; -+extern CGEN_KEYWORD ubicom32_cgen_opval_addr_names; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_cc; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_C; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_P; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_C; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_Dest_A; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T; -+extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T_addsub; -+extern CGEN_KEYWORD ubicom32_cgen_opval_acc_names; -+extern CGEN_KEYWORD ubicom32_cgen_opval_acc_names; -+extern CGEN_KEYWORD ubicom32_cgen_opval_spad_names; -+ -+extern const CGEN_HW_ENTRY ubicom32_cgen_hw_table[]; -+ -+ -+ -+#endif /* UBICOM32_CPU_H */ ---- /dev/null -+++ b/opcodes/ubicom32-dis.c -@@ -0,0 +1,809 @@ -+/* Disassembler interface for targets using CGEN. -*- C -*- -+ CGEN: Cpu tools GENerator -+ -+ THIS FILE IS MACHINE GENERATED WITH CGEN. -+ - the resultant file is machine generated, cgen-dis.in isn't -+ -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. -+ -+ This file is part of libopcodes. -+ -+ This library is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -+ -+/* ??? Eventually more and more of this stuff can go to cpu-independent files. -+ Keep that in mind. */ -+ -+#include "sysdep.h" -+#include -+#include "ansidecl.h" -+#include "dis-asm.h" -+#include "bfd.h" -+#include "symcat.h" -+#include "libiberty.h" -+#include "ubicom32-desc.h" -+#include "ubicom32-opc.h" -+#include "opintl.h" -+ -+/* Default text to print if an instruction isn't recognized. */ -+#define UNKNOWN_INSN_MSG _("*unknown*") -+ -+static void print_normal -+ (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); -+static void print_address -+ (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; -+static void print_keyword -+ (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; -+static void print_insn_normal -+ (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); -+static int print_insn -+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); -+static int default_print_insn -+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; -+static int read_insn -+ (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, -+ unsigned long *); -+ -+/* -- disassembler routines inserted here. */ -+ -+/* -- dis.c */ -+ -+/* Output a signed 4 bit integer */ -+static void -+print_imm4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ PTR dis_info, -+ long value, -+ unsigned int attrs ATTRIBUTE_UNUSED, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ (*info->fprintf_func) (info->stream, "%d", (int)value); -+} -+ -+/* Output an unsigned 7-bit integer */ -+static void -+print_imm7 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ PTR dis_info, -+ long value, -+ unsigned int attrs ATTRIBUTE_UNUSED, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ if (value != 0) -+ (*info->fprintf_func) (info->stream, "%ld", value); -+} -+ -+/* Output an unsigned 7-bit integer */ -+static void -+print_pdec_imm7 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ PTR dis_info, -+ long value, -+ unsigned int attrs ATTRIBUTE_UNUSED, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ if (value != 0) -+ { -+ value = ~value; -+ value ++; -+ value &= 0x1fc; -+ (*info->fprintf_func) (info->stream, "%ld", value); -+ } -+ else -+ { -+ (*info->fprintf_func) (info->stream, "%d", 512); -+ } -+} -+ -+/* Output either a register or a 11bit literal immediate value */ -+static void -+print_direct_addr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ PTR dis_info, -+ long value, -+ unsigned int attrs ATTRIBUTE_UNUSED, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ struct ubicom32_cgen_data_space_map *cur; -+ -+ if(cd->machs & (1< 0x3ff) -+ /* XXX: some warning? */ ; -+ value &= 0x3ff; -+ for (; cur->name; cur++) -+ if (value == cur->address) -+ { -+ (*info->fprintf_func) (info->stream, "%s", cur->name); -+ return; -+ } -+ (*info->fprintf_func) (info->stream, "#%lx", value); -+} -+ -+static void -+print_imm24 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ PTR dis_info, -+ long value, -+ unsigned int attrs ATTRIBUTE_UNUSED, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ (*info->fprintf_func) (info->stream, "%%hi(0x%08lx)", value << 7); -+} -+ -+/* -- */ -+ -+void ubicom32_cgen_print_operand -+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); -+ -+/* Main entry point for printing operands. -+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement -+ of dis-asm.h on cgen.h. -+ -+ This function is basically just a big switch statement. Earlier versions -+ used tables to look up the function to use, but -+ - if the table contains both assembler and disassembler functions then -+ the disassembler contains much of the assembler and vice-versa, -+ - there's a lot of inlining possibilities as things grow, -+ - using a switch statement avoids the function call overhead. -+ -+ This function could be moved into `print_insn_normal', but keeping it -+ separate makes clear the interface between `print_insn_normal' and each of -+ the handlers. */ -+ -+void -+ubicom32_cgen_print_operand (CGEN_CPU_DESC cd, -+ int opindex, -+ void * xinfo, -+ CGEN_FIELDS *fields, -+ void const *attrs ATTRIBUTE_UNUSED, -+ bfd_vma pc, -+ int length) -+{ -+ disassemble_info *info = (disassemble_info *) xinfo; -+ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_Am, 0); -+ break; -+ case UBICOM32_OPERAND_AN : -+ print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_An, 0); -+ break; -+ case UBICOM32_OPERAND_C : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_C, fields->f_C, 0); -+ break; -+ case UBICOM32_OPERAND_DN : -+ print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_Dn, 0); -+ break; -+ case UBICOM32_OPERAND_P : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_P, fields->f_P, 0); -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ print_normal (cd, info, fields->f_bit5, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ print_normal (cd, info, fields->f_bit5, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_CC : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_cc, fields->f_cond, 0); -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_d_An, 0); -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ print_direct_addr (cd, info, fields->f_d_direct, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ print_imm4 (cd, info, fields->f_d_i4_1, 0|(1<f_d_i4_2, 0|(1<f_d_i4_4, 0|(1<f_d_imm7_1, 0|(1<f_d_imm7_2, 0|(1<f_d_imm7_4, 0|(1<f_d_imm8, 0|(1<f_d_r, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ print_keyword (cd, info, & ubicom32_cgen_opval_acc_names, fields->f_dsp_S2, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ print_keyword (cd, info, & ubicom32_cgen_opval_acc_names, fields->f_dsp_S2, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_dsp_S2, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_dsp_S2, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ print_normal (cd, info, fields->f_dsp_S2_sel, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_C, fields->f_dsp_C, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_Dest_A, fields->f_dsp_destA, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_T, fields->f_dsp_T, 0); -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_T_addsub, fields->f_dsp_T, 0); -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ print_normal (cd, info, fields->f_imm16_1, 0|(1<f_imm16_2, 0|(1<f_imm24, 0|(1<f_int, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ print_normal (cd, info, fields->f_o16, 0|(1<f_o21, 0|(1<f_o24, 0|(1<f_op1, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ print_normal (cd, info, fields->f_op2, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ print_pdec_imm7 (cd, info, fields->f_s1_imm7_4, 0|(1<f_s1_An, 0); -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ print_direct_addr (cd, info, fields->f_s1_direct, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ print_imm4 (cd, info, fields->f_s1_i4_1, 0|(1<f_s1_i4_2, 0|(1<f_s1_i4_4, 0|(1<f_s1_imm7_1, 0|(1<f_s1_imm7_2, 0|(1<f_s1_imm7_4, 0|(1<f_s1_imm8, 0|(1<f_s1_r, 0); -+ break; -+ case UBICOM32_OPERAND_S2 : -+ print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_s2, 0); -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ print_normal (cd, info, 0, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ print_normal (cd, info, fields->f_bit26, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_X_D : -+ print_normal (cd, info, fields->f_d, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ print_normal (cd, info, fields->f_Dn, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ print_normal (cd, info, fields->f_op2, 0, pc, length); -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ print_normal (cd, info, fields->f_s1, 0, pc, length); -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), -+ opindex); -+ abort (); -+ } -+} -+ -+cgen_print_fn * const ubicom32_cgen_print_handlers[] = -+{ -+ print_insn_normal, -+}; -+ -+ -+void -+ubicom32_cgen_init_dis (CGEN_CPU_DESC cd) -+{ -+ ubicom32_cgen_init_opcode_table (cd); -+ ubicom32_cgen_init_ibld_table (cd); -+ cd->print_handlers = & ubicom32_cgen_print_handlers[0]; -+ cd->print_operand = ubicom32_cgen_print_operand; -+} -+ -+ -+/* Default print handler. */ -+ -+static void -+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ void *dis_info, -+ long value, -+ unsigned int attrs, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ -+#ifdef CGEN_PRINT_NORMAL -+ CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); -+#endif -+ -+ /* Print the operand as directed by the attributes. */ -+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) -+ ; /* nothing to do */ -+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) -+ (*info->fprintf_func) (info->stream, "%ld", value); -+ else -+ (*info->fprintf_func) (info->stream, "0x%lx", value); -+} -+ -+/* Default address handler. */ -+ -+static void -+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ void *dis_info, -+ bfd_vma value, -+ unsigned int attrs, -+ bfd_vma pc ATTRIBUTE_UNUSED, -+ int length ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ -+#ifdef CGEN_PRINT_ADDRESS -+ CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); -+#endif -+ -+ /* Print the operand as directed by the attributes. */ -+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) -+ ; /* Nothing to do. */ -+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) -+ (*info->print_address_func) (value, info); -+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) -+ (*info->print_address_func) (value, info); -+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) -+ (*info->fprintf_func) (info->stream, "%ld", (long) value); -+ else -+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value); -+} -+ -+/* Keyword print handler. */ -+ -+static void -+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ void *dis_info, -+ CGEN_KEYWORD *keyword_table, -+ long value, -+ unsigned int attrs ATTRIBUTE_UNUSED) -+{ -+ disassemble_info *info = (disassemble_info *) dis_info; -+ const CGEN_KEYWORD_ENTRY *ke; -+ -+ ke = cgen_keyword_lookup_value (keyword_table, value); -+ if (ke != NULL) -+ (*info->fprintf_func) (info->stream, "%s", ke->name); -+ else -+ (*info->fprintf_func) (info->stream, "???"); -+} -+ -+/* Default insn printer. -+ -+ DIS_INFO is defined as `void *' so the disassembler needn't know anything -+ about disassemble_info. */ -+ -+static void -+print_insn_normal (CGEN_CPU_DESC cd, -+ void *dis_info, -+ const CGEN_INSN *insn, -+ CGEN_FIELDS *fields, -+ bfd_vma pc, -+ int length) -+{ -+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); -+ disassemble_info *info = (disassemble_info *) dis_info; -+ const CGEN_SYNTAX_CHAR_TYPE *syn; -+ -+ CGEN_INIT_PRINT (cd); -+ -+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) -+ { -+ if (CGEN_SYNTAX_MNEMONIC_P (*syn)) -+ { -+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); -+ continue; -+ } -+ if (CGEN_SYNTAX_CHAR_P (*syn)) -+ { -+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); -+ continue; -+ } -+ -+ /* We have an operand. */ -+ ubicom32_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, -+ fields, CGEN_INSN_ATTRS (insn), pc, length); -+ } -+} -+ -+/* Subroutine of print_insn. Reads an insn into the given buffers and updates -+ the extract info. -+ Returns 0 if all is well, non-zero otherwise. */ -+ -+static int -+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ bfd_vma pc, -+ disassemble_info *info, -+ bfd_byte *buf, -+ int buflen, -+ CGEN_EXTRACT_INFO *ex_info, -+ unsigned long *insn_value) -+{ -+ int status = (*info->read_memory_func) (pc, buf, buflen, info); -+ -+ if (status != 0) -+ { -+ (*info->memory_error_func) (status, pc, info); -+ return -1; -+ } -+ -+ ex_info->dis_info = info; -+ ex_info->valid = (1 << buflen) - 1; -+ ex_info->insn_bytes = buf; -+ -+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); -+ return 0; -+} -+ -+/* Utility to print an insn. -+ BUF is the base part of the insn, target byte order, BUFLEN bytes long. -+ The result is the size of the insn in bytes or zero for an unknown insn -+ or -1 if an error occurs fetching data (memory_error_func will have -+ been called). */ -+ -+static int -+print_insn (CGEN_CPU_DESC cd, -+ bfd_vma pc, -+ disassemble_info *info, -+ bfd_byte *buf, -+ unsigned int buflen) -+{ -+ CGEN_INSN_INT insn_value; -+ const CGEN_INSN_LIST *insn_list; -+ CGEN_EXTRACT_INFO ex_info; -+ int basesize; -+ -+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ -+ basesize = cd->base_insn_bitsize < buflen * 8 ? -+ cd->base_insn_bitsize : buflen * 8; -+ insn_value = cgen_get_insn_value (cd, buf, basesize); -+ -+ -+ /* Fill in ex_info fields like read_insn would. Don't actually call -+ read_insn, since the incoming buffer is already read (and possibly -+ modified a la m32r). */ -+ ex_info.valid = (1 << buflen) - 1; -+ ex_info.dis_info = info; -+ ex_info.insn_bytes = buf; -+ -+ /* The instructions are stored in hash lists. -+ Pick the first one and keep trying until we find the right one. */ -+ -+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); -+ while (insn_list != NULL) -+ { -+ const CGEN_INSN *insn = insn_list->insn; -+ CGEN_FIELDS fields; -+ int length; -+ unsigned long insn_value_cropped; -+ -+#ifdef CGEN_VALIDATE_INSN_SUPPORTED -+ /* Not needed as insn shouldn't be in hash lists if not supported. */ -+ /* Supported by this cpu? */ -+ if (! ubicom32_cgen_insn_supported (cd, insn)) -+ { -+ insn_list = CGEN_DIS_NEXT_INSN (insn_list); -+ continue; -+ } -+#endif -+ -+ /* Basic bit mask must be correct. */ -+ /* ??? May wish to allow target to defer this check until the extract -+ handler. */ -+ -+ /* Base size may exceed this instruction's size. Extract the -+ relevant part from the buffer. */ -+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && -+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) -+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), -+ info->endian == BFD_ENDIAN_BIG); -+ else -+ insn_value_cropped = insn_value; -+ -+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) -+ == CGEN_INSN_BASE_VALUE (insn)) -+ { -+ /* Printing is handled in two passes. The first pass parses the -+ machine insn and extracts the fields. The second pass prints -+ them. */ -+ -+ /* Make sure the entire insn is loaded into insn_value, if it -+ can fit. */ -+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && -+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) -+ { -+ unsigned long full_insn_value; -+ int rc = read_insn (cd, pc, info, buf, -+ CGEN_INSN_BITSIZE (insn) / 8, -+ & ex_info, & full_insn_value); -+ if (rc != 0) -+ return rc; -+ length = CGEN_EXTRACT_FN (cd, insn) -+ (cd, insn, &ex_info, full_insn_value, &fields, pc); -+ } -+ else -+ length = CGEN_EXTRACT_FN (cd, insn) -+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc); -+ -+ /* Length < 0 -> error. */ -+ if (length < 0) -+ return length; -+ if (length > 0) -+ { -+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); -+ /* Length is in bits, result is in bytes. */ -+ return length / 8; -+ } -+ } -+ -+ insn_list = CGEN_DIS_NEXT_INSN (insn_list); -+ } -+ -+ return 0; -+} -+ -+/* Default value for CGEN_PRINT_INSN. -+ The result is the size of the insn in bytes or zero for an unknown insn -+ or -1 if an error occured fetching bytes. */ -+ -+#ifndef CGEN_PRINT_INSN -+#define CGEN_PRINT_INSN default_print_insn -+#endif -+ -+static int -+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -+{ -+ bfd_byte buf[CGEN_MAX_INSN_SIZE]; -+ int buflen; -+ int status; -+ -+ /* Attempt to read the base part of the insn. */ -+ buflen = cd->base_insn_bitsize / 8; -+ status = (*info->read_memory_func) (pc, buf, buflen, info); -+ -+ /* Try again with the minimum part, if min < base. */ -+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) -+ { -+ buflen = cd->min_insn_bitsize / 8; -+ status = (*info->read_memory_func) (pc, buf, buflen, info); -+ } -+ -+ if (status != 0) -+ { -+ (*info->memory_error_func) (status, pc, info); -+ return -1; -+ } -+ -+ return print_insn (cd, pc, info, buf, buflen); -+} -+ -+/* Main entry point. -+ Print one instruction from PC on INFO->STREAM. -+ Return the size of the instruction (in bytes). */ -+ -+typedef struct cpu_desc_list -+{ -+ struct cpu_desc_list *next; -+ CGEN_BITSET *isa; -+ int mach; -+ int endian; -+ CGEN_CPU_DESC cd; -+} cpu_desc_list; -+ -+int -+print_insn_ubicom32 (bfd_vma pc, disassemble_info *info) -+{ -+ static cpu_desc_list *cd_list = 0; -+ cpu_desc_list *cl = 0; -+ static CGEN_CPU_DESC cd = 0; -+ static CGEN_BITSET *prev_isa; -+ static int prev_mach; -+ static int prev_endian; -+ int length; -+ CGEN_BITSET *isa; -+ int mach; -+ int endian = (info->endian == BFD_ENDIAN_BIG -+ ? CGEN_ENDIAN_BIG -+ : CGEN_ENDIAN_LITTLE); -+ enum bfd_architecture arch; -+ -+ /* ??? gdb will set mach but leave the architecture as "unknown" */ -+#ifndef CGEN_BFD_ARCH -+#define CGEN_BFD_ARCH bfd_arch_ubicom32 -+#endif -+ arch = info->arch; -+ if (arch == bfd_arch_unknown) -+ arch = CGEN_BFD_ARCH; -+ -+ /* There's no standard way to compute the machine or isa number -+ so we leave it to the target. */ -+#ifdef CGEN_COMPUTE_MACH -+ mach = CGEN_COMPUTE_MACH (info); -+#else -+ mach = info->mach; -+#endif -+ -+#ifdef CGEN_COMPUTE_ISA -+ { -+ static CGEN_BITSET *permanent_isa; -+ -+ if (!permanent_isa) -+ permanent_isa = cgen_bitset_create (MAX_ISAS); -+ isa = permanent_isa; -+ cgen_bitset_clear (isa); -+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); -+ } -+#else -+ isa = info->insn_sets; -+#endif -+ -+ /* If we've switched cpu's, try to find a handle we've used before */ -+ if (cd -+ && (cgen_bitset_compare (isa, prev_isa) != 0 -+ || mach != prev_mach -+ || endian != prev_endian)) -+ { -+ cd = 0; -+ for (cl = cd_list; cl; cl = cl->next) -+ { -+ if (cgen_bitset_compare (cl->isa, isa) == 0 && -+ cl->mach == mach && -+ cl->endian == endian) -+ { -+ cd = cl->cd; -+ prev_isa = cd->isas; -+ break; -+ } -+ } -+ } -+ -+ /* If we haven't initialized yet, initialize the opcode table. */ -+ if (! cd) -+ { -+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); -+ const char *mach_name; -+ -+ if (!arch_type) -+ abort (); -+ mach_name = arch_type->printable_name; -+ -+ prev_isa = cgen_bitset_copy (isa); -+ prev_mach = mach; -+ prev_endian = endian; -+ cd = ubicom32_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, -+ CGEN_CPU_OPEN_BFDMACH, mach_name, -+ CGEN_CPU_OPEN_ENDIAN, prev_endian, -+ CGEN_CPU_OPEN_END); -+ if (!cd) -+ abort (); -+ -+ /* Save this away for future reference. */ -+ cl = xmalloc (sizeof (struct cpu_desc_list)); -+ cl->cd = cd; -+ cl->isa = prev_isa; -+ cl->mach = mach; -+ cl->endian = endian; -+ cl->next = cd_list; -+ cd_list = cl; -+ -+ ubicom32_cgen_init_dis (cd); -+ } -+ -+ /* We try to have as much common code as possible. -+ But at this point some targets need to take over. */ -+ /* ??? Some targets may need a hook elsewhere. Try to avoid this, -+ but if not possible try to move this hook elsewhere rather than -+ have two hooks. */ -+ length = CGEN_PRINT_INSN (cd, pc, info); -+ if (length > 0) -+ return length; -+ if (length < 0) -+ return -1; -+ -+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); -+ return cd->default_insn_bitsize / 8; -+} ---- /dev/null -+++ b/opcodes/ubicom32-ibld.c -@@ -0,0 +1,2072 @@ -+/* Instruction building/extraction support for ubicom32. -*- C -*- -+ -+ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -+ - the resultant file is machine generated, cgen-ibld.in isn't -+ -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007 -+ Free Software Foundation, Inc. -+ -+ This file is part of libopcodes. -+ -+ This library is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -+ -+/* ??? Eventually more and more of this stuff can go to cpu-independent files. -+ Keep that in mind. */ -+ -+#include "sysdep.h" -+#include -+#include "ansidecl.h" -+#include "dis-asm.h" -+#include "bfd.h" -+#include "symcat.h" -+#include "ubicom32-desc.h" -+#include "ubicom32-opc.h" -+#include "opintl.h" -+#include "safe-ctype.h" -+ -+#undef min -+#define min(a,b) ((a) < (b) ? (a) : (b)) -+#undef max -+#define max(a,b) ((a) > (b) ? (a) : (b)) -+ -+/* Used by the ifield rtx function. */ -+#define FLD(f) (fields->f) -+ -+static const char * insert_normal -+ (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, -+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); -+static const char * insert_insn_normal -+ (CGEN_CPU_DESC, const CGEN_INSN *, -+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); -+static int extract_normal -+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, -+ unsigned int, unsigned int, unsigned int, unsigned int, -+ unsigned int, unsigned int, bfd_vma, long *); -+static int extract_insn_normal -+ (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, -+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); -+#if CGEN_INT_INSN_P -+static void put_insn_int_value -+ (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); -+#endif -+#if ! CGEN_INT_INSN_P -+static CGEN_INLINE void insert_1 -+ (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); -+static CGEN_INLINE int fill_cache -+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); -+static CGEN_INLINE long extract_1 -+ (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); -+#endif -+ -+/* Operand insertion. */ -+ -+#if ! CGEN_INT_INSN_P -+ -+/* Subroutine of insert_normal. */ -+ -+static CGEN_INLINE void -+insert_1 (CGEN_CPU_DESC cd, -+ unsigned long value, -+ int start, -+ int length, -+ int word_length, -+ unsigned char *bufp) -+{ -+ unsigned long x,mask; -+ int shift; -+ -+ x = cgen_get_insn_value (cd, bufp, word_length); -+ -+ /* Written this way to avoid undefined behaviour. */ -+ mask = (((1L << (length - 1)) - 1) << 1) | 1; -+ if (CGEN_INSN_LSB0_P) -+ shift = (start + 1) - length; -+ else -+ shift = (word_length - (start + length)); -+ x = (x & ~(mask << shift)) | ((value & mask) << shift); -+ -+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); -+} -+ -+#endif /* ! CGEN_INT_INSN_P */ -+ -+/* Default insertion routine. -+ -+ ATTRS is a mask of the boolean attributes. -+ WORD_OFFSET is the offset in bits from the start of the insn of the value. -+ WORD_LENGTH is the length of the word in bits in which the value resides. -+ START is the starting bit number in the word, architecture origin. -+ LENGTH is the length of VALUE in bits. -+ TOTAL_LENGTH is the total length of the insn in bits. -+ -+ The result is an error message or NULL if success. */ -+ -+/* ??? This duplicates functionality with bfd's howto table and -+ bfd_install_relocation. */ -+/* ??? This doesn't handle bfd_vma's. Create another function when -+ necessary. */ -+ -+static const char * -+insert_normal (CGEN_CPU_DESC cd, -+ long value, -+ unsigned int attrs, -+ unsigned int word_offset, -+ unsigned int start, -+ unsigned int length, -+ unsigned int word_length, -+ unsigned int total_length, -+ CGEN_INSN_BYTES_PTR buffer) -+{ -+ static char errbuf[100]; -+ /* Written this way to avoid undefined behaviour. */ -+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; -+ -+ /* If LENGTH is zero, this operand doesn't contribute to the value. */ -+ if (length == 0) -+ return NULL; -+ -+ if (word_length > 32) -+ abort (); -+ -+ /* For architectures with insns smaller than the base-insn-bitsize, -+ word_length may be too big. */ -+ if (cd->min_insn_bitsize < cd->base_insn_bitsize) -+ { -+ if (word_offset == 0 -+ && word_length > total_length) -+ word_length = total_length; -+ } -+ -+ /* Ensure VALUE will fit. */ -+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) -+ { -+ long minval = - (1L << (length - 1)); -+ unsigned long maxval = mask; -+ -+ if ((value > 0 && (unsigned long) value > maxval) -+ || value < minval) -+ { -+ /* xgettext:c-format */ -+ sprintf (errbuf, -+ _("operand out of range (%ld not between %ld and %lu)"), -+ value, minval, maxval); -+ return errbuf; -+ } -+ } -+ else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) -+ { -+ unsigned long maxval = mask; -+ unsigned long val = (unsigned long) value; -+ -+ /* For hosts with a word size > 32 check to see if value has been sign -+ extended beyond 32 bits. If so then ignore these higher sign bits -+ as the user is attempting to store a 32-bit signed value into an -+ unsigned 32-bit field which is allowed. */ -+ if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) -+ val &= 0xFFFFFFFF; -+ -+ if (val > maxval) -+ { -+ /* xgettext:c-format */ -+ sprintf (errbuf, -+ _("operand out of range (0x%lx not between 0 and 0x%lx)"), -+ val, maxval); -+ return errbuf; -+ } -+ } -+ else -+ { -+ if (! cgen_signed_overflow_ok_p (cd)) -+ { -+ long minval = - (1L << (length - 1)); -+ long maxval = (1L << (length - 1)) - 1; -+ -+ if (value < minval || value > maxval) -+ { -+ sprintf -+ /* xgettext:c-format */ -+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"), -+ value, minval, maxval); -+ return errbuf; -+ } -+ } -+ } -+ -+#if CGEN_INT_INSN_P -+ -+ { -+ int shift; -+ -+ if (CGEN_INSN_LSB0_P) -+ shift = (word_offset + start + 1) - length; -+ else -+ shift = total_length - (word_offset + start + length); -+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); -+ } -+ -+#else /* ! CGEN_INT_INSN_P */ -+ -+ { -+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; -+ -+ insert_1 (cd, value, start, length, word_length, bufp); -+ } -+ -+#endif /* ! CGEN_INT_INSN_P */ -+ -+ return NULL; -+} -+ -+/* Default insn builder (insert handler). -+ The instruction is recorded in CGEN_INT_INSN_P byte order (meaning -+ that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is -+ recorded in host byte order, otherwise BUFFER is an array of bytes -+ and the value is recorded in target byte order). -+ The result is an error message or NULL if success. */ -+ -+static const char * -+insert_insn_normal (CGEN_CPU_DESC cd, -+ const CGEN_INSN * insn, -+ CGEN_FIELDS * fields, -+ CGEN_INSN_BYTES_PTR buffer, -+ bfd_vma pc) -+{ -+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); -+ unsigned long value; -+ const CGEN_SYNTAX_CHAR_TYPE * syn; -+ -+ CGEN_INIT_INSERT (cd); -+ value = CGEN_INSN_BASE_VALUE (insn); -+ -+ /* If we're recording insns as numbers (rather than a string of bytes), -+ target byte order handling is deferred until later. */ -+ -+#if CGEN_INT_INSN_P -+ -+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize, -+ CGEN_FIELDS_BITSIZE (fields), value); -+ -+#else -+ -+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, -+ (unsigned) CGEN_FIELDS_BITSIZE (fields)), -+ value); -+ -+#endif /* ! CGEN_INT_INSN_P */ -+ -+ /* ??? It would be better to scan the format's fields. -+ Still need to be able to insert a value based on the operand though; -+ e.g. storing a branch displacement that got resolved later. -+ Needs more thought first. */ -+ -+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) -+ { -+ const char *errmsg; -+ -+ if (CGEN_SYNTAX_CHAR_P (* syn)) -+ continue; -+ -+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), -+ fields, buffer, pc); -+ if (errmsg) -+ return errmsg; -+ } -+ -+ return NULL; -+} -+ -+#if CGEN_INT_INSN_P -+/* Cover function to store an insn value into an integral insn. Must go here -+ because it needs -desc.h for CGEN_INT_INSN_P. */ -+ -+static void -+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ CGEN_INSN_BYTES_PTR buf, -+ int length, -+ int insn_length, -+ CGEN_INSN_INT value) -+{ -+ /* For architectures with insns smaller than the base-insn-bitsize, -+ length may be too big. */ -+ if (length > insn_length) -+ *buf = value; -+ else -+ { -+ int shift = insn_length - length; -+ /* Written this way to avoid undefined behaviour. */ -+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; -+ -+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); -+ } -+} -+#endif -+ -+/* Operand extraction. */ -+ -+#if ! CGEN_INT_INSN_P -+ -+/* Subroutine of extract_normal. -+ Ensure sufficient bytes are cached in EX_INFO. -+ OFFSET is the offset in bytes from the start of the insn of the value. -+ BYTES is the length of the needed value. -+ Returns 1 for success, 0 for failure. */ -+ -+static CGEN_INLINE int -+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ CGEN_EXTRACT_INFO *ex_info, -+ int offset, -+ int bytes, -+ bfd_vma pc) -+{ -+ /* It's doubtful that the middle part has already been fetched so -+ we don't optimize that case. kiss. */ -+ unsigned int mask; -+ disassemble_info *info = (disassemble_info *) ex_info->dis_info; -+ -+ /* First do a quick check. */ -+ mask = (1 << bytes) - 1; -+ if (((ex_info->valid >> offset) & mask) == mask) -+ return 1; -+ -+ /* Search for the first byte we need to read. */ -+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) -+ if (! (mask & ex_info->valid)) -+ break; -+ -+ if (bytes) -+ { -+ int status; -+ -+ pc += offset; -+ status = (*info->read_memory_func) -+ (pc, ex_info->insn_bytes + offset, bytes, info); -+ -+ if (status != 0) -+ { -+ (*info->memory_error_func) (status, pc, info); -+ return 0; -+ } -+ -+ ex_info->valid |= ((1 << bytes) - 1) << offset; -+ } -+ -+ return 1; -+} -+ -+/* Subroutine of extract_normal. */ -+ -+static CGEN_INLINE long -+extract_1 (CGEN_CPU_DESC cd, -+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, -+ int start, -+ int length, -+ int word_length, -+ unsigned char *bufp, -+ bfd_vma pc ATTRIBUTE_UNUSED) -+{ -+ unsigned long x; -+ int shift; -+ -+ x = cgen_get_insn_value (cd, bufp, word_length); -+ -+ if (CGEN_INSN_LSB0_P) -+ shift = (start + 1) - length; -+ else -+ shift = (word_length - (start + length)); -+ return x >> shift; -+} -+ -+#endif /* ! CGEN_INT_INSN_P */ -+ -+/* Default extraction routine. -+ -+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, -+ or sometimes less for cases like the m32r where the base insn size is 32 -+ but some insns are 16 bits. -+ ATTRS is a mask of the boolean attributes. We only need `SIGNED', -+ but for generality we take a bitmask of all of them. -+ WORD_OFFSET is the offset in bits from the start of the insn of the value. -+ WORD_LENGTH is the length of the word in bits in which the value resides. -+ START is the starting bit number in the word, architecture origin. -+ LENGTH is the length of VALUE in bits. -+ TOTAL_LENGTH is the total length of the insn in bits. -+ -+ Returns 1 for success, 0 for failure. */ -+ -+/* ??? The return code isn't properly used. wip. */ -+ -+/* ??? This doesn't handle bfd_vma's. Create another function when -+ necessary. */ -+ -+static int -+extract_normal (CGEN_CPU_DESC cd, -+#if ! CGEN_INT_INSN_P -+ CGEN_EXTRACT_INFO *ex_info, -+#else -+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, -+#endif -+ CGEN_INSN_INT insn_value, -+ unsigned int attrs, -+ unsigned int word_offset, -+ unsigned int start, -+ unsigned int length, -+ unsigned int word_length, -+ unsigned int total_length, -+#if ! CGEN_INT_INSN_P -+ bfd_vma pc, -+#else -+ bfd_vma pc ATTRIBUTE_UNUSED, -+#endif -+ long *valuep) -+{ -+ long value, mask; -+ -+ /* If LENGTH is zero, this operand doesn't contribute to the value -+ so give it a standard value of zero. */ -+ if (length == 0) -+ { -+ *valuep = 0; -+ return 1; -+ } -+ -+ if (word_length > 32) -+ abort (); -+ -+ /* For architectures with insns smaller than the insn-base-bitsize, -+ word_length may be too big. */ -+ if (cd->min_insn_bitsize < cd->base_insn_bitsize) -+ { -+ if (word_offset + word_length > total_length) -+ word_length = total_length - word_offset; -+ } -+ -+ /* Does the value reside in INSN_VALUE, and at the right alignment? */ -+ -+ if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) -+ { -+ if (CGEN_INSN_LSB0_P) -+ value = insn_value >> ((word_offset + start + 1) - length); -+ else -+ value = insn_value >> (total_length - ( word_offset + start + length)); -+ } -+ -+#if ! CGEN_INT_INSN_P -+ -+ else -+ { -+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; -+ -+ if (word_length > 32) -+ abort (); -+ -+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) -+ return 0; -+ -+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); -+ } -+ -+#endif /* ! CGEN_INT_INSN_P */ -+ -+ /* Written this way to avoid undefined behaviour. */ -+ mask = (((1L << (length - 1)) - 1) << 1) | 1; -+ -+ value &= mask; -+ /* sign extend? */ -+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) -+ && (value & (1L << (length - 1)))) -+ value |= ~mask; -+ -+ *valuep = value; -+ -+ return 1; -+} -+ -+/* Default insn extractor. -+ -+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order. -+ The extracted fields are stored in FIELDS. -+ EX_INFO is used to handle reading variable length insns. -+ Return the length of the insn in bits, or 0 if no match, -+ or -1 if an error occurs fetching data (memory_error_func will have -+ been called). */ -+ -+static int -+extract_insn_normal (CGEN_CPU_DESC cd, -+ const CGEN_INSN *insn, -+ CGEN_EXTRACT_INFO *ex_info, -+ CGEN_INSN_INT insn_value, -+ CGEN_FIELDS *fields, -+ bfd_vma pc) -+{ -+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); -+ const CGEN_SYNTAX_CHAR_TYPE *syn; -+ -+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); -+ -+ CGEN_INIT_EXTRACT (cd); -+ -+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) -+ { -+ int length; -+ -+ if (CGEN_SYNTAX_CHAR_P (*syn)) -+ continue; -+ -+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), -+ ex_info, insn_value, fields, pc); -+ if (length <= 0) -+ return length; -+ } -+ -+ /* We recognized and successfully extracted this insn. */ -+ return CGEN_INSN_BITSIZE (insn); -+} -+ -+/* Machine generated code added here. */ -+ -+const char * ubicom32_cgen_insert_operand -+ (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); -+ -+/* Main entry point for operand insertion. -+ -+ This function is basically just a big switch statement. Earlier versions -+ used tables to look up the function to use, but -+ - if the table contains both assembler and disassembler functions then -+ the disassembler contains much of the assembler and vice-versa, -+ - there's a lot of inlining possibilities as things grow, -+ - using a switch statement avoids the function call overhead. -+ -+ This function could be moved into `parse_insn_normal', but keeping it -+ separate makes clear the interface between `parse_insn_normal' and each of -+ the handlers. It's also needed by GAS to insert operands that couldn't be -+ resolved during parsing. */ -+ -+const char * -+ubicom32_cgen_insert_operand (CGEN_CPU_DESC cd, -+ int opindex, -+ CGEN_FIELDS * fields, -+ CGEN_INSN_BYTES_PTR buffer, -+ bfd_vma pc ATTRIBUTE_UNUSED) -+{ -+ const char * errmsg = NULL; -+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); -+ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ errmsg = insert_normal (cd, fields->f_Am, 0, 0, 7, 3, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_AN : -+ errmsg = insert_normal (cd, fields->f_An, 0, 0, 23, 3, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_C : -+ errmsg = insert_normal (cd, fields->f_C, 0, 0, 21, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DN : -+ errmsg = insert_normal (cd, fields->f_Dn, 0, 0, 20, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_P : -+ errmsg = insert_normal (cd, fields->f_P, 0, 0, 22, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ errmsg = insert_normal (cd, fields->f_bit5, 0, 0, 15, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ errmsg = insert_normal (cd, fields->f_bit5, 0, 0, 15, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_CC : -+ errmsg = insert_normal (cd, fields->f_cond, 0, 0, 26, 4, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ errmsg = insert_normal (cd, fields->f_d_An, 0, 0, 23, 3, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ { -+ long value = fields->f_d_direct; -+ value = ((unsigned int) (value) >> (2)); -+ errmsg = insert_normal (cd, value, 0, 0, 23, 8, 32, total_length, buffer); -+ } -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ errmsg = insert_normal (cd, fields->f_d_i4_1, 0|(1<f_d_i4_2; -+ value = ((unsigned int) (value) >> (1)); -+ errmsg = insert_normal (cd, value, 0|(1<f_d_i4_4; -+ value = ((unsigned int) (value) >> (2)); -+ errmsg = insert_normal (cd, value, 0|(1<> (5))) & (3)); -+ FLD (f_d_imm7_b) = ((((unsigned int) (FLD (f_d_imm7_1)) >> (0))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_d_imm7_t, 0, 0, 25, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_d_imm7_b, 0, 0, 20, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ { -+{ -+ FLD (f_d_imm7_t) = ((((unsigned int) (FLD (f_d_imm7_2)) >> (6))) & (3)); -+ FLD (f_d_imm7_b) = ((((unsigned int) (FLD (f_d_imm7_2)) >> (1))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_d_imm7_t, 0, 0, 25, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_d_imm7_b, 0, 0, 20, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ { -+{ -+ FLD (f_d_imm7_t) = ((((unsigned int) (FLD (f_d_imm7_4)) >> (7))) & (3)); -+ FLD (f_d_imm7_b) = ((((unsigned int) (FLD (f_d_imm7_4)) >> (2))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_d_imm7_t, 0, 0, 25, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_d_imm7_b, 0, 0, 20, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ errmsg = insert_normal (cd, fields->f_d_imm8, 0|(1<f_d_r, 0, 0, 20, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ errmsg = insert_normal (cd, fields->f_dsp_S2_sel, 0, 0, 18, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ errmsg = insert_normal (cd, fields->f_dsp_C, 0, 0, 20, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ errmsg = insert_normal (cd, fields->f_dsp_destA, 0, 0, 16, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ errmsg = insert_normal (cd, fields->f_dsp_T, 0, 0, 19, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ errmsg = insert_normal (cd, fields->f_dsp_T, 0, 0, 19, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ errmsg = insert_normal (cd, fields->f_imm16_1, 0|(1<f_imm16_2, 0|(1<> (21))) & (7)); -+ FLD (f_o20_0) = ((FLD (f_imm24)) & (2097151)); -+} -+ errmsg = insert_normal (cd, fields->f_imm23_21, 0, 0, 26, 3, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_o20_0, 0, 0, 20, 21, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ errmsg = insert_normal (cd, fields->f_int, 0, 0, 5, 6, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ { -+ fields->f_o16 = ((int) (fields->f_o16) >> (2)); -+{ -+ FLD (f_o15_13) = ((((unsigned int) (FLD (f_o16)) >> (13))) & (7)); -+ FLD (f_o12_8) = ((((unsigned int) (FLD (f_o16)) >> (8))) & (31)); -+ FLD (f_o7_5) = ((((unsigned int) (FLD (f_o16)) >> (5))) & (7)); -+ FLD (f_o4_0) = ((FLD (f_o16)) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_o15_13, 0|(1<f_o12_8, 0, 0, 20, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_o7_5, 0, 0, 10, 3, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_o4_0, 0, 0, 4, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ { -+ long value = fields->f_o21; -+ value = ((unsigned int) (((value) - (pc))) >> (2)); -+ errmsg = insert_normal (cd, value, 0|(1<f_o24 = ((int) (((fields->f_o24) - (pc))) >> (2)); -+{ -+ FLD (f_o23_21) = ((((unsigned int) (FLD (f_o24)) >> (21))) & (7)); -+ FLD (f_o20_0) = ((FLD (f_o24)) & (2097151)); -+} -+ errmsg = insert_normal (cd, fields->f_o23_21, 0|(1<f_o20_0, 0, 0, 20, 21, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ errmsg = insert_normal (cd, fields->f_op1, 0, 0, 31, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ errmsg = insert_normal (cd, fields->f_op2, 0, 0, 15, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ { -+{ -+ FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (7))) & (3)); -+ FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (2))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ errmsg = insert_normal (cd, fields->f_s1_An, 0, 0, 7, 3, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ { -+ long value = fields->f_s1_direct; -+ value = ((unsigned int) (value) >> (2)); -+ errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer); -+ } -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ errmsg = insert_normal (cd, fields->f_s1_i4_1, 0|(1<f_s1_i4_2; -+ value = ((unsigned int) (value) >> (1)); -+ errmsg = insert_normal (cd, value, 0|(1<f_s1_i4_4; -+ value = ((unsigned int) (value) >> (2)); -+ errmsg = insert_normal (cd, value, 0|(1<> (5))) & (3)); -+ FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_1)) >> (0))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ { -+{ -+ FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_2)) >> (6))) & (3)); -+ FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_2)) >> (1))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ { -+{ -+ FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (7))) & (3)); -+ FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (2))) & (31)); -+} -+ errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer); -+ if (errmsg) -+ break; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ errmsg = insert_normal (cd, fields->f_s1_imm8, 0|(1<f_s1_r, 0, 0, 4, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_S2 : -+ errmsg = insert_normal (cd, fields->f_s2, 0, 0, 14, 4, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ errmsg = insert_normal (cd, fields->f_bit26, 0, 0, 26, 1, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_X_D : -+ errmsg = insert_normal (cd, fields->f_d, 0, 0, 26, 11, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ errmsg = insert_normal (cd, fields->f_Dn, 0, 0, 20, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ errmsg = insert_normal (cd, fields->f_op2, 0, 0, 15, 5, 32, total_length, buffer); -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ errmsg = insert_normal (cd, fields->f_s1, 0, 0, 10, 11, 32, total_length, buffer); -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while building insn.\n"), -+ opindex); -+ abort (); -+ } -+ -+ return errmsg; -+} -+ -+int ubicom32_cgen_extract_operand -+ (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); -+ -+/* Main entry point for operand extraction. -+ The result is <= 0 for error, >0 for success. -+ ??? Actual values aren't well defined right now. -+ -+ This function is basically just a big switch statement. Earlier versions -+ used tables to look up the function to use, but -+ - if the table contains both assembler and disassembler functions then -+ the disassembler contains much of the assembler and vice-versa, -+ - there's a lot of inlining possibilities as things grow, -+ - using a switch statement avoids the function call overhead. -+ -+ This function could be moved into `print_insn_normal', but keeping it -+ separate makes clear the interface between `print_insn_normal' and each of -+ the handlers. */ -+ -+int -+ubicom32_cgen_extract_operand (CGEN_CPU_DESC cd, -+ int opindex, -+ CGEN_EXTRACT_INFO *ex_info, -+ CGEN_INSN_INT insn_value, -+ CGEN_FIELDS * fields, -+ bfd_vma pc) -+{ -+ /* Assume success (for those operands that are nops). */ -+ int length = 1; -+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); -+ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_Am); -+ break; -+ case UBICOM32_OPERAND_AN : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_An); -+ break; -+ case UBICOM32_OPERAND_C : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 1, 32, total_length, pc, & fields->f_C); -+ break; -+ case UBICOM32_OPERAND_DN : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_Dn); -+ break; -+ case UBICOM32_OPERAND_P : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 1, 32, total_length, pc, & fields->f_P); -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_bit5); -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_bit5); -+ break; -+ case UBICOM32_OPERAND_CC : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 4, 32, total_length, pc, & fields->f_cond); -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_d_An); -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & value); -+ value = ((value) << (2)); -+ fields->f_d_direct = value; -+ } -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d_i4_1); -+ break; -+ case UBICOM32_OPERAND_D_I4_2 : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d_i4_2 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_D_I4_4 : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d_i4_4 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM7_1 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_d_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_d_imm7_1) = ((((((FLD (f_d_imm7_t)) << (5))) | (FLD (f_d_imm7_b)))) << (0)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_d_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_d_imm7_2) = ((((((FLD (f_d_imm7_t)) << (5))) | (FLD (f_d_imm7_b)))) << (1)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_d_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_d_imm7_4) = ((((((FLD (f_d_imm7_t)) << (5))) | (FLD (f_d_imm7_b)))) << (2)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d_imm8); -+ break; -+ case UBICOM32_OPERAND_D_R : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_r); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2); -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 1, 32, total_length, pc, & fields->f_dsp_S2_sel); -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_dsp_C); -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_dsp_destA); -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_dsp_T); -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_dsp_T); -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16_1); -+ break; -+ case UBICOM32_OPERAND_IMM16_2 : -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16_2); -+ break; -+ case UBICOM32_OPERAND_IMM24 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 3, 32, total_length, pc, & fields->f_imm23_21); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 21, 32, total_length, pc, & fields->f_o20_0); -+ if (length <= 0) break; -+{ -+ FLD (f_imm24) = ((FLD (f_o20_0)) | (((FLD (f_imm23_21)) << (21)))); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_int); -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_o15_13); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_o12_8); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 3, 32, total_length, pc, & fields->f_o7_5); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_o4_0); -+ if (length <= 0) break; -+{ -+ FLD (f_o16) = ((FLD (f_o4_0)) | (((((FLD (f_o15_13)) << (13))) | (((((FLD (f_o12_8)) << (8))) | (((FLD (f_o7_5)) << (5)))))))); -+} -+ fields->f_o16 = ((fields->f_o16) << (2)); -+ } -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_o21 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_OFFSET24 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_o23_21); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 21, 32, total_length, pc, & fields->f_o20_0); -+ if (length <= 0) break; -+{ -+ FLD (f_o24) = ((FLD (f_o20_0)) | (((FLD (f_o23_21)) << (21)))); -+} -+ fields->f_o24 = ((((fields->f_o24) << (2))) + (pc)); -+ } -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 5, 32, total_length, pc, & fields->f_op1); -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_op2); -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_s1_imm7_4) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (2)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_s1_An); -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value); -+ value = ((value) << (2)); -+ fields->f_s1_direct = value; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s1_i4_1); -+ break; -+ case UBICOM32_OPERAND_S1_I4_2 : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s1_i4_2 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_I4_4 : -+ { -+ long value; -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s1_i4_4 = value; -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_1 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_s1_imm7_1) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (0)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_s1_imm7_2) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (1)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ { -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t); -+ if (length <= 0) break; -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b); -+ if (length <= 0) break; -+{ -+ FLD (f_s1_imm7_4) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (2)); -+} -+ } -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s1_imm8); -+ break; -+ case UBICOM32_OPERAND_S1_R : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_r); -+ break; -+ case UBICOM32_OPERAND_S2 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_s2); -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_bit26); -+ break; -+ case UBICOM32_OPERAND_X_D : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 11, 32, total_length, pc, & fields->f_d); -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_Dn); -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_op2); -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_s1); -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), -+ opindex); -+ abort (); -+ } -+ -+ return length; -+} -+ -+cgen_insert_fn * const ubicom32_cgen_insert_handlers[] = -+{ -+ insert_insn_normal, -+}; -+ -+cgen_extract_fn * const ubicom32_cgen_extract_handlers[] = -+{ -+ extract_insn_normal, -+}; -+ -+int ubicom32_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); -+bfd_vma ubicom32_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); -+ -+/* Getting values from cgen_fields is handled by a collection of functions. -+ They are distinguished by the type of the VALUE argument they return. -+ TODO: floating point, inlining support, remove cases where result type -+ not appropriate. */ -+ -+int -+ubicom32_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ int opindex, -+ const CGEN_FIELDS * fields) -+{ -+ int value; -+ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ value = fields->f_Am; -+ break; -+ case UBICOM32_OPERAND_AN : -+ value = fields->f_An; -+ break; -+ case UBICOM32_OPERAND_C : -+ value = fields->f_C; -+ break; -+ case UBICOM32_OPERAND_DN : -+ value = fields->f_Dn; -+ break; -+ case UBICOM32_OPERAND_P : -+ value = fields->f_P; -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ value = fields->f_bit5; -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ value = fields->f_bit5; -+ break; -+ case UBICOM32_OPERAND_CC : -+ value = fields->f_cond; -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ value = fields->f_d_An; -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ value = fields->f_d_direct; -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ value = fields->f_d_i4_1; -+ break; -+ case UBICOM32_OPERAND_D_I4_2 : -+ value = fields->f_d_i4_2; -+ break; -+ case UBICOM32_OPERAND_D_I4_4 : -+ value = fields->f_d_i4_4; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_1 : -+ value = fields->f_d_imm7_1; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ value = fields->f_d_imm7_2; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ value = fields->f_d_imm7_4; -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ value = fields->f_d_imm8; -+ break; -+ case UBICOM32_OPERAND_D_R : -+ value = fields->f_d_r; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ value = fields->f_dsp_S2_sel; -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ value = fields->f_dsp_C; -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ value = fields->f_dsp_destA; -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ value = fields->f_dsp_T; -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ value = fields->f_dsp_T; -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ value = fields->f_imm16_1; -+ break; -+ case UBICOM32_OPERAND_IMM16_2 : -+ value = fields->f_imm16_2; -+ break; -+ case UBICOM32_OPERAND_IMM24 : -+ value = fields->f_imm24; -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ value = fields->f_int; -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ value = fields->f_o16; -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ value = fields->f_o21; -+ break; -+ case UBICOM32_OPERAND_OFFSET24 : -+ value = fields->f_o24; -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ value = fields->f_op1; -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ value = fields->f_op2; -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ value = fields->f_s1_imm7_4; -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ value = fields->f_s1_An; -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ value = fields->f_s1_direct; -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ value = fields->f_s1_i4_1; -+ break; -+ case UBICOM32_OPERAND_S1_I4_2 : -+ value = fields->f_s1_i4_2; -+ break; -+ case UBICOM32_OPERAND_S1_I4_4 : -+ value = fields->f_s1_i4_4; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_1 : -+ value = fields->f_s1_imm7_1; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ value = fields->f_s1_imm7_2; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ value = fields->f_s1_imm7_4; -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ value = fields->f_s1_imm8; -+ break; -+ case UBICOM32_OPERAND_S1_R : -+ value = fields->f_s1_r; -+ break; -+ case UBICOM32_OPERAND_S2 : -+ value = fields->f_s2; -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ value = fields->f_bit26; -+ break; -+ case UBICOM32_OPERAND_X_D : -+ value = fields->f_d; -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ value = fields->f_Dn; -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ value = fields->f_op2; -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ value = fields->f_s1; -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), -+ opindex); -+ abort (); -+ } -+ -+ return value; -+} -+ -+bfd_vma -+ubicom32_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ int opindex, -+ const CGEN_FIELDS * fields) -+{ -+ bfd_vma value; -+ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ value = fields->f_Am; -+ break; -+ case UBICOM32_OPERAND_AN : -+ value = fields->f_An; -+ break; -+ case UBICOM32_OPERAND_C : -+ value = fields->f_C; -+ break; -+ case UBICOM32_OPERAND_DN : -+ value = fields->f_Dn; -+ break; -+ case UBICOM32_OPERAND_P : -+ value = fields->f_P; -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ value = fields->f_bit5; -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ value = fields->f_bit5; -+ break; -+ case UBICOM32_OPERAND_CC : -+ value = fields->f_cond; -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ value = fields->f_d_An; -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ value = fields->f_d_direct; -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ value = fields->f_d_i4_1; -+ break; -+ case UBICOM32_OPERAND_D_I4_2 : -+ value = fields->f_d_i4_2; -+ break; -+ case UBICOM32_OPERAND_D_I4_4 : -+ value = fields->f_d_i4_4; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_1 : -+ value = fields->f_d_imm7_1; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ value = fields->f_d_imm7_2; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ value = fields->f_d_imm7_4; -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ value = fields->f_d_imm8; -+ break; -+ case UBICOM32_OPERAND_D_R : -+ value = fields->f_d_r; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ value = fields->f_dsp_S2; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ value = fields->f_dsp_S2_sel; -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ value = fields->f_dsp_C; -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ value = fields->f_dsp_destA; -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ value = fields->f_dsp_T; -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ value = fields->f_dsp_T; -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ value = fields->f_imm16_1; -+ break; -+ case UBICOM32_OPERAND_IMM16_2 : -+ value = fields->f_imm16_2; -+ break; -+ case UBICOM32_OPERAND_IMM24 : -+ value = fields->f_imm24; -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ value = fields->f_int; -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ value = fields->f_o16; -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ value = fields->f_o21; -+ break; -+ case UBICOM32_OPERAND_OFFSET24 : -+ value = fields->f_o24; -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ value = fields->f_op1; -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ value = fields->f_op2; -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ value = fields->f_s1_imm7_4; -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ value = fields->f_s1_An; -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ value = fields->f_s1_direct; -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ value = fields->f_s1_i4_1; -+ break; -+ case UBICOM32_OPERAND_S1_I4_2 : -+ value = fields->f_s1_i4_2; -+ break; -+ case UBICOM32_OPERAND_S1_I4_4 : -+ value = fields->f_s1_i4_4; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_1 : -+ value = fields->f_s1_imm7_1; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ value = fields->f_s1_imm7_2; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ value = fields->f_s1_imm7_4; -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ value = fields->f_s1_imm8; -+ break; -+ case UBICOM32_OPERAND_S1_R : -+ value = fields->f_s1_r; -+ break; -+ case UBICOM32_OPERAND_S2 : -+ value = fields->f_s2; -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ value = 0; -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ value = fields->f_bit26; -+ break; -+ case UBICOM32_OPERAND_X_D : -+ value = fields->f_d; -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ value = fields->f_Dn; -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ value = fields->f_op2; -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ value = fields->f_s1; -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), -+ opindex); -+ abort (); -+ } -+ -+ return value; -+} -+ -+void ubicom32_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); -+void ubicom32_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); -+ -+/* Stuffing values in cgen_fields is handled by a collection of functions. -+ They are distinguished by the type of the VALUE argument they accept. -+ TODO: floating point, inlining support, remove cases where argument type -+ not appropriate. */ -+ -+void -+ubicom32_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ int opindex, -+ CGEN_FIELDS * fields, -+ int value) -+{ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ fields->f_Am = value; -+ break; -+ case UBICOM32_OPERAND_AN : -+ fields->f_An = value; -+ break; -+ case UBICOM32_OPERAND_C : -+ fields->f_C = value; -+ break; -+ case UBICOM32_OPERAND_DN : -+ fields->f_Dn = value; -+ break; -+ case UBICOM32_OPERAND_P : -+ fields->f_P = value; -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ fields->f_bit5 = value; -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ fields->f_bit5 = value; -+ break; -+ case UBICOM32_OPERAND_CC : -+ fields->f_cond = value; -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ fields->f_d_An = value; -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ fields->f_d_direct = value; -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ fields->f_d_i4_1 = value; -+ break; -+ case UBICOM32_OPERAND_D_I4_2 : -+ fields->f_d_i4_2 = value; -+ break; -+ case UBICOM32_OPERAND_D_I4_4 : -+ fields->f_d_i4_4 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_1 : -+ fields->f_d_imm7_1 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ fields->f_d_imm7_2 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ fields->f_d_imm7_4 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ fields->f_d_imm8 = value; -+ break; -+ case UBICOM32_OPERAND_D_R : -+ fields->f_d_r = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ fields->f_dsp_S2_sel = value; -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ fields->f_dsp_C = value; -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ fields->f_dsp_destA = value; -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ fields->f_dsp_T = value; -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ fields->f_dsp_T = value; -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ fields->f_imm16_1 = value; -+ break; -+ case UBICOM32_OPERAND_IMM16_2 : -+ fields->f_imm16_2 = value; -+ break; -+ case UBICOM32_OPERAND_IMM24 : -+ fields->f_imm24 = value; -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ fields->f_int = value; -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ fields->f_o16 = value; -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ fields->f_o21 = value; -+ break; -+ case UBICOM32_OPERAND_OFFSET24 : -+ fields->f_o24 = value; -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ fields->f_op1 = value; -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ fields->f_op2 = value; -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ fields->f_s1_imm7_4 = value; -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ fields->f_s1_An = value; -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ fields->f_s1_direct = value; -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ fields->f_s1_i4_1 = value; -+ break; -+ case UBICOM32_OPERAND_S1_I4_2 : -+ fields->f_s1_i4_2 = value; -+ break; -+ case UBICOM32_OPERAND_S1_I4_4 : -+ fields->f_s1_i4_4 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_1 : -+ fields->f_s1_imm7_1 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ fields->f_s1_imm7_2 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ fields->f_s1_imm7_4 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ fields->f_s1_imm8 = value; -+ break; -+ case UBICOM32_OPERAND_S1_R : -+ fields->f_s1_r = value; -+ break; -+ case UBICOM32_OPERAND_S2 : -+ fields->f_s2 = value; -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ fields->f_bit26 = value; -+ break; -+ case UBICOM32_OPERAND_X_D : -+ fields->f_d = value; -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ fields->f_Dn = value; -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ fields->f_op2 = value; -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ fields->f_s1 = value; -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), -+ opindex); -+ abort (); -+ } -+} -+ -+void -+ubicom32_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, -+ int opindex, -+ CGEN_FIELDS * fields, -+ bfd_vma value) -+{ -+ switch (opindex) -+ { -+ case UBICOM32_OPERAND_AM : -+ fields->f_Am = value; -+ break; -+ case UBICOM32_OPERAND_AN : -+ fields->f_An = value; -+ break; -+ case UBICOM32_OPERAND_C : -+ fields->f_C = value; -+ break; -+ case UBICOM32_OPERAND_DN : -+ fields->f_Dn = value; -+ break; -+ case UBICOM32_OPERAND_P : -+ fields->f_P = value; -+ break; -+ case UBICOM32_OPERAND_ACC1HI : -+ break; -+ case UBICOM32_OPERAND_ACC1LO : -+ break; -+ case UBICOM32_OPERAND_BIT5 : -+ fields->f_bit5 = value; -+ break; -+ case UBICOM32_OPERAND_BIT5_ADDSUB : -+ fields->f_bit5 = value; -+ break; -+ case UBICOM32_OPERAND_CC : -+ fields->f_cond = value; -+ break; -+ case UBICOM32_OPERAND_D_AN : -+ fields->f_d_An = value; -+ break; -+ case UBICOM32_OPERAND_D_DIRECT_ADDR : -+ fields->f_d_direct = value; -+ break; -+ case UBICOM32_OPERAND_D_I4_1 : -+ fields->f_d_i4_1 = value; -+ break; -+ case UBICOM32_OPERAND_D_I4_2 : -+ fields->f_d_i4_2 = value; -+ break; -+ case UBICOM32_OPERAND_D_I4_4 : -+ fields->f_d_i4_4 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_1 : -+ fields->f_d_imm7_1 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_2 : -+ fields->f_d_imm7_2 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM7_4 : -+ fields->f_d_imm7_4 = value; -+ break; -+ case UBICOM32_OPERAND_D_IMM8 : -+ fields->f_d_imm8 = value; -+ break; -+ case UBICOM32_OPERAND_D_R : -+ fields->f_d_r = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB : -+ fields->f_dsp_S2 = value; -+ break; -+ case UBICOM32_OPERAND_DSP_S2_SEL : -+ fields->f_dsp_S2_sel = value; -+ break; -+ case UBICOM32_OPERAND_DSP_C : -+ fields->f_dsp_C = value; -+ break; -+ case UBICOM32_OPERAND_DSP_DESTA : -+ fields->f_dsp_destA = value; -+ break; -+ case UBICOM32_OPERAND_DSP_T : -+ fields->f_dsp_T = value; -+ break; -+ case UBICOM32_OPERAND_DSP_T_ADDSUB : -+ fields->f_dsp_T = value; -+ break; -+ case UBICOM32_OPERAND_IMM16_1 : -+ fields->f_imm16_1 = value; -+ break; -+ case UBICOM32_OPERAND_IMM16_2 : -+ fields->f_imm16_2 = value; -+ break; -+ case UBICOM32_OPERAND_IMM24 : -+ fields->f_imm24 = value; -+ break; -+ case UBICOM32_OPERAND_INTERRUPT : -+ fields->f_int = value; -+ break; -+ case UBICOM32_OPERAND_IREAD : -+ break; -+ case UBICOM32_OPERAND_IRQ_0 : -+ break; -+ case UBICOM32_OPERAND_IRQ_1 : -+ break; -+ case UBICOM32_OPERAND_MACHI : -+ break; -+ case UBICOM32_OPERAND_MACLO : -+ break; -+ case UBICOM32_OPERAND_OFFSET16 : -+ fields->f_o16 = value; -+ break; -+ case UBICOM32_OPERAND_OFFSET21 : -+ fields->f_o21 = value; -+ break; -+ case UBICOM32_OPERAND_OFFSET24 : -+ fields->f_o24 = value; -+ break; -+ case UBICOM32_OPERAND_OPC1 : -+ fields->f_op1 = value; -+ break; -+ case UBICOM32_OPERAND_OPC2 : -+ fields->f_op2 = value; -+ break; -+ case UBICOM32_OPERAND_PDEC_S1_IMM7_4 : -+ fields->f_s1_imm7_4 = value; -+ break; -+ case UBICOM32_OPERAND_S1_AN : -+ fields->f_s1_An = value; -+ break; -+ case UBICOM32_OPERAND_S1_DIRECT_ADDR : -+ fields->f_s1_direct = value; -+ break; -+ case UBICOM32_OPERAND_S1_I4_1 : -+ fields->f_s1_i4_1 = value; -+ break; -+ case UBICOM32_OPERAND_S1_I4_2 : -+ fields->f_s1_i4_2 = value; -+ break; -+ case UBICOM32_OPERAND_S1_I4_4 : -+ fields->f_s1_i4_4 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_1 : -+ fields->f_s1_imm7_1 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_2 : -+ fields->f_s1_imm7_2 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM7_4 : -+ fields->f_s1_imm7_4 = value; -+ break; -+ case UBICOM32_OPERAND_S1_IMM8 : -+ fields->f_s1_imm8 = value; -+ break; -+ case UBICOM32_OPERAND_S1_R : -+ fields->f_s1_r = value; -+ break; -+ case UBICOM32_OPERAND_S2 : -+ fields->f_s2 = value; -+ break; -+ case UBICOM32_OPERAND_SRC3 : -+ break; -+ case UBICOM32_OPERAND_X_BIT26 : -+ fields->f_bit26 = value; -+ break; -+ case UBICOM32_OPERAND_X_D : -+ fields->f_d = value; -+ break; -+ case UBICOM32_OPERAND_X_DN : -+ fields->f_Dn = value; -+ break; -+ case UBICOM32_OPERAND_X_OP2 : -+ fields->f_op2 = value; -+ break; -+ case UBICOM32_OPERAND_X_S1 : -+ fields->f_s1 = value; -+ break; -+ -+ default : -+ /* xgettext:c-format */ -+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), -+ opindex); -+ abort (); -+ } -+} -+ -+/* Function to call before using the instruction builder tables. */ -+ -+void -+ubicom32_cgen_init_ibld_table (CGEN_CPU_DESC cd) -+{ -+ cd->insert_handlers = & ubicom32_cgen_insert_handlers[0]; -+ cd->extract_handlers = & ubicom32_cgen_extract_handlers[0]; -+ -+ cd->insert_operand = ubicom32_cgen_insert_operand; -+ cd->extract_operand = ubicom32_cgen_extract_operand; -+ -+ cd->get_int_operand = ubicom32_cgen_get_int_operand; -+ cd->set_int_operand = ubicom32_cgen_set_int_operand; -+ cd->get_vma_operand = ubicom32_cgen_get_vma_operand; -+ cd->set_vma_operand = ubicom32_cgen_set_vma_operand; -+} ---- /dev/null -+++ b/opcodes/ubicom32-opc.c -@@ -0,0 +1,20075 @@ -+/* Instruction opcode table for ubicom32. -+ -+THIS FILE IS MACHINE GENERATED WITH CGEN. -+ -+Copyright 1996-2007 Free Software Foundation, Inc. -+ -+This file is part of the GNU Binutils and/or GDB, the GNU debugger. -+ -+ This file is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -+ -+*/ -+ -+#include "sysdep.h" -+#include "ansidecl.h" -+#include "bfd.h" -+#include "symcat.h" -+#include "ubicom32-desc.h" -+#include "ubicom32-opc.h" -+#include "libiberty.h" -+ -+/* -- opc.c */ -+#include "safe-ctype.h" -+ -+unsigned int -+ubicom32_dis_hash (const char *buf, CGEN_INSN_INT value ATTRIBUTE_UNUSED) -+{ -+ unsigned int hash = (*buf >> 3); -+ return hash % CGEN_DIS_HASH_SIZE; -+} -+ -+ -+/* A better hash function for instruction mnemonics. */ -+unsigned int -+ubicom32_asm_hash (const char* insn) -+{ -+ unsigned int hash; -+ const char* m = insn; -+ -+ /* for certain instructions, the variations are coded as operands -+ and so only the mnemonic will have been used to seed the hash table. -+ Examples of this are the jmp family and the int instruction. -+ If we suspect we may have these instructions, just use the first 3 chars. -+ */ -+ if (*m == 'j' || *m == 'i' || *m=='m') -+ { -+ int i = 0; -+ for (hash = 0; *m && !ISSPACE(*m) && i < 3; m++, ++i) -+ hash = (hash * 23) ^ (0x1F & TOLOWER(*m)); -+ } -+ else -+ { -+ for (hash = 0; *m && !ISSPACE(*m); m++) -+ hash = (hash * 23) ^ (0x1F & TOLOWER(*m)); -+ } -+ -+ /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ -+ -+ return hash % CGEN_ASM_HASH_SIZE; -+} -+ -+/* Special check to ensure that instruction exists for given machine. */ -+int -+ubicom32_cgen_insn_supported (CGEN_CPU_DESC cd, -+ const CGEN_INSN *insn) -+{ -+ int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); -+ -+ /* No mach attribute? Assume it's supported for all machs. */ -+ if (machs == 0) -+ return 1; -+ -+ return ((machs & cd->machs) != 0); -+} -+ -+/* -- asm.c */ -+/* The hash functions are recorded here to help keep assembler code out of -+ the disassembler and vice versa. */ -+ -+static int asm_hash_insn_p (const CGEN_INSN *); -+static unsigned int asm_hash_insn (const char *); -+static int dis_hash_insn_p (const CGEN_INSN *); -+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); -+ -+/* Instruction formats. */ -+ -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_##f] -+#else -+#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_/**/f] -+#endif -+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { -+ 0, 0, 0x0, { { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_direct_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_immediate_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_direct_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_immediate_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_direct_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_immediate_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe6071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_direct_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_immediate_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_direct_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_immediate_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_direct_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_immediate_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffee0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe6071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_direct_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_immediate_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffe0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_direct_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_immediate_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff60400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff6071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfff60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_index ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_offset ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_ierase_d_pea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_post_increment ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_pre_increment ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iread_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff1f, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffffc00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffffc00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff1f, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_immediate_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_movei_d_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f0710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_direct_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_immediate_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_index_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_offset_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_post_increment_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_pre_increment_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_direct_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_immediate_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_index_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_offset_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_post_increment_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_btst_s1_indirect_with_pre_increment_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_index_1_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_offset_1_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_1_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_post_increment_1_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_pre_increment_1_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_index_1_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_offset_1_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_1_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_post_increment_1_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_pre_increment_1_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_direct_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_immediate_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_index_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_direct_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_immediate_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_index_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_index_2_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_offset_2_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_2_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_index_2_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_offset_2_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_2_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_direct_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_immediate_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_indirect_with_index_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_indirect_with_offset_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_indirect_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_indirect_with_post_increment_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pdec_d_indirect_with_pre_increment_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000700, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000700, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000700, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000400, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf800071f, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000710, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000710, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_moveai ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_AN) }, { F (F_IMM24) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_nop_insn ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffffff, { { F (F_OP1) }, { F (F_D) }, { F (F_IMM16_2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_jmpcc ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_COND) }, { F (F_P) }, { F (F_C) }, { F (F_O21) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_AN) }, { F (F_O24) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_calli ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf800f800, { { F (F_OP1) }, { F (F_AN) }, { F (F_BIT5) }, { F (F_AM) }, { F (F_O16) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_suspend ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffffff, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_clracc ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffeffff, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_BIT5) }, { F (F_S1) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_unused_00_11 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf800f800, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_unused_02_04 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfbe00000, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_OP2) }, { F (F_S1) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_unused_01 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_unused_DSP_06 ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfbe00000, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_OP2) }, { F (F_S1) }, { 0 } } -+}; -+ -+#undef F -+ -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define A(a) (1 << CGEN_INSN_##a) -+#else -+#define A(a) (1 << CGEN_INSN_/**/a) -+#endif -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define OPERAND(op) UBICOM32_OPERAND_##op -+#else -+#define OPERAND(op) UBICOM32_OPERAND_/**/op -+#endif -+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) -+ -+/* The instruction table. */ -+ -+static const CGEN_OPCODE ubicom32_cgen_insn_opcode_table[MAX_INSNS] = -+{ -+ /* Special null first entry. -+ A `num' value of zero is thus invalid. -+ Also, the special `invalid' insn resides here. */ -+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_direct_dsp_src2_data_reg_addsub2, { 0x36600100 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_immediate_dsp_src2_data_reg_addsub2, { 0x36600000 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_data_reg_addsub2, { 0x36600300 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_data_reg_addsub2, { 0x36600400 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_data_reg_addsub2, { 0x36600400 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_data_reg_addsub2, { 0x36600200 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_data_reg_addsub2, { 0x36600210 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36640100 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36640000 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_addsub, { 0x36640300 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_addsub, { 0x36640400 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_reg_acc_reg_addsub, { 0x36640400 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36640200 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36640210 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_direct_dsp_imm_bit5_addsub2, { 0x32600100 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_immediate_dsp_imm_bit5_addsub2, { 0x32600000 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_imm_bit5_addsub2, { 0x32600300 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_imm_bit5_addsub2, { 0x32600400 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_2_dsp_imm_bit5_addsub2, { 0x32600400 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_imm_bit5_addsub2, { 0x32600200 } -+ }, -+/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_imm_bit5_addsub2, { 0x32600210 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_direct_dsp_src2_data_reg_addsub, { 0x36400100 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_immediate_dsp_src2_data_reg_addsub, { 0x36400000 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_data_reg_addsub, { 0x36400300 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_data_reg_addsub, { 0x36400400 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_data_reg_addsub, { 0x36400400 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg_addsub, { 0x36400200 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg_addsub, { 0x36400210 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36440100 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36440000 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_addsub, { 0x36440300 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_addsub, { 0x36440400 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_reg_acc_reg_addsub, { 0x36440400 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36440200 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36440210 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_direct_dsp_imm_bit5_addsub, { 0x32400100 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_immediate_dsp_imm_bit5_addsub, { 0x32400000 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_imm_bit5_addsub, { 0x32400300 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_imm_bit5_addsub, { 0x32400400 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_4_dsp_imm_bit5_addsub, { 0x32400400 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_imm_bit5_addsub, { 0x32400200 } -+ }, -+/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5_addsub, { 0x32400210 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_direct_dsp_src2_data_reg_addsub2, { 0x36200100 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_immediate_dsp_src2_data_reg_addsub2, { 0x36200000 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_data_reg_addsub2, { 0x36200300 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_data_reg_addsub2, { 0x36200400 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_data_reg_addsub2, { 0x36200400 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_data_reg_addsub2, { 0x36200200 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_data_reg_addsub2, { 0x36200210 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36240100 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36240000 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_addsub, { 0x36240300 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_addsub, { 0x36240400 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_reg_acc_reg_addsub, { 0x36240400 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36240200 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36240210 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_direct_dsp_imm_bit5_addsub2, { 0x32200100 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_immediate_dsp_imm_bit5_addsub2, { 0x32200000 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_imm_bit5_addsub2, { 0x32200300 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_imm_bit5_addsub2, { 0x32200400 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_2_dsp_imm_bit5_addsub2, { 0x32200400 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_imm_bit5_addsub2, { 0x32200200 } -+ }, -+/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_imm_bit5_addsub2, { 0x32200210 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_direct_dsp_src2_data_reg_addsub, { 0x36000100 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_immediate_dsp_src2_data_reg_addsub, { 0x36000000 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_data_reg_addsub, { 0x36000300 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_data_reg_addsub, { 0x36000400 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_data_reg_addsub, { 0x36000400 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg_addsub, { 0x36000200 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg_addsub, { 0x36000210 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36040100 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36040000 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_addsub, { 0x36040300 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_addsub, { 0x36040400 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_reg_acc_reg_addsub, { 0x36040400 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36040200 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36040210 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_direct_dsp_imm_bit5_addsub, { 0x32000100 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_immediate_dsp_imm_bit5_addsub, { 0x32000000 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_imm_bit5_addsub, { 0x32000300 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_imm_bit5_addsub, { 0x32000400 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_4_dsp_imm_bit5_addsub, { 0x32000400 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_imm_bit5_addsub, { 0x32000200 } -+ }, -+/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5-addsub} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } }, -+ & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5_addsub, { 0x32000210 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x35200100 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x35200000 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x35200300 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x35200400 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x35200400 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x35200200 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x35200210 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x35240100 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x35240000 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x35240300 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x35240400 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x35240400 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x35240200 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x35240210 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x31200100 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x31200000 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x31200300 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x31200400 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x31200400 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x31200200 } -+ }, -+/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x31200210 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34e00100 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34e00000 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34e00300 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34e00400 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34e00400 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34e00200 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34e00210 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34e40100 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34e40000 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34e40300 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34e40400 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34e40400 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34e40200 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34e40210 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30e00100 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30e00000 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30e00300 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30e00400 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30e00400 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30e00200 } -+ }, -+/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30e00210 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34a00100 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34a00000 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34a00300 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34a00400 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34a00400 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34a00200 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34a00210 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34a40100 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34a40000 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34a40300 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34a40400 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34a40400 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34a40200 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34a40210 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30a00100 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30a00000 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30a00300 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30a00400 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30a00400 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30a00200 } -+ }, -+/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30a00210 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34800100 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34800000 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34800300 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34800400 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34800400 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34800200 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34800210 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34840100 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34840000 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34840300 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34840400 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34840400 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34840200 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34840210 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30800100 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30800000 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30800300 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30800400 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30800400 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30800200 } -+ }, -+/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30800210 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34600100 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34600000 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34600300 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34600400 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34600400 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34600200 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34600210 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34640100 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34640000 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34640300 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34640400 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34640400 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34640200 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34640210 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30600100 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30600000 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30600300 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30600400 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30600400 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30600200 } -+ }, -+/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30600210 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_direct_dsp_src2_data_reg, { 0x35400100 } -+ }, -+/* mulu.4 ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_data_reg, { 0x35400000 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_data_reg, { 0x35400300 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_data_reg, { 0x35400400 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_data_reg, { 0x35400400 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg, { 0x35400200 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg, { 0x35400210 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x35440100 } -+ }, -+/* mulu.4 ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x35440000 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_mul, { 0x35440300 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_mul, { 0x35440400 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_reg_acc_reg_mul, { 0x35440400 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35440200 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35440210 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_direct_dsp_imm_bit5, { 0x31400100 } -+ }, -+/* mulu.4 ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_immediate_dsp_imm_bit5, { 0x31400000 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_imm_bit5, { 0x31400300 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_imm_bit5, { 0x31400400 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_4_dsp_imm_bit5, { 0x31400400 } -+ }, -+/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_imm_bit5, { 0x31400200 } -+ }, -+/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5, { 0x31400210 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_direct_dsp_src2_data_reg, { 0x34400100 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_immediate_dsp_src2_data_reg, { 0x34400000 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34400300 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34400400 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_data_reg, { 0x34400400 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34400200 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34400210 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34440100 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34440000 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34440300 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34440400 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34440400 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34440200 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34440210 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_direct_dsp_imm_bit5, { 0x30400100 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_immediate_dsp_imm_bit5, { 0x30400000 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30400300 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30400400 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_2_dsp_imm_bit5, { 0x30400400 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30400200 } -+ }, -+/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30400210 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34200100 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34200000 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34200300 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34200400 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34200400 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34200200 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34200210 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34240100 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34240000 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34240300 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34240400 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34240400 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34240200 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34240210 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30200100 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30200000 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30200300 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30200400 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30200400 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30200200 } -+ }, -+/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30200210 } -+ }, -+/* muls.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_direct_dsp_src2_data_reg, { 0x35000100 } -+ }, -+/* muls.4 ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_data_reg, { 0x35000000 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_data_reg, { 0x35000300 } -+ }, -+/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_data_reg, { 0x35000400 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_data_reg, { 0x35000400 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg, { 0x35000200 } -+ }, -+/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg, { 0x35000210 } -+ }, -+/* muls.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x35040100 } -+ }, -+/* muls.4 ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x35040000 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_mul, { 0x35040300 } -+ }, -+/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_mul, { 0x35040400 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_reg_acc_reg_mul, { 0x35040400 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35040200 } -+ }, -+/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35040210 } -+ }, -+/* muls.4 ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_direct_dsp_imm_bit5, { 0x31000100 } -+ }, -+/* muls.4 ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_immediate_dsp_imm_bit5, { 0x31000000 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_imm_bit5, { 0x31000300 } -+ }, -+/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_imm_bit5, { 0x31000400 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_4_dsp_imm_bit5, { 0x31000400 } -+ }, -+/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_imm_bit5, { 0x31000200 } -+ }, -+/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5, { 0x31000210 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_direct_dsp_src2_data_reg, { 0x34000100 } -+ }, -+/* muls${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_immediate_dsp_src2_data_reg, { 0x34000000 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34000300 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34000400 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_data_reg, { 0x34000400 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34000200 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34000210 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34040100 } -+ }, -+/* muls${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34040000 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34040300 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34040400 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34040400 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34040200 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34040210 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_direct_dsp_imm_bit5, { 0x30000100 } -+ }, -+/* muls${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_immediate_dsp_imm_bit5, { 0x30000000 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30000300 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30000400 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_2_dsp_imm_bit5, { 0x30000400 } -+ }, -+/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30000200 } -+ }, -+/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30000210 } -+ }, -+/* ierase (${d-An},${d-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', 0 } }, -+ & ifmt_ierase_d_pea_indirect_with_index, { 0x3002800 } -+ }, -+/* ierase ${d-imm7-4}(${d-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', 0 } }, -+ & ifmt_ierase_d_pea_indirect_with_offset, { 0x4002800 } -+ }, -+/* ierase (${d-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', 0 } }, -+ & ifmt_ierase_d_pea_indirect, { 0x4002800 } -+ }, -+/* ierase (${d-An})${d-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', 0 } }, -+ & ifmt_ierase_d_pea_indirect_with_post_increment, { 0x2002800 } -+ }, -+/* ierase ${d-i4-4}(${d-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', 0 } }, -+ & ifmt_ierase_d_pea_indirect_with_pre_increment, { 0x2102800 } -+ }, -+/* iread (${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iread_s1_ea_indirect, { 0x3400 } -+ }, -+/* iread (${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_index_4, { 0x3300 } -+ }, -+/* iread (${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_post_increment_4, { 0x3200 } -+ }, -+/* iread ${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_pre_increment_4, { 0x3210 } -+ }, -+/* iread ${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_offset_4, { 0x3400 } -+ }, -+/* iwrite (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_direct, { 0x3008100 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_direct, { 0x4008100 } -+ }, -+/* iwrite (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_direct, { 0x4008100 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_direct, { 0x2008100 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_direct, { 0x2108100 } -+ }, -+/* iwrite (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_immediate, { 0x3008000 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_immediate, { 0x4008000 } -+ }, -+/* iwrite (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_immediate, { 0x4008000 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_immediate, { 0x2008000 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_immediate, { 0x2108000 } -+ }, -+/* iwrite (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_index_4, { 0x3008300 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_index_4, { 0x4008300 } -+ }, -+/* iwrite (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_index_4, { 0x4008300 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_index_4, { 0x2008300 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_index_4, { 0x2108300 } -+ }, -+/* iwrite (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_offset_4, { 0x3008400 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_offset_4, { 0x4008400 } -+ }, -+/* iwrite (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_offset_4, { 0x4008400 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_offset_4, { 0x2008400 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_offset_4, { 0x2108400 } -+ }, -+/* iwrite (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_4, { 0x3008400 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_4, { 0x4008400 } -+ }, -+/* iwrite (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_4, { 0x4008400 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_4, { 0x2008400 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_4, { 0x2108400 } -+ }, -+/* iwrite (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_post_increment_4, { 0x3008200 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_post_increment_4, { 0x4008200 } -+ }, -+/* iwrite (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_post_increment_4, { 0x4008200 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_post_increment_4, { 0x2008200 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_post_increment_4, { 0x2108200 } -+ }, -+/* iwrite (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_pre_increment_4, { 0x3008210 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_pre_increment_4, { 0x4008210 } -+ }, -+/* iwrite (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_pre_increment_4, { 0x4008210 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_pre_increment_4, { 0x2008210 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_pre_increment_4, { 0x2108210 } -+ }, -+/* setcsr ${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_setcsr_s1_direct, { 0x12d9100 } -+ }, -+/* setcsr #${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_setcsr_s1_immediate, { 0x12d9000 } -+ }, -+/* setcsr (${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_index_4, { 0x12d9300 } -+ }, -+/* setcsr ${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_offset_4, { 0x12d9400 } -+ }, -+/* setcsr (${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_4, { 0x12d9400 } -+ }, -+/* setcsr (${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_post_increment_4, { 0x12d9200 } -+ }, -+/* setcsr ${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_pre_increment_4, { 0x12d9210 } -+ }, -+/* bkpt ${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_setcsr_s1_direct, { 0x3900 } -+ }, -+/* bkpt #${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_setcsr_s1_immediate, { 0x3800 } -+ }, -+/* bkpt (${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_index_4, { 0x3b00 } -+ }, -+/* bkpt ${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_offset_4, { 0x3c00 } -+ }, -+/* bkpt (${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_4, { 0x3c00 } -+ }, -+/* bkpt (${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_post_increment_4, { 0x3a00 } -+ }, -+/* bkpt ${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_pre_increment_4, { 0x3a10 } -+ }, -+/* ret ${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_setcsr_s1_direct, { 0x2100 } -+ }, -+/* ret #${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_setcsr_s1_immediate, { 0x2000 } -+ }, -+/* ret (${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_index_4, { 0x2300 } -+ }, -+/* ret ${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_offset_4, { 0x2400 } -+ }, -+/* ret (${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_setcsr_s1_indirect_4, { 0x2400 } -+ }, -+/* ret (${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_post_increment_4, { 0x2200 } -+ }, -+/* ret ${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_setcsr_s1_indirect_with_pre_increment_4, { 0x2210 } -+ }, -+/* movea ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x1007100 } -+ }, -+/* movea #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_direct, { 0x7100 } -+ }, -+/* movea (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x3007100 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x4007100 } -+ }, -+/* movea (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_direct, { 0x4007100 } -+ }, -+/* movea (${d-An})${d-i4-4}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x2007100 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x2107100 } -+ }, -+/* movea ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x1007000 } -+ }, -+/* movea #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_immediate, { 0x7000 } -+ }, -+/* movea (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x3007000 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x4007000 } -+ }, -+/* movea (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_immediate, { 0x4007000 } -+ }, -+/* movea (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x2007000 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x2107000 } -+ }, -+/* movea ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x1007300 } -+ }, -+/* movea #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0x7300 } -+ }, -+/* movea (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x3007300 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4007300 } -+ }, -+/* movea (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x4007300 } -+ }, -+/* movea (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2007300 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2107300 } -+ }, -+/* movea ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x1007400 } -+ }, -+/* movea #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0x7400 } -+ }, -+/* movea (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x3007400 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4007400 } -+ }, -+/* movea (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x4007400 } -+ }, -+/* movea (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2007400 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2107400 } -+ }, -+/* movea ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_4, { 0x1007400 } -+ }, -+/* movea #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_4, { 0x7400 } -+ }, -+/* movea (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x3007400 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x4007400 } -+ }, -+/* movea (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x4007400 } -+ }, -+/* movea (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2007400 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2107400 } -+ }, -+/* movea ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x1007200 } -+ }, -+/* movea #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0x7200 } -+ }, -+/* movea (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x3007200 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4007200 } -+ }, -+/* movea (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4007200 } -+ }, -+/* movea (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2007200 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2107200 } -+ }, -+/* movea ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x1007210 } -+ }, -+/* movea #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x7210 } -+ }, -+/* movea (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x3007210 } -+ }, -+/* movea ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4007210 } -+ }, -+/* movea (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4007210 } -+ }, -+/* movea (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2007210 } -+ }, -+/* movea ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2107210 } -+ }, -+/* move.4 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x1006100 } -+ }, -+/* move.4 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_direct, { 0x6100 } -+ }, -+/* move.4 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x3006100 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x4006100 } -+ }, -+/* move.4 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_direct, { 0x4006100 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x2006100 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x2106100 } -+ }, -+/* move.4 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x1006000 } -+ }, -+/* move.4 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_immediate, { 0x6000 } -+ }, -+/* move.4 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x3006000 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x4006000 } -+ }, -+/* move.4 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_immediate, { 0x4006000 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x2006000 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x2106000 } -+ }, -+/* move.4 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x1006300 } -+ }, -+/* move.4 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0x6300 } -+ }, -+/* move.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x3006300 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4006300 } -+ }, -+/* move.4 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x4006300 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2006300 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2106300 } -+ }, -+/* move.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x1006400 } -+ }, -+/* move.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0x6400 } -+ }, -+/* move.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x3006400 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4006400 } -+ }, -+/* move.4 (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x4006400 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2006400 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2106400 } -+ }, -+/* move.4 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_4, { 0x1006400 } -+ }, -+/* move.4 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_4, { 0x6400 } -+ }, -+/* move.4 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x3006400 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x4006400 } -+ }, -+/* move.4 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x4006400 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2006400 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2106400 } -+ }, -+/* move.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x1006200 } -+ }, -+/* move.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0x6200 } -+ }, -+/* move.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x3006200 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4006200 } -+ }, -+/* move.4 (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4006200 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2006200 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2106200 } -+ }, -+/* move.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x1006210 } -+ }, -+/* move.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x6210 } -+ }, -+/* move.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x3006210 } -+ }, -+/* move.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4006210 } -+ }, -+/* move.4 (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4006210 } -+ }, -+/* move.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2006210 } -+ }, -+/* move.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2106210 } -+ }, -+/* iread (${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iread_s1_ea_indirect, { 0x12f6400 } -+ }, -+/* iread (${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_index_4, { 0x12f6300 } -+ }, -+/* iread (${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_post_increment_4, { 0x12f6200 } -+ }, -+/* iread ${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_pre_increment_4, { 0x12f6210 } -+ }, -+/* iread ${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iread_s1_ea_indirect_with_offset_4, { 0x12f6400 } -+ }, -+/* iwrite (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_direct, { 0x3006100 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_direct, { 0x4006100 } -+ }, -+/* iwrite (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_direct, { 0x4006100 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_direct, { 0x2006100 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_direct, { 0x2106100 } -+ }, -+/* iwrite (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_immediate, { 0x3006000 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_immediate, { 0x4006000 } -+ }, -+/* iwrite (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_immediate, { 0x4006000 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_immediate, { 0x2006000 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_immediate, { 0x2106000 } -+ }, -+/* iwrite (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_index_4, { 0x3006300 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_index_4, { 0x4006300 } -+ }, -+/* iwrite (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_index_4, { 0x4006300 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_index_4, { 0x2006300 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_index_4, { 0x2106300 } -+ }, -+/* iwrite (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_offset_4, { 0x3006400 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_offset_4, { 0x4006400 } -+ }, -+/* iwrite (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_offset_4, { 0x4006400 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_offset_4, { 0x2006400 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_offset_4, { 0x2106400 } -+ }, -+/* iwrite (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_4, { 0x3006400 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_4, { 0x4006400 } -+ }, -+/* iwrite (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_4, { 0x4006400 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_4, { 0x2006400 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_4, { 0x2106400 } -+ }, -+/* iwrite (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_post_increment_4, { 0x3006200 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_post_increment_4, { 0x4006200 } -+ }, -+/* iwrite (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_post_increment_4, { 0x4006200 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_post_increment_4, { 0x2006200 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_post_increment_4, { 0x2106200 } -+ }, -+/* iwrite (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_pre_increment_4, { 0x3006210 } -+ }, -+/* iwrite ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_pre_increment_4, { 0x4006210 } -+ }, -+/* iwrite (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_s1_indirect_with_pre_increment_4, { 0x4006210 } -+ }, -+/* iwrite (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_pre_increment_4, { 0x2006210 } -+ }, -+/* iwrite ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_pre_increment_4, { 0x2106210 } -+ }, -+/* move.2 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x1006900 } -+ }, -+/* move.2 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_direct, { 0x6900 } -+ }, -+/* move.2 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x3006900 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x4006900 } -+ }, -+/* move.2 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_direct, { 0x4006900 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x2006900 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x2106900 } -+ }, -+/* move.2 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x1006800 } -+ }, -+/* move.2 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_immediate, { 0x6800 } -+ }, -+/* move.2 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x3006800 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x4006800 } -+ }, -+/* move.2 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_immediate, { 0x4006800 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x2006800 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x2106800 } -+ }, -+/* move.2 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x1006b00 } -+ }, -+/* move.2 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0x6b00 } -+ }, -+/* move.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x3006b00 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x4006b00 } -+ }, -+/* move.2 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x4006b00 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x2006b00 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x2106b00 } -+ }, -+/* move.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x1006c00 } -+ }, -+/* move.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0x6c00 } -+ }, -+/* move.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x3006c00 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x4006c00 } -+ }, -+/* move.2 (${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x4006c00 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x2006c00 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x2106c00 } -+ }, -+/* move.2 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_2, { 0x1006c00 } -+ }, -+/* move.2 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0x6c00 } -+ }, -+/* move.2 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x3006c00 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x4006c00 } -+ }, -+/* move.2 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x4006c00 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x2006c00 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x2106c00 } -+ }, -+/* move.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x1006a00 } -+ }, -+/* move.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x6a00 } -+ }, -+/* move.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x3006a00 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x4006a00 } -+ }, -+/* move.2 (${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x4006a00 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x2006a00 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x2106a00 } -+ }, -+/* move.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x1006a10 } -+ }, -+/* move.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x6a10 } -+ }, -+/* move.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x3006a10 } -+ }, -+/* move.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x4006a10 } -+ }, -+/* move.2 (${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x4006a10 } -+ }, -+/* move.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x2006a10 } -+ }, -+/* move.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x2106a10 } -+ }, -+/* move.1 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x1007900 } -+ }, -+/* move.1 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_direct, { 0x7900 } -+ }, -+/* move.1 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_direct, { 0x3007900 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_direct, { 0x4007900 } -+ }, -+/* move.1 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_direct, { 0x4007900 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_direct, { 0x2007900 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_direct, { 0x2107900 } -+ }, -+/* move.1 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x1007800 } -+ }, -+/* move.1 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_immediate, { 0x7800 } -+ }, -+/* move.1 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_immediate, { 0x3007800 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_immediate, { 0x4007800 } -+ }, -+/* move.1 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_immediate, { 0x4007800 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_immediate, { 0x2007800 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x2107800 } -+ }, -+/* move.1 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_index_1, { 0x1007b00 } -+ }, -+/* move.1 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_index_1, { 0x7b00 } -+ }, -+/* move.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x3007b00 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x4007b00 } -+ }, -+/* move.1 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_index_1, { 0x4007b00 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x2007b00 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x2107b00 } -+ }, -+/* move.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_offset_1, { 0x1007c00 } -+ }, -+/* move.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_offset_1, { 0x7c00 } -+ }, -+/* move.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x3007c00 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x4007c00 } -+ }, -+/* move.1 (${d-An}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_offset_1, { 0x4007c00 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x2007c00 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x2107c00 } -+ }, -+/* move.1 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_1, { 0x1007c00 } -+ }, -+/* move.1 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_1, { 0x7c00 } -+ }, -+/* move.1 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_1, { 0x3007c00 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_1, { 0x4007c00 } -+ }, -+/* move.1 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_1, { 0x4007c00 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x2007c00 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x2107c00 } -+ }, -+/* move.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_post_increment_1, { 0x1007a00 } -+ }, -+/* move.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x7a00 } -+ }, -+/* move.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x3007a00 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x4007a00 } -+ }, -+/* move.1 (${d-An}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x4007a00 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x2007a00 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x2107a00 } -+ }, -+/* move.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_pre_increment_1, { 0x1007a10 } -+ }, -+/* move.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x7a10 } -+ }, -+/* move.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x3007a10 } -+ }, -+/* move.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x4007a10 } -+ }, -+/* move.1 (${d-An}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x4007a10 } -+ }, -+/* move.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x2007a10 } -+ }, -+/* move.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x2107a10 } -+ }, -+/* ext.2 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x100a900 } -+ }, -+/* ext.2 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_direct, { 0xa900 } -+ }, -+/* ext.2 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300a900 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400a900 } -+ }, -+/* ext.2 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_direct, { 0x400a900 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200a900 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210a900 } -+ }, -+/* ext.2 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x100a800 } -+ }, -+/* ext.2 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_immediate, { 0xa800 } -+ }, -+/* ext.2 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300a800 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400a800 } -+ }, -+/* ext.2 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400a800 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200a800 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210a800 } -+ }, -+/* ext.2 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x100ab00 } -+ }, -+/* ext.2 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0xab00 } -+ }, -+/* ext.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x300ab00 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x400ab00 } -+ }, -+/* ext.2 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x400ab00 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x200ab00 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x210ab00 } -+ }, -+/* ext.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x100ac00 } -+ }, -+/* ext.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0xac00 } -+ }, -+/* ext.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x300ac00 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x400ac00 } -+ }, -+/* ext.2 (${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x400ac00 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x200ac00 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x210ac00 } -+ }, -+/* ext.2 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_2, { 0x100ac00 } -+ }, -+/* ext.2 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0xac00 } -+ }, -+/* ext.2 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x300ac00 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x400ac00 } -+ }, -+/* ext.2 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x400ac00 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x200ac00 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x210ac00 } -+ }, -+/* ext.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x100aa00 } -+ }, -+/* ext.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0xaa00 } -+ }, -+/* ext.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x300aa00 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x400aa00 } -+ }, -+/* ext.2 (${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x400aa00 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x200aa00 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x210aa00 } -+ }, -+/* ext.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x100aa10 } -+ }, -+/* ext.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0xaa10 } -+ }, -+/* ext.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x300aa10 } -+ }, -+/* ext.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x400aa10 } -+ }, -+/* ext.2 (${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x400aa10 } -+ }, -+/* ext.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x200aa10 } -+ }, -+/* ext.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x210aa10 } -+ }, -+/* ext.1 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x100b900 } -+ }, -+/* ext.1 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_direct, { 0xb900 } -+ }, -+/* ext.1 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_direct, { 0x300b900 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_direct, { 0x400b900 } -+ }, -+/* ext.1 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_direct, { 0x400b900 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_direct, { 0x200b900 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_direct, { 0x210b900 } -+ }, -+/* ext.1 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x100b800 } -+ }, -+/* ext.1 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_immediate, { 0xb800 } -+ }, -+/* ext.1 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_immediate, { 0x300b800 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_immediate, { 0x400b800 } -+ }, -+/* ext.1 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_immediate, { 0x400b800 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_immediate, { 0x200b800 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x210b800 } -+ }, -+/* ext.1 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_index_1, { 0x100bb00 } -+ }, -+/* ext.1 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_index_1, { 0xbb00 } -+ }, -+/* ext.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x300bb00 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x400bb00 } -+ }, -+/* ext.1 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_index_1, { 0x400bb00 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x200bb00 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x210bb00 } -+ }, -+/* ext.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_offset_1, { 0x100bc00 } -+ }, -+/* ext.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_offset_1, { 0xbc00 } -+ }, -+/* ext.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x300bc00 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x400bc00 } -+ }, -+/* ext.1 (${d-An}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_offset_1, { 0x400bc00 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x200bc00 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x210bc00 } -+ }, -+/* ext.1 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_1, { 0x100bc00 } -+ }, -+/* ext.1 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_1, { 0xbc00 } -+ }, -+/* ext.1 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_1, { 0x300bc00 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_1, { 0x400bc00 } -+ }, -+/* ext.1 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_1, { 0x400bc00 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x200bc00 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x210bc00 } -+ }, -+/* ext.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_post_increment_1, { 0x100ba00 } -+ }, -+/* ext.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0xba00 } -+ }, -+/* ext.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x300ba00 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x400ba00 } -+ }, -+/* ext.1 (${d-An}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x400ba00 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x200ba00 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x210ba00 } -+ }, -+/* ext.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_direct_s1_indirect_with_pre_increment_1, { 0x100ba10 } -+ }, -+/* ext.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0xba10 } -+ }, -+/* ext.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x300ba10 } -+ }, -+/* ext.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x400ba10 } -+ }, -+/* ext.1 (${d-An}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x400ba10 } -+ }, -+/* ext.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x200ba10 } -+ }, -+/* ext.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x210ba10 } -+ }, -+/* movei ${d-direct-addr},#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_direct, { 0xc9000000 } -+ }, -+/* movei #${d-imm8},#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_immediate_2, { 0xc8000000 } -+ }, -+/* movei (${d-An},${d-r}),#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_indirect_with_index_2, { 0xcb000000 } -+ }, -+/* movei ${d-imm7-2}(${d-An}),#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_indirect_with_offset_2, { 0xcc000000 } -+ }, -+/* movei (${d-An}),#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_indirect_2, { 0xcc000000 } -+ }, -+/* movei (${d-An})${d-i4-2}++,#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_indirect_with_post_increment_2, { 0xca000000 } -+ }, -+/* movei ${d-i4-2}(${d-An})++,#${imm16-2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (IMM16_2), 0 } }, -+ & ifmt_movei_d_indirect_with_pre_increment_2, { 0xca100000 } -+ }, -+/* bclr ${d-direct-addr},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_direct, { 0x29000100 } -+ }, -+/* bclr #${d-imm8},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_direct, { 0x28000100 } -+ }, -+/* bclr (${d-An},${d-r}),${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_direct, { 0x2b000100 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_direct, { 0x2c000100 } -+ }, -+/* bclr (${d-An}),${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_direct, { 0x2c000100 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_direct, { 0x2a000100 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_direct, { 0x2a100100 } -+ }, -+/* bclr ${d-direct-addr},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_immediate, { 0x29000000 } -+ }, -+/* bclr #${d-imm8},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_immediate, { 0x28000000 } -+ }, -+/* bclr (${d-An},${d-r}),#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_immediate, { 0x2b000000 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_immediate, { 0x2c000000 } -+ }, -+/* bclr (${d-An}),#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_immediate, { 0x2c000000 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_immediate, { 0x2a000000 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_immediate, { 0x2a100000 } -+ }, -+/* bclr ${d-direct-addr},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_index_4, { 0x29000300 } -+ }, -+/* bclr #${d-imm8},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_index_4, { 0x28000300 } -+ }, -+/* bclr (${d-An},${d-r}),(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x2b000300 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x2c000300 } -+ }, -+/* bclr (${d-An}),(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_index_4, { 0x2c000300 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2a000300 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2a100300 } -+ }, -+/* bclr ${d-direct-addr},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_offset_4, { 0x29000400 } -+ }, -+/* bclr #${d-imm8},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_offset_4, { 0x28000400 } -+ }, -+/* bclr (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x2b000400 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x2c000400 } -+ }, -+/* bclr (${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_offset_4, { 0x2c000400 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2a000400 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2a100400 } -+ }, -+/* bclr ${d-direct-addr},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_4, { 0x29000400 } -+ }, -+/* bclr #${d-imm8},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_4, { 0x28000400 } -+ }, -+/* bclr (${d-An},${d-r}),(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_4, { 0x2b000400 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_4, { 0x2c000400 } -+ }, -+/* bclr (${d-An}),(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_4, { 0x2c000400 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2a000400 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2a100400 } -+ }, -+/* bclr ${d-direct-addr},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_post_increment_4, { 0x29000200 } -+ }, -+/* bclr #${d-imm8},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_post_increment_4, { 0x28000200 } -+ }, -+/* bclr (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x2b000200 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x2c000200 } -+ }, -+/* bclr (${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_post_increment_4, { 0x2c000200 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2a000200 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2a100200 } -+ }, -+/* bclr ${d-direct-addr},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_pre_increment_4, { 0x29000210 } -+ }, -+/* bclr #${d-imm8},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x28000210 } -+ }, -+/* bclr (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x2b000210 } -+ }, -+/* bclr ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x2c000210 } -+ }, -+/* bclr (${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x2c000210 } -+ }, -+/* bclr (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2a000210 } -+ }, -+/* bclr ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2a100210 } -+ }, -+/* bset ${d-direct-addr},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_direct, { 0x21000100 } -+ }, -+/* bset #${d-imm8},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_direct, { 0x20000100 } -+ }, -+/* bset (${d-An},${d-r}),${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_direct, { 0x23000100 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_direct, { 0x24000100 } -+ }, -+/* bset (${d-An}),${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_direct, { 0x24000100 } -+ }, -+/* bset (${d-An})${d-i4-4}++,${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_direct, { 0x22000100 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_direct, { 0x22100100 } -+ }, -+/* bset ${d-direct-addr},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_immediate, { 0x21000000 } -+ }, -+/* bset #${d-imm8},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_immediate, { 0x20000000 } -+ }, -+/* bset (${d-An},${d-r}),#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_immediate, { 0x23000000 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_immediate, { 0x24000000 } -+ }, -+/* bset (${d-An}),#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_immediate, { 0x24000000 } -+ }, -+/* bset (${d-An})${d-i4-4}++,#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_immediate, { 0x22000000 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_immediate, { 0x22100000 } -+ }, -+/* bset ${d-direct-addr},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_index_4, { 0x21000300 } -+ }, -+/* bset #${d-imm8},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_index_4, { 0x20000300 } -+ }, -+/* bset (${d-An},${d-r}),(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x23000300 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x24000300 } -+ }, -+/* bset (${d-An}),(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_index_4, { 0x24000300 } -+ }, -+/* bset (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x22000300 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x22100300 } -+ }, -+/* bset ${d-direct-addr},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_offset_4, { 0x21000400 } -+ }, -+/* bset #${d-imm8},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_offset_4, { 0x20000400 } -+ }, -+/* bset (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x23000400 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x24000400 } -+ }, -+/* bset (${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_offset_4, { 0x24000400 } -+ }, -+/* bset (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x22000400 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x22100400 } -+ }, -+/* bset ${d-direct-addr},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_4, { 0x21000400 } -+ }, -+/* bset #${d-imm8},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_4, { 0x20000400 } -+ }, -+/* bset (${d-An},${d-r}),(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_4, { 0x23000400 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_4, { 0x24000400 } -+ }, -+/* bset (${d-An}),(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_4, { 0x24000400 } -+ }, -+/* bset (${d-An})${d-i4-4}++,(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_4, { 0x22000400 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x22100400 } -+ }, -+/* bset ${d-direct-addr},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_post_increment_4, { 0x21000200 } -+ }, -+/* bset #${d-imm8},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_post_increment_4, { 0x20000200 } -+ }, -+/* bset (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x23000200 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x24000200 } -+ }, -+/* bset (${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_post_increment_4, { 0x24000200 } -+ }, -+/* bset (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x22000200 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x22100200 } -+ }, -+/* bset ${d-direct-addr},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_direct_s1_indirect_with_pre_increment_4, { 0x21000210 } -+ }, -+/* bset #${d-imm8},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x20000210 } -+ }, -+/* bset (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x23000210 } -+ }, -+/* bset ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x24000210 } -+ }, -+/* bset (${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x24000210 } -+ }, -+/* bset (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x22000210 } -+ }, -+/* bset ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x22100210 } -+ }, -+/* btst ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_direct_imm_bit5, { 0x10c00100 } -+ }, -+/* btst #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_immediate_imm_bit5, { 0x10c00000 } -+ }, -+/* btst (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_indirect_with_index_4_imm_bit5, { 0x10c00300 } -+ }, -+/* btst ${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_indirect_with_offset_4_imm_bit5, { 0x10c00400 } -+ }, -+/* btst (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_indirect_4_imm_bit5, { 0x10c00400 } -+ }, -+/* btst (${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_indirect_with_post_increment_4_imm_bit5, { 0x10c00200 } -+ }, -+/* btst ${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_indirect_with_pre_increment_4_imm_bit5, { 0x10c00210 } -+ }, -+/* btst ${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_direct_dyn_reg, { 0x14c00100 } -+ }, -+/* btst #${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_immediate_dyn_reg, { 0x14c00000 } -+ }, -+/* btst (${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_indirect_with_index_4_dyn_reg, { 0x14c00300 } -+ }, -+/* btst ${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_indirect_with_offset_4_dyn_reg, { 0x14c00400 } -+ }, -+/* btst (${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_indirect_4_dyn_reg, { 0x14c00400 } -+ }, -+/* btst (${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_indirect_with_post_increment_4_dyn_reg, { 0x14c00200 } -+ }, -+/* btst ${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_indirect_with_pre_increment_4_dyn_reg, { 0x14c00210 } -+ }, -+/* shmrg.2 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x13c00100 } -+ }, -+/* shmrg.2 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x17c00100 } -+ }, -+/* shmrg.2 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x13c00000 } -+ }, -+/* shmrg.2 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x17c00000 } -+ }, -+/* shmrg.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x13c00300 } -+ }, -+/* shmrg.2 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x17c00300 } -+ }, -+/* shmrg.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x13c00400 } -+ }, -+/* shmrg.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x17c00400 } -+ }, -+/* shmrg.2 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x13c00400 } -+ }, -+/* shmrg.2 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x17c00400 } -+ }, -+/* shmrg.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x13c00200 } -+ }, -+/* shmrg.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x17c00200 } -+ }, -+/* shmrg.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x13c00210 } -+ }, -+/* shmrg.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x17c00210 } -+ }, -+/* shmrg.1 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x13e00100 } -+ }, -+/* shmrg.1 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x17e00100 } -+ }, -+/* shmrg.1 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x13e00000 } -+ }, -+/* shmrg.1 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x17e00000 } -+ }, -+/* shmrg.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x13e00300 } -+ }, -+/* shmrg.1 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x17e00300 } -+ }, -+/* shmrg.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x13e00400 } -+ }, -+/* shmrg.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x17e00400 } -+ }, -+/* shmrg.1 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x13e00400 } -+ }, -+/* shmrg.1 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x17e00400 } -+ }, -+/* shmrg.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x13e00200 } -+ }, -+/* shmrg.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x17e00200 } -+ }, -+/* shmrg.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x13e00210 } -+ }, -+/* shmrg.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x17e00210 } -+ }, -+/* crcgen ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_direct_imm_bit5, { 0x11000100 } -+ }, -+/* crcgen #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_immediate_imm_bit5, { 0x11000000 } -+ }, -+/* crcgen (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_index_1_imm_bit5, { 0x11000300 } -+ }, -+/* crcgen ${s1-imm7-1}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_offset_1_imm_bit5, { 0x11000400 } -+ }, -+/* crcgen (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_crcgen_s1_indirect_1_imm_bit5, { 0x11000400 } -+ }, -+/* crcgen (${s1-An})${s1-i4-1}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_post_increment_1_imm_bit5, { 0x11000200 } -+ }, -+/* crcgen ${s1-i4-1}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_pre_increment_1_imm_bit5, { 0x11000210 } -+ }, -+/* crcgen ${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_direct_dyn_reg, { 0x15000100 } -+ }, -+/* crcgen #${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_immediate_dyn_reg, { 0x15000000 } -+ }, -+/* crcgen (${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_index_1_dyn_reg, { 0x15000300 } -+ }, -+/* crcgen ${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_offset_1_dyn_reg, { 0x15000400 } -+ }, -+/* crcgen (${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_crcgen_s1_indirect_1_dyn_reg, { 0x15000400 } -+ }, -+/* crcgen (${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_post_increment_1_dyn_reg, { 0x15000200 } -+ }, -+/* crcgen ${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_crcgen_s1_indirect_with_pre_increment_1_dyn_reg, { 0x15000210 } -+ }, -+/* bfextu ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_direct_imm_bit5, { 0x12c00100 } -+ }, -+/* bfextu ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_immediate_imm_bit5, { 0x12c00000 } -+ }, -+/* bfextu ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x12c00300 } -+ }, -+/* bfextu ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x12c00400 } -+ }, -+/* bfextu ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x12c00400 } -+ }, -+/* bfextu ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x12c00200 } -+ }, -+/* bfextu ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x12c00210 } -+ }, -+/* bfextu ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_direct_dyn_reg, { 0x16c00100 } -+ }, -+/* bfextu ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_immediate_dyn_reg, { 0x16c00000 } -+ }, -+/* bfextu ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x16c00300 } -+ }, -+/* bfextu ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x16c00400 } -+ }, -+/* bfextu ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x16c00400 } -+ }, -+/* bfextu ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x16c00200 } -+ }, -+/* bfextu ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x16c00210 } -+ }, -+/* bfrvrs ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_direct_imm_bit5, { 0x13000100 } -+ }, -+/* bfrvrs ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_immediate_imm_bit5, { 0x13000000 } -+ }, -+/* bfrvrs ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x13000300 } -+ }, -+/* bfrvrs ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x13000400 } -+ }, -+/* bfrvrs ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x13000400 } -+ }, -+/* bfrvrs ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x13000200 } -+ }, -+/* bfrvrs ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x13000210 } -+ }, -+/* bfrvrs ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_direct_dyn_reg, { 0x17000100 } -+ }, -+/* bfrvrs ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_immediate_dyn_reg, { 0x17000000 } -+ }, -+/* bfrvrs ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x17000300 } -+ }, -+/* bfrvrs ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x17000400 } -+ }, -+/* bfrvrs ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x17000400 } -+ }, -+/* bfrvrs ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x17000200 } -+ }, -+/* bfrvrs ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x17000210 } -+ }, -+/* merge ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_direct_imm_bit5, { 0x13800100 } -+ }, -+/* merge ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_immediate_imm_bit5, { 0x13800000 } -+ }, -+/* merge ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x13800300 } -+ }, -+/* merge ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x13800400 } -+ }, -+/* merge ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x13800400 } -+ }, -+/* merge ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x13800200 } -+ }, -+/* merge ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x13800210 } -+ }, -+/* merge ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_direct_dyn_reg, { 0x17800100 } -+ }, -+/* merge ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_immediate_dyn_reg, { 0x17800000 } -+ }, -+/* merge ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x17800300 } -+ }, -+/* merge ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x17800400 } -+ }, -+/* merge ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x17800400 } -+ }, -+/* merge ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x17800200 } -+ }, -+/* merge ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x17800210 } -+ }, -+/* shftd ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_direct_imm_bit5, { 0x13400100 } -+ }, -+/* shftd ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_immediate_imm_bit5, { 0x13400000 } -+ }, -+/* shftd ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x13400300 } -+ }, -+/* shftd ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x13400400 } -+ }, -+/* shftd ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x13400400 } -+ }, -+/* shftd ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x13400200 } -+ }, -+/* shftd ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x13400210 } -+ }, -+/* shftd ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_direct_dyn_reg, { 0x17400100 } -+ }, -+/* shftd ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_immediate_dyn_reg, { 0x17400000 } -+ }, -+/* shftd ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x17400300 } -+ }, -+/* shftd ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x17400400 } -+ }, -+/* shftd ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x17400400 } -+ }, -+/* shftd ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x17400200 } -+ }, -+/* shftd ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x17400210 } -+ }, -+/* asr.1 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x11800100 } -+ }, -+/* asr.1 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x15800100 } -+ }, -+/* asr.1 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x11800000 } -+ }, -+/* asr.1 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x15800000 } -+ }, -+/* asr.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x11800300 } -+ }, -+/* asr.1 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x15800300 } -+ }, -+/* asr.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x11800400 } -+ }, -+/* asr.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x15800400 } -+ }, -+/* asr.1 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x11800400 } -+ }, -+/* asr.1 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x15800400 } -+ }, -+/* asr.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x11800200 } -+ }, -+/* asr.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x15800200 } -+ }, -+/* asr.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x11800210 } -+ }, -+/* asr.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x15800210 } -+ }, -+/* lsl.1 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x11400100 } -+ }, -+/* lsl.1 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x15400100 } -+ }, -+/* lsl.1 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x11400000 } -+ }, -+/* lsl.1 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x15400000 } -+ }, -+/* lsl.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x11400300 } -+ }, -+/* lsl.1 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x15400300 } -+ }, -+/* lsl.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x11400400 } -+ }, -+/* lsl.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x15400400 } -+ }, -+/* lsl.1 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x11400400 } -+ }, -+/* lsl.1 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x15400400 } -+ }, -+/* lsl.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x11400200 } -+ }, -+/* lsl.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x15400200 } -+ }, -+/* lsl.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x11400210 } -+ }, -+/* lsl.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x15400210 } -+ }, -+/* lsr.1 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x11600100 } -+ }, -+/* lsr.1 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x15600100 } -+ }, -+/* lsr.1 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x11600000 } -+ }, -+/* lsr.1 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x15600000 } -+ }, -+/* lsr.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x11600300 } -+ }, -+/* lsr.1 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x15600300 } -+ }, -+/* lsr.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x11600400 } -+ }, -+/* lsr.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x15600400 } -+ }, -+/* lsr.1 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x11600400 } -+ }, -+/* lsr.1 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x15600400 } -+ }, -+/* lsr.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x11600200 } -+ }, -+/* lsr.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x15600200 } -+ }, -+/* lsr.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x11600210 } -+ }, -+/* lsr.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x15600210 } -+ }, -+/* asr.2 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12a00100 } -+ }, -+/* asr.2 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16a00100 } -+ }, -+/* asr.2 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12a00000 } -+ }, -+/* asr.2 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16a00000 } -+ }, -+/* asr.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x12a00300 } -+ }, -+/* asr.2 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x16a00300 } -+ }, -+/* asr.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x12a00400 } -+ }, -+/* asr.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x16a00400 } -+ }, -+/* asr.2 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x12a00400 } -+ }, -+/* asr.2 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x16a00400 } -+ }, -+/* asr.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x12a00200 } -+ }, -+/* asr.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x16a00200 } -+ }, -+/* asr.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x12a00210 } -+ }, -+/* asr.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x16a00210 } -+ }, -+/* lsl.2 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12200100 } -+ }, -+/* lsl.2 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16200100 } -+ }, -+/* lsl.2 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12200000 } -+ }, -+/* lsl.2 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16200000 } -+ }, -+/* lsl.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x12200300 } -+ }, -+/* lsl.2 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x16200300 } -+ }, -+/* lsl.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x12200400 } -+ }, -+/* lsl.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x16200400 } -+ }, -+/* lsl.2 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x12200400 } -+ }, -+/* lsl.2 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x16200400 } -+ }, -+/* lsl.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x12200200 } -+ }, -+/* lsl.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x16200200 } -+ }, -+/* lsl.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x12200210 } -+ }, -+/* lsl.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x16200210 } -+ }, -+/* lsr.2 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12600100 } -+ }, -+/* lsr.2 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16600100 } -+ }, -+/* lsr.2 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12600000 } -+ }, -+/* lsr.2 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16600000 } -+ }, -+/* lsr.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x12600300 } -+ }, -+/* lsr.2 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x16600300 } -+ }, -+/* lsr.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x12600400 } -+ }, -+/* lsr.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x16600400 } -+ }, -+/* lsr.2 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x12600400 } -+ }, -+/* lsr.2 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x16600400 } -+ }, -+/* lsr.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x12600200 } -+ }, -+/* lsr.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x16600200 } -+ }, -+/* lsr.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x12600210 } -+ }, -+/* lsr.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x16600210 } -+ }, -+/* asr.4 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12800100 } -+ }, -+/* asr.4 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16800100 } -+ }, -+/* asr.4 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12800000 } -+ }, -+/* asr.4 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16800000 } -+ }, -+/* asr.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_index_4, { 0x12800300 } -+ }, -+/* asr.4 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_index_4, { 0x16800300 } -+ }, -+/* asr.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4, { 0x12800400 } -+ }, -+/* asr.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4, { 0x16800400 } -+ }, -+/* asr.4 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_4, { 0x12800400 } -+ }, -+/* asr.4 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_4, { 0x16800400 } -+ }, -+/* asr.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4, { 0x12800200 } -+ }, -+/* asr.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4, { 0x16800200 } -+ }, -+/* asr.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4, { 0x12800210 } -+ }, -+/* asr.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4, { 0x16800210 } -+ }, -+/* lsl.4 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12000100 } -+ }, -+/* lsl.4 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16000100 } -+ }, -+/* lsl.4 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12000000 } -+ }, -+/* lsl.4 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16000000 } -+ }, -+/* lsl.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_index_4, { 0x12000300 } -+ }, -+/* lsl.4 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_index_4, { 0x16000300 } -+ }, -+/* lsl.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4, { 0x12000400 } -+ }, -+/* lsl.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4, { 0x16000400 } -+ }, -+/* lsl.4 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_4, { 0x12000400 } -+ }, -+/* lsl.4 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_4, { 0x16000400 } -+ }, -+/* lsl.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4, { 0x12000200 } -+ }, -+/* lsl.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4, { 0x16000200 } -+ }, -+/* lsl.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4, { 0x12000210 } -+ }, -+/* lsl.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4, { 0x16000210 } -+ }, -+/* lsr.4 ${Dn},${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12400100 } -+ }, -+/* lsr.4 ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16400100 } -+ }, -+/* lsr.4 ${Dn},#${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12400000 } -+ }, -+/* lsr.4 ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16400000 } -+ }, -+/* lsr.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_index_4, { 0x12400300 } -+ }, -+/* lsr.4 ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_index_4, { 0x16400300 } -+ }, -+/* lsr.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4, { 0x12400400 } -+ }, -+/* lsr.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4, { 0x16400400 } -+ }, -+/* lsr.4 ${Dn},(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_4, { 0x12400400 } -+ }, -+/* lsr.4 ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_4, { 0x16400400 } -+ }, -+/* lsr.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4, { 0x12400200 } -+ }, -+/* lsr.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4, { 0x16400200 } -+ }, -+/* lsr.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4, { 0x12400210 } -+ }, -+/* lsr.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4, { 0x16400210 } -+ }, -+/* mac ${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34200100 } -+ }, -+/* mac #${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34200000 } -+ }, -+/* mac (${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34200300 } -+ }, -+/* mac ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34200400 } -+ }, -+/* mac (${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34200400 } -+ }, -+/* mac (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34200200 } -+ }, -+/* mac ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34200210 } -+ }, -+/* mac ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30200100 } -+ }, -+/* mac #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30200000 } -+ }, -+/* mac (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30200300 } -+ }, -+/* mac ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30200400 } -+ }, -+/* mac (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30200400 } -+ }, -+/* mac (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30200200 } -+ }, -+/* mac ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30200210 } -+ }, -+/* mac ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_direct_imm_bit5, { 0x11200100 } -+ }, -+/* mac #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_immediate_imm_bit5, { 0x11200000 } -+ }, -+/* mac (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x11200300 } -+ }, -+/* mac ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x11200400 } -+ }, -+/* mac (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_2_imm_bit5, { 0x11200400 } -+ }, -+/* mac (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x11200200 } -+ }, -+/* mac ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x11200210 } -+ }, -+/* mac ${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_direct_dyn_reg, { 0x15200100 } -+ }, -+/* mac #${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_immediate_dyn_reg, { 0x15200000 } -+ }, -+/* mac (${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x15200300 } -+ }, -+/* mac ${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x15200400 } -+ }, -+/* mac (${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_2_dyn_reg, { 0x15200400 } -+ }, -+/* mac (${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x15200200 } -+ }, -+/* mac ${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x15200210 } -+ }, -+/* mulf ${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34800100 } -+ }, -+/* mulf #${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34800000 } -+ }, -+/* mulf (${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34800300 } -+ }, -+/* mulf ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34800400 } -+ }, -+/* mulf (${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34800400 } -+ }, -+/* mulf (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34800200 } -+ }, -+/* mulf ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34800210 } -+ }, -+/* mulf ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30800100 } -+ }, -+/* mulf #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30800000 } -+ }, -+/* mulf (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30800300 } -+ }, -+/* mulf ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30800400 } -+ }, -+/* mulf (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30800400 } -+ }, -+/* mulf (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30800200 } -+ }, -+/* mulf ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30800210 } -+ }, -+/* mulf ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_direct_imm_bit5, { 0x10a00100 } -+ }, -+/* mulf #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_immediate_imm_bit5, { 0x10a00000 } -+ }, -+/* mulf (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x10a00300 } -+ }, -+/* mulf ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x10a00400 } -+ }, -+/* mulf (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_2_imm_bit5, { 0x10a00400 } -+ }, -+/* mulf (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x10a00200 } -+ }, -+/* mulf ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x10a00210 } -+ }, -+/* mulf ${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_direct_dyn_reg, { 0x14a00100 } -+ }, -+/* mulf #${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_immediate_dyn_reg, { 0x14a00000 } -+ }, -+/* mulf (${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x14a00300 } -+ }, -+/* mulf ${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x14a00400 } -+ }, -+/* mulf (${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_2_dyn_reg, { 0x14a00400 } -+ }, -+/* mulf (${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x14a00200 } -+ }, -+/* mulf ${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x14a00210 } -+ }, -+/* mulu ${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34400100 } -+ }, -+/* mulu #${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34400000 } -+ }, -+/* mulu (${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34400300 } -+ }, -+/* mulu ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34400400 } -+ }, -+/* mulu (${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34400400 } -+ }, -+/* mulu (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34400200 } -+ }, -+/* mulu ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34400210 } -+ }, -+/* mulu ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30400100 } -+ }, -+/* mulu #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30400000 } -+ }, -+/* mulu (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30400300 } -+ }, -+/* mulu ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30400400 } -+ }, -+/* mulu (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30400400 } -+ }, -+/* mulu (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30400200 } -+ }, -+/* mulu ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30400210 } -+ }, -+/* mulu ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_direct_imm_bit5, { 0x10600100 } -+ }, -+/* mulu #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_immediate_imm_bit5, { 0x10600000 } -+ }, -+/* mulu (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x10600300 } -+ }, -+/* mulu ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x10600400 } -+ }, -+/* mulu (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_2_imm_bit5, { 0x10600400 } -+ }, -+/* mulu (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x10600200 } -+ }, -+/* mulu ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x10600210 } -+ }, -+/* mulu ${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_direct_dyn_reg, { 0x14600100 } -+ }, -+/* mulu #${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_immediate_dyn_reg, { 0x14600000 } -+ }, -+/* mulu (${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x14600300 } -+ }, -+/* mulu ${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x14600400 } -+ }, -+/* mulu (${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_2_dyn_reg, { 0x14600400 } -+ }, -+/* mulu (${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x14600200 } -+ }, -+/* mulu ${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x14600210 } -+ }, -+/* muls ${s1-direct-addr},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34000100 } -+ }, -+/* muls #${s1-imm8},${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34000000 } -+ }, -+/* muls (${s1-An},${s1-r}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34000300 } -+ }, -+/* muls ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34000400 } -+ }, -+/* muls (${s1-An}),${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34000400 } -+ }, -+/* muls (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34000200 } -+ }, -+/* muls ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34000210 } -+ }, -+/* muls ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30000100 } -+ }, -+/* muls #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30000000 } -+ }, -+/* muls (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30000300 } -+ }, -+/* muls ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30000400 } -+ }, -+/* muls (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30000400 } -+ }, -+/* muls (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30000200 } -+ }, -+/* muls ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30000210 } -+ }, -+/* muls ${s1-direct-addr},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_direct_imm_bit5, { 0x10200100 } -+ }, -+/* muls #${s1-imm8},#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } }, -+ & ifmt_btst_s1_immediate_imm_bit5, { 0x10200000 } -+ }, -+/* muls (${s1-An},${s1-r}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x10200300 } -+ }, -+/* muls ${s1-imm7-2}(${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x10200400 } -+ }, -+/* muls (${s1-An}),#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_2_imm_bit5, { 0x10200400 } -+ }, -+/* muls (${s1-An})${s1-i4-2}++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x10200200 } -+ }, -+/* muls ${s1-i4-2}(${s1-An})++,#${bit5} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x10200210 } -+ }, -+/* muls ${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_direct_dyn_reg, { 0x14200100 } -+ }, -+/* muls #${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_btst_s1_immediate_dyn_reg, { 0x14200000 } -+ }, -+/* muls (${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x14200300 } -+ }, -+/* muls ${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x14200400 } -+ }, -+/* muls (${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_2_dyn_reg, { 0x14200400 } -+ }, -+/* muls (${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x14200200 } -+ }, -+/* muls ${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x14200210 } -+ }, -+/* swapb.4 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x100c900 } -+ }, -+/* swapb.4 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_direct, { 0xc900 } -+ }, -+/* swapb.4 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x300c900 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x400c900 } -+ }, -+/* swapb.4 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_direct, { 0x400c900 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x200c900 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x210c900 } -+ }, -+/* swapb.4 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x100c800 } -+ }, -+/* swapb.4 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_immediate, { 0xc800 } -+ }, -+/* swapb.4 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x300c800 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x400c800 } -+ }, -+/* swapb.4 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_immediate, { 0x400c800 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x200c800 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x210c800 } -+ }, -+/* swapb.4 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x100cb00 } -+ }, -+/* swapb.4 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0xcb00 } -+ }, -+/* swapb.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x300cb00 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x400cb00 } -+ }, -+/* swapb.4 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x400cb00 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x200cb00 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x210cb00 } -+ }, -+/* swapb.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x100cc00 } -+ }, -+/* swapb.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0xcc00 } -+ }, -+/* swapb.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x300cc00 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x400cc00 } -+ }, -+/* swapb.4 (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x400cc00 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x200cc00 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x210cc00 } -+ }, -+/* swapb.4 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_4, { 0x100cc00 } -+ }, -+/* swapb.4 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_4, { 0xcc00 } -+ }, -+/* swapb.4 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x300cc00 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x400cc00 } -+ }, -+/* swapb.4 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x400cc00 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x200cc00 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x210cc00 } -+ }, -+/* swapb.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x100ca00 } -+ }, -+/* swapb.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0xca00 } -+ }, -+/* swapb.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x300ca00 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x400ca00 } -+ }, -+/* swapb.4 (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x400ca00 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x200ca00 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x210ca00 } -+ }, -+/* swapb.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x100ca10 } -+ }, -+/* swapb.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xca10 } -+ }, -+/* swapb.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x300ca10 } -+ }, -+/* swapb.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x400ca10 } -+ }, -+/* swapb.4 (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x400ca10 } -+ }, -+/* swapb.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x200ca10 } -+ }, -+/* swapb.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x210ca10 } -+ }, -+/* swapb.2 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x100c100 } -+ }, -+/* swapb.2 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_direct, { 0xc100 } -+ }, -+/* swapb.2 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300c100 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400c100 } -+ }, -+/* swapb.2 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_direct, { 0x400c100 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200c100 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210c100 } -+ }, -+/* swapb.2 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x100c000 } -+ }, -+/* swapb.2 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_immediate, { 0xc000 } -+ }, -+/* swapb.2 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300c000 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400c000 } -+ }, -+/* swapb.2 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400c000 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200c000 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210c000 } -+ }, -+/* swapb.2 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x100c300 } -+ }, -+/* swapb.2 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0xc300 } -+ }, -+/* swapb.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x300c300 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x400c300 } -+ }, -+/* swapb.2 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x400c300 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x200c300 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x210c300 } -+ }, -+/* swapb.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x100c400 } -+ }, -+/* swapb.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0xc400 } -+ }, -+/* swapb.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x300c400 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x400c400 } -+ }, -+/* swapb.2 (${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x400c400 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x200c400 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x210c400 } -+ }, -+/* swapb.2 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_2, { 0x100c400 } -+ }, -+/* swapb.2 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0xc400 } -+ }, -+/* swapb.2 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x300c400 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x400c400 } -+ }, -+/* swapb.2 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x400c400 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x200c400 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x210c400 } -+ }, -+/* swapb.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x100c200 } -+ }, -+/* swapb.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0xc200 } -+ }, -+/* swapb.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x300c200 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x400c200 } -+ }, -+/* swapb.2 (${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x400c200 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x200c200 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x210c200 } -+ }, -+/* swapb.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x100c210 } -+ }, -+/* swapb.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0xc210 } -+ }, -+/* swapb.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x300c210 } -+ }, -+/* swapb.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x400c210 } -+ }, -+/* swapb.2 (${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x400c210 } -+ }, -+/* swapb.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x200c210 } -+ }, -+/* swapb.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x210c210 } -+ }, -+/* pdec ${d-direct-addr},${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_direct_pdec_s1_ea_indirect_with_offset_4, { 0x100f400 } -+ }, -+/* pdec #${d-imm8},${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_immediate_4_pdec_s1_ea_indirect_with_offset_4, { 0xf400 } -+ }, -+/* pdec (${d-An},${d-r}),${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_indirect_with_index_4_pdec_s1_ea_indirect_with_offset_4, { 0x300f400 } -+ }, -+/* pdec ${d-imm7-4}(${d-An}),${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_indirect_with_offset_4_pdec_s1_ea_indirect_with_offset_4, { 0x400f400 } -+ }, -+/* pdec (${d-An}),${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_indirect_4_pdec_s1_ea_indirect_with_offset_4, { 0x400f400 } -+ }, -+/* pdec (${d-An})${d-i4-4}++,${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_indirect_with_post_increment_4_pdec_s1_ea_indirect_with_offset_4, { 0x200f400 } -+ }, -+/* pdec ${d-i4-4}(${d-An})++,${pdec-s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pdec_d_indirect_with_pre_increment_4_pdec_s1_ea_indirect_with_offset_4, { 0x210f400 } -+ }, -+/* lea.4 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect, { 0x100e400 } -+ }, -+/* lea.4 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect, { 0xe400 } -+ }, -+/* lea.4 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect, { 0x300e400 } -+ }, -+/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect, { 0x400e400 } -+ }, -+/* lea.4 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect, { 0x400e400 } -+ }, -+/* lea.4 (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect, { 0x200e400 } -+ }, -+/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect, { 0x210e400 } -+ }, -+/* lea.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect_with_offset_4, { 0x100e400 } -+ }, -+/* lea.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_offset_4, { 0xe400 } -+ }, -+/* lea.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_offset_4, { 0x300e400 } -+ }, -+/* lea.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_offset_4, { 0x400e400 } -+ }, -+/* lea.4 (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_offset_4, { 0x400e400 } -+ }, -+/* lea.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_4, { 0x200e400 } -+ }, -+/* lea.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_4, { 0x210e400 } -+ }, -+/* lea.4 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect_with_index_4, { 0x100e300 } -+ }, -+/* lea.4 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_index_4, { 0xe300 } -+ }, -+/* lea.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_index_4, { 0x300e300 } -+ }, -+/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_index_4, { 0x400e300 } -+ }, -+/* lea.4 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_index_4, { 0x400e300 } -+ }, -+/* lea.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_4, { 0x200e300 } -+ }, -+/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_4, { 0x210e300 } -+ }, -+/* lea.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect_with_post_increment_4, { 0x100e200 } -+ }, -+/* lea.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_post_increment_4, { 0xe200 } -+ }, -+/* lea.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_4, { 0x300e200 } -+ }, -+/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_4, { 0x400e200 } -+ }, -+/* lea.4 (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_post_increment_4, { 0x400e200 } -+ }, -+/* lea.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_4, { 0x200e200 } -+ }, -+/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_4, { 0x210e200 } -+ }, -+/* lea.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect_with_pre_increment_4, { 0x100e210 } -+ }, -+/* lea.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_pre_increment_4, { 0xe210 } -+ }, -+/* lea.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_4, { 0x300e210 } -+ }, -+/* lea.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_4, { 0x400e210 } -+ }, -+/* lea.4 (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_pre_increment_4, { 0x400e210 } -+ }, -+/* lea.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_4, { 0x200e210 } -+ }, -+/* lea.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_4, { 0x210e210 } -+ }, -+/* lea.4 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_immediate, { 0x100e000 } -+ }, -+/* lea.4 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_immediate, { 0xe000 } -+ }, -+/* lea.4 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate, { 0x300e000 } -+ }, -+/* lea.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate, { 0x400e000 } -+ }, -+/* lea.4 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_immediate, { 0x400e000 } -+ }, -+/* lea.4 (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate, { 0x200e000 } -+ }, -+/* lea.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate, { 0x210e000 } -+ }, -+/* lea.2 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect, { 0x100ec00 } -+ }, -+/* lea.2 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect, { 0xec00 } -+ }, -+/* lea.2 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect, { 0x300ec00 } -+ }, -+/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect, { 0x400ec00 } -+ }, -+/* lea.2 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect, { 0x400ec00 } -+ }, -+/* lea.2 (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect, { 0x200ec00 } -+ }, -+/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect, { 0x210ec00 } -+ }, -+/* lea.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_direct_s1_ea_indirect_with_offset_2, { 0x100ec00 } -+ }, -+/* lea.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_offset_2, { 0xec00 } -+ }, -+/* lea.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_offset_2, { 0x300ec00 } -+ }, -+/* lea.2 ${d-imm7-4}(${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_offset_2, { 0x400ec00 } -+ }, -+/* lea.2 (${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_offset_2, { 0x400ec00 } -+ }, -+/* lea.2 (${d-An})${d-i4-4}++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_2, { 0x200ec00 } -+ }, -+/* lea.2 ${d-i4-4}(${d-An})++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_2, { 0x210ec00 } -+ }, -+/* lea.2 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_direct_s1_ea_indirect_with_index_2, { 0x100eb00 } -+ }, -+/* lea.2 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_index_2, { 0xeb00 } -+ }, -+/* lea.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_index_2, { 0x300eb00 } -+ }, -+/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_index_2, { 0x400eb00 } -+ }, -+/* lea.2 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_index_2, { 0x400eb00 } -+ }, -+/* lea.2 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_2, { 0x200eb00 } -+ }, -+/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_2, { 0x210eb00 } -+ }, -+/* lea.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_direct_s1_ea_indirect_with_post_increment_2, { 0x100ea00 } -+ }, -+/* lea.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_post_increment_2, { 0xea00 } -+ }, -+/* lea.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_2, { 0x300ea00 } -+ }, -+/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_2, { 0x400ea00 } -+ }, -+/* lea.2 (${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_post_increment_2, { 0x400ea00 } -+ }, -+/* lea.2 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_2, { 0x200ea00 } -+ }, -+/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_2, { 0x210ea00 } -+ }, -+/* lea.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_direct_s1_ea_indirect_with_pre_increment_2, { 0x100ea10 } -+ }, -+/* lea.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_pre_increment_2, { 0xea10 } -+ }, -+/* lea.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_2, { 0x300ea10 } -+ }, -+/* lea.2 ${d-imm7-4}(${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_2, { 0x400ea10 } -+ }, -+/* lea.2 (${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_pre_increment_2, { 0x400ea10 } -+ }, -+/* lea.2 (${d-An})${d-i4-4}++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_2, { 0x200ea10 } -+ }, -+/* lea.2 ${d-i4-4}(${d-An})++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_2, { 0x210ea10 } -+ }, -+/* lea.2 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_immediate, { 0x100e800 } -+ }, -+/* lea.2 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_immediate, { 0xe800 } -+ }, -+/* lea.2 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate, { 0x300e800 } -+ }, -+/* lea.2 ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate, { 0x400e800 } -+ }, -+/* lea.2 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_immediate, { 0x400e800 } -+ }, -+/* lea.2 (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate, { 0x200e800 } -+ }, -+/* lea.2 ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate, { 0x210e800 } -+ }, -+/* lea.1 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_indirect, { 0x100fc00 } -+ }, -+/* lea.1 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_indirect, { 0xfc00 } -+ }, -+/* lea.1 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect, { 0x300fc00 } -+ }, -+/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect, { 0x400fc00 } -+ }, -+/* lea.1 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_indirect, { 0x400fc00 } -+ }, -+/* lea.1 (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect, { 0x200fc00 } -+ }, -+/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect, { 0x210fc00 } -+ }, -+/* lea.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_direct_s1_ea_indirect_with_offset_1, { 0x100fc00 } -+ }, -+/* lea.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_offset_1, { 0xfc00 } -+ }, -+/* lea.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_offset_1, { 0x300fc00 } -+ }, -+/* lea.1 ${d-imm7-4}(${d-An}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_offset_1, { 0x400fc00 } -+ }, -+/* lea.1 (${d-An}),${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_offset_1, { 0x400fc00 } -+ }, -+/* lea.1 (${d-An})${d-i4-4}++,${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_1, { 0x200fc00 } -+ }, -+/* lea.1 ${d-i4-4}(${d-An})++,${s1-imm7-1}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_1, { 0x210fc00 } -+ }, -+/* lea.1 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_direct_s1_ea_indirect_with_index_1, { 0x100fb00 } -+ }, -+/* lea.1 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_index_1, { 0xfb00 } -+ }, -+/* lea.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_index_1, { 0x300fb00 } -+ }, -+/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_index_1, { 0x400fb00 } -+ }, -+/* lea.1 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_index_1, { 0x400fb00 } -+ }, -+/* lea.1 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_1, { 0x200fb00 } -+ }, -+/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_1, { 0x210fb00 } -+ }, -+/* lea.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_direct_s1_ea_indirect_with_post_increment_1, { 0x100fa00 } -+ }, -+/* lea.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_post_increment_1, { 0xfa00 } -+ }, -+/* lea.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_1, { 0x300fa00 } -+ }, -+/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_1, { 0x400fa00 } -+ }, -+/* lea.1 (${d-An}),(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_post_increment_1, { 0x400fa00 } -+ }, -+/* lea.1 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_1, { 0x200fa00 } -+ }, -+/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-1}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_1, { 0x210fa00 } -+ }, -+/* lea.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_direct_s1_ea_indirect_with_pre_increment_1, { 0x100fa10 } -+ }, -+/* lea.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_pre_increment_1, { 0xfa10 } -+ }, -+/* lea.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_1, { 0x300fa10 } -+ }, -+/* lea.1 ${d-imm7-4}(${d-An}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_1, { 0x400fa10 } -+ }, -+/* lea.1 (${d-An}),${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_pre_increment_1, { 0x400fa10 } -+ }, -+/* lea.1 (${d-An})${d-i4-4}++,${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_1, { 0x200fa10 } -+ }, -+/* lea.1 ${d-i4-4}(${d-An})++,${s1-i4-1}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_1, { 0x210fa10 } -+ }, -+/* lea.1 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_direct_s1_ea_immediate, { 0x100f800 } -+ }, -+/* lea.1 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_immediate_4_s1_ea_immediate, { 0xf800 } -+ }, -+/* lea.1 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate, { 0x300f800 } -+ }, -+/* lea.1 ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate, { 0x400f800 } -+ }, -+/* lea.1 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_4_s1_ea_immediate, { 0x400f800 } -+ }, -+/* lea.1 (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate, { 0x200f800 } -+ }, -+/* lea.1 ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate, { 0x210f800 } -+ }, -+/* cmpi ${s1-direct-addr},#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_direct, { 0xc0000100 } -+ }, -+/* cmpi #${s1-imm8},#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_immediate, { 0xc0000000 } -+ }, -+/* cmpi (${s1-An},${s1-r}),#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_indirect_with_index_2, { 0xc0000300 } -+ }, -+/* cmpi ${s1-imm7-2}(${s1-An}),#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_indirect_with_offset_2, { 0xc0000400 } -+ }, -+/* cmpi (${s1-An}),#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_indirect_2, { 0xc0000400 } -+ }, -+/* cmpi (${s1-An})${s1-i4-2}++,#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_indirect_with_post_increment_2, { 0xc0000200 } -+ }, -+/* cmpi ${s1-i4-2}(${s1-An})++,#${imm16-1} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (IMM16_1), 0 } }, -+ & ifmt_cmpi_s1_indirect_with_pre_increment_2, { 0xc0000210 } -+ }, -+/* pxadds.u ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0xb1008100 } -+ }, -+/* pxadds.u #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0xb0008100 } -+ }, -+/* pxadds.u (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0xb3008100 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0xb4008100 } -+ }, -+/* pxadds.u (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0xb4008100 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0xb2008100 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0xb2108100 } -+ }, -+/* pxadds.u ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0xb1008000 } -+ }, -+/* pxadds.u #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0xb0008000 } -+ }, -+/* pxadds.u (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0xb3008000 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0xb4008000 } -+ }, -+/* pxadds.u (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0xb4008000 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0xb2008000 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0xb2108000 } -+ }, -+/* pxadds.u ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xb1008300 } -+ }, -+/* pxadds.u #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_index_4, { 0xb0008300 } -+ }, -+/* pxadds.u (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_index_4, { 0xb3008300 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0xb4008300 } -+ }, -+/* pxadds.u (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_index_4, { 0xb4008300 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0xb2008300 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0xb2108300 } -+ }, -+/* pxadds.u ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xb1008400 } -+ }, -+/* pxadds.u #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_offset_4, { 0xb0008400 } -+ }, -+/* pxadds.u (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0xb3008400 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0xb4008400 } -+ }, -+/* pxadds.u (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_offset_4, { 0xb4008400 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0xb2008400 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0xb2108400 } -+ }, -+/* pxadds.u ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xb1008400 } -+ }, -+/* pxadds.u #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_4, { 0xb0008400 } -+ }, -+/* pxadds.u (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_4, { 0xb3008400 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_4, { 0xb4008400 } -+ }, -+/* pxadds.u (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_4, { 0xb4008400 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_4, { 0xb2008400 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_4, { 0xb2108400 } -+ }, -+/* pxadds.u ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xb1008200 } -+ }, -+/* pxadds.u #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_post_increment_4, { 0xb0008200 } -+ }, -+/* pxadds.u (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0xb3008200 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0xb4008200 } -+ }, -+/* pxadds.u (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_post_increment_4, { 0xb4008200 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0xb2008200 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0xb2108200 } -+ }, -+/* pxadds.u ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xb1008210 } -+ }, -+/* pxadds.u #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xb0008210 } -+ }, -+/* pxadds.u (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0xb3008210 } -+ }, -+/* pxadds.u ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0xb4008210 } -+ }, -+/* pxadds.u (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_pre_increment_4, { 0xb4008210 } -+ }, -+/* pxadds.u (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0xb2008210 } -+ }, -+/* pxadds.u ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0xb2108210 } -+ }, -+/* pxadds ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0xb1000100 } -+ }, -+/* pxadds #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0xb0000100 } -+ }, -+/* pxadds (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0xb3000100 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0xb4000100 } -+ }, -+/* pxadds (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0xb4000100 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0xb2000100 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0xb2100100 } -+ }, -+/* pxadds ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0xb1000000 } -+ }, -+/* pxadds #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0xb0000000 } -+ }, -+/* pxadds (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0xb3000000 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0xb4000000 } -+ }, -+/* pxadds (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0xb4000000 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0xb2000000 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0xb2100000 } -+ }, -+/* pxadds ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xb1000300 } -+ }, -+/* pxadds #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_index_4, { 0xb0000300 } -+ }, -+/* pxadds (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_index_4, { 0xb3000300 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0xb4000300 } -+ }, -+/* pxadds (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_index_4, { 0xb4000300 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0xb2000300 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0xb2100300 } -+ }, -+/* pxadds ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xb1000400 } -+ }, -+/* pxadds #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_offset_4, { 0xb0000400 } -+ }, -+/* pxadds (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0xb3000400 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0xb4000400 } -+ }, -+/* pxadds (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_offset_4, { 0xb4000400 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0xb2000400 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0xb2100400 } -+ }, -+/* pxadds ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xb1000400 } -+ }, -+/* pxadds #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_4, { 0xb0000400 } -+ }, -+/* pxadds (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_4, { 0xb3000400 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_4, { 0xb4000400 } -+ }, -+/* pxadds (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_4, { 0xb4000400 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_4, { 0xb2000400 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_4, { 0xb2100400 } -+ }, -+/* pxadds ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xb1000200 } -+ }, -+/* pxadds #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_post_increment_4, { 0xb0000200 } -+ }, -+/* pxadds (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0xb3000200 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0xb4000200 } -+ }, -+/* pxadds (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_post_increment_4, { 0xb4000200 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0xb2000200 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0xb2100200 } -+ }, -+/* pxadds ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xb1000210 } -+ }, -+/* pxadds #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xb0000210 } -+ }, -+/* pxadds (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0xb3000210 } -+ }, -+/* pxadds ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0xb4000210 } -+ }, -+/* pxadds (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_pre_increment_4, { 0xb4000210 } -+ }, -+/* pxadds (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0xb2000210 } -+ }, -+/* pxadds ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0xb2100210 } -+ }, -+/* pxhi.s ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_direct, { 0x14408100 } -+ }, -+/* pxhi.s ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_immediate, { 0x14408000 } -+ }, -+/* pxhi.s ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_index_4, { 0x14408300 } -+ }, -+/* pxhi.s ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_offset_4, { 0x14408400 } -+ }, -+/* pxhi.s ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_4, { 0x14408400 } -+ }, -+/* pxhi.s ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_post_increment_4, { 0x14408200 } -+ }, -+/* pxhi.s ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_pre_increment_4, { 0x14408210 } -+ }, -+/* pxhi ${Dn},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_direct, { 0x14000100 } -+ }, -+/* pxhi ${Dn},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_immediate, { 0x14000000 } -+ }, -+/* pxhi ${Dn},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_index_4, { 0x14000300 } -+ }, -+/* pxhi ${Dn},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_offset_4, { 0x14000400 } -+ }, -+/* pxhi ${Dn},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_4, { 0x14000400 } -+ }, -+/* pxhi ${Dn},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_post_increment_4, { 0x14000200 } -+ }, -+/* pxhi ${Dn},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxhi_s_s1_indirect_with_pre_increment_4, { 0x14000210 } -+ }, -+/* pxvi.s ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0xa9008100 } -+ }, -+/* pxvi.s #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa8008100 } -+ }, -+/* pxvi.s (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xab008100 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xac008100 } -+ }, -+/* pxvi.s (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xac008100 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xaa008100 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xaa108100 } -+ }, -+/* pxvi.s ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa9008000 } -+ }, -+/* pxvi.s #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa8008000 } -+ }, -+/* pxvi.s (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xab008000 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xac008000 } -+ }, -+/* pxvi.s (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xac008000 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xaa008000 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xaa108000 } -+ }, -+/* pxvi.s ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa9008300 } -+ }, -+/* pxvi.s #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa8008300 } -+ }, -+/* pxvi.s (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xab008300 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xac008300 } -+ }, -+/* pxvi.s (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xac008300 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xaa008300 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xaa108300 } -+ }, -+/* pxvi.s ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa9008400 } -+ }, -+/* pxvi.s #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa8008400 } -+ }, -+/* pxvi.s (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xab008400 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xac008400 } -+ }, -+/* pxvi.s (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xac008400 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xaa008400 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xaa108400 } -+ }, -+/* pxvi.s ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa9008400 } -+ }, -+/* pxvi.s #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa8008400 } -+ }, -+/* pxvi.s (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xab008400 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xac008400 } -+ }, -+/* pxvi.s (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xac008400 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xaa008400 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xaa108400 } -+ }, -+/* pxvi.s ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa9008200 } -+ }, -+/* pxvi.s #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa8008200 } -+ }, -+/* pxvi.s (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xab008200 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xac008200 } -+ }, -+/* pxvi.s (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xac008200 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xaa008200 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xaa108200 } -+ }, -+/* pxvi.s ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa9008210 } -+ }, -+/* pxvi.s #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa8008210 } -+ }, -+/* pxvi.s (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xab008210 } -+ }, -+/* pxvi.s ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xac008210 } -+ }, -+/* pxvi.s (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xac008210 } -+ }, -+/* pxvi.s (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xaa008210 } -+ }, -+/* pxvi.s ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xaa108210 } -+ }, -+/* pxvi ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0xa9000100 } -+ }, -+/* pxvi #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa8000100 } -+ }, -+/* pxvi (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xab000100 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xac000100 } -+ }, -+/* pxvi (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xac000100 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xaa000100 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xaa100100 } -+ }, -+/* pxvi ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa9000000 } -+ }, -+/* pxvi #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa8000000 } -+ }, -+/* pxvi (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xab000000 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xac000000 } -+ }, -+/* pxvi (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xac000000 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xaa000000 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xaa100000 } -+ }, -+/* pxvi ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa9000300 } -+ }, -+/* pxvi #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa8000300 } -+ }, -+/* pxvi (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xab000300 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xac000300 } -+ }, -+/* pxvi (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xac000300 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xaa000300 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xaa100300 } -+ }, -+/* pxvi ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa9000400 } -+ }, -+/* pxvi #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa8000400 } -+ }, -+/* pxvi (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xab000400 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xac000400 } -+ }, -+/* pxvi (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xac000400 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xaa000400 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xaa100400 } -+ }, -+/* pxvi ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa9000400 } -+ }, -+/* pxvi #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa8000400 } -+ }, -+/* pxvi (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xab000400 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xac000400 } -+ }, -+/* pxvi (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xac000400 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xaa000400 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xaa100400 } -+ }, -+/* pxvi ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa9000200 } -+ }, -+/* pxvi #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa8000200 } -+ }, -+/* pxvi (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xab000200 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xac000200 } -+ }, -+/* pxvi (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xac000200 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xaa000200 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xaa100200 } -+ }, -+/* pxvi ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa9000210 } -+ }, -+/* pxvi #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa8000210 } -+ }, -+/* pxvi (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xab000210 } -+ }, -+/* pxvi ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xac000210 } -+ }, -+/* pxvi (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xac000210 } -+ }, -+/* pxvi (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xaa000210 } -+ }, -+/* pxvi ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xaa100210 } -+ }, -+/* pxblend.t ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0xa1008100 } -+ }, -+/* pxblend.t #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa0008100 } -+ }, -+/* pxblend.t (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xa3008100 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xa4008100 } -+ }, -+/* pxblend.t (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xa4008100 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xa2008100 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xa2108100 } -+ }, -+/* pxblend.t ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa1008000 } -+ }, -+/* pxblend.t #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa0008000 } -+ }, -+/* pxblend.t (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xa3008000 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xa4008000 } -+ }, -+/* pxblend.t (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xa4008000 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xa2008000 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xa2108000 } -+ }, -+/* pxblend.t ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa1008300 } -+ }, -+/* pxblend.t #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa0008300 } -+ }, -+/* pxblend.t (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xa3008300 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xa4008300 } -+ }, -+/* pxblend.t (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xa4008300 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xa2008300 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xa2108300 } -+ }, -+/* pxblend.t ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa1008400 } -+ }, -+/* pxblend.t #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa0008400 } -+ }, -+/* pxblend.t (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xa3008400 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xa4008400 } -+ }, -+/* pxblend.t (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xa4008400 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xa2008400 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xa2108400 } -+ }, -+/* pxblend.t ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa1008400 } -+ }, -+/* pxblend.t #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa0008400 } -+ }, -+/* pxblend.t (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xa3008400 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xa4008400 } -+ }, -+/* pxblend.t (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xa4008400 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xa2008400 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xa2108400 } -+ }, -+/* pxblend.t ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa1008200 } -+ }, -+/* pxblend.t #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa0008200 } -+ }, -+/* pxblend.t (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xa3008200 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xa4008200 } -+ }, -+/* pxblend.t (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xa4008200 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xa2008200 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xa2108200 } -+ }, -+/* pxblend.t ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa1008210 } -+ }, -+/* pxblend.t #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa0008210 } -+ }, -+/* pxblend.t (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xa3008210 } -+ }, -+/* pxblend.t ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xa4008210 } -+ }, -+/* pxblend.t (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xa4008210 } -+ }, -+/* pxblend.t (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xa2008210 } -+ }, -+/* pxblend.t ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xa2108210 } -+ }, -+/* pxblend ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0xa1000100 } -+ }, -+/* pxblend #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa0000100 } -+ }, -+/* pxblend (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xa3000100 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xa4000100 } -+ }, -+/* pxblend (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xa4000100 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xa2000100 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xa2100100 } -+ }, -+/* pxblend ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa1000000 } -+ }, -+/* pxblend #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa0000000 } -+ }, -+/* pxblend (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xa3000000 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xa4000000 } -+ }, -+/* pxblend (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xa4000000 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xa2000000 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xa2100000 } -+ }, -+/* pxblend ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa1000300 } -+ }, -+/* pxblend #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa0000300 } -+ }, -+/* pxblend (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xa3000300 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xa4000300 } -+ }, -+/* pxblend (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xa4000300 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xa2000300 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xa2100300 } -+ }, -+/* pxblend ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa1000400 } -+ }, -+/* pxblend #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa0000400 } -+ }, -+/* pxblend (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xa3000400 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xa4000400 } -+ }, -+/* pxblend (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xa4000400 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xa2000400 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xa2100400 } -+ }, -+/* pxblend ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa1000400 } -+ }, -+/* pxblend #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa0000400 } -+ }, -+/* pxblend (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xa3000400 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xa4000400 } -+ }, -+/* pxblend (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xa4000400 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xa2000400 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xa2100400 } -+ }, -+/* pxblend ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa1000200 } -+ }, -+/* pxblend #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa0000200 } -+ }, -+/* pxblend (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xa3000200 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xa4000200 } -+ }, -+/* pxblend (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xa4000200 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xa2000200 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xa2100200 } -+ }, -+/* pxblend ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa1000210 } -+ }, -+/* pxblend #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa0000210 } -+ }, -+/* pxblend (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xa3000210 } -+ }, -+/* pxblend ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xa4000210 } -+ }, -+/* pxblend (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xa4000210 } -+ }, -+/* pxblend (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xa2000210 } -+ }, -+/* pxblend ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xa2100210 } -+ }, -+/* pxcnv.t ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x100d900 } -+ }, -+/* pxcnv.t #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_direct, { 0xd900 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300d900 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400d900 } -+ }, -+/* pxcnv.t (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_direct, { 0x400d900 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200d900 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210d900 } -+ }, -+/* pxcnv.t ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x100d800 } -+ }, -+/* pxcnv.t #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_immediate, { 0xd800 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300d800 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400d800 } -+ }, -+/* pxcnv.t (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400d800 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200d800 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210d800 } -+ }, -+/* pxcnv.t ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x100db00 } -+ }, -+/* pxcnv.t #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_index_4, { 0xdb00 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_index_4, { 0x300db00 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0x400db00 } -+ }, -+/* pxcnv.t (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_index_4, { 0x400db00 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0x200db00 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0x210db00 } -+ }, -+/* pxcnv.t ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x100dc00 } -+ }, -+/* pxcnv.t #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_offset_4, { 0xdc00 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0x300dc00 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0x400dc00 } -+ }, -+/* pxcnv.t (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_offset_4, { 0x400dc00 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0x200dc00 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0x210dc00 } -+ }, -+/* pxcnv.t ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_4, { 0x100dc00 } -+ }, -+/* pxcnv.t #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_4, { 0xdc00 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_4, { 0x300dc00 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_4, { 0x400dc00 } -+ }, -+/* pxcnv.t (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_4, { 0x400dc00 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_4, { 0x200dc00 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_4, { 0x210dc00 } -+ }, -+/* pxcnv.t ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x100da00 } -+ }, -+/* pxcnv.t #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_post_increment_4, { 0xda00 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0x300da00 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0x400da00 } -+ }, -+/* pxcnv.t (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_post_increment_4, { 0x400da00 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0x200da00 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0x210da00 } -+ }, -+/* pxcnv.t ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x100da10 } -+ }, -+/* pxcnv.t #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xda10 } -+ }, -+/* pxcnv.t (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0x300da10 } -+ }, -+/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0x400da10 } -+ }, -+/* pxcnv.t (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_pre_increment_4, { 0x400da10 } -+ }, -+/* pxcnv.t (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0x200da10 } -+ }, -+/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0x210da10 } -+ }, -+/* pxcnv ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x100d100 } -+ }, -+/* pxcnv #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_direct, { 0xd100 } -+ }, -+/* pxcnv (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300d100 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400d100 } -+ }, -+/* pxcnv (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_direct, { 0x400d100 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200d100 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210d100 } -+ }, -+/* pxcnv ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x100d000 } -+ }, -+/* pxcnv #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_immediate, { 0xd000 } -+ }, -+/* pxcnv (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300d000 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400d000 } -+ }, -+/* pxcnv (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400d000 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200d000 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210d000 } -+ }, -+/* pxcnv ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x100d300 } -+ }, -+/* pxcnv #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_index_4, { 0xd300 } -+ }, -+/* pxcnv (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_index_4, { 0x300d300 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0x400d300 } -+ }, -+/* pxcnv (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_index_4, { 0x400d300 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0x200d300 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0x210d300 } -+ }, -+/* pxcnv ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x100d400 } -+ }, -+/* pxcnv #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_offset_4, { 0xd400 } -+ }, -+/* pxcnv (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0x300d400 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0x400d400 } -+ }, -+/* pxcnv (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_offset_4, { 0x400d400 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0x200d400 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0x210d400 } -+ }, -+/* pxcnv ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_4, { 0x100d400 } -+ }, -+/* pxcnv #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_4, { 0xd400 } -+ }, -+/* pxcnv (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_4, { 0x300d400 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_4, { 0x400d400 } -+ }, -+/* pxcnv (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_4, { 0x400d400 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_4, { 0x200d400 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_4, { 0x210d400 } -+ }, -+/* pxcnv ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x100d200 } -+ }, -+/* pxcnv #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_post_increment_4, { 0xd200 } -+ }, -+/* pxcnv (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0x300d200 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0x400d200 } -+ }, -+/* pxcnv (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_post_increment_4, { 0x400d200 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0x200d200 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0x210d200 } -+ }, -+/* pxcnv ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x100d210 } -+ }, -+/* pxcnv #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xd210 } -+ }, -+/* pxcnv (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0x300d210 } -+ }, -+/* pxcnv ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0x400d210 } -+ }, -+/* pxcnv (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_pre_increment_4, { 0x400d210 } -+ }, -+/* pxcnv (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0x200d210 } -+ }, -+/* pxcnv ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0x210d210 } -+ }, -+/* subc ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x99000100 } -+ }, -+/* subc #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x98000100 } -+ }, -+/* subc (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x9b000100 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x9c000100 } -+ }, -+/* subc (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x9c000100 } -+ }, -+/* subc (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x9a000100 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x9a100100 } -+ }, -+/* subc ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x99000000 } -+ }, -+/* subc #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x98000000 } -+ }, -+/* subc (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x9b000000 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x9c000000 } -+ }, -+/* subc (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x9c000000 } -+ }, -+/* subc (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x9a000000 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x9a100000 } -+ }, -+/* subc ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x99000300 } -+ }, -+/* subc #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x98000300 } -+ }, -+/* subc (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x9b000300 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x9c000300 } -+ }, -+/* subc (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x9c000300 } -+ }, -+/* subc (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x9a000300 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x9a100300 } -+ }, -+/* subc ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x99000400 } -+ }, -+/* subc #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x98000400 } -+ }, -+/* subc (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x9b000400 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x9c000400 } -+ }, -+/* subc (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x9c000400 } -+ }, -+/* subc (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x9a000400 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x9a100400 } -+ }, -+/* subc ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x99000400 } -+ }, -+/* subc #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x98000400 } -+ }, -+/* subc (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x9b000400 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x9c000400 } -+ }, -+/* subc (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x9c000400 } -+ }, -+/* subc (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x9a000400 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x9a100400 } -+ }, -+/* subc ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x99000200 } -+ }, -+/* subc #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x98000200 } -+ }, -+/* subc (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x9b000200 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x9c000200 } -+ }, -+/* subc (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x9c000200 } -+ }, -+/* subc (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x9a000200 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x9a100200 } -+ }, -+/* subc ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x99000210 } -+ }, -+/* subc #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x98000210 } -+ }, -+/* subc (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x9b000210 } -+ }, -+/* subc ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x9c000210 } -+ }, -+/* subc (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x9c000210 } -+ }, -+/* subc (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x9a000210 } -+ }, -+/* subc ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x9a100210 } -+ }, -+/* addc ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x81000100 } -+ }, -+/* addc #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x80000100 } -+ }, -+/* addc (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x83000100 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x84000100 } -+ }, -+/* addc (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x84000100 } -+ }, -+/* addc (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x82000100 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x82100100 } -+ }, -+/* addc ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x81000000 } -+ }, -+/* addc #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x80000000 } -+ }, -+/* addc (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x83000000 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x84000000 } -+ }, -+/* addc (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x84000000 } -+ }, -+/* addc (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x82000000 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x82100000 } -+ }, -+/* addc ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x81000300 } -+ }, -+/* addc #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x80000300 } -+ }, -+/* addc (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x83000300 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x84000300 } -+ }, -+/* addc (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x84000300 } -+ }, -+/* addc (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x82000300 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x82100300 } -+ }, -+/* addc ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x81000400 } -+ }, -+/* addc #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x80000400 } -+ }, -+/* addc (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x83000400 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x84000400 } -+ }, -+/* addc (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x84000400 } -+ }, -+/* addc (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x82000400 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x82100400 } -+ }, -+/* addc ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x81000400 } -+ }, -+/* addc #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x80000400 } -+ }, -+/* addc (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x83000400 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x84000400 } -+ }, -+/* addc (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x84000400 } -+ }, -+/* addc (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x82000400 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x82100400 } -+ }, -+/* addc ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x81000200 } -+ }, -+/* addc #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x80000200 } -+ }, -+/* addc (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x83000200 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x84000200 } -+ }, -+/* addc (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x84000200 } -+ }, -+/* addc (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x82000200 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x82100200 } -+ }, -+/* addc ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x81000210 } -+ }, -+/* addc #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x80000210 } -+ }, -+/* addc (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x83000210 } -+ }, -+/* addc ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x84000210 } -+ }, -+/* addc (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x84000210 } -+ }, -+/* addc (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x82000210 } -+ }, -+/* addc ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x82100210 } -+ }, -+/* sub.1 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x89008100 } -+ }, -+/* sub.1 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_direct, { 0x88008100 } -+ }, -+/* sub.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x8b008100 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x8c008100 } -+ }, -+/* sub.1 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_direct, { 0x8c008100 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x8a008100 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x8a108100 } -+ }, -+/* sub.1 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x89008000 } -+ }, -+/* sub.1 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x88008000 } -+ }, -+/* sub.1 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x8b008000 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x8c008000 } -+ }, -+/* sub.1 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x8c008000 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x8a008000 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x8a108000 } -+ }, -+/* sub.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x89008300 } -+ }, -+/* sub.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x88008300 } -+ }, -+/* sub.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x8b008300 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x8c008300 } -+ }, -+/* sub.1 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x8c008300 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x8a008300 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x8a108300 } -+ }, -+/* sub.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x89008400 } -+ }, -+/* sub.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x88008400 } -+ }, -+/* sub.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x8b008400 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x8c008400 } -+ }, -+/* sub.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x8c008400 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x8a008400 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x8a108400 } -+ }, -+/* sub.1 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_1, { 0x89008400 } -+ }, -+/* sub.1 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x88008400 } -+ }, -+/* sub.1 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x8b008400 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x8c008400 } -+ }, -+/* sub.1 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x8c008400 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x8a008400 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x8a108400 } -+ }, -+/* sub.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x89008200 } -+ }, -+/* sub.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x88008200 } -+ }, -+/* sub.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x8b008200 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x8c008200 } -+ }, -+/* sub.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x8c008200 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x8a008200 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x8a108200 } -+ }, -+/* sub.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x89008210 } -+ }, -+/* sub.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x88008210 } -+ }, -+/* sub.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x8b008210 } -+ }, -+/* sub.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x8c008210 } -+ }, -+/* sub.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x8c008210 } -+ }, -+/* sub.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x8a008210 } -+ }, -+/* sub.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x8a108210 } -+ }, -+/* sub.4 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x91000100 } -+ }, -+/* sub.4 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x90000100 } -+ }, -+/* sub.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x93000100 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x94000100 } -+ }, -+/* sub.4 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x94000100 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x92000100 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x92100100 } -+ }, -+/* sub.4 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x91000000 } -+ }, -+/* sub.4 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x90000000 } -+ }, -+/* sub.4 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x93000000 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x94000000 } -+ }, -+/* sub.4 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x94000000 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x92000000 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x92100000 } -+ }, -+/* sub.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x91000300 } -+ }, -+/* sub.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x90000300 } -+ }, -+/* sub.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x93000300 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x94000300 } -+ }, -+/* sub.4 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x94000300 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x92000300 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x92100300 } -+ }, -+/* sub.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x91000400 } -+ }, -+/* sub.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x90000400 } -+ }, -+/* sub.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x93000400 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x94000400 } -+ }, -+/* sub.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x94000400 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x92000400 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x92100400 } -+ }, -+/* sub.4 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x91000400 } -+ }, -+/* sub.4 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x90000400 } -+ }, -+/* sub.4 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x93000400 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x94000400 } -+ }, -+/* sub.4 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x94000400 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x92000400 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x92100400 } -+ }, -+/* sub.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x91000200 } -+ }, -+/* sub.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x90000200 } -+ }, -+/* sub.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x93000200 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x94000200 } -+ }, -+/* sub.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x94000200 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x92000200 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x92100200 } -+ }, -+/* sub.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x91000210 } -+ }, -+/* sub.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x90000210 } -+ }, -+/* sub.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x93000210 } -+ }, -+/* sub.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x94000210 } -+ }, -+/* sub.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x94000210 } -+ }, -+/* sub.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x92000210 } -+ }, -+/* sub.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x92100210 } -+ }, -+/* sub.2 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x89000100 } -+ }, -+/* sub.2 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x88000100 } -+ }, -+/* sub.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x8b000100 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x8c000100 } -+ }, -+/* sub.2 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x8c000100 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x8a000100 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x8a100100 } -+ }, -+/* sub.2 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x89000000 } -+ }, -+/* sub.2 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x88000000 } -+ }, -+/* sub.2 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x8b000000 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x8c000000 } -+ }, -+/* sub.2 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x8c000000 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x8a000000 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x8a100000 } -+ }, -+/* sub.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x89000300 } -+ }, -+/* sub.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x88000300 } -+ }, -+/* sub.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x8b000300 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x8c000300 } -+ }, -+/* sub.2 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x8c000300 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x8a000300 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x8a100300 } -+ }, -+/* sub.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x89000400 } -+ }, -+/* sub.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x88000400 } -+ }, -+/* sub.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x8b000400 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x8c000400 } -+ }, -+/* sub.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x8c000400 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x8a000400 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x8a100400 } -+ }, -+/* sub.2 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_2, { 0x89000400 } -+ }, -+/* sub.2 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x88000400 } -+ }, -+/* sub.2 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x8b000400 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x8c000400 } -+ }, -+/* sub.2 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x8c000400 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x8a000400 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x8a100400 } -+ }, -+/* sub.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x89000200 } -+ }, -+/* sub.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x88000200 } -+ }, -+/* sub.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x8b000200 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x8c000200 } -+ }, -+/* sub.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x8c000200 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x8a000200 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x8a100200 } -+ }, -+/* sub.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x89000210 } -+ }, -+/* sub.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x88000210 } -+ }, -+/* sub.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x8b000210 } -+ }, -+/* sub.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x8c000210 } -+ }, -+/* sub.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x8c000210 } -+ }, -+/* sub.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x8a000210 } -+ }, -+/* sub.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x8a100210 } -+ }, -+/* add.1 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x71008100 } -+ }, -+/* add.1 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_direct, { 0x70008100 } -+ }, -+/* add.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x73008100 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x74008100 } -+ }, -+/* add.1 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_direct, { 0x74008100 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x72008100 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x72108100 } -+ }, -+/* add.1 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x71008000 } -+ }, -+/* add.1 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x70008000 } -+ }, -+/* add.1 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x73008000 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x74008000 } -+ }, -+/* add.1 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x74008000 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x72008000 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x72108000 } -+ }, -+/* add.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x71008300 } -+ }, -+/* add.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x70008300 } -+ }, -+/* add.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x73008300 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x74008300 } -+ }, -+/* add.1 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x74008300 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x72008300 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x72108300 } -+ }, -+/* add.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x71008400 } -+ }, -+/* add.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x70008400 } -+ }, -+/* add.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x73008400 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x74008400 } -+ }, -+/* add.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x74008400 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x72008400 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x72108400 } -+ }, -+/* add.1 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_1, { 0x71008400 } -+ }, -+/* add.1 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x70008400 } -+ }, -+/* add.1 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x73008400 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x74008400 } -+ }, -+/* add.1 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x74008400 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x72008400 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x72108400 } -+ }, -+/* add.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x71008200 } -+ }, -+/* add.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x70008200 } -+ }, -+/* add.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x73008200 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x74008200 } -+ }, -+/* add.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x74008200 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x72008200 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x72108200 } -+ }, -+/* add.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x71008210 } -+ }, -+/* add.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x70008210 } -+ }, -+/* add.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x73008210 } -+ }, -+/* add.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x74008210 } -+ }, -+/* add.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x74008210 } -+ }, -+/* add.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x72008210 } -+ }, -+/* add.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x72108210 } -+ }, -+/* add.4 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x79000100 } -+ }, -+/* add.4 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x78000100 } -+ }, -+/* add.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x7b000100 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x7c000100 } -+ }, -+/* add.4 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x7c000100 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x7a000100 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x7a100100 } -+ }, -+/* add.4 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x79000000 } -+ }, -+/* add.4 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x78000000 } -+ }, -+/* add.4 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x7b000000 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x7c000000 } -+ }, -+/* add.4 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x7c000000 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x7a000000 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x7a100000 } -+ }, -+/* add.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x79000300 } -+ }, -+/* add.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x78000300 } -+ }, -+/* add.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x7b000300 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x7c000300 } -+ }, -+/* add.4 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x7c000300 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x7a000300 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x7a100300 } -+ }, -+/* add.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x79000400 } -+ }, -+/* add.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x78000400 } -+ }, -+/* add.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x7b000400 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x7c000400 } -+ }, -+/* add.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x7c000400 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x7a000400 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x7a100400 } -+ }, -+/* add.4 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x79000400 } -+ }, -+/* add.4 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x78000400 } -+ }, -+/* add.4 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x7b000400 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x7c000400 } -+ }, -+/* add.4 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x7c000400 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x7a000400 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x7a100400 } -+ }, -+/* add.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x79000200 } -+ }, -+/* add.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x78000200 } -+ }, -+/* add.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x7b000200 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x7c000200 } -+ }, -+/* add.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x7c000200 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x7a000200 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x7a100200 } -+ }, -+/* add.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x79000210 } -+ }, -+/* add.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x78000210 } -+ }, -+/* add.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x7b000210 } -+ }, -+/* add.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x7c000210 } -+ }, -+/* add.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x7c000210 } -+ }, -+/* add.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x7a000210 } -+ }, -+/* add.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x7a100210 } -+ }, -+/* add.2 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x71000100 } -+ }, -+/* add.2 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x70000100 } -+ }, -+/* add.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x73000100 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x74000100 } -+ }, -+/* add.2 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x74000100 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x72000100 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x72100100 } -+ }, -+/* add.2 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x71000000 } -+ }, -+/* add.2 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x70000000 } -+ }, -+/* add.2 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x73000000 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x74000000 } -+ }, -+/* add.2 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x74000000 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x72000000 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x72100000 } -+ }, -+/* add.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x71000300 } -+ }, -+/* add.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x70000300 } -+ }, -+/* add.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x73000300 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x74000300 } -+ }, -+/* add.2 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x74000300 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x72000300 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x72100300 } -+ }, -+/* add.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x71000400 } -+ }, -+/* add.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x70000400 } -+ }, -+/* add.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x73000400 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x74000400 } -+ }, -+/* add.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x74000400 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x72000400 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x72100400 } -+ }, -+/* add.2 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_2, { 0x71000400 } -+ }, -+/* add.2 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x70000400 } -+ }, -+/* add.2 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x73000400 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x74000400 } -+ }, -+/* add.2 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x74000400 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x72000400 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x72100400 } -+ }, -+/* add.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x71000200 } -+ }, -+/* add.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x70000200 } -+ }, -+/* add.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x73000200 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x74000200 } -+ }, -+/* add.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x74000200 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x72000200 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x72100200 } -+ }, -+/* add.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x71000210 } -+ }, -+/* add.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x70000210 } -+ }, -+/* add.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x73000210 } -+ }, -+/* add.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x74000210 } -+ }, -+/* add.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x74000210 } -+ }, -+/* add.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x72000210 } -+ }, -+/* add.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x72100210 } -+ }, -+/* not.4 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x1005100 } -+ }, -+/* not.4 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_direct, { 0x5100 } -+ }, -+/* not.4 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x3005100 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x4005100 } -+ }, -+/* not.4 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_direct, { 0x4005100 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x2005100 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x2105100 } -+ }, -+/* not.4 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x1005000 } -+ }, -+/* not.4 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_immediate_4_s1_immediate, { 0x5000 } -+ }, -+/* not.4 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x3005000 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x4005000 } -+ }, -+/* not.4 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_4_s1_immediate, { 0x4005000 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x2005000 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x2105000 } -+ }, -+/* not.4 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x1005300 } -+ }, -+/* not.4 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0x5300 } -+ }, -+/* not.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x3005300 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4005300 } -+ }, -+/* not.4 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x4005300 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2005300 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2105300 } -+ }, -+/* not.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x1005400 } -+ }, -+/* not.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0x5400 } -+ }, -+/* not.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x3005400 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4005400 } -+ }, -+/* not.4 (${d-An}),${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x4005400 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2005400 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2105400 } -+ }, -+/* not.4 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_4, { 0x1005400 } -+ }, -+/* not.4 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_4, { 0x5400 } -+ }, -+/* not.4 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x3005400 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x4005400 } -+ }, -+/* not.4 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x4005400 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2005400 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2105400 } -+ }, -+/* not.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x1005200 } -+ }, -+/* not.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0x5200 } -+ }, -+/* not.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x3005200 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4005200 } -+ }, -+/* not.4 (${d-An}),(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4005200 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2005200 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2105200 } -+ }, -+/* not.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x1005210 } -+ }, -+/* not.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x5210 } -+ }, -+/* not.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x3005210 } -+ }, -+/* not.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4005210 } -+ }, -+/* not.4 (${d-An}),${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4005210 } -+ }, -+/* not.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2005210 } -+ }, -+/* not.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2105210 } -+ }, -+/* not.2 ${d-direct-addr},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_movea_d_direct_s1_direct, { 0x1005900 } -+ }, -+/* not.2 #${d-imm8},${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_direct, { 0x5900 } -+ }, -+/* not.2 (${d-An},${d-r}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x3005900 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x4005900 } -+ }, -+/* not.2 (${d-An}),${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_direct, { 0x4005900 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x2005900 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x2105900 } -+ }, -+/* not.2 ${d-direct-addr},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_movea_d_direct_s1_immediate, { 0x1005800 } -+ }, -+/* not.2 #${d-imm8},#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_immediate, { 0x5800 } -+ }, -+/* not.2 (${d-An},${d-r}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x3005800 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x4005800 } -+ }, -+/* not.2 (${d-An}),#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_immediate, { 0x4005800 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x2005800 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x2105800 } -+ }, -+/* not.2 ${d-direct-addr},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x1005b00 } -+ }, -+/* not.2 #${d-imm8},(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0x5b00 } -+ }, -+/* not.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x3005b00 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x4005b00 } -+ }, -+/* not.2 (${d-An}),(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x4005b00 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x2005b00 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x2105b00 } -+ }, -+/* not.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x1005c00 } -+ }, -+/* not.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0x5c00 } -+ }, -+/* not.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x3005c00 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x4005c00 } -+ }, -+/* not.2 (${d-An}),${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x4005c00 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x2005c00 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x2105c00 } -+ }, -+/* not.2 ${d-direct-addr},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_2, { 0x1005c00 } -+ }, -+/* not.2 #${d-imm8},(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0x5c00 } -+ }, -+/* not.2 (${d-An},${d-r}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x3005c00 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x4005c00 } -+ }, -+/* not.2 (${d-An}),(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x4005c00 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x2005c00 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,(${s1-An}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x2105c00 } -+ }, -+/* not.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x1005a00 } -+ }, -+/* not.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x5a00 } -+ }, -+/* not.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x3005a00 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x4005a00 } -+ }, -+/* not.2 (${d-An}),(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x4005a00 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x2005a00 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x2105a00 } -+ }, -+/* not.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x1005a10 } -+ }, -+/* not.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x5a10 } -+ }, -+/* not.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x3005a10 } -+ }, -+/* not.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x4005a10 } -+ }, -+/* not.2 (${d-An}),${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x4005a10 } -+ }, -+/* not.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x2005a10 } -+ }, -+/* not.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } }, -+ & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x2105a10 } -+ }, -+/* xor.1 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x61008100 } -+ }, -+/* xor.1 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_direct, { 0x60008100 } -+ }, -+/* xor.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x63008100 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x64008100 } -+ }, -+/* xor.1 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_direct, { 0x64008100 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x62008100 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x62108100 } -+ }, -+/* xor.1 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x61008000 } -+ }, -+/* xor.1 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x60008000 } -+ }, -+/* xor.1 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x63008000 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x64008000 } -+ }, -+/* xor.1 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x64008000 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x62008000 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x62108000 } -+ }, -+/* xor.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x61008300 } -+ }, -+/* xor.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x60008300 } -+ }, -+/* xor.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x63008300 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x64008300 } -+ }, -+/* xor.1 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x64008300 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x62008300 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x62108300 } -+ }, -+/* xor.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x61008400 } -+ }, -+/* xor.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x60008400 } -+ }, -+/* xor.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x63008400 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x64008400 } -+ }, -+/* xor.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x64008400 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x62008400 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x62108400 } -+ }, -+/* xor.1 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_1, { 0x61008400 } -+ }, -+/* xor.1 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x60008400 } -+ }, -+/* xor.1 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x63008400 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x64008400 } -+ }, -+/* xor.1 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x64008400 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x62008400 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x62108400 } -+ }, -+/* xor.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x61008200 } -+ }, -+/* xor.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x60008200 } -+ }, -+/* xor.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x63008200 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x64008200 } -+ }, -+/* xor.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x64008200 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x62008200 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x62108200 } -+ }, -+/* xor.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x61008210 } -+ }, -+/* xor.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x60008210 } -+ }, -+/* xor.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x63008210 } -+ }, -+/* xor.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x64008210 } -+ }, -+/* xor.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x64008210 } -+ }, -+/* xor.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x62008210 } -+ }, -+/* xor.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x62108210 } -+ }, -+/* or.1 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x51008100 } -+ }, -+/* or.1 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_direct, { 0x50008100 } -+ }, -+/* or.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x53008100 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x54008100 } -+ }, -+/* or.1 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_direct, { 0x54008100 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x52008100 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x52108100 } -+ }, -+/* or.1 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x51008000 } -+ }, -+/* or.1 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x50008000 } -+ }, -+/* or.1 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x53008000 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x54008000 } -+ }, -+/* or.1 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x54008000 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x52008000 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x52108000 } -+ }, -+/* or.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x51008300 } -+ }, -+/* or.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x50008300 } -+ }, -+/* or.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x53008300 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x54008300 } -+ }, -+/* or.1 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x54008300 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x52008300 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x52108300 } -+ }, -+/* or.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x51008400 } -+ }, -+/* or.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x50008400 } -+ }, -+/* or.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x53008400 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x54008400 } -+ }, -+/* or.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x54008400 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x52008400 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x52108400 } -+ }, -+/* or.1 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_1, { 0x51008400 } -+ }, -+/* or.1 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x50008400 } -+ }, -+/* or.1 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x53008400 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x54008400 } -+ }, -+/* or.1 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x54008400 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x52008400 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x52108400 } -+ }, -+/* or.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x51008200 } -+ }, -+/* or.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x50008200 } -+ }, -+/* or.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x53008200 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x54008200 } -+ }, -+/* or.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x54008200 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x52008200 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x52108200 } -+ }, -+/* or.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x51008210 } -+ }, -+/* or.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x50008210 } -+ }, -+/* or.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x53008210 } -+ }, -+/* or.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x54008210 } -+ }, -+/* or.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x54008210 } -+ }, -+/* or.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x52008210 } -+ }, -+/* or.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x52108210 } -+ }, -+/* and.1 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x41008100 } -+ }, -+/* and.1 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_direct, { 0x40008100 } -+ }, -+/* and.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x43008100 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x44008100 } -+ }, -+/* and.1 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_direct, { 0x44008100 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x42008100 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x42108100 } -+ }, -+/* and.1 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x41008000 } -+ }, -+/* and.1 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x40008000 } -+ }, -+/* and.1 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x43008000 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x44008000 } -+ }, -+/* and.1 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x44008000 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x42008000 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x42108000 } -+ }, -+/* and.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x41008300 } -+ }, -+/* and.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x40008300 } -+ }, -+/* and.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x43008300 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x44008300 } -+ }, -+/* and.1 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x44008300 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x42008300 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x42108300 } -+ }, -+/* and.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x41008400 } -+ }, -+/* and.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x40008400 } -+ }, -+/* and.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x43008400 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x44008400 } -+ }, -+/* and.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x44008400 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x42008400 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x42108400 } -+ }, -+/* and.1 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_1, { 0x41008400 } -+ }, -+/* and.1 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x40008400 } -+ }, -+/* and.1 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x43008400 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x44008400 } -+ }, -+/* and.1 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x44008400 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x42008400 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x42108400 } -+ }, -+/* and.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x41008200 } -+ }, -+/* and.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x40008200 } -+ }, -+/* and.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x43008200 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x44008200 } -+ }, -+/* and.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x44008200 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x42008200 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x42108200 } -+ }, -+/* and.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x41008210 } -+ }, -+/* and.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x40008210 } -+ }, -+/* and.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x43008210 } -+ }, -+/* and.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x44008210 } -+ }, -+/* and.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x44008210 } -+ }, -+/* and.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x42008210 } -+ }, -+/* and.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x42108210 } -+ }, -+/* xor.4 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x69000100 } -+ }, -+/* xor.4 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x68000100 } -+ }, -+/* xor.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x6b000100 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x6c000100 } -+ }, -+/* xor.4 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x6c000100 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x6a000100 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x6a100100 } -+ }, -+/* xor.4 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x69000000 } -+ }, -+/* xor.4 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x68000000 } -+ }, -+/* xor.4 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x6b000000 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x6c000000 } -+ }, -+/* xor.4 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x6c000000 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x6a000000 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x6a100000 } -+ }, -+/* xor.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x69000300 } -+ }, -+/* xor.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x68000300 } -+ }, -+/* xor.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x6b000300 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x6c000300 } -+ }, -+/* xor.4 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x6c000300 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x6a000300 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x6a100300 } -+ }, -+/* xor.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x69000400 } -+ }, -+/* xor.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x68000400 } -+ }, -+/* xor.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x6b000400 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x6c000400 } -+ }, -+/* xor.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x6c000400 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x6a000400 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x6a100400 } -+ }, -+/* xor.4 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x69000400 } -+ }, -+/* xor.4 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x68000400 } -+ }, -+/* xor.4 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x6b000400 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x6c000400 } -+ }, -+/* xor.4 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x6c000400 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x6a000400 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x6a100400 } -+ }, -+/* xor.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x69000200 } -+ }, -+/* xor.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x68000200 } -+ }, -+/* xor.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x6b000200 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x6c000200 } -+ }, -+/* xor.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x6c000200 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x6a000200 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x6a100200 } -+ }, -+/* xor.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x69000210 } -+ }, -+/* xor.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x68000210 } -+ }, -+/* xor.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x6b000210 } -+ }, -+/* xor.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x6c000210 } -+ }, -+/* xor.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x6c000210 } -+ }, -+/* xor.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x6a000210 } -+ }, -+/* xor.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x6a100210 } -+ }, -+/* xor.2 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x61000100 } -+ }, -+/* xor.2 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x60000100 } -+ }, -+/* xor.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x63000100 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x64000100 } -+ }, -+/* xor.2 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x64000100 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x62000100 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x62100100 } -+ }, -+/* xor.2 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x61000000 } -+ }, -+/* xor.2 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x60000000 } -+ }, -+/* xor.2 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x63000000 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x64000000 } -+ }, -+/* xor.2 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x64000000 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x62000000 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x62100000 } -+ }, -+/* xor.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x61000300 } -+ }, -+/* xor.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x60000300 } -+ }, -+/* xor.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x63000300 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x64000300 } -+ }, -+/* xor.2 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x64000300 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x62000300 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x62100300 } -+ }, -+/* xor.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x61000400 } -+ }, -+/* xor.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x60000400 } -+ }, -+/* xor.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x63000400 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x64000400 } -+ }, -+/* xor.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x64000400 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x62000400 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x62100400 } -+ }, -+/* xor.2 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_2, { 0x61000400 } -+ }, -+/* xor.2 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x60000400 } -+ }, -+/* xor.2 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x63000400 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x64000400 } -+ }, -+/* xor.2 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x64000400 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x62000400 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x62100400 } -+ }, -+/* xor.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x61000200 } -+ }, -+/* xor.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x60000200 } -+ }, -+/* xor.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x63000200 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x64000200 } -+ }, -+/* xor.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x64000200 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x62000200 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x62100200 } -+ }, -+/* xor.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x61000210 } -+ }, -+/* xor.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x60000210 } -+ }, -+/* xor.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x63000210 } -+ }, -+/* xor.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x64000210 } -+ }, -+/* xor.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x64000210 } -+ }, -+/* xor.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x62000210 } -+ }, -+/* xor.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x62100210 } -+ }, -+/* or.4 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x59000100 } -+ }, -+/* or.4 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x58000100 } -+ }, -+/* or.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x5b000100 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x5c000100 } -+ }, -+/* or.4 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x5c000100 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x5a000100 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x5a100100 } -+ }, -+/* or.4 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x59000000 } -+ }, -+/* or.4 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x58000000 } -+ }, -+/* or.4 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x5b000000 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x5c000000 } -+ }, -+/* or.4 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x5c000000 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x5a000000 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x5a100000 } -+ }, -+/* or.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x59000300 } -+ }, -+/* or.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x58000300 } -+ }, -+/* or.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x5b000300 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x5c000300 } -+ }, -+/* or.4 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x5c000300 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x5a000300 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x5a100300 } -+ }, -+/* or.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x59000400 } -+ }, -+/* or.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x58000400 } -+ }, -+/* or.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x5b000400 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x5c000400 } -+ }, -+/* or.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x5c000400 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x5a000400 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x5a100400 } -+ }, -+/* or.4 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x59000400 } -+ }, -+/* or.4 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x58000400 } -+ }, -+/* or.4 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x5b000400 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x5c000400 } -+ }, -+/* or.4 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x5c000400 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x5a000400 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x5a100400 } -+ }, -+/* or.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x59000200 } -+ }, -+/* or.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x58000200 } -+ }, -+/* or.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x5b000200 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x5c000200 } -+ }, -+/* or.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x5c000200 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x5a000200 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x5a100200 } -+ }, -+/* or.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x59000210 } -+ }, -+/* or.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x58000210 } -+ }, -+/* or.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x5b000210 } -+ }, -+/* or.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x5c000210 } -+ }, -+/* or.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x5c000210 } -+ }, -+/* or.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x5a000210 } -+ }, -+/* or.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x5a100210 } -+ }, -+/* or.2 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x51000100 } -+ }, -+/* or.2 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x50000100 } -+ }, -+/* or.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x53000100 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x54000100 } -+ }, -+/* or.2 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x54000100 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x52000100 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x52100100 } -+ }, -+/* or.2 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x51000000 } -+ }, -+/* or.2 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x50000000 } -+ }, -+/* or.2 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x53000000 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x54000000 } -+ }, -+/* or.2 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x54000000 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x52000000 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x52100000 } -+ }, -+/* or.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x51000300 } -+ }, -+/* or.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x50000300 } -+ }, -+/* or.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x53000300 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x54000300 } -+ }, -+/* or.2 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x54000300 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x52000300 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x52100300 } -+ }, -+/* or.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x51000400 } -+ }, -+/* or.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x50000400 } -+ }, -+/* or.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x53000400 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x54000400 } -+ }, -+/* or.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x54000400 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x52000400 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x52100400 } -+ }, -+/* or.2 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_2, { 0x51000400 } -+ }, -+/* or.2 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x50000400 } -+ }, -+/* or.2 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x53000400 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x54000400 } -+ }, -+/* or.2 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x54000400 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x52000400 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x52100400 } -+ }, -+/* or.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x51000200 } -+ }, -+/* or.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x50000200 } -+ }, -+/* or.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x53000200 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x54000200 } -+ }, -+/* or.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x54000200 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x52000200 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x52100200 } -+ }, -+/* or.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x51000210 } -+ }, -+/* or.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x50000210 } -+ }, -+/* or.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x53000210 } -+ }, -+/* or.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x54000210 } -+ }, -+/* or.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x54000210 } -+ }, -+/* or.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x52000210 } -+ }, -+/* or.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x52100210 } -+ }, -+/* and.4 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x49000100 } -+ }, -+/* and.4 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x48000100 } -+ }, -+/* and.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x4b000100 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x4c000100 } -+ }, -+/* and.4 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x4c000100 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x4a000100 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x4a100100 } -+ }, -+/* and.4 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x49000000 } -+ }, -+/* and.4 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x48000000 } -+ }, -+/* and.4 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x4b000000 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x4c000000 } -+ }, -+/* and.4 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x4c000000 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x4a000000 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x4a100000 } -+ }, -+/* and.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x49000300 } -+ }, -+/* and.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x48000300 } -+ }, -+/* and.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x4b000300 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4c000300 } -+ }, -+/* and.4 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x4c000300 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x4a000300 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x4a100300 } -+ }, -+/* and.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x49000400 } -+ }, -+/* and.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x48000400 } -+ }, -+/* and.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x4b000400 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4c000400 } -+ }, -+/* and.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x4c000400 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x4a000400 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x4a100400 } -+ }, -+/* and.4 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x49000400 } -+ }, -+/* and.4 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x48000400 } -+ }, -+/* and.4 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x4b000400 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x4c000400 } -+ }, -+/* and.4 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x4c000400 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x4a000400 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x4a100400 } -+ }, -+/* and.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x49000200 } -+ }, -+/* and.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x48000200 } -+ }, -+/* and.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x4b000200 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4c000200 } -+ }, -+/* and.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4c000200 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x4a000200 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x4a100200 } -+ }, -+/* and.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x49000210 } -+ }, -+/* and.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x48000210 } -+ }, -+/* and.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x4b000210 } -+ }, -+/* and.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4c000210 } -+ }, -+/* and.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4c000210 } -+ }, -+/* and.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x4a000210 } -+ }, -+/* and.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x4a100210 } -+ }, -+/* and.2 ${d-direct-addr},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_direct, { 0x41000100 } -+ }, -+/* and.2 #${d-imm8},${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x40000100 } -+ }, -+/* and.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x43000100 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x44000100 } -+ }, -+/* and.2 (${d-An}),${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x44000100 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x42000100 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x42100100 } -+ }, -+/* and.2 ${d-direct-addr},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_direct_s1_immediate, { 0x41000000 } -+ }, -+/* and.2 #${d-imm8},#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x40000000 } -+ }, -+/* and.2 (${d-An},${d-r}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x43000000 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x44000000 } -+ }, -+/* and.2 (${d-An}),#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x44000000 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x42000000 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } }, -+ & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x42100000 } -+ }, -+/* and.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x41000300 } -+ }, -+/* and.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x40000300 } -+ }, -+/* and.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x43000300 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x44000300 } -+ }, -+/* and.2 (${d-An}),(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x44000300 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x42000300 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x42100300 } -+ }, -+/* and.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x41000400 } -+ }, -+/* and.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x40000400 } -+ }, -+/* and.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x43000400 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x44000400 } -+ }, -+/* and.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x44000400 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x42000400 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x42100400 } -+ }, -+/* and.2 ${d-direct-addr},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_2, { 0x41000400 } -+ }, -+/* and.2 #${d-imm8},(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x40000400 } -+ }, -+/* and.2 (${d-An},${d-r}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x43000400 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x44000400 } -+ }, -+/* and.2 (${d-An}),(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x44000400 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x42000400 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x42100400 } -+ }, -+/* and.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x41000200 } -+ }, -+/* and.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x40000200 } -+ }, -+/* and.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x43000200 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x44000200 } -+ }, -+/* and.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x44000200 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x42000200 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x42100200 } -+ }, -+/* and.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x41000210 } -+ }, -+/* and.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x40000210 } -+ }, -+/* and.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x43000210 } -+ }, -+/* and.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x44000210 } -+ }, -+/* and.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x44000210 } -+ }, -+/* and.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x42000210 } -+ }, -+/* and.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } }, -+ & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x42100210 } -+ }, -+/* moveai ${An},#${imm24} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (AN), ',', '#', OP (IMM24), 0 } }, -+ & ifmt_moveai, { 0xe0000000 } -+ }, -+/* __nop__ */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_nop_insn, { 0xc8000000 } -+ }, -+/* jmp${cc}${C}${P} $offset21 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, OP (CC), OP (C), OP (P), ' ', OP (OFFSET21), 0 } }, -+ & ifmt_jmpcc, { 0xd0000000 } -+ }, -+/* call $An,$offset24 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (AN), ',', OP (OFFSET24), 0 } }, -+ & ifmt_call, { 0xd8000000 } -+ }, -+/* calli ${An},${offset16}(${Am}) */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (AN), ',', OP (OFFSET16), '(', OP (AM), ')', 0 } }, -+ & ifmt_calli, { 0xf0000000 } -+ }, -+/* suspend */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_suspend, { 0x800 } -+ }, -+/* __clracc__ ${dsp-destA} */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, ' ', OP (DSP_DESTA), 0 } }, -+ & ifmt_dsp_clracc, { 0x36400100 } -+ }, -+/* __unused__00_11 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_00_11, { 0x8800 } -+ }, -+/* __unused__00_13 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_00_11, { 0x9800 } -+ }, -+/* __unused__00_14 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_00_11, { 0xa000 } -+ }, -+/* __unused__00_16 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_00_11, { 0xb000 } -+ }, -+/* __unused__02_04 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x10800000 } -+ }, -+/* __unused__02_07 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x10e00000 } -+ }, -+/* __unused__02_0D */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x11a00000 } -+ }, -+/* __unused__02_0E */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x11c00000 } -+ }, -+/* __unused__02_0F */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x11e00000 } -+ }, -+/* __unused__02_17 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x12e00000 } -+ }, -+/* __unused__02_19 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x13200000 } -+ }, -+/* __unused__02_1B */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x13600000 } -+ }, -+/* __unused__02_1D */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_02_04, { 0x13a00000 } -+ }, -+/* __unused__01 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_01, { 0x8000000 } -+ }, -+/* __unused__03 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_01, { 0x18000000 } -+ }, -+/* __unused__07 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_01, { 0x38000000 } -+ }, -+/* __unused__17 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_01, { 0xb8000000 } -+ }, -+/* __unused__1D */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_01, { 0xe8000000 } -+ }, -+/* __unused__1F */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_01, { 0xf8000000 } -+ }, -+/* __unused__DSP_06 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x30c00000 } -+ }, -+/* __unused__DSP_0b */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x31600000 } -+ }, -+/* __unused__DSP_0c */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x31800000 } -+ }, -+/* __unused__DSP_0d */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x31a00000 } -+ }, -+/* __unused__DSP_0e */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x31c00000 } -+ }, -+/* __unused__DSP_0f */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x31e00000 } -+ }, -+/* __unused__DSP_14 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x32800000 } -+ }, -+/* __unused__DSP_15 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x32a00000 } -+ }, -+/* __unused__DSP_16 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x32c00000 } -+ }, -+/* __unused__DSP_17 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x32e00000 } -+ }, -+/* __unused__DSP_18 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33000000 } -+ }, -+/* __unused__DSP_19 */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33200000 } -+ }, -+/* __unused__DSP_1a */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33400000 } -+ }, -+/* __unused__DSP_1b */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33600000 } -+ }, -+/* __unused__DSP_1c */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33800000 } -+ }, -+/* __unused__DSP_1d */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33a00000 } -+ }, -+/* __unused__DSP_1e */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33c00000 } -+ }, -+/* __unused__DSP_1f */ -+ { -+ { 0, 0, 0, 0 }, -+ { { MNEM, 0 } }, -+ & ifmt_unused_DSP_06, { 0x33e00000 } -+ }, -+}; -+ -+#undef A -+#undef OPERAND -+#undef MNEM -+#undef OP -+ -+/* Formats for ALIAS macro-insns. */ -+ -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_##f] -+#else -+#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_/**/f] -+#endif -+static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { -+ 32, 32, 0xffffffff, { { F (F_OP1) }, { F (F_D) }, { F (F_IMM16_2) }, { 0 } } -+}; -+ -+static const CGEN_IFMT ifmt_dsp_clracc_macro ATTRIBUTE_UNUSED = { -+ 32, 32, 0xfffeffff, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_DESTA) }, { F (F_S1) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { F (F_DSP_T) }, { F (F_DSP_C) }, { F (F_BIT26) }, { F (F_DSP_R) }, { 0 } } -+}; -+ -+#undef F -+ -+/* Each non-simple macro entry points to an array of expansion possibilities. */ -+ -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define A(a) (1 << CGEN_INSN_##a) -+#else -+#define A(a) (1 << CGEN_INSN_/**/a) -+#endif -+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -+#define OPERAND(op) UBICOM32_OPERAND_##op -+#else -+#define OPERAND(op) UBICOM32_OPERAND_/**/op -+#endif -+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) -+ -+/* The macro instruction table. */ -+ -+static const CGEN_IBASE ubicom32_cgen_macro_insn_table[] = -+{ -+/* nop */ -+ { -+ -1, "nop", "nop", 32, -+ { 0|A(ALIAS), { { { (1<macro_insn_table.init_entries = insns; -+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); -+ cd->macro_insn_table.num_init_entries = num_macros; -+ -+ oc = & ubicom32_cgen_insn_opcode_table[0]; -+ insns = (CGEN_INSN *) cd->insn_table.init_entries; -+ for (i = 0; i < MAX_INSNS; ++i) -+ { -+ insns[i].opcode = &oc[i]; -+ ubicom32_cgen_build_insn_regex (& insns[i]); -+ } -+ -+ cd->sizeof_fields = sizeof (CGEN_FIELDS); -+ cd->set_fields_bitsize = set_fields_bitsize; -+ -+ cd->asm_hash_p = asm_hash_insn_p; -+ cd->asm_hash = asm_hash_insn; -+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE; -+ -+ cd->dis_hash_p = dis_hash_insn_p; -+ cd->dis_hash = dis_hash_insn; -+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE; -+} ---- /dev/null -+++ b/opcodes/ubicom32-opc.h -@@ -0,0 +1,868 @@ -+/* Instruction opcode header for ubicom32. -+ -+THIS FILE IS MACHINE GENERATED WITH CGEN. -+ -+Copyright 1996-2007 Free Software Foundation, Inc. -+ -+This file is part of the GNU Binutils and/or GDB, the GNU debugger. -+ -+ This file is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with this program; if not, write to the Free Software Foundation, Inc., -+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -+ -+*/ -+ -+#ifndef UBICOM32_OPC_H -+#define UBICOM32_OPC_H -+ -+/* -- opc.h */ -+ -+/* Check applicability of instructions against machines. */ -+#define CGEN_VALIDATE_INSN_SUPPORTED -+extern int ubicom32_cgen_insn_supported -+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *)); -+ -+/* Allows reason codes to be output when assembler errors occur. */ -+#define CGEN_VERBOSE_ASSEMBLER_ERRORS -+ -+/* Override disassembly hashing */ -+ -+#define CGEN_DIS_HASH_SIZE 32 -+#define CGEN_DIS_HASH(buf,value) ubicom32_dis_hash(buf,value) -+ -+#define CGEN_ASM_HASH_SIZE 509 -+#define CGEN_ASM_HASH(insn) ubicom32_asm_hash(insn) -+ -+extern unsigned int ubicom32_dis_hash (const char *buf, CGEN_INSN_INT value); -+extern unsigned int ubicom32_asm_hash (const char *insn); -+ -+/* Structure used to map between directly addressable registers and -+ their human-readable names. Used by both the assembler and the -+ disassembler. -+*/ -+struct ubicom32_cgen_data_space_map { -+ long address; -+ char *name; -+ int type; -+}; -+ -+extern struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mars[]; -+extern struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mercury[]; -+ -+#define A0_ADDRESS 0x80 -+#define A1_ADDRESS (A0_ADDRESS + 4) -+#define A2_ADDRESS (A0_ADDRESS + 8) -+#define A3_ADDRESS (A0_ADDRESS + 12) -+#define A4_ADDRESS (A0_ADDRESS + 16) -+#define A5_ADDRESS (A0_ADDRESS + 20) -+#define A6_ADDRESS (A0_ADDRESS + 24) -+#define A7_ADDRESS (A0_ADDRESS + 28) -+ -+/* XXX */ -+typedef unsigned char UQI; -+ -+ -+/* -- opc.c */ -+/* Enum declaration for ubicom32 instruction types. */ -+typedef enum cgen_insn_type { -+ UBICOM32_INSN_INVALID, UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG_ADDSUB2 -+ , UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2 -+ , UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_IMM_BIT5_ADDSUB2 -+ , UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_IMM_BIT5_ADDSUB2 -+ , UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5_ADDSUB -+ , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB2 -+ , UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_SRC2_DATA_REG_ADDSUB2 -+ , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5_ADDSUB2 -+ , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2 -+ , UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5_ADDSUB -+ , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL -+ , UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_INDEX -+ , UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_OFFSET, UBICOM32_INSN_IERASE_D_PEA_INDIRECT, UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_POST_INCREMENT, UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_PRE_INCREMENT -+ , UBICOM32_INSN_IREAD_S1_EA_INDIRECT, UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_DIRECT -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_IMMEDIATE -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_4 -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_SETCSR_S1_DIRECT, UBICOM32_INSN_SETCSR_S1_IMMEDIATE, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SETCSR_S1_INDIRECT_4, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BKPT_S1_DIRECT -+ , UBICOM32_INSN_BKPT_S1_IMMEDIATE, UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BKPT_S1_INDIRECT_4 -+ , UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_RET_S1_DIRECT, UBICOM32_INSN_RET_S1_IMMEDIATE -+ , UBICOM32_INSN_RET_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_RET_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_RET_S1_INDIRECT_4, UBICOM32_INSN_RET_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_RET_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_DIRECT, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_DIRECT -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_MOVEA_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_DIRECT -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT -+ , UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_DIRECT -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_DIRECT -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_2 -+ , UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_MOVE_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_IMMEDIATE -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT -+ , UBICOM32_INSN_EXT_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_DIRECT -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE -+ , UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVEI_D_DIRECT -+ , UBICOM32_INSN_MOVEI_D_IMMEDIATE_2, UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVEI_D_INDIRECT_2 -+ , UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_BCLR_D_DIRECT_S1_DIRECT, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_DIRECT -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_DIRECT -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_BSET_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_IMMEDIATE -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_4 -+ , UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_BTST_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_BTST_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5 -+ , UBICOM32_INSN_BTST_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_BTST_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_INDEX_4_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_4_DYN_REG -+ , UBICOM32_INSN_BTST_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_DIRECT -+ , UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_2 -+ , UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_DIRECT, UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_IMMEDIATE -+ , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_1, UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_CRCGEN_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_IMMEDIATE_IMM_BIT5 -+ , UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_INDEX_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_OFFSET_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_INDIRECT_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_POST_INCREMENT_1_IMM_BIT5 -+ , UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_PRE_INCREMENT_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_DIRECT_DYN_REG, UBICOM32_INSN_CRCGEN_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_INDEX_1_DYN_REG -+ , UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_OFFSET_1_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_1_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_POST_INCREMENT_1_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_PRE_INCREMENT_1_DYN_REG -+ , UBICOM32_INSN_BFEXTU_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5 -+ , UBICOM32_INSN_BFEXTU_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_BFEXTU_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_INDEX_4_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_4_DYN_REG -+ , UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_IMMEDIATE_IMM_BIT5 -+ , UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5 -+ , UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_DIRECT_DYN_REG, UBICOM32_INSN_BFRVRS_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_INDEX_4_DYN_REG -+ , UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG -+ , UBICOM32_INSN_MERGE_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MERGE_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5 -+ , UBICOM32_INSN_MERGE_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_MERGE_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_INDEX_4_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_4_DYN_REG -+ , UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_IMMEDIATE_IMM_BIT5 -+ , UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5 -+ , UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_DIRECT_DYN_REG, UBICOM32_INSN_SHFTD_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_INDEX_4_DYN_REG -+ , UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG -+ , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_ASR_1_DYN_REG_S1_DIRECT, UBICOM32_INSN_ASR_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_ASR_1_DYN_REG_S1_IMMEDIATE -+ , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_1, UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSL_1_DYN_REG_S1_DIRECT -+ , UBICOM32_INSN_LSL_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSL_1_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_1 -+ , UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSR_1_DYN_REG_S1_DIRECT, UBICOM32_INSN_LSR_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSR_1_DYN_REG_S1_IMMEDIATE -+ , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_1, UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_ASR_2_DYN_REG_S1_DIRECT -+ , UBICOM32_INSN_ASR_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_ASR_2_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_2 -+ , UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSL_2_DYN_REG_S1_DIRECT, UBICOM32_INSN_LSL_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSL_2_DYN_REG_S1_IMMEDIATE -+ , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_2, UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSR_2_DYN_REG_S1_DIRECT -+ , UBICOM32_INSN_LSR_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSR_2_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_2 -+ , UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_ASR_4_DYN_REG_S1_DIRECT, UBICOM32_INSN_ASR_4_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_ASR_4_DYN_REG_S1_IMMEDIATE -+ , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_4, UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSL_4_DYN_REG_S1_DIRECT -+ , UBICOM32_INSN_LSL_4_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSL_4_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_4 -+ , UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSR_4_DYN_REG_S1_DIRECT, UBICOM32_INSN_LSR_4_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSR_4_DYN_REG_S1_IMMEDIATE -+ , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_4, UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_MAC_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_MAC_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MAC_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5 -+ , UBICOM32_INSN_MAC_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_MAC_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_2_DYN_REG -+ , UBICOM32_INSN_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_MULF_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MULF_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5 -+ , UBICOM32_INSN_MULF_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_MULF_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_2_DYN_REG -+ , UBICOM32_INSN_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_MULU_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MULU_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5 -+ , UBICOM32_INSN_MULU_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_MULU_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_2_DYN_REG -+ , UBICOM32_INSN_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_IMMEDIATE_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG -+ , UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5 -+ , UBICOM32_INSN_MULS_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MULS_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5 -+ , UBICOM32_INSN_MULS_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_DIRECT_DYN_REG -+ , UBICOM32_INSN_MULS_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_2_DYN_REG -+ , UBICOM32_INSN_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_DIRECT -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_DIRECT -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_IMMEDIATE -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_2 -+ , UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_PDEC_D_DIRECT_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_IMMEDIATE_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_INDEX_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_OFFSET_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PDEC_D_INDIRECT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_POST_INCREMENT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_PRE_INCREMENT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT -+ , UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_IMMEDIATE -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE -+ , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT -+ , UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE -+ , UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT -+ , UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_IMMEDIATE -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE -+ , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_CMPI_S1_DIRECT, UBICOM32_INSN_CMPI_S1_IMMEDIATE, UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_CMPI_S1_INDIRECT_2, UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_DIRECT -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT -+ , UBICOM32_INSN_PXADDS_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXHI_S_S1_DIRECT, UBICOM32_INSN_PXHI_S_S1_IMMEDIATE -+ , UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXHI_S_S1_INDIRECT_4, UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXHI_S1_DIRECT, UBICOM32_INSN_PXHI_S1_IMMEDIATE, UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXHI_S1_INDIRECT_4, UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_S_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_DIRECT -+ , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_PXVI_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE -+ , UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_DIRECT -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_DIRECT -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_IMMEDIATE -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_DIRECT -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT -+ , UBICOM32_INSN_PXCNV_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4 -+ , UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_DIRECT -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_DIRECT -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_IMMEDIATE -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_4 -+ , UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_SUB_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_IMMEDIATE -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_SUB_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_DIRECT -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_1_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_DIRECT -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_IMMEDIATE -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_1 -+ , UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_ADD_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT -+ , UBICOM32_INSN_ADD_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_DIRECT -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_2_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_DIRECT -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_IMMEDIATE -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_2 -+ , UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_XOR_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_IMMEDIATE -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT -+ , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT -+ , UBICOM32_INSN_OR_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE -+ , UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_DIRECT -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE -+ , UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1 -+ , UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1 -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1 -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1 -+ , UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1 -+ , UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_4_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_DIRECT -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_IMMEDIATE -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_4 -+ , UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_XOR_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT -+ , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT -+ , UBICOM32_INSN_OR_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE -+ , UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_DIRECT -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_4_D_DIRECT_S1_DIRECT -+ , UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_DIRECT -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_IMMEDIATE -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4 -+ , UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4 -+ , UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_4 -+ , UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_4 -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4 -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4 -+ , UBICOM32_INSN_AND_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT -+ , UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_DIRECT_S1_IMMEDIATE -+ , UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_IMMEDIATE -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2 -+ , UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2 -+ , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVEAI, UBICOM32_INSN_NOP_INSN, UBICOM32_INSN_JMPCC -+ , UBICOM32_INSN_CALL, UBICOM32_INSN_CALLI, UBICOM32_INSN_SUSPEND, UBICOM32_INSN_DSP_CLRACC -+ , UBICOM32_INSN_UNUSED_00_11, UBICOM32_INSN_UNUSED_00_13, UBICOM32_INSN_UNUSED_00_14, UBICOM32_INSN_UNUSED_00_16 -+ , UBICOM32_INSN_UNUSED_02_04, UBICOM32_INSN_UNUSED_02_07, UBICOM32_INSN_UNUSED_02_0D, UBICOM32_INSN_UNUSED_02_0E -+ , UBICOM32_INSN_UNUSED_02_0F, UBICOM32_INSN_UNUSED_02_17, UBICOM32_INSN_UNUSED_02_19, UBICOM32_INSN_UNUSED_02_1B -+ , UBICOM32_INSN_UNUSED_02_1D, UBICOM32_INSN_UNUSED_01, UBICOM32_INSN_UNUSED_03, UBICOM32_INSN_UNUSED_07 -+ , UBICOM32_INSN_UNUSED_17, UBICOM32_INSN_UNUSED_1D, UBICOM32_INSN_UNUSED_1F, UBICOM32_INSN_UNUSED_DSP_06 -+ , UBICOM32_INSN_UNUSED_DSP_0B, UBICOM32_INSN_UNUSED_DSP_0C, UBICOM32_INSN_UNUSED_DSP_0D, UBICOM32_INSN_UNUSED_DSP_0E -+ , UBICOM32_INSN_UNUSED_DSP_0F, UBICOM32_INSN_UNUSED_DSP_14, UBICOM32_INSN_UNUSED_DSP_15, UBICOM32_INSN_UNUSED_DSP_16 -+ , UBICOM32_INSN_UNUSED_DSP_17, UBICOM32_INSN_UNUSED_DSP_18, UBICOM32_INSN_UNUSED_DSP_19, UBICOM32_INSN_UNUSED_DSP_1A -+ , UBICOM32_INSN_UNUSED_DSP_1B, UBICOM32_INSN_UNUSED_DSP_1C, UBICOM32_INSN_UNUSED_DSP_1D, UBICOM32_INSN_UNUSED_DSP_1E -+ , UBICOM32_INSN_UNUSED_DSP_1F -+} CGEN_INSN_TYPE; -+ -+/* Index of `invalid' insn place holder. */ -+#define CGEN_INSN_INVALID UBICOM32_INSN_INVALID -+ -+/* Total number of insns in table. */ -+#define MAX_INSNS ((int) UBICOM32_INSN_UNUSED_DSP_1F + 1) -+ -+/* This struct records data prior to insertion or after extraction. */ -+struct cgen_fields -+{ -+ int length; -+ long f_nil; -+ long f_anyof; -+ long f_d; -+ long f_d_bit10; -+ long f_d_type; -+ long f_d_r; -+ long f_d_M; -+ long f_d_i4_1; -+ long f_d_i4_2; -+ long f_d_i4_4; -+ long f_d_An; -+ long f_d_direct; -+ long f_d_imm8; -+ long f_d_imm7_t; -+ long f_d_imm7_b; -+ long f_d_imm7_1; -+ long f_d_imm7_2; -+ long f_d_imm7_4; -+ long f_s1; -+ long f_s1_bit10; -+ long f_s1_type; -+ long f_s1_r; -+ long f_s1_M; -+ long f_s1_i4_1; -+ long f_s1_i4_2; -+ long f_s1_i4_4; -+ long f_s1_An; -+ long f_s1_direct; -+ long f_s1_imm8; -+ long f_s1_imm7_t; -+ long f_s1_imm7_b; -+ long f_s1_imm7_1; -+ long f_s1_imm7_2; -+ long f_s1_imm7_4; -+ long f_op1; -+ long f_op2; -+ long f_bit26; -+ long f_opext; -+ long f_cond; -+ long f_imm16_1; -+ long f_imm16_2; -+ long f_o21; -+ long f_o23_21; -+ long f_o20_0; -+ long f_o24; -+ long f_imm23_21; -+ long f_imm24; -+ long f_o15_13; -+ long f_o12_8; -+ long f_o7_5; -+ long f_o4_0; -+ long f_o16; -+ long f_An; -+ long f_Am; -+ long f_Dn; -+ long f_bit5; -+ long f_P; -+ long f_C; -+ long f_int; -+ long f_dsp_C; -+ long f_dsp_T; -+ long f_dsp_S2_sel; -+ long f_dsp_R; -+ long f_dsp_destA; -+ long f_dsp_b15; -+ long f_dsp_S2; -+ long f_dsp_J; -+ long f_s2; -+ long f_b15; -+}; -+ -+#define CGEN_INIT_PARSE(od) \ -+{\ -+} -+#define CGEN_INIT_INSERT(od) \ -+{\ -+} -+#define CGEN_INIT_EXTRACT(od) \ -+{\ -+} -+#define CGEN_INIT_PRINT(od) \ -+{\ -+} -+ -+ -+#endif /* UBICOM32_OPC_H */ ---- /dev/null -+++ b/ubicom32.exp -@@ -0,0 +1,45 @@ -+# Expect control file for DEJAGNU test system and ubicom32 -+# -+ -+# Needed for isnative. -+load_lib "framework.exp" -+ -+# Turn off plum-hall testing -+# -+set PLUMHALL no -+set PLUMHALL_99b no -+ -+# And Perennial too -+set PERENNIAL_C no -+set PERENNIAL_CLASSIC_C yes -+ -+set UNDERSCORES yes -+ -+if ![info exists tool] { -+ set run_multiple_targets 0; -+} elseif { $tool == "g++" || $tool == "gcc" || $tool == "gdb"} { -+ set run_multiple_targets 1; -+} else { -+ set run_multiple_targets 0; -+} -+ -+verbose "Global Config FIle: target_triplet is $target_triplet" 2 -+global target_list -+case "$target_triplet" in { -+ { "ubicom32-*" } { -+ set target_list "ubicom32-sid" -+ } -+ -+ { "ip3k-*" } { -+ set target_list "ip3k-sid" -+ } -+ -+ default { -+ set target_list { "unix" } -+ } -+} -+ -+if { ! $run_multiple_targets } { -+ set target_list [lindex $target_list 0]; -+} -+ diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index 5526b4be79..b5218aee3b 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -9,7 +9,7 @@ choice config GCC_VERSION_4_4_7 bool "gcc 4.4.7" - depends (avr32 || ubicom32) + depends avr32 config GCC_VERSION_4_6_2 bool "gcc 4.6.2" diff --git a/toolchain/gcc/Config.version b/toolchain/gcc/Config.version index 67165b767f..a473430395 100644 --- a/toolchain/gcc/Config.version +++ b/toolchain/gcc/Config.version @@ -3,7 +3,7 @@ config GCC_DEFAULT_VERSION config GCC_DEFAULT_VERSION_4_4_7 select GCC_DEFAULT_VERSION - default y if (avr32 || ubicom32) + default y if avr32 bool config GCC_DEFAULT_VERSION_4_6_LINARO diff --git a/toolchain/gcc/patches/4.4.7/600-ubicom_support.patch b/toolchain/gcc/patches/4.4.7/600-ubicom_support.patch deleted file mode 100644 index f9f93c1b4e..0000000000 --- a/toolchain/gcc/patches/4.4.7/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -2690,6 +2690,9 @@ case "${target}" in - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2340,6 +2340,34 @@ spu-*-elf*) - c_target_objs="${c_target_objs} spu-c.o" - cxx_target_objs="${cxx_target_objs} spu-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850e1-*-*) - target_cpu_default="TARGET_CPU_v850e1" - tm_file="dbxelf.h elfos.h svr4.h v850/v850.h" ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -551,6 +551,15 @@ sparc64-*-netbsd*) - ;; - spu-*-elf*) - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850e1-*-*) - ;; - v850e-*-*) diff --git a/toolchain/gcc/patches/4.5-linaro/600-ubicom_support.patch b/toolchain/gcc/patches/4.5-linaro/600-ubicom_support.patch deleted file mode 100644 index dd5c3a732a..0000000000 --- a/toolchain/gcc/patches/4.5-linaro/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -3728,6 +3728,9 @@ case "${target}" in - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libstdc++-v3 ${libgcj}" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2525,6 +2525,34 @@ spu-*-elf*) - c_target_objs="${c_target_objs} spu-c.o" - cxx_target_objs="${cxx_target_objs} spu-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850e1-*-*) - target_cpu_default="TARGET_CPU_v850e1" - tm_file="dbxelf.h elfos.h svr4.h newlib-stdint.h v850/v850.h" ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -562,6 +562,15 @@ sparc64-*-netbsd*) - ;; - spu-*-elf*) - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850e1-*-*) - ;; - v850e-*-*) diff --git a/toolchain/gcc/patches/4.6-linaro/600-ubicom_support.patch b/toolchain/gcc/patches/4.6-linaro/600-ubicom_support.patch deleted file mode 100644 index 79f8c3f39f..0000000000 --- a/toolchain/gcc/patches/4.6-linaro/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -3602,6 +3602,9 @@ case "${target}" in - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libstdc++-v3 ${libgcj}" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2675,6 +2675,34 @@ spu-*-elf*) - c_target_objs="${c_target_objs} spu-c.o" - cxx_target_objs="${cxx_target_objs} spu-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850e1-*-*) - target_cpu_default="TARGET_CPU_v850e1" - tm_file="dbxelf.h elfos.h newlib-stdint.h v850/v850.h" ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -563,6 +563,15 @@ sparc64-*-netbsd*) - ;; - spu-*-elf*) - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850e1-*-*) - ;; - v850e-*-*) diff --git a/toolchain/gcc/patches/4.6.2/600-ubicom_support.patch b/toolchain/gcc/patches/4.6.2/600-ubicom_support.patch deleted file mode 100644 index 6b6816157b..0000000000 --- a/toolchain/gcc/patches/4.6.2/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -3602,6 +3602,9 @@ case "${target}" in - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libstdc++-v3 ${libgcj}" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2675,6 +2675,34 @@ spu-*-elf*) - c_target_objs="${c_target_objs} spu-c.o" - cxx_target_objs="${cxx_target_objs} spu-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850e1-*-*) - target_cpu_default="TARGET_CPU_v850e1" - tm_file="dbxelf.h elfos.h newlib-stdint.h v850/v850.h" ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -572,6 +572,15 @@ sparc64-*-netbsd*) - ;; - spu-*-elf*) - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850e1-*-*) - ;; - v850e-*-*) diff --git a/toolchain/gcc/patches/4.6.3/600-ubicom_support.patch b/toolchain/gcc/patches/4.6.3/600-ubicom_support.patch deleted file mode 100644 index 6b6816157b..0000000000 --- a/toolchain/gcc/patches/4.6.3/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -3602,6 +3602,9 @@ case "${target}" in - ip2k-*-*) - noconfigdirs="$noconfigdirs target-libstdc++-v3 ${libgcj}" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2675,6 +2675,34 @@ spu-*-elf*) - c_target_objs="${c_target_objs} spu-c.o" - cxx_target_objs="${cxx_target_objs} spu-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850e1-*-*) - target_cpu_default="TARGET_CPU_v850e1" - tm_file="dbxelf.h elfos.h newlib-stdint.h v850/v850.h" ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -572,6 +572,15 @@ sparc64-*-netbsd*) - ;; - spu-*-elf*) - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850e1-*-*) - ;; - v850e-*-*) diff --git a/toolchain/gcc/patches/4.7-linaro/600-ubicom_support.patch b/toolchain/gcc/patches/4.7-linaro/600-ubicom_support.patch deleted file mode 100644 index f343903cf1..0000000000 --- a/toolchain/gcc/patches/4.7-linaro/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -3350,6 +3350,9 @@ case "${target}" in - *-*-freebsd*) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2503,6 +2503,34 @@ tilepro-*-linux*) - c_target_objs="tilepro-c.o" - cxx_target_objs="tilepro-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850*-*-*) - case ${target} in - v850e2v3-*-*) ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -1098,6 +1098,15 @@ tilepro-*-linux*) - tmake_file="${tmake_file} tilepro/t-crtstuff t-softfp-sfdf t-softfp tilepro/t-tilepro" - md_unwind_header=tilepro/linux-unwind.h - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850*-*-*) - tmake_file="v850/t-v850 t-fdpbit" - ;; diff --git a/toolchain/gcc/patches/4.7.2/600-ubicom_support.patch b/toolchain/gcc/patches/4.7.2/600-ubicom_support.patch deleted file mode 100644 index f343903cf1..0000000000 --- a/toolchain/gcc/patches/4.7.2/600-ubicom_support.patch +++ /dev/null @@ -1,9368 +0,0 @@ ---- a/configure -+++ b/configure -@@ -3350,6 +3350,9 @@ case "${target}" in - *-*-freebsd*) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; -+ ubicom32-*-*) -+ noconfigdirs="$noconfigdirs target-libffi" -+ ;; - *-*-linux* | *-*-gnu* | *-*-k*bsd*-gnu | *-*-kopensolaris*-gnu) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; ---- /dev/null -+++ b/gcc/config/ubicom32/constraints.md -@@ -0,0 +1,149 @@ -+; Constraint definitions for Ubicom32 -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_register_constraint "a" "ALL_ADDRESS_REGS" -+ "An An register.") -+ -+(define_register_constraint "d" "DATA_REGS" -+ "A Dn register.") -+ -+(define_register_constraint "h" "ACC_REGS" -+ "An accumulator register.") -+ -+(define_register_constraint "l" "ACC_LO_REGS" -+ "An accn_lo register.") -+ -+(define_register_constraint "Z" "FDPIC_REG" -+ "The FD-PIC GOT pointer: A0.") -+ -+(define_constraint "I" -+ "An 8-bit signed constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -128) && (ival <= 127)"))) -+ -+(define_constraint "Q" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0x00) && (ival <= 0xff)"))) -+ -+(define_constraint "R" -+ "An 8-bit signed constant value represented as unsigned." -+ (and (match_code "const_int") -+ (match_test "((ival >= 0x0000) && (ival <= 0x007f)) || ((ival >= 0xff80) && (ival <= 0xffff))"))) -+ -+(define_constraint "J" -+ "A 7-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 127)"))) -+ -+(define_constraint "K" -+ "A 7-bit unsigned constant value shifted << 1." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 254) && ((ival & 1) == 0)"))) -+ -+(define_constraint "L" -+ "A 7-bit unsigned constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 508) && ((ival & 3) == 0)"))) -+ -+(define_constraint "M" -+ "A 5-bit unsigned constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= 0) && (ival <= 31)"))) -+ -+(define_constraint "N" -+ "A signed 16 bit constant value." -+ (and (match_code "const_int") -+ (match_test "(ival >= -32768) && (ival <= 32767)"))) -+ -+(define_constraint "O" -+ "An exact bitmask of contiguous 1 bits starting at bit 0." -+ (and (match_code "const_int") -+ (match_test "exact_log2 (ival + 1) != -1"))) -+ -+(define_constraint "P" -+ "A 7-bit negative constant value shifted << 2." -+ (and (match_code "const_int") -+ (match_test "(ival >= -504) && (ival <= 0) && ((ival & 3) == 0)"))) -+ -+(define_constraint "S" -+ "A symbolic reference." -+ (match_code "symbol_ref")) -+ -+(define_constraint "Y" -+ "An FD-PIC symbolic reference." -+ (and (match_test "TARGET_FDPIC") -+ (match_test "GET_CODE (op) == UNSPEC") -+ (ior (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT") -+ (match_test "XINT (op, 1) == UNSPEC_FDPIC_GOT_FUNCDESC")))) -+ -+(define_memory_constraint "T1" -+ "A memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode"))) -+ -+(define_memory_constraint "T2" -+ "A memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode"))) -+ -+(define_memory_constraint "T4" -+ "A memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")))) -+ -+(define_memory_constraint "U1" -+ "An offsettable memory operand that can be used for .1 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == QImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U2" -+ "An offsettable memory operand that can be used for .2 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (match_test "GET_MODE (op) == HImode") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ -+(define_memory_constraint "U4" -+ "An offsettable memory operand that can be used for .4 instruction." -+ (and (match_test "memory_operand (op, GET_MODE(op))") -+ (ior (match_test "GET_MODE (op) == SImode") -+ (match_test "GET_MODE (op) == DImode") -+ (match_test "GET_MODE (op) == SFmode")) -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_DEC") -+ (match_test "GET_CODE (XEXP (op, 0)) != POST_MODIFY") -+ (match_test "GET_CODE (XEXP (op, 0)) != PRE_MODIFY"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/gcc/config/ubicom32/elf.h -@@ -0,0 +1,29 @@ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "\ -+%{msim:%{!shared:crt0%O%s}} \ -+crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+#ifdef __UBICOM32_FDPIC__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm (SECTION_OP); \ -+ asm ("move.4 a0, 0(sp);\n\t" \ -+ "call a5," USER_LABEL_PREFIX #FUNC ";"); \ -+ asm (TEXT_SECTION_ASM_OP); -+#endif -+ -+#undef SUBTARGET_DRIVER_SELF_SPECS -+#define SUBTARGET_DRIVER_SELF_SPECS \ -+ "%{mfdpic:-msim} " -+ -+#define NO_IMPLICIT_EXTERN_C -+ -+/* -+ * We need this to compile crtbegin/crtend. This should really be picked -+ * up from elfos.h but at the moment including elfos.h causes other more -+ * serous linker issues. -+ */ -+#define INIT_SECTION_ASM_OP "\t.section\t.init" -+#define FINI_SECTION_ASM_OP "\t.section\t.fini" ---- /dev/null -+++ b/gcc/config/ubicom32/linux.h -@@ -0,0 +1,80 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "-lc" -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{static:--start-group} %G %L %{static:--end-group} " \ -+ "%{!static: %G}" -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: %{pg|p|profile:gcrt1%O%s;pie:Scrt1%O%s;:crt1%O%s}} " \ -+ "crtreloc%O%s crti%O%s %{shared|pie:crtbeginS%O%s;:crtbegin%O%s}" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC \ -+ "%{shared|pie:crtendS%O%s;:crtend%O%s} crtn%O%s" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) -+ -+#define OBJECT_FORMAT_ELF -+ -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fdpic:-mfdpic}" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{mfdpic: -m elf32ubicom32fdpic -z text } %{shared} %{pie} \ -+ %{static:-dn -Bstatic} \ -+ %{shared:-G -Bdynamic} \ -+ %{!shared: %{!static: \ -+ %{rdynamic:-export-dynamic} \ -+ %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0}} \ -+ %{static}} " -+ -+/* -+#define MD_UNWIND_SUPPORT "config/bfin/linux-unwind.h" -+*/ ---- /dev/null -+++ b/gcc/config/ubicom32/predicates.md -@@ -0,0 +1,327 @@ -+; Predicate definitions for Ubicom32. -+ -+; Copyright (C) 2009 Free Software Foundation, Inc. -+; Contributed by Ubicom, Inc. -+ -+; This file is part of GCC. -+ -+; GCC is free software; you can redistribute it and/or modify it -+; under the terms of the GNU General Public License as published -+; by the Free Software Foundation; either version 3, or (at your -+; option) any later version. -+ -+; GCC is distributed in the hope that it will be useful, but WITHOUT -+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+; License for more details. -+ -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_predicate "ubicom32_move_operand" -+ (match_code "const_int, const_double, const, mem, subreg, reg, lo_sum") -+{ -+ if (CONST_INT_P (op)) -+ return true; -+ -+ if (GET_CODE (op) == CONST_DOUBLE) -+ return true; -+ -+ if (GET_CODE (op) == CONST) -+ return memory_address_p (mode, op); -+ -+ if (GET_MODE (op) != mode) -+ return false; -+ -+ if (MEM_P (op)) -+ return memory_address_p (mode, XEXP (op, 0)); -+ -+ if (GET_CODE (op) == SUBREG) { -+ op = SUBREG_REG (op); -+ -+ if (REG_P (op)) -+ return true; -+ -+ if (! MEM_P (op)) -+ return false; -+ -+ /* Paradoxical SUBREG. */ -+ if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (op))) -+ return false; -+ -+ return memory_address_p (GET_MODE (op), XEXP (op, 0)); -+ } -+ -+ return register_operand (op, mode); -+}) -+ -+;; Returns true if OP is either a symbol reference or a sum of a -+;; symbol reference and a constant. -+ -+(define_predicate "ubicom32_symbolic_address_operand" -+ (match_code "symbol_ref, label_ref, const") -+{ -+ switch (GET_CODE (op)) -+ { -+ case SYMBOL_REF: -+ case LABEL_REF: -+ return true; -+ -+ case CONST: -+ op = XEXP (op, 0); -+ return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF -+ || GET_CODE (XEXP (op, 0)) == LABEL_REF) -+ && CONST_INT_P (XEXP (op, 1))); -+ -+ default: -+ return false; -+ } -+}) -+ -+;; Return true if operand is the uClinux FD-PIC register. -+ -+(define_predicate "ubicom32_fdpic_operand" -+ (match_code "reg") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (!REG_P (op)) -+ return false; -+ -+ if (GET_MODE (op) != mode && mode != VOIDmode) -+ return false; -+ -+ if (REGNO (op) != FDPIC_REGNUM && REGNO (op) < FIRST_PSEUDO_REGISTER) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_fdpic_got_offset_operand" -+ (match_code "unspec") -+{ -+ if (! TARGET_FDPIC) -+ return false; -+ -+ if (GET_CODE (op) != UNSPEC) -+ return false; -+ -+ if (XINT (op, 1) != UNSPEC_FDPIC_GOT -+ && XINT (op, 1) != UNSPEC_FDPIC_GOT_FUNCDESC) -+ return false; -+ -+ return true; -+}) -+ -+(define_predicate "ubicom32_arith_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_I (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot1" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_Q (op))); -+}) -+ -+(define_predicate "ubicom32_arith_operand_dot2" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_R (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_move_operand (op, mode) -+ && ! ubicom32_symbolic_address_operand (op, mode) -+ && (! CONST_INT_P (op) -+ || satisfies_constraint_N (op))); -+}) -+ -+(define_predicate "ubicom32_compare_operator" -+ (match_code "compare")) -+ -+(define_predicate "ubicom32_and_or_si3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && ((exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 31) -+ || (exact_log2 (INTVAL (op)) != -1 -+ && exact_log2 (INTVAL (op)) <= 31) -+ || (exact_log2 (~INTVAL (op)) != -1 -+ && exact_log2 (~INTVAL (op)) <= 31)))); -+}) -+ -+(define_predicate "ubicom32_and_or_hi3_operand" -+ (match_code "subreg, reg, const_int, lo_sum, mem") -+{ -+ return (ubicom32_arith_operand (op, mode) -+ || (CONST_INT_P (op) -+ && exact_log2 (INTVAL (op) + 1) != -1 -+ && exact_log2 (INTVAL (op) + 1) <= 15)); -+}) -+ -+(define_predicate "ubicom32_mem_or_address_register_operand" -+ (match_code "subreg, reg, mem") -+{ -+ unsigned int regno; -+ -+ if (MEM_P (op) -+ && memory_operand (op, mode)) -+ return true; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_data_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == DATA_REGS); -+}) -+ -+(define_predicate "ubicom32_address_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return (regno >= FIRST_PSEUDO_REGISTER -+ || REGNO_REG_CLASS (regno) == FDPIC_REG -+ || REGNO_REG_CLASS (regno) == ADDRESS_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_lo_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_LO_REGS); -+}) -+ -+(define_predicate "ubicom32_acc_hi_register_operand" -+ (match_code "subreg, reg") -+{ -+ unsigned int regno; -+ -+ if (REG_P (op)) -+ regno = REGNO (op); -+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) -+ { -+ int offset; -+ if (REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER) -+ offset = SUBREG_BYTE (op) / (GET_MODE_SIZE (GET_MODE (op))); -+ else -+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), -+ GET_MODE (SUBREG_REG (op)), -+ SUBREG_BYTE (op), -+ GET_MODE (op)); -+ regno = REGNO (SUBREG_REG (op)) + offset; -+ } -+ else -+ return false; -+ -+ return ((regno >= FIRST_PSEUDO_REGISTER -+ && regno != REGNO (virtual_stack_vars_rtx)) -+ || REGNO_REG_CLASS (regno) == ACC_REGS); -+}) -+ -+(define_predicate "ubicom32_call_address_operand" -+ (match_code "symbol_ref, subreg, reg") -+{ -+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op)); -+}) -+ -+(define_special_predicate "ubicom32_cc_register_operand" -+ (and (match_code "reg") -+ (match_test "REGNO (op) == CC_REGNUM"))) -+ ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32 -@@ -0,0 +1,52 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# Commented out to speed up compiler development! -+# -+# MULTILIB_OPTIONS = march=ubicom32v1/march=ubicom32v2/march=ubicom32v3/march=ubicom32v4 -+# MULTILIB_DIRNAMES = ubicom32v1 ubicom32v2 ubicom32v3 ubicom32v4 -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+MULTILIB_OPTIONS += mfdpic -+MULTILIB_OPTIONS += mno-ipos-abi/mipos-abi -+MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -+ -+# Assemble startup files. -+$(T)crti.o: $(srcdir)/config/ubicom32/crti.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crti.S -+ -+$(T)crtn.o: $(srcdir)/config/ubicom32/crtn.S $(GCC_PASSES) -+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/ubicom32/crtn.S -+ -+# these parts are required because uClibc ldso needs them to link. -+# they are not in the specfile so they will not be included automatically. -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-linux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+#EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/t-ubicom32-uclinux -@@ -0,0 +1,35 @@ -+# Name of assembly file containing libgcc1 functions. -+# This entry must be present, but it can be empty if the target does -+# not need any assembler functions to support its code generation. -+CROSS_LIBGCC1 = -+ -+# Alternatively if assembler functions *are* needed then define the -+# entries below: -+# CROSS_LIBGCC1 = libgcc1-asm.a -+ -+LIB2FUNCS_EXTRA = \ -+ $(srcdir)/config/udivmodsi4.c \ -+ $(srcdir)/config/divmod.c \ -+ $(srcdir)/config/udivmod.c -+ -+# If any special flags are necessary when building libgcc2 put them here. -+# -+# TARGET_LIBGCC2_CFLAGS = -+ -+# We want fine grained libraries, so use the new code to build the -+# floating point emulation libraries. -+FPBIT = fp-bit.c -+DPBIT = dp-bit.c -+ -+fp-bit.c: $(srcdir)/config/fp-bit.c -+ echo '#define FLOAT' > fp-bit.c -+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c -+ -+dp-bit.c: $(srcdir)/config/fp-bit.c -+ cat $(srcdir)/config/fp-bit.c > dp-bit.c -+ -+# We only support v3 and v4 ISAs for uClinux. -+ -+MULTILIB_OPTIONS = march=ubicom32v3/march=ubicom32v4 -+ -+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # crtbeginS.o crtendS.o ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-modes.def -@@ -0,0 +1,30 @@ -+/* Definitions of target machine for GNU compiler, Ubicom32 architecture. -+ Copyright (C) 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Some insns set all condition code flags, some only set the Z and N flags, and -+ some only set the Z flag. */ -+ -+CC_MODE (CCW); -+CC_MODE (CCWZN); -+CC_MODE (CCWZ); -+CC_MODE (CCS); -+CC_MODE (CCSZN); -+CC_MODE (CCSZ); -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32-protos.h -@@ -0,0 +1,84 @@ -+/* Function prototypes for Ubicom IP3000. -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GNU CC. -+ -+ GNU CC is free software; you can redistribute it and/or modify it under -+ the terms of the GNU General Public License as published by the Free -+ Software Foundation; either version 2, or (at your option) any later -+ version. -+ -+ GNU CC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ for more details. -+ -+ You should have received a copy of the GNU General Public License along -+ with GNU CC; see the file COPYING. If not, write to the Free Software -+ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifdef RTX_CODE -+ -+#ifdef TREE_CODE -+extern void ubicom32_va_start (tree, rtx); -+#endif /* TREE_CODE */ -+ -+extern void ubicom32_print_operand (FILE *, rtx, int); -+extern void ubicom32_print_operand_address (FILE *, rtx); -+ -+extern void ubicom32_conditional_register_usage (void); -+extern enum reg_class ubicom32_preferred_reload_class (rtx, enum reg_class); -+extern int ubicom32_regno_ok_for_index_p (int, int); -+extern void ubicom32_expand_movsi (rtx *); -+extern void ubicom32_expand_addsi3 (rtx *); -+extern int ubicom32_emit_mult_sequence (rtx *); -+extern void ubicom32_emit_move_const_int (rtx, rtx); -+extern bool ubicom32_legitimate_constant_p (rtx); -+extern bool ubicom32_legitimate_address_p (enum machine_mode, rtx, int); -+extern rtx ubicom32_legitimize_address (rtx, rtx, enum machine_mode); -+extern rtx ubicom32_legitimize_reload_address (rtx, enum machine_mode, int, int); -+extern void ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1); -+extern int ubicom32_mode_dependent_address_p (rtx); -+extern void ubicom32_output_cond_jump (rtx, rtx, rtx); -+extern void ubicom32_expand_eh_return (rtx *); -+extern void ubicom32_expand_call_fdpic (rtx *); -+extern void ubicom32_expand_call_value_fdpic (rtx *); -+extern enum machine_mode ubicom32_select_cc_mode (RTX_CODE, rtx, rtx); -+extern rtx ubicom32_gen_compare_reg (RTX_CODE, rtx, rtx); -+extern int ubicom32_shiftable_const_int (int); -+#endif /* RTX_CODE */ -+ -+#ifdef TREE_CODE -+extern void init_cumulative_args (CUMULATIVE_ARGS *cum, -+ tree fntype, -+ struct rtx_def *libname, -+ int indirect); -+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *function_incoming_arg (CUMULATIVE_ARGS *, -+ enum machine_mode, -+ tree, int); -+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *, -+ enum machine_mode, tree, int); -+extern struct rtx_def *ubicom32_va_arg (tree, tree); -+extern int ubicom32_reg_parm_stack_space (tree); -+#endif /* TREE_CODE */ -+ -+extern struct rtx_def * ubicom32_builtin_saveregs (void); -+extern void asm_file_start (FILE *); -+extern void ubicom32_expand_prologue (void); -+extern void ubicom32_expand_epilogue (void); -+extern int ubicom32_initial_elimination_offset (int, int); -+extern int ubicom32_regno_ok_for_base_p (int, int); -+extern bool ubicom32_hard_regno_mode_ok (unsigned int, enum machine_mode); -+extern int ubicom32_can_use_return_insn_p (void); -+extern rtx ubicom32_return_addr_rtx (int, rtx); -+extern void ubicom32_optimization_options (int, int); -+extern void ubicom32_override_options (void); -+extern bool ubicom32_match_cc_mode (rtx, enum machine_mode); -+ -+extern int ubicom32_reorg_completed; -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.c -@@ -0,0 +1,2881 @@ -+/* Subroutines for insn-output.c for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "insn-flags.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "insn-codes.h" -+#include "flags.h" -+#include "recog.h" -+#include "expr.h" -+#include "function.h" -+#include "obstack.h" -+#include "toplev.h" -+#include "tm_p.h" -+#include "tm-constrs.h" -+#include "basic-block.h" -+#include "integrate.h" -+#include "target.h" -+#include "target-def.h" -+#include "reload.h" -+#include "df.h" -+#include "langhooks.h" -+#include "optabs.h" -+ -+static tree ubicom32_handle_fndecl_attribute (tree *, tree, tree, int, bool *); -+static void ubicom32_layout_frame (void); -+static void ubicom32_function_prologue (FILE *, HOST_WIDE_INT); -+static void ubicom32_function_epilogue (FILE *, HOST_WIDE_INT); -+static bool ubicom32_rtx_costs (rtx, int, int, int *, bool speed); -+static bool ubicom32_fixed_condition_code_regs (unsigned int *, -+ unsigned int *); -+static enum machine_mode ubicom32_cc_modes_compatible (enum machine_mode, -+ enum machine_mode); -+static int ubicom32_naked_function_p (void); -+static void ubicom32_machine_dependent_reorg (void); -+static bool ubicom32_assemble_integer (rtx, unsigned int, int); -+static void ubicom32_asm_init_sections (void); -+static int ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,tree, -+ bool); -+static bool ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+static bool ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED); -+ -+static bool ubicom32_return_in_memory (const_tree type, -+ const_tree fntype ATTRIBUTE_UNUSED); -+static bool ubicom32_is_base_reg (rtx, int); -+static void ubicom32_init_builtins (void); -+static rtx ubicom32_expand_builtin (tree, rtx, rtx, enum machine_mode, int); -+static tree ubicom32_fold_builtin (tree, tree, bool); -+static int ubicom32_get_valid_offset_mask (enum machine_mode); -+static bool ubicom32_cannot_force_const_mem (rtx); -+ -+/* Case values threshold */ -+int ubicom32_case_values_threshold = 6; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+int ubicom32_v3 = 1; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+int ubicom32_v4 = 1; -+ -+/* Valid attributes: -+ naked - don't generate function prologue/epilogue and `ret' command. */ -+const struct attribute_spec ubicom32_attribute_table[] = -+{ -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ { "naked", 0, 0, true, false, false, ubicom32_handle_fndecl_attribute }, -+ { NULL, 0, 0, false, false, false, NULL } -+}; -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE ubicom32_function_prologue -+ -+#undef TARGET_ASM_FUNCTION_EPILOGUE -+#define TARGET_ASM_FUNCTION_EPILOGUE ubicom32_function_epilogue -+ -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE ubicom32_attribute_table -+ -+/* All addresses cost the same amount. */ -+#undef TARGET_ADDRESS_COST -+#define TARGET_ADDRESS_COST hook_int_rtx_bool_0 -+ -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS ubicom32_rtx_costs -+ -+#undef TARGET_FIXED_CONDITION_CODE_REGS -+#define TARGET_FIXED_CONDITION_CODE_REGS ubicom32_fixed_condition_code_regs -+ -+#undef TARGET_CC_MODES_COMPATIBLE -+#define TARGET_CC_MODES_COMPATIBLE ubicom32_cc_modes_compatible -+ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG ubicom32_machine_dependent_reorg -+ -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER ubicom32_assemble_integer -+ -+#undef TARGET_ASM_INIT_SECTIONS -+#define TARGET_ASM_INIT_SECTIONS ubicom32_asm_init_sections -+ -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES ubicom32_arg_partial_bytes -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE ubicom32_pass_by_reference -+ -+#undef TARGET_CALLEE_COPIES -+#define TARGET_CALLEE_COPIES ubicom32_callee_copies -+ -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY ubicom32_return_in_memory -+ -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS ubicom32_init_builtins -+ -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN ubicom32_expand_builtin -+ -+#undef TARGET_FOLD_BUILTIN -+#define TARGET_FOLD_BUILTIN ubicom32_fold_builtin -+ -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM ubicom32_cannot_force_const_mem -+ -+struct gcc_target targetm = TARGET_INITIALIZER; -+ -+static char save_regs[FIRST_PSEUDO_REGISTER]; -+static int nregs; -+static int frame_size; -+int ubicom32_stack_size = 0; /* size of allocated stack (including frame) */ -+int ubicom32_can_use_calli_to_ret; -+ -+#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) -+#define ROUND_CALL_BLOCK_SIZE(BYTES) \ -+ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) -+ -+/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we -+ must report the mode of the memory reference from PRINT_OPERAND to -+ PRINT_OPERAND_ADDRESS. */ -+enum machine_mode output_memory_reference_mode; -+ -+/* Flag for some split insns from the ubicom32.md. */ -+int ubicom32_reorg_completed; -+ -+enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER] = -+{ -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ADDRESS_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ ACC_LO_REGS, -+ SOURCE3_REG, -+ ADDRESS_REGS, -+ NO_REGS, /* CC_REG must be NO_REGS */ -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS, -+ SPECIAL_REGS -+}; -+ -+rtx ubicom32_compare_op0; -+rtx ubicom32_compare_op1; -+ -+/* Handle command line option overrides. */ -+ -+void -+ubicom32_override_options (void) -+{ -+ flag_pic = 0; -+ -+ if (strcmp (ubicom32_arch_name, "ubicom32v1") == 0) { -+ /* If we have a version 1 architecture then we want to avoid using jump -+ tables. */ -+ ubicom32_case_values_threshold = 30000; -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v2") == 0) { -+ ubicom32_v3 = 0; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v3") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 0; -+ } else if (strcmp (ubicom32_arch_name, "ubicom32v4") == 0) { -+ ubicom32_v3 = 1; -+ ubicom32_v4 = 1; -+ } -+ -+ /* There is no single unaligned SI op for PIC code. Sometimes we -+ need to use ".4byte" and sometimes we need to use ".picptr". -+ See ubicom32_assemble_integer for details. */ -+ if (TARGET_FDPIC) -+ targetm.asm_out.unaligned_op.si = 0; -+} -+ -+void -+ubicom32_conditional_register_usage (void) -+{ -+ /* If we're using the old ipOS ABI we need to make D10 through D13 -+ caller-clobbered. */ -+ if (TARGET_IPOS_ABI) -+ { -+ call_used_regs[D10_REGNUM] = 1; -+ call_used_regs[D11_REGNUM] = 1; -+ call_used_regs[D12_REGNUM] = 1; -+ call_used_regs[D13_REGNUM] = 1; -+ } -+} -+ -+/* We have some number of optimizations that don't really work for the Ubicom32 -+ architecture so we deal with them here. */ -+ -+void -+ubicom32_optimization_options (int level ATTRIBUTE_UNUSED, -+ int size ATTRIBUTE_UNUSED) -+{ -+ /* The tree IVOPTs pass seems to do really bad things for the Ubicom32 -+ architecture - it tends to turn things that would happily use pre/post -+ increment/decrement into operations involving unecessary loop -+ indicies. */ -+ flag_ivopts = 0; -+ -+ /* We have problems where DSE at the RTL level misses partial stores -+ to the stack. For now we disable it to avoid this. */ -+ flag_dse = 0; -+} -+ -+/* Print operand X using operand code CODE to assembly language output file -+ FILE. */ -+ -+void -+ubicom32_print_operand (FILE *file, rtx x, int code) -+{ -+ switch (code) -+ { -+ case 'A': -+ /* Identify the correct accumulator to use. */ -+ if (REGNO (x) == ACC0_HI_REGNUM || REGNO (x) == ACC0_LO_REGNUM) -+ fprintf (file, "acc0"); -+ else if (REGNO (x) == ACC1_HI_REGNUM || REGNO (x) == ACC1_LO_REGNUM) -+ fprintf (file, "acc1"); -+ else -+ abort (); -+ break; -+ -+ case 'b': -+ case 'B': -+ { -+ enum machine_mode mode; -+ -+ mode = GET_MODE (XEXP (x, 0)); -+ -+ /* These are normal and reversed branches. */ -+ switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) -+ { -+ case NE: -+ fprintf (file, "ne"); -+ break; -+ -+ case EQ: -+ fprintf (file, "eq"); -+ break; -+ -+ case GE: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "pl"); -+ else -+ fprintf (file, "ge"); -+ break; -+ -+ case GT: -+ fprintf (file, "gt"); -+ break; -+ -+ case LE: -+ fprintf (file, "le"); -+ break; -+ -+ case LT: -+ if (mode == CCSZNmode || mode == CCWZNmode) -+ fprintf (file, "mi"); -+ else -+ fprintf (file, "lt"); -+ break; -+ -+ case GEU: -+ fprintf (file, "cs"); -+ break; -+ -+ case GTU: -+ fprintf (file, "hi"); -+ break; -+ -+ case LEU: -+ fprintf (file, "ls"); -+ break; -+ -+ case LTU: -+ fprintf (file, "cc"); -+ break; -+ -+ default: -+ abort (); -+ } -+ } -+ break; -+ -+ case 'C': -+ /* This is used for the operand to a call instruction; -+ if it's a REG, enclose it in parens, else output -+ the operand normally. */ -+ if (REG_P (x)) -+ { -+ fputc ('(', file); -+ ubicom32_print_operand (file, x, 0); -+ fputc (')', file); -+ } -+ else -+ ubicom32_print_operand (file, x, 0); -+ break; -+ -+ case 'd': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (INTVAL (x))); -+ break; -+ -+ case 'D': -+ /* Bit operations we need bit numbers. */ -+ fprintf (file, "%d", exact_log2 (~ INTVAL (x))); -+ break; -+ -+ case 'E': -+ /* For lea, which we use to add address registers. -+ We don't want the '#' on a constant. */ -+ if (CONST_INT_P (x)) -+ { -+ fprintf (file, "%ld", INTVAL (x)); -+ break; -+ } -+ /* FALL THROUGH */ -+ -+ default: -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ output_memory_reference_mode = GET_MODE (x); -+ output_address (XEXP (x, 0)); -+ break; -+ -+ case PLUS: -+ output_address (x); -+ break; -+ -+ case REG: -+ fprintf (file, "%s", reg_names[REGNO (x)]); -+ break; -+ -+ case SUBREG: -+ fprintf (file, "%s", reg_names[subreg_regno (x)]); -+ break; -+ -+ /* This will only be single precision.... */ -+ case CONST_DOUBLE: -+ { -+ unsigned long val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ fprintf (file, "0x%lx", val); -+ break; -+ } -+ -+ case CONST_INT: -+ case SYMBOL_REF: -+ case CONST: -+ case LABEL_REF: -+ case CODE_LABEL: -+ case LO_SUM: -+ ubicom32_print_operand_address (file, x); -+ break; -+ -+ case HIGH: -+ fprintf (file, "#%%hi("); -+ ubicom32_print_operand_address (file, XEXP (x, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC: -+ switch (XINT (x, 1)) -+ { -+ case UNSPEC_FDPIC_GOT: -+ fprintf (file, "#%%got_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ case UNSPEC_FDPIC_GOT_FUNCDESC: -+ fprintf (file, "#%%got_funcdesc_lo("); -+ ubicom32_print_operand_address (file, XVECEXP (x, 0, 0)); -+ fprintf (file, ")"); -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ -+ default: -+ abort (); -+ } -+ break; -+ } -+} -+ -+/* Output assembly language output for the address ADDR to FILE. */ -+ -+void -+ubicom32_print_operand_address (FILE *file, rtx addr) -+{ -+ switch (GET_CODE (addr)) -+ { -+ case POST_INC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_INC: -+ fprintf (file, "%d", GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_DEC: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%d++", -GET_MODE_SIZE (output_memory_reference_mode)); -+ break; -+ -+ case PRE_DEC: -+ fprintf (file, "%d", -GET_MODE_SIZE (output_memory_reference_mode)); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case POST_MODIFY: -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "%ld++", INTVAL (XEXP (XEXP (addr,1), 1))); -+ break; -+ -+ case PRE_MODIFY: -+ fprintf (file, "%ld", INTVAL (XEXP (XEXP (addr,1), 1))); -+ ubicom32_print_operand_address (file, XEXP (addr, 0)); -+ fprintf (file, "++"); -+ break; -+ -+ case REG: -+ fputc ('(', file); -+ fprintf (file, "%s", reg_names[REGNO (addr)]); -+ fputc (')', file); -+ break; -+ -+ case PLUS: -+ { -+ rtx base = XEXP (addr, 0); -+ rtx index = XEXP (addr, 1); -+ -+ /* Switch around addresses of the form index * scaling + base. */ -+ if (! ubicom32_is_base_reg (base, 1)) -+ { -+ rtx tmp = base; -+ base = index; -+ index = tmp; -+ } -+ -+ if (CONST_INT_P (index)) -+ { -+ fprintf (file, "%ld", INTVAL (index)); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ } -+ else if (GET_CODE (index) == MULT -+ || REG_P (index)) -+ { -+ if (GET_CODE (index) == MULT) -+ index = XEXP (index, 0); -+ fputc ('(', file); -+ fputs (reg_names[REGNO (base)], file); -+ fputc (',', file); -+ fputs (reg_names[REGNO (index)], file); -+ } -+ else -+ abort (); -+ -+ fputc (')', file); -+ break; -+ } -+ -+ case LO_SUM: -+ fprintf (file, "%%lo("); -+ ubicom32_print_operand (file, XEXP (addr, 1), 'L'); -+ fprintf (file, ")("); -+ ubicom32_print_operand (file, XEXP (addr, 0), 0); -+ fprintf (file, ")"); -+ break; -+ -+ case CONST_INT: -+ fputc ('#', file); -+ output_addr_const (file, addr); -+ break; -+ -+ default: -+ output_addr_const (file, addr); -+ break; -+ } -+} -+ -+/* X and Y are two things to compare using CODE. Emit the compare insn and -+ return the rtx for the cc reg in the proper mode. */ -+ -+rtx -+ubicom32_gen_compare_reg (enum rtx_code code, rtx x, rtx y) -+{ -+ enum machine_mode mode = SELECT_CC_MODE (code, x, y); -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (mode, CC_REGNUM); -+ -+ emit_insn (gen_rtx_SET (VOIDmode, cc_reg, -+ gen_rtx_COMPARE (mode, x, y))); -+ -+ return cc_reg; -+} -+ -+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, -+ return the mode to be used for the comparison. */ -+ -+enum machine_mode -+ubicom32_select_cc_mode (enum rtx_code op, rtx x, rtx y) -+{ -+ /* Is this a short compare? */ -+ if (GET_MODE (x) == QImode -+ || GET_MODE (x) == HImode -+ || GET_MODE (y) == QImode -+ || GET_MODE (y) == HImode) -+ { -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCSZmode; -+ -+ case GE: -+ case LT: -+ if (y == const0_rtx) -+ return CCSZNmode; -+ -+ default : -+ return CCSmode; -+ } -+ } -+ -+ /* We have a word compare. */ -+ switch (op) -+ { -+ case EQ : -+ case NE : -+ return CCWZmode; -+ -+ case GE : -+ case LT : -+ if (y == const0_rtx) -+ return CCWZNmode; -+ -+ default : -+ return CCWmode; -+ } -+} -+ -+/* Return TRUE or FALSE depending on whether the first SET in INSN -+ has source and destination with matching CC modes, and that the -+ CC mode is at least as constrained as REQ_MODE. */ -+bool -+ubicom32_match_cc_mode (rtx insn, enum machine_mode req_mode) -+{ -+ rtx set; -+ enum machine_mode set_mode; -+ -+ set = PATTERN (insn); -+ if (GET_CODE (set) == PARALLEL) -+ set = XVECEXP (set, 0, 0); -+ gcc_assert (GET_CODE (set) == SET); -+ gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); -+ -+ /* SET_MODE is the mode we have in the instruction. This must either -+ be the same or less restrictive that the required mode REQ_MODE. */ -+ set_mode = GET_MODE (SET_DEST (set)); -+ -+ switch (req_mode) -+ { -+ case CCSZmode: -+ if (set_mode != CCSZmode) -+ return 0; -+ break; -+ -+ case CCSZNmode: -+ if (set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCSmode: -+ if (set_mode != CCSmode -+ && set_mode != CCSZmode -+ && set_mode != CCSZNmode) -+ return 0; -+ break; -+ -+ case CCWZmode: -+ if (set_mode != CCWZmode) -+ return 0; -+ break; -+ -+ case CCWZNmode: -+ if (set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ case CCWmode: -+ if (set_mode != CCWmode -+ && set_mode != CCWZmode -+ && set_mode != CCWZNmode) -+ return 0; -+ break; -+ -+ default: -+ gcc_unreachable (); -+ } -+ -+ return (GET_MODE (SET_SRC (set)) == set_mode); -+} -+ -+/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one -+ that we can implement more efficiently. */ -+ -+void -+ubicom32_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) -+{ -+ /* If we have a REG and a MEM then compare the MEM with the REG and not -+ the other way round. */ -+ if (REG_P (*op0) && MEM_P (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+ -+ /* If we have a REG and a CONST_INT then we may want to reverse things -+ if the constant can be represented as an "I" constraint. */ -+ if (REG_P (*op0) && CONST_INT_P (*op1) && satisfies_constraint_I (*op1)) -+ { -+ rtx tem = *op0; -+ *op0 = *op1; -+ *op1 = tem; -+ *code = swap_condition (*code); -+ return; -+ } -+} -+ -+/* Return the fixed registers used for condition codes. */ -+ -+static bool -+ubicom32_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) -+{ -+ *p1 = CC_REGNUM; -+ *p2 = INVALID_REGNUM; -+ -+ return true; -+} -+ -+/* If two condition code modes are compatible, return a condition code -+ mode which is compatible with both. Otherwise, return -+ VOIDmode. */ -+ -+static enum machine_mode -+ubicom32_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) -+{ -+ if (m1 == m2) -+ return m1; -+ -+ if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC) -+ return VOIDmode; -+ -+ switch (m1) -+ { -+ case CCWmode: -+ if (m2 == CCWZNmode || m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZNmode: -+ if (m2 == CCWmode) -+ return m2; -+ -+ if (m2 == CCWZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCWZmode: -+ if (m2 == CCWmode || m2 == CCWZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ case CCSmode: -+ if (m2 == CCSZNmode || m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZNmode: -+ if (m2 == CCSmode) -+ return m2; -+ -+ if (m2 == CCSZmode) -+ return m1; -+ -+ return VOIDmode; -+ -+ case CCSZmode: -+ if (m2 == CCSmode || m2 == CCSZNmode) -+ return m2; -+ -+ return VOIDmode; -+ -+ default: -+ gcc_unreachable (); -+ } -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address_symbol (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ int unspec; -+ rtx got_offs; -+ rtx got_offs_scaled; -+ rtx plus_scaled; -+ rtx tmp; -+ rtx new_rtx; -+ -+ gcc_assert (reg != 0); -+ -+ if (GET_CODE (orig) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (orig)) -+ unspec = UNSPEC_FDPIC_GOT_FUNCDESC; -+ else -+ unspec = UNSPEC_FDPIC_GOT; -+ -+ got_offs = gen_reg_rtx (SImode); -+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig), unspec); -+ emit_move_insn (got_offs, tmp); -+ -+ got_offs_scaled = gen_rtx_MULT (SImode, got_offs, GEN_INT (4)); -+ plus_scaled = gen_rtx_PLUS (Pmode, fdpic_reg, got_offs_scaled); -+ new_rtx = gen_const_mem (Pmode, plus_scaled); -+ emit_move_insn (reg, new_rtx); -+ -+ return reg; -+} -+ -+static rtx -+ubicom32_legitimize_fdpic_address (rtx orig, rtx reg, rtx fdpic_reg) -+{ -+ rtx addr = orig; -+ rtx new_rtx = orig; -+ -+ if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) -+ { -+ rtx base; -+ -+ if (GET_CODE (addr) == CONST) -+ { -+ addr = XEXP (addr, 0); -+ gcc_assert (GET_CODE (addr) == PLUS); -+ } -+ -+ base = ubicom32_legitimize_fdpic_address_symbol (XEXP (addr, 0), reg, fdpic_reg); -+ return gen_rtx_PLUS (Pmode, base, XEXP (addr, 1)); -+ } -+ -+ return new_rtx; -+} -+ -+/* Code generation. */ -+ -+void -+ubicom32_expand_movsi (rtx *operands) -+{ -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || (GET_CODE (operands[1]) == CONST -+ && GET_CODE (XEXP (operands[1], 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (operands[1])) -+ { -+ if (TARGET_FDPIC) -+ { -+ rtx tmp; -+ rtx fdpic_reg; -+ -+ gcc_assert (can_create_pseudo_p ()); -+ tmp = gen_reg_rtx (Pmode); -+ fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ if (GET_CODE (operands[1]) == SYMBOL_REF -+ || GET_CODE (operands[1]) == LABEL_REF) -+ operands[1] = ubicom32_legitimize_fdpic_address_symbol (operands[1], tmp, fdpic_reg); -+ else -+ operands[1] = ubicom32_legitimize_fdpic_address (operands[1], tmp, fdpic_reg); -+ } -+ else -+ { -+ rtx tmp; -+ enum machine_mode mode; -+ -+ /* We want to avoid reusing operand 0 if we can because it limits -+ our ability to optimize later. */ -+ tmp = ! can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); -+ -+ mode = GET_MODE (operands[0]); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, -+ gen_rtx_HIGH (mode, operands[1]))); -+ operands[1] = gen_rtx_LO_SUM (mode, tmp, operands[1]); -+ if (can_create_pseudo_p() && ! REG_P (operands[0])) -+ { -+ tmp = gen_reg_rtx (mode); -+ emit_insn (gen_rtx_SET (VOIDmode, tmp, operands[1])); -+ operands[1] = tmp; -+ } -+ } -+ } -+} -+ -+/* Emit code for addsi3. */ -+ -+void -+ubicom32_expand_addsi3 (rtx *operands) -+{ -+ rtx op, clob; -+ -+ if (can_create_pseudo_p ()) -+ { -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ -+ /* Emit the instruction. */ -+ -+ op = gen_rtx_SET (VOIDmode, operands[0], -+ gen_rtx_PLUS (SImode, operands[1], operands[2])); -+ -+ if (! can_create_pseudo_p ()) -+ { -+ /* Reload doesn't know about the flags register, and doesn't know that -+ it doesn't want to clobber it. We can only do this with PLUS. */ -+ emit_insn (op); -+ } -+ else -+ { -+ clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); -+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); -+ } -+} -+ -+/* Emit code for mulsi3. Return 1 if we have generated all the code -+ necessary to do the multiplication. */ -+ -+int -+ubicom32_emit_mult_sequence (rtx *operands) -+{ -+ if (! ubicom32_v4) -+ { -+ rtx a1, a1_1, a2; -+ rtx b1, b1_1, b2; -+ rtx mac_lo_rtx; -+ rtx t1, t2, t3; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ /* Synthesize 32-bit multiplication using 16-bit operations: -+ -+ a1 = highpart (a) -+ a2 = lowpart (a) -+ -+ b1 = highpart (b) -+ b2 = lowpart (b) -+ -+ c = (a1 * b1) << 32 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ = 0 + (a1 * b2) << 16 + (a2 * b1) << 16 + a2 * b2 -+ ^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^ ^^^^^^^ -+ Signed Signed Unsigned */ -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ /* a1 = highpart (a) */ -+ a1 = gen_reg_rtx (HImode); -+ a1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (a1_1, operands[1], GEN_INT (16))); -+ emit_move_insn (a1, gen_lowpart (HImode, a1_1)); -+ -+ /* a2 = lowpart (a) */ -+ a2 = gen_reg_rtx (HImode); -+ emit_move_insn (a2, gen_lowpart (HImode, operands[1])); -+ -+ /* b1 = highpart (b) */ -+ b1 = gen_reg_rtx (HImode); -+ b1_1 = gen_reg_rtx (SImode); -+ emit_insn (gen_ashrsi3 (b1_1, operands[2], GEN_INT (16))); -+ emit_move_insn (b1, gen_lowpart (HImode, b1_1)); -+ -+ /* b2 = lowpart (b) */ -+ b2 = gen_reg_rtx (HImode); -+ emit_move_insn (b2, gen_lowpart (HImode, operands[2])); -+ -+ /* t1 = (a1 * b2) << 16 */ -+ t1 = gen_reg_rtx (SImode); -+ mac_lo_rtx = gen_rtx_REG (SImode, ACC0_LO_REGNUM); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a1, b2)); -+ emit_insn (gen_ashlsi3 (t1, mac_lo_rtx, GEN_INT (16))); -+ -+ /* t2 = (a2 * b1) << 16 */ -+ t2 = gen_reg_rtx (SImode); -+ emit_insn (gen_mulhisi3 (mac_lo_rtx, a2, b1)); -+ emit_insn (gen_ashlsi3 (t2, mac_lo_rtx, GEN_INT (16))); -+ -+ /* mac_lo = a2 * b2 */ -+ emit_insn (gen_umulhisi3 (mac_lo_rtx, a2, b2)); -+ -+ /* t3 = t1 + t2 */ -+ t3 = gen_reg_rtx (SImode); -+ emit_insn (gen_addsi3 (t3, t1, t2)); -+ -+ /* c = t3 + mac_lo_rtx */ -+ emit_insn (gen_addsi3 (operands[0], mac_lo_rtx, t3)); -+ -+ return 1; -+ } -+ else -+ { -+ rtx acc_rtx; -+ -+ /* Give up if we cannot create new pseudos. */ -+ if (!can_create_pseudo_p()) -+ return 0; -+ -+ if (!ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ rtx op1; -+ -+ op1 = gen_reg_rtx (SImode); -+ emit_move_insn (op1, operands[1]); -+ operands[1] = op1; -+ } -+ -+ if (!ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ { -+ rtx op2; -+ -+ op2 = gen_reg_rtx (SImode); -+ emit_move_insn (op2, operands[2]); -+ operands[2] = op2; -+ } -+ -+ acc_rtx = gen_reg_rtx (DImode); -+ emit_insn (gen_umulsidi3 (acc_rtx, operands[1], operands[2])); -+ emit_move_insn (operands[0], gen_lowpart (SImode, acc_rtx)); -+ -+ return 1; -+ } -+} -+ -+/* Move the integer value VAL into OPERANDS[0]. */ -+ -+void -+ubicom32_emit_move_const_int (rtx dest, rtx imm) -+{ -+ rtx xoperands[2]; -+ -+ xoperands[0] = dest; -+ xoperands[1] = imm; -+ -+ /* Treat mem destinations separately. Values must be explicitly sign -+ extended. */ -+ if (MEM_P (dest)) -+ { -+ rtx low_hword_mem; -+ rtx low_hword_addr; -+ -+ /* Emit shorter sequence for signed 7-bit quantities. */ -+ if (satisfies_constraint_I (imm)) -+ { -+ output_asm_insn ("move.4\t%0, %1", xoperands); -+ return; -+ } -+ -+ /* Special case for pushing constants. */ -+ if (GET_CODE (XEXP (dest, 0)) == PRE_DEC -+ && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* See if we can add 2 to the original address. This is only -+ possible if the original address is of the form REG or -+ REG+const. */ -+ low_hword_addr = plus_constant (XEXP (dest, 0), 2); -+ if (ubicom32_legitimate_address_p (HImode, low_hword_addr, 1)) -+ { -+ low_hword_mem = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (low_hword_mem, dest); -+ output_asm_insn ("movei\t%0, #%%hi(%E1)", xoperands); -+ xoperands[0] = low_hword_mem; -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ return; -+ } -+ -+ /* The original address is too complex. We need to use a -+ scratch memory by (sp) and move that to the original -+ destination. */ -+ if (! reg_mentioned_p (stack_pointer_rtx, dest)) -+ { -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+ return; -+ } -+ -+ /* Our address mentions the stack pointer so we need to -+ use our scratch data register here as well as scratch -+ memory. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\td15, (sp)4++", xoperands); -+ output_asm_insn ("move.4\t%0, d15", xoperands); -+ return; -+ } -+ -+ /* Move into registers are zero extended by default. */ -+ if (! REG_P (dest)) -+ abort (); -+ -+ if (satisfies_constraint_N (imm)) -+ { -+ output_asm_insn ("movei\t%0, %1", xoperands); -+ return; -+ } -+ -+ if (INTVAL (xoperands[1]) >= 0xff80 -+ && INTVAL (xoperands[1]) < 0x10000) -+ { -+ xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 0x10000); -+ output_asm_insn ("move.2\t%0, %1", xoperands); -+ return; -+ } -+ -+ if ((REGNO_REG_CLASS (REGNO (xoperands[0])) == ADDRESS_REGS -+ || REGNO_REG_CLASS (REGNO (xoperands[0])) == FDPIC_REG) -+ && ((INTVAL (xoperands[1]) & 0x80000000) == 0)) -+ { -+ output_asm_insn ("moveai\t%0, #%%hi(%E1)", xoperands); -+ if ((INTVAL (xoperands[1]) & 0x7f) != 0) -+ output_asm_insn ("lea.1\t%0, %%lo(%E1)(%0)", xoperands); -+ return; -+ } -+ -+ if ((INTVAL (xoperands[1]) & 0xffff0000) == 0) -+ { -+ output_asm_insn ("movei\t%0, #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.2\t%0, %0", xoperands); -+ return; -+ } -+ -+ /* This is very expensive. The constant is so large that we -+ need to use the stack to do the load. */ -+ output_asm_insn ("movei\t-4(sp)++, #%%hi(%E1)", xoperands); -+ output_asm_insn ("movei\t2(sp), #%%lo(%E1)", xoperands); -+ output_asm_insn ("move.4\t%0, (sp)4++", xoperands); -+} -+ -+/* Stack layout. Prologue/Epilogue. */ -+ -+static int save_regs_size; -+ -+static void -+ubicom32_layout_frame (void) -+{ -+ int regno; -+ -+ memset ((char *) &save_regs[0], 0, sizeof (save_regs)); -+ nregs = 0; -+ frame_size = get_frame_size (); -+ -+ if (frame_pointer_needed || df_regs_ever_live_p (FRAME_POINTER_REGNUM)) -+ { -+ save_regs[FRAME_POINTER_REGNUM] = 1; -+ ++nregs; -+ } -+ -+ if (current_function_is_leaf && ! df_regs_ever_live_p (LINK_REGNO)) -+ ubicom32_can_use_calli_to_ret = 1; -+ else -+ { -+ ubicom32_can_use_calli_to_ret = 0; -+ save_regs[LINK_REGNO] = 1; -+ ++nregs; -+ } -+ -+ /* Figure out which register(s) needs to be saved. */ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; regno++) -+ if (df_regs_ever_live_p(regno) -+ && ! call_used_regs[regno] -+ && ! fixed_regs[regno] -+ && ! save_regs[regno]) -+ { -+ save_regs[regno] = 1; -+ ++nregs; -+ } -+ -+ save_regs_size = 4 * nregs; -+} -+ -+static void -+ubicom32_emit_add_movsi (int regno, int adj) -+{ -+ rtx x; -+ rtx reg = gen_rtx_REG (SImode, regno); -+ -+ adj += 4; -+ if (adj > 8 * 4) -+ { -+ x = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ RTX_FRAME_RELATED_P (x) = 1; -+ x = emit_move_insn (gen_rtx_MEM (SImode, stack_pointer_rtx), reg); -+ } -+ else -+ { -+ rtx addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, -+ gen_rtx_PLUS (Pmode, stack_pointer_rtx, -+ GEN_INT (-adj))); -+ x = emit_move_insn (gen_rtx_MEM (SImode, addr), reg); -+ } -+ RTX_FRAME_RELATED_P (x) = 1; -+} -+ -+void -+ubicom32_expand_prologue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ -+ if (ubicom32_naked_function_p ()) -+ return; -+ -+ ubicom32_builtin_saveregs (); -+ -+ ubicom32_layout_frame (); -+ adj = (outgoing_args_size + get_frame_size () + save_regs_size -+ + crtl->args.pretend_args_size); -+ -+ if (!adj) -+ ; -+ else if (outgoing_args_size + save_regs_size < 508 -+ && get_frame_size () + save_regs_size > 508) -+ { -+ int i = 0; -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ ++i; -+ } -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, -+ gen_rtx_PLUS (Pmode, -+ stack_pointer_rtx, -+ GEN_INT (i * 4 + outgoing_args_size))); -+ x = emit_move_insn (x, gen_rtx_REG (SImode, LINK_REGNO)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ else -+ { -+ int regno; -+ int adj = get_frame_size () + crtl->args.pretend_args_size; -+ int i = 0; -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ ubicom32_emit_add_movsi (LINK_REGNO, adj); -+ ++i; -+ } -+ -+ for (regno = 0; regno <= LAST_ADDRESS_REGNUM; ++regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ if (i) -+ { -+ rtx mem = gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (Pmode, -+ stack_pointer_rtx)); -+ x = emit_move_insn (mem, gen_rtx_REG (SImode, regno)); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ else -+ ubicom32_emit_add_movsi (regno, adj); -+ ++i; -+ } -+ -+ if (outgoing_args_size || (!i && adj)) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (-outgoing_args_size - (i ? 0 : adj))); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+ } -+ -+ if (frame_pointer_needed) -+ { -+ int fp_adj = save_regs_size + outgoing_args_size; -+ x = gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (fp_adj)); -+ x = emit_insn (x); -+ RTX_FRAME_RELATED_P (x) = 1; -+ } -+} -+ -+void -+ubicom32_expand_epilogue (void) -+{ -+ rtx x; -+ int regno; -+ int outgoing_args_size = crtl->outgoing_args_size; -+ int adj; -+ int i; -+ -+ if (ubicom32_naked_function_p ()) -+ { -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, -+ LINK_REGNO))); -+ return; -+ } -+ -+ if (cfun->calls_alloca) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, -+ GEN_INT (-save_regs_size)); -+ emit_insn (x); -+ outgoing_args_size = 0; -+ } -+ -+ if (outgoing_args_size) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (outgoing_args_size)); -+ emit_insn (x); -+ } -+ -+ i = 0; -+ for (regno = LAST_ADDRESS_REGNUM; regno >= 0; --regno) -+ if (save_regs[regno] && regno != LINK_REGNO) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, regno), x); -+ ++i; -+ } -+ -+ /* Do we have to adjust the stack after we've finished restoring regs? */ -+ adj = get_frame_size() + crtl->args.pretend_args_size; -+ if (cfun->stdarg) -+ adj += UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+#if 0 -+ if (crtl->calls_eh_return && 0) -+ { -+ if (save_regs[LINK_REGNO]) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ } -+ -+ /* Perform the additional bump for __throw. */ -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ EH_RETURN_STACKADJ_RTX)); -+ emit_jump_insn (gen_eh_return_internal ()); -+ return; -+ } -+#endif -+ -+ if (save_regs[LINK_REGNO]) -+ { -+ if (adj >= 4 && adj <= (6 * 4)) -+ { -+ x = GEN_INT (adj + 4); -+ emit_jump_insn (gen_return_from_post_modify_sp (x)); -+ return; -+ } -+ -+ if (adj == 0) -+ { -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_jump_insn (gen_return_internal (x)); -+ return; -+ } -+ -+ x = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); -+ emit_move_insn (gen_rtx_REG (SImode, LINK_REGNO), x); -+ } -+ -+ if (adj) -+ { -+ x = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ GEN_INT (adj)); -+ x = emit_insn (x); -+ adj = 0; -+ } -+ -+ /* Given that we've just done all the hard work here we may as well use -+ a calli to return. */ -+ ubicom32_can_use_calli_to_ret = 1; -+ emit_jump_insn (gen_return_internal (gen_rtx_REG (SImode, LINK_REGNO))); -+} -+ -+void -+ubicom32_expand_call_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[0], 0); -+ -+ c = gen_call_fdpic (addr, operands[1], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_call_value_fdpic (rtx *operands) -+{ -+ rtx c; -+ rtx addr; -+ rtx fdpic_reg = get_hard_reg_initial_val (SImode, FDPIC_REGNUM); -+ -+ addr = XEXP (operands[1], 0); -+ -+ c = gen_call_value_fdpic (operands[0], addr, operands[2], fdpic_reg); -+ emit_call_insn (c); -+} -+ -+void -+ubicom32_expand_eh_return (rtx *operands) -+{ -+ if (REG_P (operands[0]) -+ || REGNO (operands[0]) != EH_RETURN_STACKADJ_REGNO) -+ { -+ rtx sp = EH_RETURN_STACKADJ_RTX; -+ emit_move_insn (sp, operands[0]); -+ operands[0] = sp; -+ } -+ -+ if (REG_P (operands[1]) -+ || REGNO (operands[1]) != EH_RETURN_HANDLER_REGNO) -+ { -+ rtx ra = EH_RETURN_HANDLER_RTX; -+ emit_move_insn (ra, operands[1]); -+ operands[1] = ra; -+ } -+} -+ -+/* Compute the offsets between eliminable registers. */ -+ -+int -+ubicom32_initial_elimination_offset (int from, int to) -+{ -+ ubicom32_layout_frame (); -+ if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return save_regs_size + crtl->outgoing_args_size; -+ -+ if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) -+ return get_frame_size ()/* + save_regs_size */; -+ -+ if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) -+ return get_frame_size () -+ + crtl->outgoing_args_size -+ + save_regs_size; -+ -+ return 0; -+} -+ -+/* Return 1 if it is appropriate to emit `ret' instructions in the -+ body of a function. Do this only if the epilogue is simple, needing a -+ couple of insns. Prior to reloading, we can't tell how many registers -+ must be saved, so return 0 then. Return 0 if there is no frame -+ marker to de-allocate. -+ -+ If NON_SAVING_SETJMP is defined and true, then it is not possible -+ for the epilogue to be simple, so return 0. This is a special case -+ since NON_SAVING_SETJMP will not cause regs_ever_live to change -+ until final, but jump_optimize may need to know sooner if a -+ `return' is OK. */ -+ -+int -+ubicom32_can_use_return_insn_p (void) -+{ -+ if (! reload_completed || frame_pointer_needed) -+ return 0; -+ -+ return 1; -+} -+ -+/* Attributes and CC handling. */ -+ -+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in -+ struct attribute_spec.handler. */ -+static tree -+ubicom32_handle_fndecl_attribute (tree *node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, -+ bool *no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning ("'%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } -+ -+ return NULL_TREE; -+} -+ -+/* A C expression that places additional restrictions on the register class to -+ use when it is necessary to copy value X into a register in class CLASS. -+ The value is a register class; perhaps CLASS, or perhaps another, smaller -+ class. On many machines, the following definition is safe: -+ -+ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS -+ -+ Sometimes returning a more restrictive class makes better code. For -+ example, on the 68000, when X is an integer constant that is in range for a -+ `moveq' instruction, the value of this macro is always `DATA_REGS' as long -+ as CLASS includes the data registers. Requiring a data register guarantees -+ that a `moveq' will be used. -+ -+ If X is a `const_double', by returning `NO_REGS' you can force X into a -+ memory constant. This is useful on certain machines where immediate -+ floating values cannot be loaded into certain kinds of registers. */ -+ -+enum reg_class -+ubicom32_preferred_reload_class (rtx x, enum reg_class class) -+{ -+ /* If a symbolic constant, HIGH or a PLUS is reloaded, -+ it is most likely being used as an address, so -+ prefer ADDRESS_REGS. If 'class' is not a superset -+ of ADDRESS_REGS, e.g. DATA_REGS, then reject this reload. */ -+ if (GET_CODE (x) == PLUS -+ || GET_CODE (x) == HIGH -+ || GET_CODE (x) == LABEL_REF -+ || GET_CODE (x) == SYMBOL_REF -+ || GET_CODE (x) == CONST) -+ { -+ if (reg_class_subset_p (ALL_ADDRESS_REGS, class)) -+ return ALL_ADDRESS_REGS; -+ -+ return NO_REGS; -+ } -+ -+ return class; -+} -+ -+/* Function arguments and varargs. */ -+ -+int -+ubicom32_reg_parm_stack_space (tree fndecl) -+{ -+ return 0; -+ -+ if (fndecl -+ && TYPE_ARG_TYPES (TREE_TYPE (fndecl)) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (fndecl)))) -+ != void_type_node)) -+ return UBICOM32_FUNCTION_ARG_REGS * UNITS_PER_WORD; -+ -+ return 0; -+} -+ -+/* Flush the argument registers to the stack for a stdarg function; -+ return the new argument pointer. */ -+ -+rtx -+ubicom32_builtin_saveregs (void) -+{ -+ int regno; -+ -+ if (! cfun->stdarg) -+ return 0; -+ -+ for (regno = UBICOM32_FUNCTION_ARG_REGS - 1; regno >= 0; --regno) -+ emit_move_insn (gen_rtx_MEM (SImode, -+ gen_rtx_PRE_DEC (SImode, -+ stack_pointer_rtx)), -+ gen_rtx_REG (SImode, regno)); -+ -+ return stack_pointer_rtx; -+} -+ -+void -+ubicom32_va_start (tree valist, rtx nextarg) -+{ -+ std_expand_builtin_va_start (valist, nextarg); -+} -+ -+rtx -+ubicom32_va_arg (tree valist, tree type) -+{ -+ HOST_WIDE_INT size, rsize; -+ tree addr, incr, tmp; -+ rtx addr_rtx; -+ int indirect = 0; -+ -+ /* Round up sizeof(type) to a word. */ -+ size = int_size_in_bytes (type); -+ rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; -+ -+ /* Large types are passed by reference. */ -+ if (size > 8) -+ { -+ indirect = 1; -+ size = rsize = UNITS_PER_WORD; -+ } -+ -+ incr = valist; -+ addr = incr = save_expr (incr); -+ -+ /* FIXME Nat's version - is it correct? */ -+ tmp = fold_convert (ptr_type_node, size_int (rsize)); -+ tmp = build2 (PLUS_EXPR, ptr_type_node, incr, tmp); -+ incr = fold (tmp); -+ -+ /* FIXME Nat's version - is it correct? */ -+ incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); -+ -+ TREE_SIDE_EFFECTS (incr) = 1; -+ expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); -+ -+ addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); -+ -+ if (size < UNITS_PER_WORD) -+ emit_insn (gen_addsi3 (addr_rtx, addr_rtx, -+ GEN_INT (UNITS_PER_WORD - size))); -+ -+ if (indirect) -+ { -+ addr_rtx = force_reg (Pmode, addr_rtx); -+ addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); -+ set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); -+ } -+ -+ return addr_rtx; -+} -+ -+void -+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, -+ int indirect ATTRIBUTE_UNUSED) -+{ -+ cum->nbytes = 0; -+ -+ if (!libname) -+ { -+ cum->stdarg = (TYPE_ARG_TYPES (fntype) != 0 -+ && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) -+ != void_type_node)); -+ } -+} -+ -+/* Return an RTX to represent where a value in mode MODE will be passed -+ to a function. If the result is 0, the argument will be pushed. */ -+ -+rtx -+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ rtx result = 0; -+ int size, align; -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* Figure out the alignment of the object to be passed. */ -+ align = size; -+ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ /* Don't pass this arg via a register if all the argument registers -+ are used up. */ -+ if (cum->nbytes >= nregs * UNITS_PER_WORD) -+ return 0; -+ -+ /* Don't pass this arg via a register if it would be split between -+ registers and memory. */ -+ result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); -+ -+ return result; -+} -+ -+rtx -+function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, -+ int named ATTRIBUTE_UNUSED) -+{ -+ if (cfun->stdarg) -+ return 0; -+ -+ return function_arg (cum, mode, type, named); -+} -+ -+ -+/* Implement hook TARGET_ARG_PARTIAL_BYTES. -+ -+ Returns the number of bytes at the beginning of an argument that -+ must be put in registers. The value must be zero for arguments -+ that are passed entirely in registers or that are entirely pushed -+ on the stack. */ -+static int -+ubicom32_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ int size, diff; -+ -+ int nregs = UBICOM32_FUNCTION_ARG_REGS; -+ -+ /* round up to full word */ -+ cum->nbytes = (cum->nbytes + 3) & ~3; -+ -+ if (targetm.calls.pass_by_reference (cum, mode, type, named)) -+ return 0; -+ -+ /* number of bytes left in registers */ -+ diff = nregs*UNITS_PER_WORD - cum->nbytes; -+ -+ /* regs all used up */ -+ if (diff <= 0) -+ return 0; -+ -+ /* Figure out the size of the object to be passed. */ -+ if (mode == BLKmode) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ /* enough space left in regs for size */ -+ if (size <= diff) -+ return 0; -+ -+ /* put diff bytes in regs and rest on stack */ -+ return diff; -+ -+} -+ -+static bool -+ubicom32_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_callee_copies (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, -+ enum machine_mode mode, const_tree type, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ int size; -+ -+ if (type) -+ size = int_size_in_bytes (type); -+ else -+ size = GET_MODE_SIZE (mode); -+ -+ return size <= 0 || size > 8; -+} -+ -+static bool -+ubicom32_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -+{ -+ int size, mode; -+ -+ if (!type) -+ return true; -+ -+ size = int_size_in_bytes(type); -+ if (size > 8) -+ return true; -+ -+ mode = TYPE_MODE(type); -+ if (mode == BLKmode) -+ return true; -+ -+ return false; -+} -+ -+/* Return true if a given register number REGNO is acceptable for machine -+ mode MODE. */ -+bool -+ubicom32_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) -+{ -+ /* If we're not at least a v3 ISA then ACC0_HI is only 16 bits. */ -+ if (! ubicom32_v3) -+ { -+ if (regno == ACC0_HI_REGNUM) -+ return (mode == QImode || mode == HImode); -+ } -+ -+ /* Only the flags reg can hold CCmode. */ -+ if (GET_MODE_CLASS (mode) == MODE_CC) -+ return regno == CC_REGNUM; -+ -+ /* We restrict the choice of DImode registers to only being address, -+ data or accumulator regs. We also restrict them to only start on -+ even register numbers so we never have to worry about partial -+ overlaps between operands in instructions. */ -+ if (GET_MODE_SIZE (mode) > 4) -+ { -+ switch (REGNO_REG_CLASS (regno)) -+ { -+ case ADDRESS_REGS: -+ case DATA_REGS: -+ case ACC_REGS: -+ return (regno & 1) == 0; -+ -+ default: -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx -+ and check its validity for a certain class. -+ We have two alternate definitions for each of them. -+ The usual definition accepts all pseudo regs; the other rejects -+ them unless they have been allocated suitable hard regs. -+ The symbol REG_OK_STRICT causes the latter definition to be used. -+ -+ Most source files want to accept pseudo regs in the hope that -+ they will get allocated to the class that the insn wants them to be in. -+ Source files for reload pass need to be strict. -+ After reload, it makes no difference, since pseudo regs have -+ been eliminated by then. -+ -+ These assume that REGNO is a hard or pseudo reg number. -+ They give nonzero only if REGNO is a hard reg of the suitable class -+ or a pseudo reg currently allocated to a suitable hard reg. -+ Since they use reg_renumber, they are safe only once reg_renumber -+ has been allocated, which happens in local-alloc.c. */ -+ -+int -+ubicom32_regno_ok_for_base_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_ADDRESS_REGNUM && regno <= STACK_POINTER_REGNUM) -+ || (!strict -+ && (regno >= FIRST_PSEUDO_REGISTER -+ || regno == ARG_POINTER_REGNUM)) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_ADDRESS_REGNUM -+ && reg_renumber[regno] <= STACK_POINTER_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+int -+ubicom32_regno_ok_for_index_p (int regno, int strict) -+{ -+ if ((regno >= FIRST_DATA_REGNUM && regno <= LAST_DATA_REGNUM) -+ || (!strict && regno >= FIRST_PSEUDO_REGISTER) -+ || (strict && (reg_renumber -+ && reg_renumber[regno] >= FIRST_DATA_REGNUM -+ && reg_renumber[regno] <= LAST_DATA_REGNUM))) -+ return 1; -+ -+ return 0; -+} -+ -+/* Returns 1 if X is a valid index register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_index_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_index_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_index_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+/* Return 1 if X is a valid index for a memory address. */ -+ -+static bool -+ubicom32_is_index_expr (enum machine_mode mode, rtx x, int strict) -+{ -+ /* Immediate index must be an unsigned 7-bit offset multiple of 1, 2 -+ or 4 depending on mode. */ -+ if (CONST_INT_P (x)) -+ { -+ switch (mode) -+ { -+ case QImode: -+ return satisfies_constraint_J (x); -+ -+ case HImode: -+ return satisfies_constraint_K (x); -+ -+ case SImode: -+ case SFmode: -+ return satisfies_constraint_L (x); -+ -+ case DImode: -+ return satisfies_constraint_L (x) -+ && satisfies_constraint_L (GEN_INT (INTVAL (x) + 4)); -+ -+ default: -+ return false; -+ } -+ } -+ -+ if (mode != SImode && mode != HImode && mode != QImode) -+ return false; -+ -+ /* Register index scaled by mode of operand: REG + REG * modesize. -+ Valid scaled index registers are: -+ -+ SImode (mult (dreg) 4)) -+ HImode (mult (dreg) 2)) -+ QImode (mult (dreg) 1)) */ -+ if (GET_CODE (x) == MULT -+ && ubicom32_is_index_reg (XEXP (x, 0), strict) -+ && CONST_INT_P (XEXP (x, 1)) -+ && INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT)GET_MODE_SIZE (mode)) -+ return true; -+ -+ /* REG + REG addressing is allowed for QImode. */ -+ if (ubicom32_is_index_reg (x, strict) && mode == QImode) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_is_valid_offset (enum machine_mode mode, HOST_WIDE_INT offs) -+{ -+ if (offs < 0) -+ return false; -+ -+ switch (mode) -+ { -+ case QImode: -+ return offs <= 127; -+ -+ case HImode: -+ return offs <= 254; -+ -+ case SImode: -+ case SFmode: -+ return offs <= 508; -+ -+ case DImode: -+ return offs <= 504; -+ -+ default: -+ return false; -+ } -+} -+ -+static int -+ubicom32_get_valid_offset_mask (enum machine_mode mode) -+{ -+ switch (mode) -+ { -+ case QImode: -+ return 127; -+ -+ case HImode: -+ return 255; -+ -+ case SImode: -+ case SFmode: -+ return 511; -+ -+ case DImode: -+ return 255; -+ -+ default: -+ return 0; -+ } -+} -+ -+/* Returns 1 if X is a valid base register. STRICT is 1 if only hard -+ registers should be accepted. Accept either REG or SUBREG where a -+ register is valid. */ -+ -+static bool -+ubicom32_is_base_reg (rtx x, int strict) -+{ -+ if ((REG_P (x) && ubicom32_regno_ok_for_base_p (REGNO (x), strict)) -+ || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) -+ && ubicom32_regno_ok_for_base_p (REGNO (SUBREG_REG (x)), strict))) -+ return true; -+ -+ return false; -+} -+ -+static bool -+ubicom32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ return TARGET_FDPIC; -+} -+ -+/* Determine if X is a legitimate constant. */ -+ -+bool -+ubicom32_legitimate_constant_p (rtx x) -+{ -+ /* Among its other duties, LEGITIMATE_CONSTANT_P decides whether -+ a constant can be entered into reg_equiv_constant[]. If we return true, -+ reload can create new instances of the constant whenever it likes. -+ -+ The idea is therefore to accept as many constants as possible (to give -+ reload more freedom) while rejecting constants that can only be created -+ at certain times. In particular, anything with a symbolic component will -+ require use of the pseudo FDPIC register, which is only available before -+ reload. */ -+ if (TARGET_FDPIC) -+ { -+ if (GET_CODE (x) == SYMBOL_REF -+ || (GET_CODE (x) == CONST -+ && GET_CODE (XEXP (x, 0)) == PLUS -+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) -+ || CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ return true; -+ } -+ -+ /* For non-PIC code anything goes! */ -+ return true; -+} -+ -+/* Address validation. */ -+ -+bool -+ubicom32_legitimate_address_p (enum machine_mode mode, rtx x, int strict) -+{ -+ if (TARGET_DEBUG_ADDRESS) -+ { -+ fprintf (stderr, "\n==> GO_IF_LEGITIMATE_ADDRESS%s\n", -+ (strict) ? " (STRICT)" : ""); -+ debug_rtx (x); -+ } -+ -+ if (CONSTANT_ADDRESS_P (x)) -+ return false; -+ -+ if (ubicom32_is_base_reg (x, strict)) -+ return true; -+ -+ if ((GET_CODE (x) == POST_INC -+ || GET_CODE (x) == PRE_INC -+ || GET_CODE (x) == POST_DEC -+ || GET_CODE (x) == PRE_DEC) -+ && REG_P (XEXP (x, 0)) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && mode != DImode) -+ return true; -+ -+ if ((GET_CODE (x) == PRE_MODIFY || GET_CODE (x) == POST_MODIFY) -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && GET_CODE (XEXP (x, 1)) == PLUS -+ && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0)) -+ && CONST_INT_P (XEXP (XEXP (x, 1), 1)) -+ && mode != DImode) -+ { -+ HOST_WIDE_INT disp = INTVAL (XEXP (XEXP (x, 1), 1)); -+ switch (mode) -+ { -+ case QImode: -+ return disp >= -8 && disp <= 7; -+ -+ case HImode: -+ return disp >= -16 && disp <= 14 && ! (disp & 1); -+ -+ case SImode: -+ return disp >= -32 && disp <= 28 && ! (disp & 3); -+ -+ default: -+ return false; -+ } -+ } -+ -+ /* Accept base + index * scale. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 1), strict)) -+ return true; -+ -+ /* Accept index * scale + base. */ -+ if (GET_CODE (x) == PLUS -+ && ubicom32_is_base_reg (XEXP (x, 1), strict) -+ && ubicom32_is_index_expr (mode, XEXP (x, 0), strict)) -+ return true; -+ -+ if (! TARGET_FDPIC) -+ { -+ /* Accept (lo_sum (reg) (symbol_ref)) that can be used as a mem+7bits -+ displacement operand: -+ -+ moveai a1, #%hi(SYM) -+ move.4 d3, %lo(SYM)(a1) */ -+ if (GET_CODE (x) == LO_SUM -+ && ubicom32_is_base_reg (XEXP (x, 0), strict) -+ && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF -+ || GET_CODE (XEXP (x, 1)) == LABEL_REF /* FIXME: wrong */) -+ && mode != DImode) -+ return true; -+ } -+ -+ if (TARGET_DEBUG_ADDRESS) -+ fprintf (stderr, "\nNot a legitimate address.\n"); -+ -+ return false; -+} -+ -+rtx -+ubicom32_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, -+ enum machine_mode mode) -+{ -+ if (mode == BLKmode) -+ return NULL_RTX; -+ -+ if (GET_CODE (x) == PLUS -+ && REG_P (XEXP (x, 0)) -+ && ! REGNO_PTR_FRAME_P (REGNO (XEXP (x, 0))) -+ && CONST_INT_P (XEXP (x, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (x, 1)))) -+ { -+ rtx base; -+ rtx plus; -+ rtx new_rtx; -+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ if (val < 0) -+ return NULL_RTX; -+ -+ if (! low) -+ return NULL_RTX; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ base = XEXP (x, 0); -+ if (! ubicom32_is_base_reg (base, 0)) -+ base = copy_to_mode_reg (Pmode, base); -+ -+ plus = expand_simple_binop (Pmode, PLUS, -+ gen_int_mode (high, Pmode), -+ base, NULL, 0, OPTAB_WIDEN); -+ new_rtx = plus_constant (plus, low); -+ -+ return new_rtx; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address AD -+ operand. If we find one, push the reload and and return the new address. -+ -+ MODE is the mode of the enclosing MEM. OPNUM is the operand number -+ and TYPE is the reload type of the current reload. */ -+ -+rtx -+ubicom32_legitimize_reload_address (rtx ad, enum machine_mode mode, -+ int opnum, int type) -+{ -+ /* Is this an address that we've already fixed up? If it is then -+ recognize it and move on. */ -+ if (GET_CODE (ad) == PLUS -+ && GET_CODE (XEXP (ad, 0)) == PLUS -+ && REG_P (XEXP (XEXP (ad, 0), 0)) -+ && CONST_INT_P (XEXP (XEXP (ad, 0), 1)) -+ && CONST_INT_P (XEXP (ad, 1))) -+ { -+ push_reload (XEXP (ad, 0), NULL_RTX, &XEXP (ad, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return ad; -+ } -+ -+ /* Have we got an address where the offset is simply out of range? If -+ yes then reload the range as a high part and smaller offset. */ -+ if (GET_CODE (ad) == PLUS -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0))) -+ && CONST_INT_P (XEXP (ad, 1)) -+ && ! ubicom32_is_valid_offset (mode, INTVAL (XEXP (ad, 1)))) -+ { -+ rtx temp; -+ rtx new_rtx; -+ -+ HOST_WIDE_INT val = INTVAL (XEXP (ad, 1)); -+ HOST_WIDE_INT low = val & ubicom32_get_valid_offset_mask (mode); -+ HOST_WIDE_INT high = val ^ low; -+ -+ /* Reload the high part into a base reg; leave the low part -+ in the mem directly. */ -+ temp = gen_rtx_PLUS (Pmode, XEXP (ad, 0), GEN_INT (high)); -+ new_rtx = gen_rtx_PLUS (Pmode, temp, GEN_INT (low)); -+ -+ push_reload (XEXP (new_rtx, 0), NULL_RTX, &XEXP (new_rtx, 0), NULL, -+ BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, -+ opnum, (enum reload_type) type); -+ return new_rtx; -+ } -+ -+ /* If we're presented with an pre/post inc/dec then we must force this -+ to be done in an address register. The register allocator should -+ work this out for itself but at times ends up trying to use the wrong -+ class. If we get the wrong class then reload will end up generating -+ at least 3 instructions whereas this way we can hopefully keep it to -+ just 2. */ -+ if ((GET_CODE (ad) == POST_INC -+ || GET_CODE (ad) == PRE_INC -+ || GET_CODE (ad) == POST_DEC -+ || GET_CODE (ad) == PRE_DEC) -+ && REG_P (XEXP (ad, 0)) -+ && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER -+ && ! REGNO_OK_FOR_BASE_P (REGNO (XEXP (ad, 0)))) -+ { -+ push_reload (XEXP (ad, 0), XEXP (ad, 0), &XEXP (ad, 0), &XEXP (ad, 0), -+ BASE_REG_CLASS, GET_MODE (XEXP (ad, 0)), GET_MODE (XEXP (ad, 0)), 0, 0, -+ opnum, RELOAD_OTHER); -+ return ad; -+ } -+ -+ return NULL_RTX; -+} -+ -+/* Compute a (partial) cost for rtx X. Return true if the complete -+ cost has been computed, and false if subexpressions should be -+ scanned. In either case, *TOTAL contains the cost result. */ -+ -+static bool -+ubicom32_rtx_costs (rtx x, int code, int outer_code, int *total, -+ bool speed ATTRIBUTE_UNUSED) -+{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (code) -+ { -+ case CONST_INT: -+ /* Very short constants often fold into instructions so -+ we pretend that they don't cost anything! This is -+ really important as regards zero values as otherwise -+ the compiler has a nasty habit of wanting to reuse -+ zeroes that are in regs but that tends to pessimize -+ the code. */ -+ if (satisfies_constraint_I (x)) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit clearing costs nothing */ -+ if (outer_code == AND -+ && exact_log2 (~INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Masking the lower set of bits costs nothing. */ -+ if (outer_code == AND -+ && exact_log2 (INTVAL (x) + 1) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Bit setting costs nothing. */ -+ if (outer_code == IOR -+ && exact_log2 (INTVAL (x)) != -1) -+ { -+ *total = 0; -+ return true; -+ } -+ -+ /* Larger constants that can be loaded via movei aren't too -+ bad. If we're just doing a set they cost nothing extra. */ -+ if (satisfies_constraint_N (x)) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ return true; -+ } -+ -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (5); -+ else -+ *total = COSTS_N_INSNS (3); -+ return true; -+ -+ case CONST_DOUBLE: -+ /* We don't optimize CONST_DOUBLEs well nor do we relax them well, -+ so their cost is very high. */ -+ *total = COSTS_N_INSNS (6); -+ return true; -+ -+ case CONST: -+ case SYMBOL_REF: -+ case MEM: -+ *total = 0; -+ return true; -+ -+ case IF_THEN_ELSE: -+ *total = COSTS_N_INSNS (1); -+ return true; -+ -+ case LABEL_REF: -+ case HIGH: -+ case LO_SUM: -+ case BSWAP: -+ case PLUS: -+ case MINUS: -+ case AND: -+ case IOR: -+ case XOR: -+ case ASHIFT: -+ case ASHIFTRT: -+ case LSHIFTRT: -+ case NEG: -+ case NOT: -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ case ZERO_EXTRACT: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case COMPARE: -+ if (outer_code == SET) -+ { -+ if (GET_MODE (XEXP (x, 0)) == DImode -+ || GET_MODE (XEXP (x, 1)) == DImode) -+ *total = COSTS_N_INSNS (2); -+ else -+ *total = COSTS_N_INSNS (1); -+ } -+ return true; -+ -+ case UMOD: -+ case UDIV: -+ case MOD: -+ case DIV: -+ if (outer_code == SET) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (600); -+ else -+ *total = COSTS_N_INSNS (200); -+ } -+ return true; -+ -+ case MULT: -+ if (outer_code == SET) -+ { -+ if (! ubicom32_v4) -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (15); -+ else -+ *total = COSTS_N_INSNS (5); -+ } -+ else -+ { -+ if (mode == DImode) -+ *total = COSTS_N_INSNS (6); -+ else -+ *total = COSTS_N_INSNS (2); -+ } -+ } -+ return true; -+ -+ case UNSPEC: -+ if (XINT (x, 1) == UNSPEC_FDPIC_GOT -+ || XINT (x, 1) == UNSPEC_FDPIC_GOT_FUNCDESC) -+ *total = 0; -+ return true; -+ -+ default: -+ return false; -+ } -+} -+ -+/* Return 1 if ADDR can have different meanings depending on the machine -+ mode of the memory reference it is used for or if the address is -+ valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have -+ mode-dependent effects because the amount of the increment or -+ decrement is the size of the operand being addressed. Some machines -+ have other mode-dependent addresses. Many RISC machines have no -+ mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+ -+int -+ubicom32_mode_dependent_address_p (rtx addr) -+{ -+ if (GET_CODE (addr) == POST_INC -+ || GET_CODE (addr) == PRE_INC -+ || GET_CODE (addr) == POST_DEC -+ || GET_CODE (addr) == PRE_DEC -+ || GET_CODE (addr) == POST_MODIFY -+ || GET_CODE (addr) == PRE_MODIFY) -+ return 1; -+ -+ return 0; -+} -+ -+static void -+ubicom32_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ fprintf (file, "/* frame/pretend: %ld/%d save_regs: %d out_args: %d %s */\n", -+ get_frame_size (), crtl->args.pretend_args_size, -+ save_regs_size, crtl->outgoing_args_size, -+ current_function_is_leaf ? "leaf" : "nonleaf"); -+} -+ -+static void -+ubicom32_function_epilogue (FILE *file ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT size ATTRIBUTE_UNUSED) -+{ -+ ubicom32_reorg_completed = 0; -+} -+ -+static void -+ubicom32_machine_dependent_reorg (void) -+{ -+#if 0 /* Commenting out this optimization until it is fixed */ -+ if (optimize) -+ { -+ compute_bb_for_insn (); -+ -+ /* Do a very simple CSE pass over just the hard registers. */ -+ reload_cse_regs (get_insns ()); -+ -+ /* Reload_cse_regs can eliminate potentially-trapping MEMs. -+ Remove any EH edges associated with them. */ -+ if (flag_non_call_exceptions) -+ purge_all_dead_edges (); -+ } -+#endif -+ ubicom32_reorg_completed = 1; -+} -+ -+void -+ubicom32_output_cond_jump (rtx insn, rtx cond, rtx target) -+{ -+ rtx note; -+ int mostly_false_jump; -+ rtx xoperands[2]; -+ rtx cc_reg; -+ -+ note = find_reg_note (insn, REG_BR_PROB, 0); -+ mostly_false_jump = !note || (INTVAL (XEXP (note, 0)) -+ <= REG_BR_PROB_BASE / 2); -+ -+ xoperands[0] = target; -+ xoperands[1] = cond; -+ cc_reg = XEXP (cond, 0); -+ -+ if (GET_MODE (cc_reg) == CCWmode -+ || GET_MODE (cc_reg) == CCWZmode -+ || GET_MODE (cc_reg) == CCWZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.w.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.w.t\t%0", xoperands); -+ return; -+ } -+ -+ if (GET_MODE (cc_reg) == CCSmode -+ || GET_MODE (cc_reg) == CCSZmode -+ || GET_MODE (cc_reg) == CCSZNmode) -+ { -+ if (mostly_false_jump) -+ output_asm_insn ("jmp%b1.s.f\t%0", xoperands); -+ else -+ output_asm_insn ("jmp%b1.s.t\t%0", xoperands); -+ return; -+ } -+ -+ abort (); -+} -+ -+/* Return non-zero if FUNC is a naked function. */ -+ -+static int -+ubicom32_naked_function_p (void) -+{ -+ return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; -+} -+ -+/* Return an RTX indicating where the return address to the -+ calling function can be found. */ -+rtx -+ubicom32_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) -+{ -+ if (count != 0) -+ return NULL_RTX; -+ -+ return get_hard_reg_initial_val (Pmode, LINK_REGNO); -+} -+ -+/* -+ * ubicom32_readonly_data_section: This routtine handles code -+ * at the start of readonly data sections -+ */ -+static void -+ubicom32_readonly_data_section (const void *data ATTRIBUTE_UNUSED) -+{ -+ static int num = 0; -+ if (in_section == readonly_data_section){ -+ fprintf (asm_out_file, "%s", DATA_SECTION_ASM_OP); -+ if (flag_data_sections){ -+ fprintf (asm_out_file, ".rodata%d", num); -+ fprintf (asm_out_file, ",\"a\""); -+ } -+ fprintf (asm_out_file, "\n"); -+ } -+ num++; -+} -+ -+/* -+ * ubicom32_text_section: not in readonly section -+ */ -+static void -+ubicom32_text_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_data_section: not in readonly section -+ */ -+static void -+ubicom32_data_section(const void *data ATTRIBUTE_UNUSED) -+{ -+ fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); -+} -+ -+/* -+ * ubicom32_asm_init_sections: This routine implements special -+ * section handling -+ */ -+static void -+ubicom32_asm_init_sections(void) -+{ -+ text_section = get_unnamed_section(SECTION_CODE, ubicom32_text_section, NULL); -+ -+ data_section = get_unnamed_section(SECTION_WRITE, ubicom32_data_section, NULL); -+ -+ readonly_data_section = get_unnamed_section(0, ubicom32_readonly_data_section, NULL); -+} -+ -+/* -+ * ubicom32_profiler: This routine would call -+ * mcount to support prof and gprof if mcount -+ * was supported. Currently, do nothing. -+ */ -+void -+ubicom32_profiler(void) -+{ -+} -+ -+/* Initialise the builtin functions. Start by initialising -+ descriptions of different types of functions (e.g., void fn(int), -+ int fn(void)), and then use these to define the builtins. */ -+static void -+ubicom32_init_builtins (void) -+{ -+ tree endlink; -+ tree short_unsigned_endlink; -+ tree unsigned_endlink; -+ tree short_unsigned_ftype_short_unsigned; -+ tree unsigned_ftype_unsigned; -+ -+ endlink = void_list_node; -+ -+ short_unsigned_endlink -+ = tree_cons (NULL_TREE, short_unsigned_type_node, endlink); -+ -+ unsigned_endlink -+ = tree_cons (NULL_TREE, unsigned_type_node, endlink); -+ -+ short_unsigned_ftype_short_unsigned -+ = build_function_type (short_unsigned_type_node, short_unsigned_endlink); -+ -+ unsigned_ftype_unsigned -+ = build_function_type (unsigned_type_node, unsigned_endlink); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_2", -+ short_unsigned_ftype_short_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+ -+ /* Initialise the byte swap function. */ -+ add_builtin_function ("__builtin_ubicom32_swapb_4", -+ unsigned_ftype_unsigned, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4, -+ BUILT_IN_MD, NULL, -+ NULL_TREE); -+} -+ -+/* Given a builtin function taking 2 operands (i.e., target + source), -+ emit the RTL for the underlying instruction. */ -+static rtx -+ubicom32_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target) -+{ -+ tree arg0; -+ rtx op0, pat; -+ enum machine_mode tmode, mode0; -+ -+ /* Grab the incoming argument and emit its RTL. */ -+ arg0 = TREE_VALUE (arglist); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ /* Determine the modes of the instruction operands. */ -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ /* Ensure that the incoming argument RTL is in a register of the -+ correct mode. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); -+ -+ /* If there isn't a suitable target, emit a target register. */ -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ -+ /* Emit and return the new instruction. */ -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ -+ return target; -+} -+ -+/* Expand a call to a builtin function. */ -+static rtx -+ubicom32_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) -+{ -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arglist = CALL_EXPR_ARGS(exp); -+ int fcode = DECL_FUNCTION_CODE (fndecl); -+ -+ switch (fcode) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswaphi, arglist, target); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_expand_builtin_2op (CODE_FOR_bswapsi, arglist, target); -+ -+ default: -+ gcc_unreachable(); -+ } -+ -+ /* Should really do something sensible here. */ -+ return NULL_RTX; -+} -+ -+/* Fold any constant argument for a swapb.2 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_2 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ HOST_WIDE_INT v; -+ HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 8) & 0xff) -+ | ((v & 0xff) << 8); -+ -+ return build_int_cst (TREE_TYPE (TREE_TYPE (fndecl)), res); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant argument for a swapb.4 instruction. */ -+static tree -+ubicom32_fold_builtin_ubicom32_swapb_4 (tree fndecl, tree arglist) -+{ -+ tree arg0; -+ -+ arg0 = TREE_VALUE (arglist); -+ -+ /* Optimize constant value. */ -+ if (TREE_CODE (arg0) == INTEGER_CST) -+ { -+ unsigned HOST_WIDE_INT v; -+ unsigned HOST_WIDE_INT res; -+ -+ v = TREE_INT_CST_LOW (arg0); -+ res = ((v >> 24) & 0xff) -+ | (((v >> 16) & 0xff) << 8) -+ | (((v >> 8) & 0xff) << 16) -+ | ((v & 0xff) << 24); -+ -+ return build_int_cst_wide (TREE_TYPE (TREE_TYPE (fndecl)), res, 0); -+ } -+ -+ return NULL_TREE; -+} -+ -+/* Fold any constant arguments for builtin functions. */ -+static tree -+ubicom32_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED) -+{ -+ switch (DECL_FUNCTION_CODE (fndecl)) -+ { -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_2: -+ return ubicom32_fold_builtin_ubicom32_swapb_2 (fndecl, arglist); -+ -+ case UBICOM32_BUILTIN_UBICOM32_SWAPB_4: -+ return ubicom32_fold_builtin_ubicom32_swapb_4 (fndecl, arglist); -+ -+ default: -+ return NULL; -+ } -+} -+ -+/* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to -+ tell the assembler to generate pointers to function descriptors in -+ some cases. */ -+static bool -+ubicom32_assemble_integer (rtx value, unsigned int size, int aligned_p) -+{ -+ if (TARGET_FDPIC && size == UNITS_PER_WORD) -+ { -+ if (GET_CODE (value) == SYMBOL_REF -+ && SYMBOL_REF_FUNCTION_P (value)) -+ { -+ fputs ("\t.picptr\t%funcdesc(", asm_out_file); -+ output_addr_const (asm_out_file, value); -+ fputs (")\n", asm_out_file); -+ return true; -+ } -+ -+ if (!aligned_p) -+ { -+ /* We've set the unaligned SI op to NULL, so we always have to -+ handle the unaligned case here. */ -+ assemble_integer_with_op ("\t.4byte\t", value); -+ return true; -+ } -+ } -+ -+ return default_assemble_integer (value, size, aligned_p); -+} -+ -+/* If the constant I can be constructed by shifting a source-1 immediate -+ by a constant number of bits then return the bit count. If not -+ return 0. */ -+ -+int -+ubicom32_shiftable_const_int (int i) -+{ -+ int shift = 0; -+ -+ /* Note that any constant that can be represented as an immediate to -+ a movei instruction is automatically ignored here in the interests -+ of the clarity of the output asm code. */ -+ if (i >= -32768 && i <= 32767) -+ return 0; -+ -+ /* Find the number of trailing zeroes. We could use __builtin_ctz -+ here but it's not obvious if this is supported on all build -+ compilers so we err on the side of caution. */ -+ if ((i & 0xffff) == 0) -+ { -+ shift += 16; -+ i >>= 16; -+ } -+ -+ if ((i & 0xff) == 0) -+ { -+ shift += 8; -+ i >>= 8; -+ } -+ -+ if ((i & 0xf) == 0) -+ { -+ shift += 4; -+ i >>= 4; -+ } -+ -+ if ((i & 0x3) == 0) -+ { -+ shift += 2; -+ i >>= 2; -+ } -+ -+ if ((i & 0x1) == 0) -+ { -+ shift += 1; -+ i >>= 1; -+ } -+ -+ if (i >= -128 && i <= 127) -+ return shift; -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.h -@@ -0,0 +1,1564 @@ -+/* Definitions of target machine for Ubicom32 -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+ -+ -+#define OBJECT_FORMAT_ELF -+ -+/* Run-time target specifications. */ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ \ -+ if (TARGET_FDPIC) \ -+ { \ -+ builtin_define ("__UBICOM32_FDPIC__"); \ -+ builtin_define ("__FDPIC__"); \ -+ } \ -+ } \ -+ while (0) -+ -+#ifndef TARGET_DEFAULT -+#define TARGET_DEFAULT 0 -+#endif -+ -+extern int ubicom32_case_values_threshold; -+ -+/* Nonzero if this chip supports the Ubicom32 v3 ISA. */ -+extern int ubicom32_v3; -+ -+/* Nonzero if this chip supports the Ubicom32 v4 ISA. */ -+extern int ubicom32_v4; -+ -+extern int ubicom32_stack_size; -+ -+/* Flag for whether we can use calli instead of ret in returns. */ -+extern int ubicom32_can_use_calli_to_ret; -+ -+/* This macro is a C statement to print on `stderr' a string describing the -+ particular machine description choice. Every machine description should -+ define `TARGET_VERSION'. */ -+#define TARGET_VERSION fprintf (stderr, " (UBICOM32)"); -+ -+/* We don't need a frame pointer to debug things. Doing this means -+ that gcc can turn on -fomit-frame-pointer when '-O' is specified. */ -+#define CAN_DEBUG_WITHOUT_FP -+ -+/* We need to handle processor-specific options. */ -+#define OVERRIDE_OPTIONS ubicom32_override_options () -+ -+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ -+ ubicom32_optimization_options (LEVEL, SIZE) -+ -+/* For Ubicom32 the least significant bit has the lowest bit number -+ so we define this to be 0. */ -+#define BITS_BIG_ENDIAN 0 -+ -+/* For Ubicom32 the most significant byte in a word has the lowest -+ number. */ -+#define BYTES_BIG_ENDIAN 1 -+ -+/* For Ubicom32, in a multiword object, the most signifant word has the -+ lowest number. */ -+#define WORDS_BIG_ENDIAN 1 -+ -+/* Ubicom32 has 8 bits per byte. */ -+#define BITS_PER_UNIT 8 -+ -+/* Ubicom32 has 32 bits per word. */ -+#define BITS_PER_WORD 32 -+ -+/* Width of a word, in units (bytes). */ -+#define UNITS_PER_WORD 4 -+ -+/* Width of a pointer, in bits. */ -+#define POINTER_SIZE 32 -+ -+/* Alias for pointers. Ubicom32 is a 32-bit architecture so we use -+ SImode. */ -+#define Pmode SImode -+ -+/* Normal alignment required for function parameters on the stack, in -+ bits. */ -+#define PARM_BOUNDARY 32 -+ -+/* We need to maintain the stack on a 32-bit boundary. */ -+#define STACK_BOUNDARY 32 -+ -+/* Alignment required for a function entry point, in bits. */ -+#define FUNCTION_BOUNDARY 32 -+ -+/* Alias for the machine mode used for memory references to functions being -+ called, in `call' RTL expressions. We use byte-oriented addresses -+ here. */ -+#define FUNCTION_MODE QImode -+ -+/* Biggest alignment that any data type can require on this machine, -+ in bits. */ -+#define BIGGEST_ALIGNMENT 32 -+ -+/* this default to BIGGEST_ALIGNMENT unless defined */ -+/* ART: What's the correct value here? Default is (((unsigned int)1<<28)*8)*/ -+#undef MAX_OFILE_ALIGNMENT -+#define MAX_OFILE_ALIGNMENT (128 * 8) -+ -+/* Alignment in bits to be given to a structure bit field that follows an empty -+ field such as `int : 0;'. */ -+#define EMPTY_FIELD_BOUNDARY 32 -+ -+/* All structures must be a multiple of 32 bits in size. */ -+#define STRUCTURE_SIZE_BOUNDARY 32 -+ -+/* A bit-field declared as `int' forces `int' alignment for the struct. */ -+#define PCC_BITFIELD_TYPE_MATTERS 1 -+ -+/* For Ubicom32 we absolutely require that data be aligned with nominal -+ alignment. */ -+#define STRICT_ALIGNMENT 1 -+ -+/* Make strcpy of constants fast. */ -+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ -+ (TREE_CODE (EXP) == STRING_CST \ -+ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -+ -+/* Define this macro as an expression for the alignment of a structure -+ (given by STRUCT as a tree node) if the alignment computed in the -+ usual way is COMPUTED and the alignment explicitly specified was -+ SPECIFIED. */ -+#define DATA_ALIGNMENT(TYPE, ALIGN) \ -+ ((((ALIGN) < BITS_PER_WORD) \ -+ && (TREE_CODE (TYPE) == ARRAY_TYPE \ -+ || TREE_CODE (TYPE) == UNION_TYPE \ -+ || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) -+ -+#define LOCAL_ALIGNMENT(TYPE,ALIGN) DATA_ALIGNMENT(TYPE,ALIGN) -+ -+/* For Ubicom32 we default to unsigned chars. */ -+#define DEFAULT_SIGNED_CHAR 0 -+ -+/* Machine-specific data register numbers. */ -+#define FIRST_DATA_REGNUM 0 -+#define D10_REGNUM 10 -+#define D11_REGNUM 11 -+#define D12_REGNUM 12 -+#define D13_REGNUM 13 -+#define LAST_DATA_REGNUM 15 -+ -+/* Machine-specific address register numbers. */ -+#define FIRST_ADDRESS_REGNUM 16 -+#define LAST_ADDRESS_REGNUM 22 -+ -+/* Register numbers used for passing a function's static chain pointer. If -+ register windows are used, the register number as seen by the called -+ function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as -+ seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers -+ are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. -+ -+ The static chain register need not be a fixed register. -+ -+ If the static chain is passed in memory, these macros should not be defined; -+ instead, the next two macros should be defined. */ -+#define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) -+ -+/* The register number of the frame pointer register, which is used to access -+ automatic variables in the stack frame. We generally eliminate this anyway -+ for Ubicom32 but we make it A6 by default. */ -+#define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM) -+ -+/* The register number of the stack pointer register, which is also be a -+ fixed register according to `FIXED_REGISTERS'. For Ubicom32 we don't -+ have a hardware requirement about which register this is, but by convention -+ we use A7. */ -+#define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) -+ -+/* Machine-specific accumulator register numbers. */ -+#define ACC0_HI_REGNUM 24 -+#define ACC0_LO_REGNUM 25 -+#define ACC1_HI_REGNUM 26 -+#define ACC1_LO_REGNUM 27 -+ -+/* source3 register number */ -+#define SOURCE3_REGNUM 28 -+ -+/* The register number of the arg pointer register, which is used to access the -+ function's argument list. On some machines, this is the same as the frame -+ pointer register. On some machines, the hardware determines which register -+ this is. On other machines, you can choose any register you wish for this -+ purpose. If this is not the same register as the frame pointer register, -+ then you must mark it as a fixed register according to `FIXED_REGISTERS', or -+ arrange to be able to eliminate it. */ -+#define ARG_POINTER_REGNUM 29 -+ -+/* Pseudo-reg for condition code. */ -+#define CC_REGNUM 30 -+ -+/* Interrupt set/clear registers. */ -+#define INT_SET0_REGNUM 31 -+#define INT_SET1_REGNUM 32 -+#define INT_CLR0_REGNUM 33 -+#define INT_CLR1_REGNUM 34 -+ -+/* Scratchpad registers. */ -+#define SCRATCHPAD0_REGNUM 35 -+#define SCRATCHPAD1_REGNUM 36 -+#define SCRATCHPAD2_REGNUM 37 -+#define SCRATCHPAD3_REGNUM 38 -+ -+/* FDPIC register. */ -+#define FDPIC_REGNUM 16 -+ -+/* Number of hardware registers known to the compiler. They receive numbers 0 -+ through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number -+ really is assigned the number `FIRST_PSEUDO_REGISTER'. */ -+#define FIRST_PSEUDO_REGISTER 39 -+ -+/* An initializer that says which registers are used for fixed purposes all -+ throughout the compiled code and are therefore not available for general -+ allocation. These would include the stack pointer, the frame pointer -+ (except on machines where that can be used as a general register when no -+ frame pointer is needed), the program counter on machines where that is -+ considered one of the addressable registers, and any other numbered register -+ with a standard use. -+ -+ This information is expressed as a sequence of numbers, separated by commas -+ and surrounded by braces. The Nth number is 1 if register N is fixed, 0 -+ otherwise. -+ -+ The table initialized from this macro, and the table initialized by the -+ following one, may be overridden at run time either automatically, by the -+ actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the -+ command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ -+#define FIXED_REGISTERS \ -+ { \ -+ 0, 0, 0, 0, 0, 0, 0, 0, /* d0 - d7 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* d8 - d15 */ \ -+ 0, 0, 0, 0, 0, 0, 0, 1, /* a0 - a7 */ \ -+ 0, 0, /* acc0 hi/lo */ \ -+ 0, 0, /* acc1 hi/lo */ \ -+ 0, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in -+ general) by function calls as well as for fixed registers. This macro -+ therefore identifies the registers that are not available for general -+ allocation of values that must live across function calls. -+ -+ If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically -+ saves it on function entry and restores it on function exit, if the register -+ is used within the function. */ -+#define CALL_USED_REGISTERS \ -+ { \ -+ 1, 1, 1, 1, 1, 1, 1, 1, /* d0 - d7 */ \ -+ 1, 1, 0, 0, 0, 0, 1, 1, /* d8 - d15 */ \ -+ 1, 0, 0, 1, 1, 1, 0, 1, /* a0 - a7 */ \ -+ 1, 1, /* acc0 hi/lo */ \ -+ 1, 1, /* acc1 hi/lo */ \ -+ 1, /* source3 */ \ -+ 1, /* arg */ \ -+ 1, /* cc */ \ -+ 1, 1, /* int_set[01] */ \ -+ 1, 1, /* int_clr[01] */ \ -+ 1, 1, 1, 1 /* scratchpad[0123] */ \ -+ } -+ -+/* How to refer to registers in assembler output. -+ This sequence is indexed by compiler's hard-register-number (see above). */ -+ -+/* A C initializer containing the assembler's names for the machine registers, -+ each one as a C string constant. This is what translates register numbers -+ in the compiler into assembler language. */ -+#define REGISTER_NAMES \ -+ { \ -+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", \ -+ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ -+ "acc0_hi", "acc0_lo", \ -+ "acc1_hi", "acc1_lo", \ -+ "source3", \ -+ "arg", \ -+ "cc", \ -+ "int_set0", "int_set1", \ -+ "int_clr0", "int_clr1", \ -+ "scratchpad0", "scratchpad1", "scratchpad2", "scratchpad3" \ -+ } -+ -+#define CONDITIONAL_REGISTER_USAGE \ -+ ubicom32_conditional_register_usage (); -+ -+/* Order of allocation of registers. */ -+ -+/* If defined, an initializer for a vector of integers, containing the numbers -+ of hard registers in the order in which GNU CC should prefer to use them -+ (from most preferred to least). -+ -+ For Ubicom32 we try using caller-clobbered data registers first, then -+ callee-saved data registers, then caller-clobbered address registers, -+ then callee-saved address registers and finally everything else. -+ -+ The caller-clobbered registers are usually slightly cheaper to use because -+ there's no need to save/restore. */ -+#define REG_ALLOC_ORDER \ -+ { \ -+ 0, 1, 2, 3, 4, /* d0 - d4 */ \ -+ 5, 6, 7, 8, 9, /* d5 - d9 */ \ -+ 14, /* d14 */ \ -+ 10, 11, 12, 13, /* d10 - d13 */ \ -+ 19, 20, 16, 21, /* a3, a4, a0, a5 */ \ -+ 17, 18, 22, /* a1, a2, a6 */ \ -+ 24, 25, /* acc0 hi/lo */ \ -+ 26, 27, /* acc0 hi/lo */ \ -+ 28 /* source3 */ \ -+ } -+ -+/* C expression for the number of consecutive hard registers, starting at -+ register number REGNO, required to hold a value of mode MODE. */ -+#define HARD_REGNO_NREGS(REGNO, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* Most registers can hold QImode, HImode and SImode values but we have to -+ be able to indicate any hard registers that cannot hold values with some -+ modes. */ -+#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -+ ubicom32_hard_regno_mode_ok(REGNO, MODE) -+ -+/* We can rename most registers aside from the FDPIC register if we're using -+ FDPIC. */ -+#define HARD_REGNO_RENAME_OK(from, to) (TARGET_FDPIC ? ((to) != FDPIC_REGNUM) : 1) -+ -+/* A C expression that is nonzero if it is desirable to choose register -+ allocation so as to avoid move instructions between a value of mode MODE1 -+ and a value of mode MODE2. -+ -+ If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are -+ ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be -+ zero. */ -+#define MODES_TIEABLE_P(MODE1, MODE2) 1 -+ -+/* An enumeral type that must be defined with all the register class names as -+ enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last -+ register class, followed by one more enumeral value, `LIM_REG_CLASSES', -+ which is not a register class but rather tells how many classes there are. -+ -+ Each register class has a number, which is the value of casting the class -+ name to type `int'. The number serves as an index in many of the tables -+ described below. */ -+ -+enum reg_class -+{ -+ NO_REGS, -+ DATA_REGS, -+ FDPIC_REG, -+ ADDRESS_REGS, -+ ALL_ADDRESS_REGS, -+ ACC_LO_REGS, -+ ACC_REGS, -+ CC_REG, -+ DATA_ACC_REGS, -+ SOURCE3_REG, -+ SPECIAL_REGS, -+ GENERAL_REGS, -+ ALL_REGS, -+ LIM_REG_CLASSES -+}; -+ -+/* The number of distinct register classes. */ -+#define N_REG_CLASSES (int) LIM_REG_CLASSES -+ -+/* An initializer containing the names of the register classes as C string -+ constants. These names are used in writing some of the debugging dumps. */ -+ -+#define REG_CLASS_NAMES \ -+{ \ -+ "NO_REGS", \ -+ "DATA_REGS", \ -+ "FDPIC_REG", \ -+ "ADDRESS_REGS", \ -+ "ALL_ADDRESS_REGS", \ -+ "ACC_LO_REGS", \ -+ "ACC_REGS", \ -+ "CC_REG", \ -+ "DATA_ACC_REGS", \ -+ "SOURCE3_REG", \ -+ "SPECIAL_REGS", \ -+ "GENERAL_REGS", \ -+ "ALL_REGS", \ -+ "LIM_REGS" \ -+} -+ -+/* An initializer containing the contents of the register classes, as integers -+ which are bit masks. The Nth integer specifies the contents of class N. -+ The way the integer MASK is interpreted is that register R is in the class -+ if `MASK & (1 << R)' is 1. -+ -+ When the machine has more than 32 registers, an integer does not suffice. -+ Then the integers are replaced by sub-initializers, braced groupings -+ containing several integers. Each sub-initializer must be suitable as an -+ initializer for the type `HARD_REG_SET' which is defined in -+ `hard-reg-set.h'. */ -+#define REG_CLASS_CONTENTS \ -+{ \ -+ {0x00000000, 0x00000000}, /* No regs */ \ -+ {0x0000ffff, 0x00000000}, /* DATA_REGS */ \ -+ {0x00010000, 0x00000000}, /* FDPIC_REG */ \ -+ {0x20fe0000, 0x00000000}, /* ADDRESS_REGS */ \ -+ {0x20ff0000, 0x00000000}, /* ALL_ADDRESS_REGS */ \ -+ {0x0a000000, 0x00000000}, /* ACC_LO_REGS */ \ -+ {0x0f000000, 0x00000000}, /* ACC_REGS */ \ -+ {0x40000000, 0x00000000}, /* CC_REG */ \ -+ {0x0f00ffff, 0x00000000}, /* DATA_ACC_REGS */ \ -+ {0x10000000, 0x00000000}, /* SOURGE3_REG */ \ -+ {0x80000000, 0x0000007f}, /* SPECIAL_REGS */ \ -+ {0xbfffffff, 0x0000007f}, /* GENERAL_REGS */ \ -+ {0xbfffffff, 0x0000007f} /* ALL_REGS */ \ -+} -+ -+extern enum reg_class const ubicom32_regclass_map[FIRST_PSEUDO_REGISTER]; -+ -+/* A C expression whose value is a register class containing hard register -+ REGNO. In general there is more than one such class; choose a class which -+ is "minimal", meaning that no smaller class also contains the register. */ -+#define REGNO_REG_CLASS(REGNO) (ubicom32_regclass_map[REGNO]) -+ -+#define IRA_COVER_CLASSES \ -+{ \ -+ GENERAL_REGS, \ -+ LIM_REG_CLASSES \ -+} -+ -+/* Ubicom32 base registers must be address registers since addresses can -+ only be reached via address registers. */ -+#define BASE_REG_CLASS ALL_ADDRESS_REGS -+ -+/* Ubicom32 index registers must be data registers since we cannot add -+ two address registers together to form an address. */ -+#define INDEX_REG_CLASS DATA_REGS -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as a base register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. */ -+ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 0) -+#else -+#define REGNO_OK_FOR_BASE_P(regno) \ -+ ubicom32_regno_ok_for_base_p (regno, 1) -+#endif -+ -+/* A C expression which is nonzero if register number NUM is suitable for use -+ as an index register in operand addresses. It may be either a suitable hard -+ register or a pseudo register that has been allocated such a hard register. -+ -+ The difference between an index register and a base register is that the -+ index register may be scaled. If an address involves the sum of two -+ registers, neither one of them scaled, then either one may be labeled the -+ "base" and the other the "index"; but whichever labeling is used must fit -+ the machine's constraints of which registers may serve in each capacity. -+ The compiler will try both labelings, looking for one that is valid, and -+ will reload one or both registers only if neither labeling works. */ -+#ifndef REG_OK_STRICT -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 0) -+#else -+#define REGNO_OK_FOR_INDEX_P(regno) \ -+ ubicom32_regno_ok_for_index_p (regno, 1) -+#endif -+ -+/* Attempt to restrict the register class we need to copy value X intoto the -+ would-be register class CLASS. Most things are fine for Ubicom32 but we -+ have to restrict certain types of address loads. */ -+#define PREFERRED_RELOAD_CLASS(X, CLASS) \ -+ ubicom32_preferred_reload_class (X, CLASS) -+ -+/* A C expression for the maximum number of consecutive registers of -+ class CLASS needed to hold a value of mode MODE. For Ubicom32 this -+ is pretty much identical to HARD_REGNO_NREGS. */ -+#define CLASS_MAX_NREGS(CLASS, MODE) \ -+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -+ -+/* For Ubicom32 the stack grows downwards when we push a word onto the stack -+ - i.e. it moves to a smaller address. */ -+#define STACK_GROWS_DOWNWARD 1 -+ -+/* Offset from the frame pointer to the first local variable slot to -+ be allocated. */ -+#define STARTING_FRAME_OFFSET 0 -+ -+/* Offset from the argument pointer register to the first argument's -+ address. */ -+#define FIRST_PARM_OFFSET(FNDECL) 0 -+ -+/* A C expression whose value is RTL representing the value of the return -+ address for the frame COUNT steps up from the current frame, after the -+ prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame -+ pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is -+ defined. -+ -+ The value of the expression must always be the correct address when COUNT is -+ zero, but may be `NULL_RTX' if there is not way to determine the return -+ address of other frames. */ -+#define RETURN_ADDR_RTX(COUNT, FRAME) \ -+ ubicom32_return_addr_rtx (COUNT, FRAME) -+ -+/* Register That Address the Stack Frame. */ -+ -+/* We don't actually require a frame pointer in most functions with the -+ Ubicom32 architecture so we allow it to be eliminated. */ -+#define FRAME_POINTER_REQUIRED 0 -+ -+/* Macro that defines a table of register pairs used to eliminate unecessary -+ registers that point into the stack frame. -+ -+ For Ubicom32 we don't generally need an arg pointer of a frame pointer -+ so we allow the arg pointer to be replaced by either the frame pointer or -+ the stack pointer. We also allow the frame pointer to be replaced by -+ the stack pointer. */ -+#define ELIMINABLE_REGS \ -+{ \ -+ {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ -+ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -+ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ -+} -+ -+/* Let the compiler know that we want to use the ELIMINABLE_REGS macro -+ above. */ -+#define CAN_ELIMINATE(FROM, TO) 1 -+ -+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the -+ initial difference between the specified pair of registers. This macro must -+ be defined if `ELIMINABLE_REGS' is defined. */ -+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -+ (OFFSET) = ubicom32_initial_elimination_offset (FROM, TO) -+ -+/* If defined, the maximum amount of space required for outgoing arguments will -+ be computed and placed into the variable -+ `current_function_outgoing_args_size'. No space will be pushed onto the -+ stack for each call; instead, the function prologue should increase the -+ stack frame size by this amount. -+ -+ Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not -+ proper. */ -+#define ACCUMULATE_OUTGOING_ARGS 1 -+ -+/* Define this macro if functions should assume that stack space has been -+ allocated for arguments even when their values are passed in registers. -+ -+ The value of this macro is the size, in bytes, of the area reserved for -+ arguments passed in registers for the function represented by FNDECL. -+ -+ This space can be allocated by the caller, or be a part of the -+ machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says -+ which. */ -+#define REG_PARM_STACK_SPACE(FNDECL) ubicom32_reg_parm_stack_space(FNDECL) -+ -+/* A C expression that should indicate the number of bytes of its own arguments -+ that a function pops on returning, or 0 if the function pops no arguments -+ and the caller must therefore pop them all after the function returns. -+ -+ FUNDECL is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_DECL' that -+ describes the declaration of the function. From this it is possible to -+ obtain the DECL_MACHINE_ATTRIBUTES of the function. -+ -+ FUNTYPE is a C variable whose value is a tree node that describes the -+ function in question. Normally it is a node of type `FUNCTION_TYPE' that -+ describes the data type of the function. From this it is possible to obtain -+ the data types of the value and arguments (if known). -+ -+ When a call to a library function is being considered, FUNTYPE will contain -+ an identifier node for the library function. Thus, if you need to -+ distinguish among various library functions, you can do so by their names. -+ Note that "library function" in this context means a function used to -+ perform arithmetic, whose name is known specially in the compiler and was -+ not mentioned in the C code being compiled. -+ -+ STACK-SIZE is the number of bytes of arguments passed on the stack. If a -+ variable number of bytes is passed, it is zero, and argument popping will -+ always be the responsibility of the calling function. -+ -+ On the Vax, all functions always pop their arguments, so the definition of -+ this macro is STACK-SIZE. On the 68000, using the standard calling -+ convention, no functions pop their arguments, so the value of the macro is -+ always 0 in this case. But an alternative calling convention is available -+ in which functions that take a fixed number of arguments pop them but other -+ functions (such as `printf') pop nothing (the caller pops all). When this -+ convention is in use, FUNTYPE is examined to determine whether a function -+ takes a fixed number of arguments. */ -+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 -+ -+/* A C expression that controls whether a function argument is passed in a -+ register, and which register. -+ -+ The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way -+ defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous -+ arguments so far passed in registers; MODE, the machine mode of the argument; -+ TYPE, the data type of the argument as a tree node or 0 if that is not known -+ (which happens for C support library functions); and NAMED, which is 1 for an -+ ordinary argument and 0 for nameless arguments that correspond to `...' in the -+ called function's prototype. -+ -+ The value of the expression should either be a `reg' RTX for the hard -+ register in which to pass the argument, or zero to pass the argument on the -+ stack. -+ -+ For machines like the Vax and 68000, where normally all arguments are -+ pushed, zero suffices as a definition. -+ -+ The usual way to make the ANSI library `stdarg.h' work on a machine where -+ some arguments are usually passed in registers, is to cause nameless -+ arguments to be passed on the stack instead. This is done by making -+ `FUNCTION_ARG' return 0 whenever NAMED is 0. -+ -+ You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of -+ this macro to determine if this argument is of a type that must be passed in -+ the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG' -+ returns non-zero for such an argument, the compiler will abort. If -+ `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the -+ stack and then loaded into a register. */ -+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_arg (&CUM, MODE, TYPE, NAMED) -+ -+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ -+ function_incoming_arg (&CUM, MODE, TYPE, NAMED) -+ -+/* A C expression for the number of words, at the beginning of an argument, -+ must be put in registers. The value must be zero for arguments that are -+ passed entirely in registers or that are entirely pushed on the stack. -+ -+ On some machines, certain arguments must be passed partially in registers -+ and partially in memory. On these machines, typically the first N words of -+ arguments are passed in registers, and the rest on the stack. If a -+ multi-word argument (a `double' or a structure) crosses that boundary, its -+ first few words must be passed in registers and the rest must be pushed. -+ This macro tells the compiler when this occurs, and how many of the words -+ should go in registers. -+ -+ `FUNCTION_ARG' for these arguments should return the first register to be -+ used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for -+ the called function. */ -+ -+/* A C expression that indicates when an argument must be passed by reference. -+ If nonzero for an argument, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The -+ pointer is passed in whatever way is appropriate for passing a pointer to -+ that type. -+ -+ On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable -+ definition of this macro might be -+ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ -+ MUST_PASS_IN_STACK (MODE, TYPE) */ -+ -+/* If defined, a C expression that indicates when it is the called function's -+ responsibility to make a copy of arguments passed by invisible reference. -+ Normally, the caller makes a copy and passes the address of the copy to the -+ routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is -+ nonzero, the caller does not make a copy. Instead, it passes a pointer to -+ the "live" value. The called function must not modify this value. If it -+ can be determined that the value won't be modified, it need not make a copy; -+ otherwise a copy must be made. */ -+ -+/* A C type for declaring a variable that is used as the first argument of -+ `FUNCTION_ARG' and other related values. For some target machines, the type -+ `int' suffices and can hold the number of bytes of argument so far. -+ -+ There is no need to record in `CUMULATIVE_ARGS' anything about the arguments -+ that have been passed on the stack. The compiler has other variables to -+ keep track of that. For target machines on which all arguments are passed -+ on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; -+ however, the data structure must exist and should not be empty, so use -+ `int'. */ -+struct cum_arg -+{ -+ int nbytes; -+ int reg; -+ int stdarg; -+}; -+#define CUMULATIVE_ARGS struct cum_arg -+ -+/* A C statement (sans semicolon) for initializing the variable CUM for the -+ state at the beginning of the argument list. The variable has type -+ `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type -+ of the function which will receive the args, or 0 if the args are to a -+ compiler support library function. The value of INDIRECT is nonzero when -+ processing an indirect call, for example a call through a function pointer. -+ The value of INDIRECT is zero for a call to an explicitly named function, a -+ library function call, or when `INIT_CUMULATIVE_ARGS' is used to find -+ arguments for the function being compiled. -+ -+ When processing a call to a compiler support library function, LIBNAME -+ identifies which one. It is a `symbol_ref' rtx which contains the name of -+ the function, as a string. LIBNAME is 0 when an ordinary C function call is -+ being processed. Thus, each time this macro is called, either LIBNAME or -+ FNTYPE is nonzero, but never both of them at once. */ -+ -+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, NAMED_ARGS) \ -+ init_cumulative_args (&(CUM), FNTYPE, LIBNAME, INDIRECT); -+ -+/* A C statement (sans semicolon) to update the summarizer variable CUM to -+ advance past an argument in the argument list. The values MODE, TYPE and -+ NAMED describe that argument. Once this is done, the variable CUM is -+ suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. -+ -+ This macro need not do anything if the argument in question was passed on -+ the stack. The compiler knows how to track the amount of stack space used -+ for arguments without any special help. */ -+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ -+ ((CUM).nbytes += ((MODE) != BLKmode \ -+ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ -+ : (int_size_in_bytes (TYPE) + 3) & ~3)) -+ -+/* For the Ubicom32 we define the upper function argument register here. */ -+#define UBICOM32_FUNCTION_ARG_REGS 10 -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which function arguments are sometimes passed. This does *not* include -+ implicit arguments such as the static chain and the structure-value address. -+ On many machines, no registers can be used for this purpose since all -+ function arguments are pushed on the stack. */ -+#define FUNCTION_ARG_REGNO_P(N) ((N) < UBICOM32_FUNCTION_ARG_REGS) -+ -+ -+/* How Scalar Function Values are Returned. */ -+ -+/* The number of the hard register that is used to return a scalar value from a -+ function call. */ -+#define RETURN_VALUE_REGNUM 0 -+ -+/* A C expression to create an RTX representing the place where a function -+ returns a value of data type VALTYPE. VALTYPE is a tree node representing a -+ data type. Write `TYPE_MODE (VALTYPE)' to get the machine mode used to -+ represent that type. On many machines, only the mode is relevant. -+ (Actually, on most machines, scalar values are returned in the same place -+ regardless of mode). -+ -+ If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion -+ rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type. -+ -+ If the precise function being called is known, FUNC is a tree node -+ (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer. This makes it -+ possible to use a different value-returning convention for specific -+ functions when all their calls are known. -+ -+ `FUNCTION_VALUE' is not used for return vales with aggregate data types, -+ because these are returned in another way. See `STRUCT_VALUE_REGNUM' and -+ related macros, below. */ -+#define FUNCTION_VALUE(VALTYPE, FUNC) \ -+ gen_rtx_REG (TYPE_MODE (VALTYPE), FIRST_DATA_REGNUM) -+ -+/* A C expression to create an RTX representing the place where a library -+ function returns a value of mode MODE. -+ -+ Note that "library function" in this context means a compiler support -+ routine, used to perform arithmetic, whose name is known specially by the -+ compiler and was not mentioned in the C code being compiled. -+ -+ The definition of `LIBRARY_VALUE' need not be concerned aggregate data -+ types, because none of the library functions returns such types. */ -+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_DATA_REGNUM) -+ -+/* A C expression that is nonzero if REGNO is the number of a hard register in -+ which the values of called function may come back. -+ -+ A register whose use for returning values is limited to serving as the -+ second of a pair (for a value of type `double', say) need not be recognized -+ by this macro. So for most machines, this definition suffices: -+ -+ #define FUNCTION_VALUE_REGNO_P(N) ((N) == RETURN) -+ -+ If the machine has register windows, so that the caller and the called -+ function use different registers for the return value, this macro should -+ recognize only the caller's register numbers. */ -+#define FUNCTION_VALUE_REGNO_P(N) ((N) == FIRST_DATA_REGNUM) -+ -+ -+/* How Large Values are Returned. */ -+ -+/* A C expression which can inhibit the returning of certain function values in -+ registers, based on the type of value. A nonzero value says to return the -+ function value in memory, just as large structures are always returned. -+ Here TYPE will be a C expression of type `tree', representing the data type -+ of the value. -+ -+ Note that values of mode `BLKmode' must be explicitly handled by this macro. -+ Also, the option `-fpcc-struct-return' takes effect regardless of this -+ macro. On most systems, it is possible to leave the macro undefined; this -+ causes a default definition to be used, whose value is the constant 1 for -+ `BLKmode' values, and 0 otherwise. -+ -+ Do not use this macro to indicate that structures and unions should always -+ be returned in memory. You should instead use `DEFAULT_PCC_STRUCT_RETURN' -+ to indicate this. */ -+#define RETURN_IN_MEMORY(TYPE) \ -+ (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode) -+ -+/* Define this macro to be 1 if all structure and union return values must be -+ in memory. Since this results in slower code, this should be defined only -+ if needed for compatibility with other compilers or with an ABI. If you -+ define this macro to be 0, then the conventions used for structure and union -+ return values are decided by the `RETURN_IN_MEMORY' macro. -+ -+ If not defined, this defaults to the value 1. */ -+#define DEFAULT_PCC_STRUCT_RETURN 0 -+ -+/* If the structure value address is not passed in a register, define -+ `STRUCT_VALUE' as an expression returning an RTX for the place -+ where the address is passed. If it returns 0, the address is -+ passed as an "invisible" first argument. */ -+#define STRUCT_VALUE 0 -+ -+/* Define this macro as a C expression that is nonzero if the return -+ instruction or the function epilogue ignores the value of the stack pointer; -+ in other words, if it is safe to delete an instruction to adjust the stack -+ pointer before a return from the function. -+ -+ Note that this macro's value is relevant only for functions for which frame -+ pointers are maintained. It is never safe to delete a final stack -+ adjustment in a function that has no frame pointer, and the compiler knows -+ this regardless of `EXIT_IGNORE_STACK'. */ -+#define EXIT_IGNORE_STACK 1 -+ -+/* A C statement or compound statement to output to FILE some assembler code to -+ call the profiling subroutine `mcount'. Before calling, the assembler code -+ must load the address of a counter variable into a register where `mcount' -+ expects to find the address. The name of this variable is `LP' followed by -+ the number LABELNO, so you would generate the name using `LP%d' in a -+ `fprintf'. -+ -+ The details of how the address should be passed to `mcount' are determined -+ by your operating system environment, not by GNU CC. To figure them out, -+ compile a small program for profiling using the system's installed C -+ compiler and look at the assembler code that results. -+ -+ This declaration must be present, but it can be an abort if profiling is -+ not implemented. */ -+ -+#define FUNCTION_PROFILER(file, labelno) ubicom32_profiler(file, labelno) -+ -+/* A C statement to output, on the stream FILE, assembler code for a block of -+ data that contains the constant parts of a trampoline. This code should not -+ include a label--the label is taken care of automatically. */ -+#if 0 -+#define TRAMPOLINE_TEMPLATE(FILE) \ -+ do { \ -+ fprintf (FILE, "\tadd -4,sp\n"); \ -+ fprintf (FILE, "\t.long 0x0004fffa\n"); \ -+ fprintf (FILE, "\tmov (0,sp),a0\n"); \ -+ fprintf (FILE, "\tadd 4,sp\n"); \ -+ fprintf (FILE, "\tmov (13,a0),a1\n"); \ -+ fprintf (FILE, "\tmov (17,a0),a0\n"); \ -+ fprintf (FILE, "\tjmp (a0)\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ fprintf (FILE, "\t.long 0\n"); \ -+ } while (0) -+#endif -+ -+/* A C expression for the size in bytes of the trampoline, as an integer. */ -+#define TRAMPOLINE_SIZE 0x1b -+ -+/* Alignment required for trampolines, in bits. -+ -+ If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for -+ aligning trampolines. */ -+#define TRAMPOLINE_ALIGNMENT 32 -+ -+/* A C statement to initialize the variable parts of a trampoline. ADDR is an -+ RTX for the address of the trampoline; FNADDR is an RTX for the address of -+ the nested function; STATIC_CHAIN is an RTX for the static chain value that -+ should be passed to the function when it is called. */ -+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -+{ \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x14)), \ -+ (CXT)); \ -+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 0x18)), \ -+ (FNADDR)); \ -+} -+ -+/* Ubicom32 supports pre and post increment/decrement addressing. */ -+#define HAVE_POST_INCREMENT 1 -+#define HAVE_PRE_INCREMENT 1 -+#define HAVE_POST_DECREMENT 1 -+#define HAVE_PRE_DECREMENT 1 -+ -+/* Ubicom32 supports pre and post address side-effects with constants -+ other than the size of the memory operand. */ -+#define HAVE_PRE_MODIFY_DISP 1 -+#define HAVE_POST_MODIFY_DISP 1 -+ -+/* A C expression that is 1 if the RTX X is a constant which is a valid -+ address. On most machines, this can be defined as `CONSTANT_P (X)', -+ but a few machines are more restrictive in which constant addresses -+ are supported. -+ -+ `CONSTANT_P' accepts integer-values expressions whose values are not -+ explicitly known, such as `symbol_ref', `label_ref', and `high' -+ expressions and `const' arithmetic expressions, in addition to -+ `const_int' and `const_double' expressions. */ -+#define CONSTANT_ADDRESS_P(X) \ -+ (GET_CODE (X) == LABEL_REF \ -+ || (GET_CODE (X) == CONST \ -+ && GET_CODE (XEXP (X, 0)) == PLUS \ -+ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)) -+ -+/* Ubicom32 supports a maximum of 2 registers in a valid memory address. -+ One is always an address register while a second, optional, one may be a -+ data register. */ -+#define MAX_REGS_PER_ADDRESS 2 -+ -+/* A C compound statement with a conditional `goto LABEL;' executed if X (an -+ RTX) is a legitimate memory address on the target machine for a memory -+ operand of mode MODE. -+ -+ It usually pays to define several simpler macros to serve as subroutines for -+ this one. Otherwise it may be too complicated to understand. -+ -+ This macro must exist in two variants: a strict variant and a non-strict -+ one. The strict variant is used in the reload pass. It must be defined so -+ that any pseudo-register that has not been allocated a hard register is -+ considered a memory reference. In contexts where some kind of register is -+ required, a pseudo-register with no hard register must be rejected. -+ -+ The non-strict variant is used in other passes. It must be defined to -+ accept all pseudo-registers in every context where some kind of register is -+ required. -+ -+ Compiler source files that want to use the strict variant of this macro -+ define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' -+ conditional to define the strict variant in that case and the non-strict -+ variant otherwise. -+ -+ Subroutines to check for acceptable registers for various purposes (one for -+ base registers, one for index registers, and so on) are typically among the -+ subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these -+ subroutine macros need have two variants; the higher levels of macros may be -+ the same whether strict or not. -+ -+ Normally, constant addresses which are the sum of a `symbol_ref' and an -+ integer are stored inside a `const' RTX to mark them as constant. -+ Therefore, there is no need to recognize such sums specifically as -+ legitimate addresses. Normally you would simply recognize any `const' as -+ legitimate. -+ -+ Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that -+ are not marked with `const'. It assumes that a naked `plus' indicates -+ indexing. If so, then you *must* reject such naked constant sums as -+ illegitimate addresses, so that none of them will be given to -+ `PRINT_OPERAND_ADDRESS'. -+ -+ On some machines, whether a symbolic address is legitimate depends on the -+ section that the address refers to. On these machines, define the macro -+ `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and -+ then check for it here. When you see a `const', you will have to look -+ inside it to find the `symbol_ref' in order to determine the section. -+ -+ The best way to modify the name string is by adding text to the beginning, -+ with suitable punctuation to prevent any ambiguity. Allocate the new name -+ in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to -+ remove and decode the added text and output the name accordingly, and define -+ `STRIP_NAME_ENCODING' to access the original name string. -+ -+ You can check the information stored here into the `symbol_ref' in the -+ definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and -+ `PRINT_OPERAND_ADDRESS'. */ -+/* On the ubicom32, the value in the address register must be -+ in the same memory space/segment as the effective address. -+ -+ This is problematical for reload since it does not understand -+ that base+index != index+base in a memory reference. */ -+ -+#ifdef REG_OK_STRICT -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 1)) goto ADDR; -+#else -+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -+ if (ubicom32_legitimate_address_p (MODE, X, 0)) goto ADDR; -+#endif -+ -+/* Try machine-dependent ways of modifying an illegitimate address -+ to be legitimate. If we find one, return the new, valid address. -+ This macro is used in only one place: `memory_address' in explow.c. -+ -+ OLDX is the address as it was before break_out_memory_refs was called. -+ In some cases it is useful to look at this to decide what needs to be done. -+ -+ MODE and WIN are passed so that this macro can use -+ GO_IF_LEGITIMATE_ADDRESS. -+ -+ It is always safe for this macro to do nothing. It exists to recognize -+ opportunities to optimize the output. -+ -+ On RS/6000, first check for the sum of a register with a constant -+ integer that is out of range. If so, generate code to add the -+ constant with the low-order 16 bits masked to the register and force -+ this result into another register (this can be done with `cau'). -+ Then generate an address of REG+(CONST&0xffff), allowing for the -+ possibility of bit 16 being a one. -+ -+ Then check for the sum of a register and something not constant, try to -+ load the other things into a register and return the sum. */ -+ -+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -+{ \ -+ rtx result = ubicom32_legitimize_address ((X), (OLDX), (MODE)); \ -+ if (result != NULL_RTX) \ -+ { \ -+ (X) = result; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* Try a machine-dependent way of reloading an illegitimate address -+ operand. If we find one, push the reload and jump to WIN. This -+ macro is used in only one place: `find_reloads_address' in reload.c. */ -+#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ -+{ \ -+ rtx new_rtx = ubicom32_legitimize_reload_address ((AD), (MODE), (OPNUM), (int)(TYPE)); \ -+ if (new_rtx) \ -+ { \ -+ (AD) = new_rtx; \ -+ goto WIN; \ -+ } \ -+} -+ -+/* A C statement or compound statement with a conditional `goto LABEL;' -+ executed if memory address X (an RTX) can have different meanings depending -+ on the machine mode of the memory reference it is used for or if the address -+ is valid for some modes but not others. -+ -+ Autoincrement and autodecrement addresses typically have mode-dependent -+ effects because the amount of the increment or decrement is the size of the -+ operand being addressed. Some machines have other mode-dependent addresses. -+ Many RISC machines have no mode-dependent addresses. -+ -+ You may assume that ADDR is a valid address for the machine. */ -+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ -+ if (ubicom32_mode_dependent_address_p (ADDR)) \ -+ goto LABEL; -+ -+/* A C expression that is nonzero if X is a legitimate constant for an -+ immediate operand on the target machine. You can assume that X -+ satisfies `CONSTANT_P', so you need not check this. In fact, `1' is -+ a suitable definition for this macro on machines where anything -+ `CONSTANT_P' is valid. */ -+#define LEGITIMATE_CONSTANT_P(X) \ -+ ubicom32_legitimate_constant_p ((X)) -+ -+/* Moves between registers are pretty-much single instructions for -+ Ubicom32. We make this the default "2" that gcc likes. */ -+#define REGISTER_MOVE_COST(MODE, FROM, TO) 2 -+ -+/* This is a little bit of magic from the S390 port that wins 2% on code -+ size when building the Linux kernel! Unfortunately while it wins on -+ that size the user-space apps built using FD-PIC don't improve and the -+ performance is lower because we put more pressure on the caches. We may -+ want this back on some future CPU that has higher cache performance. */ -+/* #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) 0.5 */ -+ -+/* Moves between registers and memory are more expensive than between -+ registers because we have caches and write buffers that slow things -+ down! */ -+#define MEMORY_MOVE_COST(MODE, CLASS, IN) 2 -+ -+/* A fall-through branch is very low cost but anything that changes the PC -+ incurs a major pipeline hazard. We don't make the full extent of this -+ hazard visible because we hope that multiple threads will absorb much -+ of the cost and so we don't want a jump being replaced with, say, 7 -+ instructions. */ -+#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ -+ ((PREDICTABLE_P) ? 1 : 3) -+ -+/* Define this macro as a C expression which is nonzero if accessing less than -+ a word of memory (i.e. a `char' or a `short') is no faster than accessing a -+ word of memory, i.e., if such access require more than one instruction or if -+ there is no difference in cost between byte and (aligned) word loads. -+ -+ When this macro is not defined, the compiler will access a field by finding -+ the smallest containing object; when it is defined, a fullword load will be -+ used if alignment permits. Unless bytes accesses are faster than word -+ accesses, using word accesses is preferable since it may eliminate -+ subsequent memory access if subsequent accesses occur to other fields in the -+ same word of the structure, but to different bytes. */ -+#define SLOW_BYTE_ACCESS 0 -+ -+/* The number of scalar move insns which should be generated instead of a -+ string move insn or a library call. Increasing the value will always make -+ code faster, but eventually incurs high cost in increased code size. -+ -+ If you don't define this, a reasonable default is used. */ -+/* According to expr.c, a value of around 6 should minimize code size. */ -+#define MOVE_RATIO(SPEED) 6 -+ -+/* We're much better off calling a constant function address with the -+ Ubicom32 architecture because we have an opcode for doing so. Don't -+ let the compiler extract function addresses as common subexpressions -+ into an address register. */ -+#define NO_FUNCTION_CSE -+ -+#define SELECT_CC_MODE(OP, X, Y) ubicom32_select_cc_mode (OP, X, Y) -+ -+#define REVERSIBLE_CC_MODE(MODE) 1 -+ -+/* Canonicalize a comparison from one we don't have to one we do have. */ -+#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ -+ ubicom32_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) -+ -+/* Dividing the output into sections. */ -+ -+/* A C expression whose value is a string containing the assembler operation -+ that should precede instructions and read-only data. Normally `".text"' is -+ right. */ -+#define TEXT_SECTION_ASM_OP "\t.section .text" -+ -+/* A C expression whose value is a string containing the assembler operation to -+ identify the following data as writable initialized data. Normally -+ `".data"' is right. */ -+#define DATA_SECTION_ASM_OP "\t.section .data" -+ -+ -+/* If defined, a C expression whose value is a string containing the -+ assembler operation to identify the following data as -+ uninitialized global data. If not defined, and neither -+ `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, -+ uninitialized global data will be output in the data section if -+ `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be -+ used. */ -+#define BSS_SECTION_ASM_OP "\t.section .bss" -+ -+/* This is how we tell the assembler that a symbol is weak. */ -+ -+#define ASM_WEAKEN_LABEL(FILE, NAME) \ -+ do \ -+ { \ -+ fputs ("\t.weak\t", (FILE)); \ -+ assemble_name ((FILE), (NAME)); \ -+ fputc ('\n', (FILE)); \ -+ } \ -+ while (0) -+ -+/* The Overall Framework of an Assembler File. */ -+ -+#undef SET_ASM_OP -+#define SET_ASM_OP "\t.set\t" -+ -+/* A C string constant describing how to begin a comment in the target -+ assembler language. The compiler assumes that the comment will end at the -+ end of the line. */ -+#define ASM_COMMENT_START ";" -+ -+/* A C string constant for text to be output before each `asm' statement or -+ group of consecutive ones. Normally this is `"#APP"', which is a comment -+ that has no effect on most assemblers but tells the GNU assembler that it -+ must check the lines that follow for all valid assembler constructs. */ -+#define ASM_APP_ON "#APP\n" -+ -+/* A C string constant for text to be output after each `asm' statement or -+ group of consecutive ones. Normally this is `"#NO_APP"', which tells the -+ GNU assembler to resume making the time-saving assumptions that are valid -+ for ordinary compiler output. */ -+#define ASM_APP_OFF "#NO_APP\n" -+ -+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate, -+ explicit argument. If you define this macro, it is used in place of -+ `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required -+ alignment of the variable. The alignment is specified as the number of -+ bits. -+ -+ Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when -+ defining this macro. */ -+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ -+ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -+ -+/* A C expression to assign to OUTVAR (which is a variable of type `char *') a -+ newly allocated string made from the string NAME and the number NUMBER, with -+ some suitable punctuation added. Use `alloca' to get space for the string. -+ -+ The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce -+ an assembler label for an internal static variable whose name is NAME. -+ Therefore, the string must be such as to result in valid assembler code. -+ The argument NUMBER is different each time this macro is executed; it -+ prevents conflicts between similarly-named internal static variables in -+ different scopes. -+ -+ Ideally this string should not be a valid C identifier, to prevent any -+ conflict with the user's own symbols. Most assemblers allow periods or -+ percent signs in assembler symbols; putting at least one of these between -+ the name and the number will suffice. */ -+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ -+ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) -+ -+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ -+ sprintf (STRING, "*.%s%ld", PREFIX, (long)(NUM)) -+/* A C statement to store into the string STRING a label whose name -+ is made from the string PREFIX and the number NUM. -+ -+ This string, when output subsequently by `assemble_name', should -+ produce the output that `(*targetm.asm_out.internal_label)' would produce -+ with the same PREFIX and NUM. -+ -+ If the string begins with `*', then `assemble_name' will output -+ the rest of the string unchanged. It is often convenient for -+ `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way. If the -+ string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to -+ output the string, and may change it. (Of course, -+ `ASM_OUTPUT_LABELREF' is also part of your machine description, so -+ you should know what it does on your machine.) */ -+ -+/* This says how to output assembler code to declare an -+ uninitialized external linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+ -+#define COMMON_ASM_OP "\t.comm\t" -+ -+#undef ASM_OUTPUT_COMMON -+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", COMMON_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* This says how to output assembler code to declare an -+ uninitialized internal linkage data object. Under SVR4, -+ the linker seems to want the alignment of data objects -+ to depend on their types. We do exactly that here. */ -+#define LOCAL_ASM_OP "\t.lcomm\t" -+ -+#undef ASM_OUTPUT_LOCAL -+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -+ do \ -+ { \ -+ fprintf ((FILE), "%s", LOCAL_ASM_OP); \ -+ assemble_name ((FILE), (NAME)); \ -+ fprintf ((FILE), ", %u\n", (SIZE)); \ -+ } \ -+ while (0) -+ -+/* Globalizing directive for a label. */ -+#define GLOBAL_ASM_OP ".global\t" -+ -+/* Output the operand of an instruction. */ -+#define PRINT_OPERAND(FILE, X, CODE) \ -+ ubicom32_print_operand(FILE, X, CODE) -+ -+/* Output the address of an operand. */ -+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ -+ ubicom32_print_operand_address (FILE, ADDR) -+ -+/* A C expression to output to STREAM some assembler code which will push hard -+ register number REGNO onto the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) -+ -+/* A C expression to output to STREAM some assembler code which will pop hard -+ register number REGNO off of the stack. The code need not be optimal, since -+ this macro is used only when profiling. */ -+#define ASM_OUTPUT_REG_POP(FILE, REGNO) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are relative to the table's own address. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a difference between two labels. -+ VALUE and REL are the numbers of two internal labels. The definitions of -+ these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be -+ printed in the same way here. For example, -+ -+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ -+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ -+ fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) -+ -+/* This macro should be provided on machines where the addresses in a dispatch -+ table are absolute. -+ -+ The definition should be a C statement to output to the stdio stream STREAM -+ an assembler pseudo-instruction to generate a reference to a label. VALUE -+ is the number of an internal label whose definition is output using -+ `ASM_OUTPUT_INTERNAL_LABEL'. For example, -+ -+ fprintf (STREAM, "\t.word L%d\n", VALUE) */ -+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ -+ fprintf (STREAM, "\t.word .L%d\n", VALUE) -+ -+/* Switch into a generic section. */ -+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -+ -+/* Assembler Commands for Alignment. */ -+ -+#define ASM_OUTPUT_SKIP(STREAM, N) fprintf (STREAM, "\t.skip %d,0\n", N) -+/* A C statement to output to the stdio stream STREAM an assembler -+ instruction to advance the location counter by NBYTES bytes. -+ Those bytes should be zero when loaded. NBYTES will be a C -+ expression of type `int'. */ -+ -+/* A C statement to output to the stdio stream STREAM an assembler command to -+ advance the location counter to a multiple of 2 to the POWER bytes. POWER -+ will be a C expression of type `int'. */ -+#define ASM_OUTPUT_ALIGN(FILE, LOG) \ -+ if ((LOG) != 0) \ -+ fprintf (FILE, "\t.align %d\n", (LOG)) -+ -+/* A C expression that returns the DBX register number for the compiler -+ register number REGNO. In simple cases, the value of this expression may be -+ REGNO itself. But sometimes there are some registers that the compiler -+ knows about and DBX does not, or vice versa. In such cases, some register -+ may need to have one number in the compiler and another for DBX. -+ -+ If two registers have consecutive numbers inside GNU CC, and they can be -+ used as a pair to hold a multiword value, then they *must* have consecutive -+ numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers -+ will be unable to access such a pair, because they expect register pairs to -+ be consecutive in their own numbering scheme. -+ -+ If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not -+ preserve register pairs, then what you must do instead is redefine the -+ actual register numbering scheme. -+ -+ This declaration is required. */ -+#define DBX_REGISTER_NUMBER(REGNO) REGNO -+ -+/* A C expression that returns the integer offset value for an automatic -+ variable having address X (an RTL expression). The default computation -+ assumes that X is based on the frame-pointer and gives the offset from the -+ frame-pointer. This is required for targets that produce debugging output -+ for DBX or COFF-style debugging output for SDB and allow the frame-pointer -+ to be eliminated when the `-g' options is used. */ -+#define DEBUGGER_AUTO_OFFSET(X) \ -+ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (FRAME_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the integer offset value for an argument having -+ address X (an RTL expression). The nominal offset is OFFSET. */ -+#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ -+ ((GET_CODE (X) == PLUS ? OFFSET : 0) \ -+ + (frame_pointer_needed \ -+ ? 0 : -initial_elimination_offset (ARG_POINTER_REGNUM, \ -+ STACK_POINTER_REGNUM))) -+ -+/* A C expression that returns the type of debugging output GNU CC produces -+ when the user specifies `-g' or `-ggdb'. Define this if you have arranged -+ for GNU CC to support more than one format of debugging output. Currently, -+ the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG', -+ `DWARF2_DEBUG', and `XCOFF_DEBUG'. -+ -+ The value of this macro only affects the default debugging output; the user -+ can always get a specific type of output by using `-gstabs', `-gcoff', -+ `-gdwarf-1', `-gdwarf-2', or `-gxcoff'. -+ -+ Defined in svr4.h. -+*/ -+#undef PREFERRED_DEBUGGING_TYPE -+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+ -+/* Define this macro if GNU CC should produce dwarf version 2 format debugging -+ output in response to the `-g' option. -+ -+ To support optional call frame debugging information, you must also define -+ `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the -+ prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa' -+ and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you -+ don't. -+ -+ Defined in svr4.h. */ -+ -+#define DWARF2_DEBUGGING_INFO 1 -+/*#define DWARF2_UNWIND_INFO 1*/ -+#define DWARF2_UNWIND_INFO 0 -+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNO) -+#define INCOMING_FRAME_SP_OFFSET 0 -+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNO) -+#define EH_RETURN_FIRST 9 -+#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + EH_RETURN_FIRST : INVALID_REGNUM) -+ -+/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the -+ location used to store the amount to ajdust the stack. This is -+ usually a registers that is available from end of the function's body -+ to the end of the epilogue. Thus, this cannot be a register used as a -+ temporary by the epilogue. -+ -+ This must be an integer register. */ -+#define EH_RETURN_STACKADJ_REGNO 11 -+#define EH_RETURN_STACKADJ_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) -+ -+/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the -+ location used to store the address the processor should jump to -+ catch exception. This is usually a registers that is available from -+ end of the function's body to the end of the epilogue. Thus, this -+ cannot be a register used as a temporary by the epilogue. -+ -+ This must be an address register. */ -+#define EH_RETURN_HANDLER_REGNO 18 -+#define EH_RETURN_HANDLER_RTX \ -+ gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) -+ -+/* #define DWARF2_DEBUGGING_INFO */ -+ -+/* Define this macro if GNU CC should produce dwarf version 2-style -+ line numbers. This usually requires extending the assembler to -+ support them, and #defining DWARF2_LINE_MIN_INSN_LENGTH in the -+ assembler configuration header files. */ -+/* #define DWARF2_ASM_LINE_DEBUG_INFO 1 */ -+ -+ -+/* An alias for a machine mode name. This is the machine mode that elements -+ of a jump-table have. */ -+#define CASE_VECTOR_MODE Pmode -+ -+/* Smallest number of different values for which it is best to use a -+ jump-table instead of a tree of conditional branches. For most Ubicom32 -+ targets this is quite small, but for the v1 architecture implementations -+ we had very little data memory and so heavily prefer the tree approach -+ rather than the jump tables. */ -+#define CASE_VALUES_THRESHOLD ubicom32_case_values_threshold -+ -+/* Register operations within the Ubicom32 architecture always operate on -+ the whole register word and not just the sub-bits required for the opcode -+ mode size. */ -+#define WORD_REGISTER_OPERATIONS -+ -+/* The maximum number of bytes that a single instruction can move quickly from -+ memory to memory. */ -+#define MOVE_MAX 4 -+ -+/* A C expression that is nonzero if on this machine the number of bits -+ actually used for the count of a shift operation is equal to the number of -+ bits needed to represent the size of the object being shifted. When this -+ macro is non-zero, the compiler will assume that it is safe to omit a -+ sign-extend, zero-extend, and certain bitwise `and' instructions that -+ truncates the count of a shift operation. On machines that have -+ instructions that act on bitfields at variable positions, which may include -+ `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables -+ deletion of truncations of the values that serve as arguments to bitfield -+ instructions. -+ -+ If both types of instructions truncate the count (for shifts) and position -+ (for bitfield operations), or if no variable-position bitfield instructions -+ exist, you should define this macro. -+ -+ However, on some machines, such as the 80386 and the 680x0, truncation only -+ applies to shift operations and not the (real or pretended) bitfield -+ operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. -+ Instead, add patterns to the `md' file that include the implied truncation -+ of the shift instructions. -+ -+ You need not define this macro if it would always have the value of zero. */ -+#define SHIFT_COUNT_TRUNCATED 1 -+ -+/* A C expression which is nonzero if on this machine it is safe to "convert" -+ an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller -+ than INPREC) by merely operating on it as if it had only OUTPREC bits. -+ -+ On many machines, this expression can be 1. -+ -+ When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for -+ which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the -+ case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve -+ things. */ -+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 -+ -+/* A C string constant that tells the GNU CC driver program options to pass -+ to the assembler. It can also specify how to translate options you give -+ to GNU CC into options for GNU CC to pass to the assembler. See the -+ file `sun3.h' for an example of this. -+ -+ Defined in svr4.h. */ -+#undef ASM_SPEC -+#define ASM_SPEC \ -+ "%{march=*:-m%*} %{!march=*:-mubicom32v4} %{mfdpic:-mfdpic}" -+ -+#define LINK_SPEC "\ -+%{h*} %{v:-V} \ -+%{b} \ -+%{mfdpic:-melf32ubicom32fdpic -z text} \ -+%{static:-dn -Bstatic} \ -+%{shared:-G -Bdynamic} \ -+%{symbolic:-Bsymbolic} \ -+%{G*} \ -+%{YP,*} \ -+%{Qy:} %{!Qn:-Qy}" -+ -+#undef STARTFILE_SPEC -+#undef ENDFILE_SPEC -+ -+/* The svr4.h LIB_SPEC with -leval and --*group tacked on */ -+ -+#undef LIB_SPEC -+#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" -+ -+#undef HAVE_GAS_SHF_MERGE -+#define HAVE_GAS_SHF_MERGE 0 -+ -+#define HANDLE_SYSV_PRAGMA 1 -+#undef HANDLE_PRAGMA_PACK -+ -+typedef void (*ubicom32_func_ptr) (void); -+ -+/* Define builtins for selected special-purpose instructions. */ -+enum ubicom32_builtins -+{ -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_2, -+ UBICOM32_BUILTIN_UBICOM32_SWAPB_4 -+}; -+ -+extern rtx ubicom32_compare_op0; -+extern rtx ubicom32_compare_op1; -+ -+#define TYPE_ASM_OP "\t.type\t" -+#define TYPE_OPERAND_FMT "@%s" -+ -+#ifndef ASM_DECLARE_RESULT -+#define ASM_DECLARE_RESULT(FILE, RESULT) -+#endif -+ -+/* These macros generate the special .type and .size directives which -+ are used to set the corresponding fields of the linker symbol table -+ entries in an ELF object file under SVR4. These macros also output -+ the starting labels for the relevant functions/objects. */ -+ -+/* Write the extra assembler code needed to declare a function properly. -+ Some svr4 assemblers need to also have something extra said about the -+ function's return value. We allow for that here. */ -+ -+#ifndef ASM_DECLARE_FUNCTION_NAME -+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ -+ do \ -+ { \ -+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ -+ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ -+ ASM_OUTPUT_LABEL (FILE, NAME); \ -+ } \ -+ while (0) -+#endif ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.md -@@ -0,0 +1,3753 @@ -+; GCC machine description for Ubicom32 -+; -+; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+; Foundation, Inc. -+; Contributed by Ubicom, Inc. -+; -+; This file is part of GCC. -+; -+; GCC is free software; you can redistribute it and/or modify -+; it under the terms of the GNU General Public License as published by -+; the Free Software Foundation; either version 3, or (at your option) -+; any later version. -+; -+; GCC is distributed in the hope that it will be useful, -+; but WITHOUT ANY WARRANTY; without even the implied warranty of -+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+; GNU General Public License for more details. -+; -+; You should have received a copy of the GNU General Public License -+; along with GCC; see the file COPYING3. If not see -+; . -+ -+(define_constants -+ [(AUX_DATA_REGNO 15) -+ (LINK_REGNO 21) -+ (SP_REGNO 23) -+ (ACC0_HI_REGNO 24) -+ (ACC1_HI_REGNO 26) -+ (CC_REGNO 30)]) -+ -+(define_constants -+ [(UNSPEC_FDPIC_GOT 0) -+ (UNSPEC_FDPIC_GOT_FUNCDESC 1)]) -+ -+(define_constants -+ [(UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC 0)]) -+ -+;; Types of instructions (for scheduling purposes). -+ -+(define_attr "type" "mul,addr,other" -+ (const_string "other")) -+ -+; Define instruction scheduling characteristics. We can only issue -+; one instruction per clock so we don't need to define CPU units. -+; -+(define_automaton "ubicom32") -+ -+(define_cpu_unit "i_pipeline" "ubicom32"); -+ -+; We have a 4 cycle hazard associated with address calculations which -+; seems rather tricky to avoid so we go with a defensive assumption -+; that almost anything can be used to generate addresses. -+; -+;(define_insn_reservation "ubicom32_other" 4 -+; (eq_attr "type" "other") -+; "i_pipeline") -+ -+; Some moves don't generate hazards. -+; -+;(define_insn_reservation "ubicom32_addr" 1 -+; (eq_attr "type" "addr") -+; "i_pipeline") -+ -+; We need 3 cycles between a multiply instruction and any use of the -+; matching accumulator register(s). -+; -+(define_insn_reservation "ubicom32_mul" 4 -+ (eq_attr "type" "mul") -+ "i_pipeline") -+ -+(define_attr "length" "" -+ (const_int 4)) -+ -+(include "predicates.md") -+(include "constraints.md") -+ -+; 8-bit move with no change to the flags reg. -+; -+(define_insn "movqi" -+ [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+ (match_operand:QI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "move.1\\t%0, %1") -+ -+; Combiner-generated 8-bit move with the zero flag set accordingly. -+; -+(define_insn "movqi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:QI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "nonimmediate_operand" "") -+ (match_operand:QI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 16-bit move with no change to the flags reg. -+; -+(define_insn "movhi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (match_operand:HI 1 "ubicom32_move_operand" "g"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ return \"movei\\t%0, %1\"; -+ -+ return \"move.2\\t%0, %1\"; -+ }") -+ -+; Combiner-generated 16-bit move with the zero flag set accordingly. -+; -+(define_insn "movhi_ccszn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (set (match_operand:HI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t%1, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "nonimmediate_operand" "") -+ (match_operand:HI 1 "nonimmediate_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)]))] -+ "(GET_MODE (operands[2]) == CCSZNmode -+ || GET_MODE (operands[2]) == CCSZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; 32-bit move with no change to the flags reg. -+; -+(define_expand "movsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ /* Convert any complexities in operand 1 into something that can just -+ fall into the default expander code. */ -+ ubicom32_expand_movsi (operands); -+ }") -+ -+(define_insn "movsi_high" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (high:SI (match_operand:SI 1 "ubicom32_symbolic_address_operand" "s")))] -+ "" -+ "moveai\\t%0, #%%hi(%E1)") -+ -+(define_insn "movsi_lo_sum" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (lo_sum:SI (match_operand:SI 1 "ubicom32_address_register_operand" "a") -+ (match_operand:SI 2 "immediate_operand" "s")))] -+ "" -+ "lea.1\\t%0, %%lo(%E2)(%1)") -+ -+(define_insn "movsi_internal" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (match_operand:SI 1 "ubicom32_move_operand" "rmnY"))] -+ "" -+ "* -+ { -+ if (CONST_INT_P (operands[1])) -+ { -+ ubicom32_emit_move_const_int (operands[0], operands[1]); -+ return \"\"; -+ } -+ -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT i = CONST_DOUBLE_LOW (operands[1]); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (i)); -+ return \"\"; -+ } -+ -+ if (ubicom32_address_register_operand (operands[0], VOIDmode) -+ && register_operand (operands[1], VOIDmode)) -+ { -+ if (ubicom32_address_register_operand (operands[1], VOIDmode)) -+ return \"lea.1\\t%0, 0(%1)\"; -+ -+ /* Use movea here to utilize the hazard bypass in the >= v4 ISA. */ -+ if (ubicom32_v4) -+ return \"movea\\t%0, %1\"; -+ -+ return \"move.4\\t%0, %1\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value 2^n by using a bset. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ior:SI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value ~(2^n) by using a bclr. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (~INTVAL (operands[1])) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (and:SI (const_int -1) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "") -+ -+; For 32-bit constants that have bits 0 through 24 and bit 31 set the same -+; we can use swapb.4! -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffffffff) != 0xffffffff -+ && (INTVAL (operands[1]) & 0xffffffff) != 0 -+ && ((INTVAL (operands[1]) & 0x80ffffff) == 0 -+ || (INTVAL (operands[1]) & 0x80ffffff) == 0x80ffffff))" -+ [(set (match_dup 0) -+ (bswap:SI (match_dup 2)))] -+ "{ -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> 24); -+ }") -+ -+; If this is a write of a constant to memory look to see if we can usefully -+; transform this into 2 smaller writes. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1]) -+ && ubicom32_legitimate_address_p (HImode, plus_constant (XEXP (operands[0], 0), 2), 1)" -+ [(set (match_dup 4) (match_dup 2)) -+ (set (match_dup 5) (match_dup 3))] -+ "{ -+ rtx low_hword_addr; -+ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ -+ operands[4] = gen_rtx_MEM (HImode, XEXP (operands[0], 0)); -+ MEM_COPY_ATTRIBUTES (operands[4], operands[0]); -+ -+ low_hword_addr = plus_constant (XEXP (operands[0], 0), 2); -+ operands[5] = gen_rtx_MEM (HImode, low_hword_addr); -+ MEM_COPY_ATTRIBUTES (operands[5], operands[0]); -+ }") -+ -+; If we're writing memory and we've not found a better way to do this then -+; try loading into a D register and then copying to memory. This will -+; perform the fewest possible memory read/writes. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "memory_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "! satisfies_constraint_I (operands[1])" -+ [(set (match_dup 2) (match_dup 1)) -+ (set (match_dup 0) (match_dup 2))] -+ "") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 2))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; constants of value (2^n - 1) by using an lsr.4. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(exact_log2 (INTVAL (operands[1]) + 1) > 14 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (lshiftrt:SI (const_int -1) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = GEN_INT (32 - exact_log2 (INTVAL (operands[1]) + 1)); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 0) -+ (ashift:SI (match_dup 2) -+ (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[2] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[3] = GEN_INT (shift); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; some other constants by using an lsl.4 to shift 7 bits left by some -+; constant. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_shiftable_const_int (INTVAL (operands[1])) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(parallel -+ [(set (match_dup 2) -+ (ashift:SI (match_dup 3) -+ (match_dup 4))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ int shift = ubicom32_shiftable_const_int (INTVAL (operands[1])); -+ operands[3] = GEN_INT (INTVAL (operands[1]) >> shift); -+ operands[4] = GEN_INT (shift); -+ }") -+ -+; For some 16-bit unsigned constants that have bit 15 set we can use -+; swapb.2! -+; -+; Note that the movsi code emits the same sequence but by using a peephole2 -+; we split the pattern early enough to allow instruction scheduling to -+; occur. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[1]) & 0xffff80ff) == 0x80ff)" -+ [(set (match_dup 0) -+ (zero_extend:SI (bswap:HI (match_dup 2))))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]) >> 8; -+ if (i >= 0x80) -+ i -= 0x100; -+ operands[2] = GEN_INT (i); -+ }") -+ -+; In general for a 16-bit unsigned constant that has bit 15 set -+; then we need a movei/move.2 pair unless we can represent it -+; via just a move.2. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(INTVAL (operands[1]) & 0xffff8000) == 0x8000 -+ && (INTVAL (operands[1]) & 0xffff) < 0xff80" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 0) -+ (zero_extend:SI (match_dup 2)))] -+ "{ -+ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; 32-bit constants that have bits 16 through 31 set to arbitrary values -+; and have bits 0 through 15 set to something representable as a default -+; source-1 immediate - we use movei/shmrg.2 -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 2)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[3] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000 -+ || INTVAL (operands[1]) < -0x8000) -+ && ((INTVAL (operands[1]) & 0xffff) >= 0xff80 -+ || (INTVAL (operands[1]) & 0xffff) < 0x80) -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 4)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; If we have a load of a large integer constant which does not have bit 31 -+; set and we have a spare A reg then construct it with a moveai/lea.1 pair -+; instead. This avoids constructing it in 3 instructions on the stack. -+; -+; Note that we have to be careful not to match anything that matches -+; something we can do in a single instruction! There aren't many such -+; constants but there are some. -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "a") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" ""))] -+ "(! (INTVAL (operands[1]) & 0x80000000) -+ && ((INTVAL (operands[1]) >= 0x8000 -+ && INTVAL (operands[1]) < 0xff80) -+ || INTVAL (operands[1]) >= 0x10000))" -+ [(set (match_dup 2) -+ (match_dup 3)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 2) -+ (match_dup 4)))] -+ "{ -+ HOST_WIDE_INT i = INTVAL (operands[1]); -+ operands[3] = GEN_INT (i & 0xffffff80); -+ operands[4] = GEN_INT (i & 0x7f); -+ }") -+ -+; If we're not dependent on the state of the condition codes we can construct -+; a 32-bit constant with a movei/movei/shmrg.2 sequence if possible. -+; -+(define_peephole2 -+ [(match_scratch:HI 2 "d") -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 2)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 0) -+ (match_dup 3)) -+ (set (match_dup 2) -+ (match_dup 4)) -+ (parallel -+ [(set (match_dup 0) -+ (ior:SI -+ (ashift:SI (match_dup 0) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 2)))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[4] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+; Exactly the same as the peephole2 preceding except that this targets a -+; general register instead of D register. Hopefully the later optimization -+; passes will notice that the value ended up in a D register first here -+; and eliminate away the other register! -+; -+(define_peephole2 -+ [(match_scratch:SI 2 "d") -+ (match_scratch:HI 3 "d") -+ (set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (match_dup 3)] -+ "(INTVAL (operands[1]) & 0x80000000 -+ && INTVAL (operands[1]) < -0x8000 -+ && peep2_regno_dead_p (0, CC_REGNO))" -+ [(set (match_dup 2) -+ (match_dup 4)) -+ (set (match_dup 3) -+ (match_dup 5)) -+ (parallel -+ [(set (match_dup 2) -+ (ior:SI -+ (ashift:SI (match_dup 2) -+ (const_int 16)) -+ (zero_extend:SI -+ (match_dup 3)))) -+ (clobber (reg:CC CC_REGNO))]) -+ (set (match_dup 0) -+ (match_dup 2))] -+ "{ -+ operands[4] = gen_highpart_mode (HImode, SImode, operands[1]); -+ operands[5] = gen_lowpart (HImode, operands[1]); -+ }") -+ -+(define_insn "movsi_fdpic_got_offset" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (match_operand:SI 1 "ubicom32_fdpic_got_offset_operand" "Y"))] -+ "" -+ "movei\\t%0, %1") -+ -+; The explicit MEM inside the UNSPEC prevents the compiler from moving -+; the load before a branch after a NULL test, or before a store that -+; initializes a function descriptor. -+ -+(define_insn_and_split "load_fdpic_funcdesc" -+ [(set (match_operand:SI 0 "ubicom32_address_register_operand" "=a") -+ (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))] -+ UNSPEC_VOLATILE_LOAD_FDPIC_FUNCDESC))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 0) -+ (mem:SI (match_dup 1)))]) -+ -+; Combiner-generated 32-bit move with the zero flag set accordingly. -+; -+(define_insn "movsi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm, d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=d,rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ lsl.4\\t%1, %0, #0 -+ add.4\\t%1, #0, %0") -+ -+; Combiner-generated 32-bit move with all flags set accordingly. -+; -+(define_insn "movsi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (const_int 0))) -+ (set (match_operand:SI 1 "nonimmediate_operand" "=rm") -+ (match_dup 0))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "add.4\\t%1, #0, %0") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode)" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 0) -+ (match_dup 1))])] -+ "") -+ -+; Combine isn't very good at merging some types of operations so we -+; have to make do with a peephole. It's not as effective but it's better -+; than doing nothing. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (set (match_operand:SI 4 "ubicom32_data_register_operand" "") -+ (match_dup 0))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (set (match_dup 4) -+ (match_dup 1))])] -+ "") -+ -+; Register renaming may make a general reg into a D reg in which case -+; we may be able to simplify a compare. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (parallel -+ [(set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (match_operator 3 "ubicom32_compare_operator" -+ [(match_dup 0) -+ (const_int 0)])) -+ (clobber (match_operand:SI 4 "ubicom32_data_register_operand" ""))])] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && (GET_MODE (operands[2]) == CCWZNmode -+ || GET_MODE (operands[2]) == CCWZmode))" -+ [(parallel -+ [(set (match_dup 2) -+ (match_op_dup 3 -+ [(match_dup 1) -+ (const_int 0)])) -+ (clobber (match_dup 4))])] -+ "") -+ -+(define_insn_and_split "movdi" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") -+ (match_operand:DI 1 "general_operand" "rmi,ri"))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) (match_dup 3)) -+ (set (match_dup 4) (match_dup 5))] -+ "{ -+ rtx dest_low; -+ rtx src_low; -+ -+ dest_low = gen_lowpart (SImode, operands[0]); -+ src_low = gen_lowpart (SImode, operands[1]); -+ -+ if (REG_P (operands[0]) -+ && REG_P (operands[1]) -+ && REGNO (operands[0]) < REGNO (operands[1])) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else if (reg_mentioned_p (dest_low, src_low)) -+ { -+ operands[2] = gen_highpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[4] = dest_low; -+ operands[5] = src_low; -+ } -+ else -+ { -+ operands[2] = dest_low; -+ operands[3] = src_low; -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ }" -+ [(set_attr "length" "8")]) -+ -+; Combiner-generated 64-bit move with all flags set accordingly. -+; -+(define_insn "movdi_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movdi_ccw" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "nonimmediate_operand" "d, m, r") -+ (const_int 0))) -+ (set (match_operand:DI 1 "nonimmediate_operand" "=&rm,rm,!&rm") -+ (match_dup 0)) -+ (clobber (match_scratch:SI 2 "=X, d, d"))] -+ "ubicom32_match_cc_mode(insn, CCWmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[1]); -+ -+ if (ubicom32_data_register_operand (operands[0], VOIDmode)) -+ return \"add.4\\t%4, #0, %3\;addc\\t%6, #0, %5\"; -+ -+ return \"movei\\t%2, #0\;add.4\\t%4, %3, %2\;addc\\t%6, %5, %2\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "movsf" -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!d,*rm") -+ (match_operand:SF 1 "ubicom32_move_operand" "rmF,rmF"))] -+ "" -+ "* -+ { -+ if (GET_CODE (operands[1]) == CONST_DOUBLE) -+ { -+ HOST_WIDE_INT val; -+ REAL_VALUE_TYPE rv; -+ -+ REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); -+ REAL_VALUE_TO_TARGET_SINGLE (rv, val); -+ -+ ubicom32_emit_move_const_int (operands[0], GEN_INT (val)); -+ return \"\"; -+ } -+ -+ return \"move.4\\t%0, %1\"; -+ }") -+ -+(define_insn "zero_extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.1\\t%0, %1") -+ -+(define_insn "zero_extendqisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.1\\t%0, %1, #0") -+ -+(define_insn "zero_extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "move.2\\t%0, %1") -+ -+(define_insn "zero_extendhisi2_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extend:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "shmrg.2\\t%0, %1, #0") -+ -+(define_insn_and_split "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (zero_extend:SI (match_dup 1))) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn_and_split "zero_extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (set (match_dup 3) -+ (const_int 0))] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "extendqihi2" -+ [(set (match_operand:HI 0 "register_operand" "=r") -+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendqisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.1\\t%0, %1") -+ -+(define_insn "extendhisi2" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "ext.2\\t%0, %1") -+ -+(define_insn_and_split "extendsidi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (match_dup 2) -+ (match_dup 1)) -+ (parallel -+ [(set (match_dup 3) -+ (ashiftrt:SI (match_dup 2) -+ (const_int 31))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart (SImode, operands[0]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "bswaphi" -+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswaphisi" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extend:SI -+ (bswap:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI"))))] -+ "(ubicom32_v4)" -+ "swapb.2\\t%0, %1"); -+ -+(define_insn "bswapsi" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (bswap:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "swapb.4\\t%0, %1"); -+ -+(define_insn "tstqi_ext1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.1\\t#0, %0") -+ -+(define_expand "cmpqi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "")))] -+ "(ubicom32_v4)" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "sub1_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:QI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub1_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "nonimmediate_operand" "rm") -+ (match_operand:QI 1 "ubicom32_data_register_operand" "d")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %0, %1") -+ -+(define_insn "sub1_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:QI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI")))] -+ "(ubicom32_v4)" -+ "sub.1\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.1 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:QI 0 "register_operand" "") -+ (match_operand:QI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:QI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "tsthi_ext2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "ext.2\\t#0, %0") -+ -+(define_expand "cmphi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "") -+ (match_operand:HI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? */ -+ if (CONST_INT_P (operands[1])) -+ break; -+ -+ /* Must be a sub.2 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], HImode)) -+ operands[1] = copy_to_mode_reg (HImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "N")))] -+ "" -+ "cmpi\\t%0, %1") -+ -+(define_insn "sub2_ccs" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:HI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "sub2_ccsz_1" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "nonimmediate_operand" "rm") -+ (match_operand:HI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.2\\t#0, %0, %1") -+ -+(define_insn "sub2_ccsz_2" -+ [(set (reg:CCSZ CC_REGNO) -+ (compare:CCSZ (match_operand:HI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI")))] -+ "" -+ "sub.2\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.2 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:HI 0 "register_operand" "") -+ (match_operand:HI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:HI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstsi_lsl4" -+ [(set (match_operand 0 "ubicom32_cc_register_operand" "=r") -+ (match_operator 1 "ubicom32_compare_operator" -+ [(match_operand:SI 2 "nonimmediate_operand" "rm") -+ (const_int 0)]))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "#" -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ [(parallel -+ [(set (match_dup 0) -+ (match_op_dup 1 -+ [(match_dup 2) -+ (const_int 0)])) -+ (clobber (match_dup 3))])] -+ "{ -+ operands[3] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstsi_lsl4_d" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "lsl.4\\t%1, %0, #0") -+ -+; Comparison for equality with -1. -+; -+(define_insn "cmpsi_not4_ccwz" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int -1)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "not.4\\t#0, %0") -+ -+(define_expand "cmpsi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "") -+ (match_operand:SI 1 "ubicom32_compare_operand" "")))] -+ "" -+ "{ -+ do -+ { -+ /* Is this a cmpi? We can't take a memory address as cmpi takes -+ 16-bit operands. */ -+ if (register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[1]) -+ && satisfies_constraint_N (operands[1])) -+ break; -+ -+ /* Must be a sub.4 - if necessary copy an operand into a reg. */ -+ if (! ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ } -+ while (0); -+ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpsi_cmpi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "register_operand" "r") -+ (match_operand 1 "const_int_operand" "N")))] -+ "(satisfies_constraint_N (operands[1]))" -+ "cmpi\\t%0, %1") -+ -+(define_insn "cmpsi_sub4" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "sub.4\\t#0, %0, %1") -+ -+; If we're testing for equality we don't have to worry about reversing conditions. -+; -+(define_insn "cmpsi_sub4_ccwz_1" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %0, %1") -+ -+(define_insn "cmpsi_sub4_ccwz_2" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (match_operand:SI 1 "nonimmediate_operand" "rm")))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "sub.4\\t#0, %1, %0") -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4 more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:SI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn_and_split "tstdi_or4" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0)))] -+ "" -+ "#" -+ "" -+ [(parallel -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_dup 0) -+ (const_int 0))) -+ (clobber (match_dup 1))])] -+ "{ -+ operands[1] = gen_reg_rtx (SImode); -+ }") -+ -+(define_insn "tstdi_or4_d" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ (match_operand:DI 0 "nonimmediate_operand" "rm") -+ (const_int 0))) -+ (clobber (match_operand:SI 1 "ubicom32_data_register_operand" "=d"))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_highpart_mode (SImode, DImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ return \"or.4\\t#0, %2, %3\"; -+ -+ return \"move.4\\t%1, %2\;or.4\\t%1, %3, %1\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "cmpdi" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "")))] -+ "" -+ "{ -+ ubicom32_compare_op0 = operands[0]; -+ ubicom32_compare_op1 = operands[1]; -+ DONE; -+ }") -+ -+(define_insn "cmpdi_sub4subc" -+ [(set (reg CC_REGNO) -+ (compare (match_operand:DI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:DI 1 "ubicom32_data_register_operand" "d")))] -+ "" -+ "* -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart_mode (SImode, DImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ -+ return \"sub.4\\t#0, %2, %3\;subc\\t#0, %4, %5\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+; When the combiner runs it doesn't have any insight into whether or not an argument -+; to a compare is spilled to the stack and therefore can't swap the comparison in -+; an attempt to use sub.4/subc more effectively. We peephole this case here. -+; -+(define_peephole2 -+ [(set (match_operand:DI 0 "register_operand" "") -+ (match_operand:DI 1 "ubicom32_arith_operand" "")) -+ (set (match_operand 2 "ubicom32_cc_register_operand" "") -+ (compare (match_operand:DI 3 "ubicom32_data_register_operand" "") -+ (match_dup 0))) -+ (set (pc) -+ (if_then_else (match_operator 4 "comparison_operator" -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_operand 5 "" "")) -+ (pc)))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ && peep2_regno_dead_p (3, CC_REGNO))" -+ [(set (match_dup 2) -+ (compare (match_dup 1) -+ (match_dup 3))) -+ (set (pc) -+ (if_then_else (match_op_dup 6 -+ [(match_dup 2) -+ (const_int 0)]) -+ (label_ref (match_dup 5)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[6] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[4])), -+ GET_MODE (operands[4]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "btst" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (const_int 1) -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0)))] -+ "" -+ "btst\\t%0, %1") -+ -+(define_insn "bfextu_ccwz_null" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_operand:SI 0 "nonimmediate_operand" "rm") -+ (match_operand 1 "const_int_operand" "M") -+ (const_int 0)) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "" -+ "bfextu\\t%2, %0, %1") -+ -+(define_expand "addqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "addqi3_add1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ add.1\\t%0, %2, %1 -+ add.1\\t%0, %1, %2") -+ -+(define_insn "addqi3_add1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ add.1\\t#0, %1, %0 -+ add.1\\t#0, %0, %1") -+ -+(define_expand "addhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "addhi3_add2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ add.2\\t%0, %2, %1 -+ add.2\\t%0, %1, %2") -+ -+(define_insn "addhi3_add2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ add.2\\t#0, %1, %0 -+ add.2\\t#0, %0, %1") -+ -+(define_expand "addsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_move_operand" "")))] -+ "" -+ "{ -+ ubicom32_expand_addsi3 (operands); -+ DONE; -+ }") -+ -+; We start with an instruction pattern that can do all sorts of interesting -+; things but we split out any uses of lea or pdec instructions because -+; those instructions don't clobber the condition codes. -+; -+(define_insn_and_split "addsi3_1" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm, rm,rm") -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%a, a, a, a, a, d,rm") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ # -+ # -+ # -+ # -+ # -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2" -+ "(reload_completed -+ && ubicom32_address_register_operand (operands[1], GET_MODE (operands[1])))" -+ [(set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "" -+) -+ -+(define_insn "addsi3_1_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (plus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t%0, %2, %1 -+ add.4\\t%0, %1, %2") -+ -+(define_insn "addsi3_1_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ add.4\\t#0, %1, %0 -+ add.4\\t#0, %0, %1") -+ -+(define_insn_and_split "addsi3_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,rm,rm,rm,rm") -+ (plus:SI (match_operand:SI 1 "ubicom32_address_register_operand" "%a, a, a, a, a, a") -+ (match_operand:SI 2 "ubicom32_move_operand" "L, K, J, P, d, n")))] -+ "" -+ "@ -+ lea.4\\t%0, %E2(%1) -+ lea.2\\t%0, %E2(%1) -+ lea.1\\t%0, %E2(%1) -+ pdec\\t%0, %n2(%1) -+ lea.1\\t%0, (%1,%2) -+ #" -+ "(reload_completed -+ && ! satisfies_constraint_L (operands[2]) -+ && ! satisfies_constraint_K (operands[2]) -+ && ! satisfies_constraint_J (operands[2]) -+ && ! satisfies_constraint_P (operands[2]) -+ && ! ubicom32_data_register_operand (operands[2], GET_MODE (operands[2])))" -+ [(set (reg:SI AUX_DATA_REGNO) -+ (match_dup 2)) -+ (set (match_dup 0) -+ (plus:SI (match_dup 1) -+ (reg:SI AUX_DATA_REGNO)))] -+ "" -+) -+ -+(define_insn "lea_2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 2)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.2\\t%0, (%2,%1)") -+ -+(define_insn "lea_4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (plus:SI (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 4)) -+ (match_operand:SI 2 "ubicom32_address_register_operand" "a")))] -+ "" -+ "lea.4\\t%0, (%2,%1)") -+ -+(define_expand "adddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "adddi3_add4addc" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ -+ if (ubicom32_data_register_operand (operands[2], GET_MODE (operands[2]))) -+ return \"add.4\\t%3, %4, %5\;addc\\t%6, %7, %8\"; -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d, d,rmI,rmI, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r,rm, d, m, m") -+ (plus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ -+ if (ubicom32_data_register_operand (operands[1], GET_MODE (operands[1]))) -+ { -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ } -+ else -+ { -+ operands[4] = gen_lowpart (SImode, operands[2]); -+ operands[5] = gen_lowpart (SImode, operands[1]); -+ operands[7] = gen_highpart (SImode, operands[2]); -+ operands[8] = gen_highpart (SImode, operands[1]); -+ } -+ -+ return \"add.4\\t%3, %5, %4\;addc\\t%6, %8, %7\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "adddi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (neg:DI (match_operand:DI 0 "nonimmediate_operand" "%d,rm")) -+ (match_operand:DI 1 "ubicom32_arith_operand" "rmI, d")))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ if (ubicom32_data_register_operand (operands[0], GET_MODE (operands[0]))) -+ { -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart_mode (SImode, DImode, operands[1]); -+ } -+ else -+ { -+ operands[2] = gen_lowpart (SImode, operands[1]); -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_highpart (SImode, operands[1]); -+ operands[5] = gen_highpart (SImode, operands[0]); -+ } -+ -+ return \"add.4\\t#0, %3, %2\;addc\\t#0, %5, %4\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "subqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "") -+ (match_operand:QI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ }") -+ -+(define_insn "subqi3_sub1" -+ [(set (match_operand:QI 0 "memory_operand" "=m") -+ (minus:QI (match_operand:QI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:QI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "sub.1\\t%0, %1, %2") -+ -+(define_expand "subhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "") -+ (match_operand:HI 2 "ubicom32_data_register_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ }") -+ -+(define_insn "subhi3_sub2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (minus:HI (match_operand:HI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:HI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.2\\t%0, %1, %2") -+ -+(define_insn "subsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, %1, %2") -+ -+(define_insn "subsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_data_register_operand" "d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (minus:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "sub.4\\t%0, %1, %2") -+ -+; We construct a 64-bit add from 32-bit operations. Note that we use the -+; & constraint to prevent overlapping registers being allocated. We do -+; allow identical registers though as that won't break anything. -+; -+(define_insn "subdi3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r, d, m") -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,0,rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d,d, 0, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "subdi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (minus:DI (match_operand:DI 1 "ubicom32_arith_operand" "rmI,rmI") -+ (match_operand:DI 2 "ubicom32_data_register_operand" "d, d")) -+ (const_int 0))) -+ (set (match_operand:DI 0 "nonimmediate_operand" "=&r, m") -+ (minus:DI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "* -+ { -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart_mode (SImode, DImode, operands[1]); -+ operands[8] = gen_highpart (SImode, operands[2]); -+ -+ return \"sub.4\\t%3, %4, %5\;subc\\t%6, %7, %8\"; -+ }" -+ [(set_attr "length" "8")]) -+ -+;(define_insn "negqi2" -+; [(set (match_operand:QI 0 "nonimmediate_operand" "=rm") -+; (neg:QI (match_operand:QI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "(ubicom32_v4)" -+; "sub.1\\t%0, #0, %1") -+ -+;(define_insn "neghi2" -+; [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") -+; (neg:HI (match_operand:HI 1 "ubicom32_data_register_operand" "d"))) -+; (clobber (reg:CC CC_REGNO))] -+; "" -+; "sub.2\\t%0, #0, %1") -+ -+(define_insn "negsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (neg:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "sub.4\\t%0, #0, %1") -+ -+(define_insn_and_split "negdi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (neg:DI (match_operand:DI 1 "ubicom32_data_register_operand" "d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 0) -+ (minus:DI (const_int 0) -+ (match_dup 1))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ [(set_attr "length" "8")]) -+ -+(define_insn "umulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ mulu\\t%A0, %2, %1 -+ mulu\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_insn "mulhisi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_lo_register_operand" "=l, l") -+ (mult:SI -+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm, d")))) -+ (clobber (reg:HI ACC0_HI_REGNO)) -+ (clobber (reg:HI ACC1_HI_REGNO))] -+ "" -+ "@ -+ muls\\t%A0, %2, %1 -+ muls\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_expand "mulsi3" -+ [(set (match_operand:SI 0 "ubicom32_acc_hi_register_operand" "") -+ (mult:SI (match_operand:SI 1 "ubicom32_arith_operand" "") -+ (match_operand:SI 2 "ubicom32_arith_operand" "")))] -+ "" -+ "{ -+ if (ubicom32_emit_mult_sequence (operands)) -+ DONE; -+ }") -+ -+(define_insn "umulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ mulu.4\\t%A0, %2, %1 -+ mulu.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_dup 0)) -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (zero_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (zero_extend:DI (match_dup 1)) -+ (zero_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "umulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (zero_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "mulu.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_insn "mulsidi3" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h, h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%d,rm")) -+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm, d"))))] -+ "(ubicom32_v4)" -+ "@ -+ muls.4\\t%A0, %2, %1 -+ muls.4\\t%A0, %1, %2" -+ [(set_attr "type" "mul,mul")]) -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_dup 0)) -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" ""))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "nonimmediate_operand" "")) -+ (set (match_operand:DI 2 "ubicom32_acc_hi_register_operand" "") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 3 "ubicom32_data_register_operand" "")) -+ (sign_extend:DI (match_dup 0))))] -+ "(peep2_reg_dead_p (2, operands[0]) -+ || REGNO (operands[0]) == REGNO (operands[2]) -+ || REGNO (operands[0]) == REGNO (operands[2]) + 1) -+ && ! rtx_equal_p (operands[0], operands[3])" -+ [(set (match_dup 2) -+ (mult:DI -+ (sign_extend:DI (match_dup 1)) -+ (sign_extend:DI (match_dup 3))))] -+ "") -+ -+(define_insn "mulsidi3_const" -+ [(set (match_operand:DI 0 "ubicom32_acc_hi_register_operand" "=h") -+ (mult:DI -+ (sign_extend:DI (match_operand:SI 1 "ubicom32_data_register_operand" "%d")) -+ (match_operand 2 "const_int_operand" "I")))] -+ "(ubicom32_v4 && satisfies_constraint_I (operands[2]))" -+ "muls.4\\t%A0, %2, %1" -+ [(set_attr "type" "mul")]) -+ -+(define_expand "andqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "andqi3_and1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (and:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t%0, %2, %1 -+ and.1\\t%0, %1, %2") -+ -+(define_insn "andqi3_and1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ and.1\\t#0, %1, %0 -+ and.1\\t#0, %0, %1") -+ -+(define_insn "and1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %1, %0") -+ -+(define_insn "and1_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (and:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "and.1\\t#0, %0, %1") -+ -+(define_expand "andhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "andhi3_and2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (and:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t%0, %2, %1 -+ and.2\\t%0, %1, %2") -+ -+(define_insn "andhi3_and2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ and.2\\t#0, %1, %0 -+ and.2\\t#0, %0, %1") -+ -+(define_insn "and2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %1, %0") -+ -+(define_insn "and2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (and:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "and.2\\t#0, %0, %1") -+ -+(define_expand "andsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bfextu? */ -+ if (ubicom32_data_register_operand (operands[0], SImode) -+ && CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2]) + 1) != -1) -+ break; -+ -+ /* Is this a bclr? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (~INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an and.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "andsi3_bfextu" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(satisfies_constraint_O (operands[2]))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%rm") -+ (match_operand:SI 2 "const_int_operand" "O")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "(satisfies_constraint_O (operands[2]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[2]) + 1)); -+ -+ return \"bfextu\\t%0, %1, %3\"; -+ }") -+ -+(define_insn "andsi3_bfextu_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "O")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(satisfies_constraint_O (operands[1]) -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); -+ -+ return \"bfextu\\t%2, %0, %3\"; -+ }") -+ -+(define_insn "andsi3_bclr" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (and:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand:SI 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (~INTVAL (operands[2])) != -1)" -+ "bclr\\t%0, %1, #%D2") -+ -+(define_insn "andsi3_and4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (and:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t%0, %2, %1 -+ and.4\\t%0, %1, %2") -+ -+(define_insn "andsi3_and4_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ and.4\\t#0, %1, %0 -+ and.4\\t#0, %0, %1") -+ -+(define_insn "andsi3_lsr4_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm") -+ (match_operand:SI 1 "const_int_operand" "n")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "(exact_log2 ((~(INTVAL (operands[1]))) + 1) != -1 -+ && ubicom32_match_cc_mode(insn, CCWZmode))" -+ "* -+ { -+ operands[3] = GEN_INT (exact_log2 ((~(INTVAL (operands[1]))) + 1)); -+ -+ return \"lsr.4\\t%2, %0, %3\"; -+ }") -+ -+; We really would like the combiner to recognize this scenario and deal with -+; it but unfortunately it tries to canonicalize zero_extract ops on MEMs -+; into QImode operations and we can't match them in any useful way. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (match_operand:SI 1 "const_int_operand" "")) -+ (set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (and:SI (match_operand:SI 2 "nonimmediate_operand" "") -+ (match_dup 0)) -+ (const_int 0)))] -+ "(exact_log2 (INTVAL (operands[1])) != -1 -+ && peep2_reg_dead_p (2, operands[0]))" -+ [(set (reg:CCWZ CC_REGNO) -+ (compare:CCWZ -+ (zero_extract:SI -+ (match_dup 2) -+ (const_int 1) -+ (match_dup 3)) -+ (const_int 0)))] -+ "{ -+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands[1]))); -+ }") -+ -+(define_expand "anddi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "anddi3_and4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (and:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (and:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "iorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "iorqi3_or1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ or.1\\t%0, %2, %1 -+ or.1\\t%0, %1, %2") -+ -+(define_expand "iorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "iorhi3_or2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.2\\t%0, %2, %1 -+ or.2\\t%0, %1, %2") -+ -+(define_expand "iorsi3" -+ [(parallel -+ [(set (match_operand:SI 0 "nonimmediate_operand" "") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") -+ (match_operand:SI 2 "ubicom32_and_or_si3_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ do -+ { -+ /* Is this a bset? */ -+ if (CONST_INT_P (operands[2]) -+ && exact_log2 (INTVAL (operands[2])) != -1) -+ break; -+ -+ /* Must be an or.4 */ -+ if (!ubicom32_data_register_operand (operands[1], SImode)) -+ operands[1] = copy_to_mode_reg (SImode, operands[1]); -+ -+ if (!ubicom32_arith_operand (operands[2], SImode)) -+ operands[2] = copy_to_mode_reg (SImode, operands[2]); -+ } -+ while (0); -+ }") -+ -+(define_insn "iorsi3_bset" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (ior:SI (match_operand:SI 1 "ubicom32_arith_operand" "%rmI") -+ (match_operand 2 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(exact_log2 (INTVAL (operands[2])) != -1)" -+ "bset\\t%0, %1, #%d2") -+ -+(define_insn "iorsi3_or4" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (ior:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t%0, %2, %1 -+ or.4\\t%0, %1, %2") -+ -+(define_insn "iorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ior:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ or.4\\t#0, %1, %0 -+ or.4\\t#0, %0, %1") -+ -+(define_expand "iordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "iordi3_or4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (ior:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (ior:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_expand "xorqi3" -+ [(parallel -+ [(set (match_operand:QI 0 "memory_operand" "") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") -+ (match_operand:QI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "(ubicom32_v4)" -+ "{ -+ if (!memory_operand (operands[0], QImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (QImode, operands[2]); -+ }") -+ -+(define_insn "xorqi3_xor1" -+ [(set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:QI 0 "memory_operand" "=m, m") -+ (xor:QI (match_dup 1) -+ (match_dup 2)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t%0, %2, %1 -+ xor.1\\t%0, %1, %2") -+ -+(define_insn "xorqi3_xor1_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:QI (match_operand:QI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:QI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "@ -+ xor.1\\t#0, %1, %0 -+ xor.1\\t#0, %0, %1") -+ -+(define_insn "xor1_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0)) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %1, %0") -+ -+(define_insn "xor1_ccwzn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:QI -+ (xor:SI (subreg:SI -+ (match_operand:QI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 3) -+ (const_int 0)))] -+ "(ubicom32_v4 -+ && ubicom32_match_cc_mode(insn, CCSZNmode))" -+ "xor.1\\t#0, %0, %1") -+ -+(define_expand "xorhi3" -+ [(parallel -+ [(set (match_operand:HI 0 "memory_operand" "") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") -+ (match_operand:HI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ if (!memory_operand (operands[0], HImode)) -+ FAIL; -+ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (HImode, operands[2]); -+ }") -+ -+(define_insn "xorhi3_xor2" -+ [(set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:HI 0 "memory_operand" "=m, m") -+ (xor:HI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t%0, %2, %1 -+ xor.2\\t%0, %1, %2") -+ -+(define_insn "xorhi3_xor2_ccszn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:HI (match_operand:HI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:HI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "@ -+ xor.2\\t#0, %1, %0 -+ xor.2\\t#0, %0, %1") -+ -+(define_insn "xor2_ccszn_null_1" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "%d") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rI")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_2" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (match_operand:SI 0 "ubicom32_data_register_operand" "d") -+ (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0)) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %1, %0") -+ -+(define_insn "xor2_ccszn_null_3" -+ [(set (reg CC_REGNO) -+ (compare -+ (subreg:HI -+ (xor:SI (subreg:SI -+ (match_operand:HI 0 "memory_operand" "m") -+ 0) -+ (match_operand:SI 1 "ubicom32_data_register_operand" "d")) -+ 2) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCSZNmode)" -+ "xor.2\\t#0, %0, %1") -+ -+(define_insn "xorsi3" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 2 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") -+ (xor:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t%0, %2, %1 -+ xor.4\\t%0, %1, %2") -+ -+(define_insn "xorsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (xor:SI (match_operand:SI 0 "nonimmediate_operand" "%d,rm") -+ (match_operand:SI 1 "ubicom32_arith_operand" "rmI, d")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "@ -+ xor.4\\t#0, %1, %0 -+ xor.4\\t#0, %0, %1") -+ -+(define_expand "xordi3" -+ [(parallel -+ [(set (match_operand:DI 0 "nonimmediate_operand" "") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") -+ (match_operand:DI 2 "ubicom32_arith_operand" ""))) -+ (clobber (reg:CC CC_REGNO))])] -+ "" -+ "{ -+ /* If we have a non-data reg for operand 1 then prefer that over -+ a CONST_INT in operand 2. */ -+ if (! ubicom32_data_register_operand (operands[1], GET_MODE (operands[1])) -+ && CONST_INT_P (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ -+ if (CONST_INT_P (operands[2]) && ! satisfies_constraint_I (operands[2])) -+ operands[2] = copy_to_mode_reg (DImode, operands[2]); -+ }") -+ -+(define_insn_and_split "xordi3_xor4" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,&r, d,rm, m, m") -+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%d,rm, 0, 0, d,rm") -+ (match_operand:DI 2 "ubicom32_arith_operand" "rmI, d,rmI, d,rmI, d"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "reload_completed" -+ [(parallel [(set (match_dup 3) -+ (xor:SI (match_dup 4) -+ (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 6) -+ (xor:SI (match_dup 7) -+ (match_dup 8))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[3] = gen_lowpart (SImode, operands[0]); -+ operands[4] = gen_lowpart (SImode, operands[1]); -+ operands[5] = gen_lowpart (SImode, operands[2]); -+ operands[6] = gen_highpart (SImode, operands[0]); -+ operands[7] = gen_highpart (SImode, operands[1]); -+ operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -+ }" -+ [(set_attr "length" "8")]) -+ -+(define_insn "not2_2" -+ [(set (match_operand:HI 0 "memory_operand" "=m") -+ (subreg:HI -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ 2)) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.2\\t%0, %1") -+ -+(define_insn "one_cmplsi2" -+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") -+ (not:SI (match_dup 1)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t%0, %1") -+ -+(define_insn "one_cmplsi2_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (not:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI")) -+ (const_int 0)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "not.4\\t#0, %0") -+ -+(define_insn_and_split "one_cmpldi2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=&rm") -+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "rmI0"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "#" -+ "" -+ [(parallel [(set (match_dup 2) -+ (not:SI (match_dup 3))) -+ (clobber (reg:CC CC_REGNO))]) -+ (parallel [(set (match_dup 4) -+ (not:SI (match_dup 5))) -+ (clobber (reg:CC CC_REGNO))])] -+ "{ -+ operands[2] = gen_lowpart (SImode, operands[0]); -+ operands[3] = gen_lowpart (SImode, operands[1]); -+ operands[4] = gen_highpart (SImode, operands[0]); -+ operands[5] = gen_highpart (SImode, operands[1]); -+ }" -+ [(set_attr "length" "8")]) -+ -+; Conditional jump instructions -+ -+(define_expand "beq" -+ [(set (pc) -+ (if_then_else (eq (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (EQ, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bne" -+ [(set (pc) -+ (if_then_else (ne (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (NE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgt" -+ [(set (pc) -+ (if_then_else (gt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "ble" -+ [(set (pc) -+ (if_then_else (le (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bge" -+ [(set (pc) -+ (if_then_else (ge (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GE, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "blt" -+ [(set (pc) -+ (if_then_else (lt (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LT, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgtu" -+ [(set (pc) -+ (if_then_else (gtu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bleu" -+ [(set (pc) -+ (if_then_else (leu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (GEU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_expand "bltu" -+ [(set (pc) -+ (if_then_else (ltu (match_dup 1) -+ (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "{ -+ operands[1] = ubicom32_gen_compare_reg (LTU, ubicom32_compare_op0, -+ ubicom32_compare_op1); -+ }") -+ -+(define_insn "jcc" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "" -+ "* -+ { -+ ubicom32_output_cond_jump (insn, operands[1], operands[0]); -+ return \"\"; -+ }") -+ -+; Reverse branch - reverse our comparison condition so that we can -+; branch in the opposite sense. -+; -+(define_insn_and_split "jcc_reverse" -+ [(set (pc) -+ (if_then_else (match_operator 1 "comparison_operator" -+ [(match_operand 2 "ubicom32_cc_register_operand" "") -+ (const_int 0)]) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "" -+ "#" -+ "reload_completed" -+ [(set (pc) -+ (if_then_else (match_dup 3) -+ (label_ref (match_dup 0)) -+ (pc)))] -+ "{ -+ rtx cc_reg; -+ -+ cc_reg = gen_rtx_REG (GET_MODE (operands[2]), CC_REGNO); -+ operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), -+ GET_MODE (operands[1]), -+ cc_reg, -+ const0_rtx); -+ }") -+ -+(define_insn "jump" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "" -+ "jmpt\\t%l0") -+ -+(define_expand "indirect_jump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "register_operand" "")) -+ (clobber (match_dup 0))])] -+ "" -+ "") -+ -+(define_insn "indirect_jump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "register_operand" "a")) -+ (clobber (match_dup 0))] -+ "" -+ "calli\\t%0,0(%0)") -+ -+; Program Space: The table contains instructions, typically jumps. -+; CALL An,TABLE_SIZE(PC) ;An = Jump Table Base Address. -+; ;An -> Here. -+; LEA Ak, (An,Dn) ;Ak -> Table Entry -+; JMP/CALL (Ak) -+ -+(define_expand "tablejump" -+ [(parallel [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "")) -+ (use (label_ref (match_operand 1 "" "")))])] -+ "" -+ "") -+ -+(define_insn "tablejump_internal" -+ [(set (pc) -+ (match_operand:SI 0 "nonimmediate_operand" "rm")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "" -+ "ret\\t%0") -+ -+; Call subroutine with no return value. -+; -+(define_expand "call" -+ [(call (match_operand:QI 0 "general_operand" "") -+ (match_operand:SI 1 "general_operand" ""))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[0], 0), VOIDmode)) -+ XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_1" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g"))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_slow" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ moveai\\ta5, #%%hi(%C0)\;calli\\ta5, %%lo(%C0)(a5)") -+ -+(define_insn "call_fast" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%0) -+ call\\ta5, %C0") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_fdpic" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(call (mem:QI (match_dup 0)) -+ (match_dup 1)) -+ (use (match_dup 2)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_fdpic_clobber" -+ [(call (mem:QI (match_operand:SI 0 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 1 "general_operand" "g,g")) -+ (use (match_operand:SI 2 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%0)\;move.4\\t%2, 4(%0)\;calli\\ta5, 0(a5) -+ call\\ta5, %C0") -+ -+; Call subroutine, returning value in operand 0 -+; (which must be a hard register). -+; -+(define_expand "call_value" -+ [(set (match_operand 0 "" "") -+ (call (match_operand:QI 1 "general_operand" "") -+ (match_operand:SI 2 "general_operand" "")))] -+ "" -+ "{ -+ if (TARGET_FDPIC) -+ { -+ ubicom32_expand_call_value_fdpic (operands); -+ DONE; -+ } -+ -+ if (! ubicom32_call_address_operand (XEXP (operands[1], 0), VOIDmode)) -+ XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); -+ }") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_1" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g")))] -+ "! TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_slow" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && ! TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ moveai\\ta5, #%%hi(%C1)\;calli\\ta5, %%lo(%C1)(a5)") -+ -+(define_insn "call_value_fast" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (clobber (reg:SI LINK_REGNO))] -+ "(! TARGET_FDPIC && TARGET_FASTCALL)" -+ "@ -+ calli\\ta5, 0(%1) -+ call\\ta5, %C1") -+ -+; We expand to a simple form that doesn't clobber the link register and -+; then split to a form that does. This allows the RTL optimizers that -+; run before the splitter to have the opportunity to eliminate the call -+; without marking A5 as being clobbered and this in turn avoids saves -+; and returns in a number of cases. -+; -+(define_insn_and_split "call_value_fdpic" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z"))] -+ "TARGET_FDPIC" -+ "#" -+ "" -+ [(parallel -+ [(set (match_dup 0) -+ (call (mem:QI (match_dup 1)) -+ (match_dup 2))) -+ (use (match_dup 3)) -+ (clobber (reg:SI LINK_REGNO))])] -+ "") -+ -+(define_insn "call_value_fdpic_clobber" -+ [(set (match_operand 0 "register_operand" "=r,r") -+ (call (mem:QI (match_operand:SI 1 "ubicom32_call_address_operand" "a,S")) -+ (match_operand:SI 2 "general_operand" "g,g"))) -+ (use (match_operand:SI 3 "ubicom32_fdpic_operand" "Z,Z")) -+ (clobber (reg:SI LINK_REGNO))] -+ "TARGET_FDPIC" -+ "@ -+ move.4\\ta5, 0(%1)\;move.4\\t%3, 4(%1)\;calli\\ta5, 0(a5) -+ call\\ta5, %C1") -+ -+(define_expand "untyped_call" -+ [(parallel [(call (match_operand 0 "" "") -+ (const_int 0)) -+ (match_operand 1 "" "") -+ (match_operand 2 "" "")])] -+ "" -+ "{ -+ int i; -+ -+ emit_call_insn (gen_call (operands[0], const0_rtx)); -+ -+ for (i = 0; i < XVECLEN (operands[2], 0); i++) -+ { -+ rtx set = XVECEXP (operands[2], 0, i); -+ emit_move_insn (SET_DEST (set), SET_SRC (set)); -+ } -+ DONE; -+ }") -+ -+(define_insn "lsl1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.1\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xff << INTVAL (operands[2])))" -+ "lsl.1\\t%0, %1, %2") -+ -+(define_insn "lsl2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsl.2\\t%0, %1, %2") -+ -+; The combiner gets rather creative about left shifts of sub-word memory -+; operands because it's uncertain about whether the memory is sign or -+; zero extended. It only wants zero-extended behaviour and so throws -+; in an extra and operation. -+; -+(define_insn "lsl2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (and:SI -+ (ashift:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "const_int_operand" "M")) -+ (match_operand:SI 3 "const_int_operand" "n"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && INTVAL (operands[3]) == (0xffff << INTVAL (operands[2])))" -+ "lsl.2\\t%0, %1, %2") -+ -+(define_insn "ashlsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashift:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%0, %1, %2") -+ -+(define_insn "lshlsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashift:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsl.4\\t%2, %0, %1") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "asr.1\\t%0, %1, %3") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "asr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (sign_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "asr.2\\t%0, %1, %3") -+ -+(define_insn "ashrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ashiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%0, %1, %2") -+ -+(define_insn "ashrsi3_ccwzn_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (ashiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmJ") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZNmode)" -+ "asr.4\\t%2, %0, %1") -+ -+(define_insn "lsr1_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:QI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.1\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr1_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 8))" -+ "lsr.1\\t%0, %1, %3") -+ -+(define_insn "lsr2_1" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (subreg:SI -+ (match_operand:HI 1 "memory_operand" "m") -+ 0) -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4)" -+ "lsr.2\\t%0, %1, %2") -+ -+; The combiner finds this canonical form for what is in essence a right -+; shift. -+; -+(define_insn "lsr2_2" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (zero_extract:SI (match_operand:HI 1 "memory_operand" "m") -+ (match_operand:SI 2 "const_int_operand" "M") -+ (match_operand:SI 3 "const_int_operand" "M"))) -+ (clobber (reg:CC CC_REGNO))] -+ "(ubicom32_v4 -+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 16))" -+ "lsr.2\\t%0, %1, %3") -+ -+(define_insn "lshrsi3" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM"))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 1 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 2 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (lshiftrt:SI (match_dup 1) -+ (match_dup 2)))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%0, %1, %2") -+ -+(define_insn "lshrsi3_ccwz_null" -+ [(set (reg CC_REGNO) -+ (compare -+ (lshiftrt:SI (match_operand:SI 0 "ubicom32_arith_operand" "rmI") -+ (match_operand:SI 1 "ubicom32_arith_operand" "dM")) -+ (const_int 0))) -+ (clobber (match_scratch:SI 2 "=d"))] -+ "ubicom32_match_cc_mode(insn, CCWZmode)" -+ "lsr.4\\t%2, %0, %1") -+ -+(define_expand "prologue" -+ [(const_int 0)] -+ "" -+ "{ -+ ubicom32_expand_prologue (); -+ DONE; -+ }") -+ -+(define_expand "epilogue" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "return" -+ [(return)] -+ "" -+ "{ -+ ubicom32_expand_epilogue (); -+ DONE; -+ }") -+ -+(define_expand "_eh_return" -+ [(use (match_operand:SI 0 "register_operand" "r")) -+ (use (match_operand:SI 1 "register_operand" "r"))] -+ "" -+ "{ -+ ubicom32_expand_eh_return (operands); -+ DONE; -+ }") -+ -+; XXX - it looks almost certain that we could make return_internal use a Dn -+; register too. In that instance we'd have to use a ret instruction -+; rather than a calli but it might save cycles. -+; -+(define_insn "return_internal" -+ [(const_int 2) -+ (return) -+ (use (match_operand:SI 0 "ubicom32_mem_or_address_register_operand" "rm"))] -+ "" -+ "* -+ { -+ if (REG_P (operands[0]) && REGNO (operands[0]) == LINK_REGNO -+ && ubicom32_can_use_calli_to_ret) -+ return \"calli\\t%0, 0(%0)\"; -+ -+ return \"ret\\t%0\"; -+ }") -+ -+(define_insn "return_from_post_modify_sp" -+ [(parallel -+ [(const_int 2) -+ (return) -+ (use (mem:SI (post_modify:SI -+ (reg:SI SP_REGNO) -+ (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 0 "const_int_operand" "n")))))])] -+ "INTVAL (operands[0]) >= 4 && INTVAL (operands[0]) <= 7 * 4" -+ "ret\\t(sp)%E0++") -+ -+;(define_insn "eh_return_internal" -+; [(const_int 4) -+; (return) -+; (use (reg:SI 34))] -+; "" -+; "ret\\ta2") -+ -+; No operation, needed in case the user uses -g but not -O. -+(define_expand "nop" -+ [(const_int 0)] -+ "" -+ "") -+ -+(define_insn "nop_internal" -+ [(const_int 0)] -+ "" -+ "nop") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg1_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 256)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg1_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 8)) -+ (zero_extend:SI -+ (match_operand:QI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.1\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and add operations. -+; The canonical form that the combiner wants to use appears to be multiplies -+; instead of shifts even if the compiled sources use shifts. -+; -+(define_insn "shmrg2_add" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (plus:SI -+ (mult:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 65536)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; The combiner will generate this pattern given shift and or operations. -+; -+(define_insn "shmrg2_ior" -+ [(set (match_operand:SI 0 "ubicom32_data_register_operand" "=d") -+ (ior:SI -+ (ashift:SI (match_operand:SI 1 "ubicom32_data_register_operand" "d") -+ (const_int 16)) -+ (zero_extend:SI -+ (match_operand:HI 2 "ubicom32_arith_operand" "rmI")))) -+ (clobber (reg:CC CC_REGNO))] -+ "" -+ "shmrg.2\\t%0, %2, %1") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a zero-extended load of that useful -+; 16 bits direct from the stack where possible. -+; -+ -+; XXX - do these peephole2 ops actually work after the CCmode conversion? -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:HI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 16 bits. We turn this into a 16-bit load of that useful -+; 16 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:HI 2 "nonimmediate_operand" "") -+ (match_operand:HI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 252 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:HI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 2); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into a zero-extended load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:SI 2 "nonimmediate_operand" "") -+ (zero_extend:SI (match_operand:QI 3 "register_operand" "")))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (zero_extend:SI (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4)))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ -+; Match the case where we load a word from the stack but then discard the -+; upper 24 bits. We turn this into an 8-bit load of that useful -+; 8 bits direct from the stack where possible. -+; -+(define_peephole2 -+ [(set (match_operand:SI 0 "register_operand" "") -+ (mem:SI (plus:SI (reg:SI SP_REGNO) -+ (match_operand:SI 1 "const_int_operand" "")))) -+ (set (match_operand:QI 2 "nonimmediate_operand" "") -+ (match_operand:QI 3 "register_operand" ""))] -+ "(INTVAL (operands[1]) <= 124 -+ && REGNO (operands[3]) == REGNO (operands[0]) -+ && ((peep2_reg_dead_p (2, operands[0]) -+ && ! reg_mentioned_p (operands[0], operands[2])) -+ || rtx_equal_p (operands[0], operands[2])))" -+ [(set (match_dup 2) -+ (mem:QI (plus:SI (reg:SI SP_REGNO) -+ (match_dup 4))))] -+ "{ -+ operands[4] = GEN_INT (INTVAL (operands[1]) + 3); -+ }") -+ ---- /dev/null -+++ b/gcc/config/ubicom32/ubicom32.opt -@@ -0,0 +1,27 @@ -+mdebug-address -+Target RejectNegative Report Undocumented Mask(DEBUG_ADDRESS) -+Debug addresses -+ -+mdebug-context -+Target RejectNegative Report Undocumented Mask(DEBUG_CONTEXT) -+Debug contexts -+ -+march= -+Target Report Var(ubicom32_arch_name) Init("ubicom32v4") Joined -+Specify the name of the target architecture -+ -+mfdpic -+Target Report Mask(FDPIC) -+Enable Function Descriptor PIC mode -+ -+minline-plt -+Target Report Mask(INLINE_PLT) -+Enable inlining of PLT in function calls -+ -+mfastcall -+Target Report Mask(FASTCALL) -+Enable default fast (call) calling sequence for smaller applications -+ -+mipos-abi -+Target Report Mask(IPOS_ABI) -+Enable the ipOS ABI in which D10-D13 are caller-clobbered ---- /dev/null -+++ b/gcc/config/ubicom32/uclinux.h -@@ -0,0 +1,67 @@ -+/* Definitions of target machine for Ubicom32-uclinux -+ -+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009 Free Software Foundation, Inc. -+ Contributed by Ubicom, Inc. -+ -+ This file is part of GCC. -+ -+ GCC is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published -+ by the Free Software Foundation; either version 3, or (at your -+ option) any later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GCC; see the file COPYING3. If not see -+ . */ -+ -+/* Don't assume anything about the header files. */ -+#define NO_IMPLICIT_EXTERN_C -+ -+#undef LIB_SPEC -+#define LIB_SPEC \ -+ "%{pthread:-lpthread} " \ -+ "%{!shared:%{!symbolic: -lc}} " -+ -+ -+#undef LINK_GCC_C_SEQUENCE_SPEC -+#define LINK_GCC_C_SEQUENCE_SPEC \ -+ "%{!shared:--start-group} %G %L %{!shared:--end-group}%{shared:%G} " -+ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC \ -+ "%{!shared: crt1%O%s}" \ -+ " crti%O%s crtbegin%O%s" -+ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+/* This macro applies on top of OBJECT_FORMAT_ELF and indicates that -+ we want to support both flat and ELF output. */ -+#define OBJECT_FORMAT_FLAT -+ -+#undef DRIVER_SELF_SPECS -+#define DRIVER_SELF_SPECS \ -+ "%{!mno-fastcall:-mfastcall}" -+ -+/* taken from linux.h */ -+/* The GNU C++ standard library requires that these macros be defined. */ -+#undef CPLUSPLUS_CPP_SPEC -+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" -+ -+#define TARGET_OS_CPP_BUILTINS() \ -+ do { \ -+ builtin_define_std ("__UBICOM32__"); \ -+ builtin_define_std ("__ubicom32__"); \ -+ builtin_define ("__gnu_linux__"); \ -+ builtin_define_std ("linux"); \ -+ builtin_define_std ("unix"); \ -+ builtin_assert ("system=linux"); \ -+ builtin_assert ("system=unix"); \ -+ builtin_assert ("system=posix"); \ -+ } while (0) ---- /dev/null -+++ b/gcc/config/ubicom32/xm-ubicom32.h -@@ -0,0 +1,36 @@ -+/* Configuration for Ubicom's Ubicom32 architecture. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software -+ Foundation, Inc. -+ Contributed by Ubicom Inc. -+ -+This file is part of GNU CC. -+ -+GNU CC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GNU CC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GNU CC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* #defines that need visibility everywhere. */ -+#define FALSE 0 -+#define TRUE 1 -+ -+/* This describes the machine the compiler is hosted on. */ -+#define HOST_BITS_PER_CHAR 8 -+#define HOST_BITS_PER_SHORT 16 -+#define HOST_BITS_PER_INT 32 -+#define HOST_BITS_PER_LONG 32 -+#define HOST_BITS_PER_LONGLONG 64 -+ -+/* Arguments to use with `exit'. */ -+#define SUCCESS_EXIT_CODE 0 -+#define FATAL_EXIT_CODE 33 ---- a/gcc/config.gcc -+++ b/gcc/config.gcc -@@ -2503,6 +2503,34 @@ tilepro-*-linux*) - c_target_objs="tilepro-c.o" - cxx_target_objs="tilepro-c.o" - ;; -+ubicom32-*-elf) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h" # still need dbxelf.h elfos.h -+ tmake_file=ubicom32/t-ubicom32 -+ ;; -+ubicom32-*-uclinux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h ubicom32/uclinux.h" # still need dbxelf.h elfos.h linux.h -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_options="${extra_options} linux.opt" -+ tmake_file=ubicom32/t-ubicom32-uclinux -+ use_collect2=no -+ ;; -+ubicom32-*-linux-uclibc) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; -+ubicom32-*-linux*) -+ xm_file=ubicom32/xm-ubicom32.h -+ tm_file="${tm_file} ubicom32/elf.h linux.h ubicom32/linux.h" # still need dbxelf.h elfos.h -+ tmake_file="t-slibgcc-elf-ver ubicom32/t-ubicom32-linux" -+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1" -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ use_collect2=no -+ ;; - v850*-*-*) - case ${target} in - v850e2v3-*-*) ---- a/libgcc/config.host -+++ b/libgcc/config.host -@@ -1098,6 +1098,15 @@ tilepro-*-linux*) - tmake_file="${tmake_file} tilepro/t-crtstuff t-softfp-sfdf t-softfp tilepro/t-tilepro" - md_unwind_header=tilepro/linux-unwind.h - ;; -+ubicom32*-*-elf*) -+ ;; -+ubicom32*-*-uclinux*) -+ ;; -+ubicom32*-*-linux*) -+ # No need to build crtbeginT.o on uClibc systems. Should probably -+ # be moved to the OS specific section above. -+ extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" -+ ;; - v850*-*-*) - tmake_file="v850/t-v850 t-fdpbit" - ;; diff --git a/toolchain/kernel-headers/Makefile b/toolchain/kernel-headers/Makefile index 7f0962ef9d..9427f82c7a 100644 --- a/toolchain/kernel-headers/Makefile +++ b/toolchain/kernel-headers/Makefile @@ -70,15 +70,6 @@ define Host/Configure/post/cris $(SED) '/#include /d' $(BUILD_DIR_TOOLCHAIN)/linux-dev/include/asm/user.h endef -define Host/Configure/post/ubicom32 - $(CP) \ - $(HOST_BUILD_DIR)/arch/ubicom32/include/asm/elf.h \ - $(HOST_BUILD_DIR)/arch/ubicom32/include/asm/user.h \ - $(HOST_BUILD_DIR)/arch/ubicom32/include/asm/page.h \ - $(HOST_BUILD_DIR)/arch/ubicom32/include/asm/page_offset.h \ - $(BUILD_DIR_TOOLCHAIN)/linux-dev/include/asm/ -endef - define Host/Configure/post/mips $(call Host/Configure/lzma) endef diff --git a/toolchain/kernel-headers/patches-2.6.30/100-ubicom32_headers.patch b/toolchain/kernel-headers/patches-2.6.30/100-ubicom32_headers.patch deleted file mode 100644 index 49cde88c39..0000000000 --- a/toolchain/kernel-headers/patches-2.6.30/100-ubicom32_headers.patch +++ /dev/null @@ -1,4852 +0,0 @@ ---- /dev/null -+++ b/arch/ubicom32/include/asm/a.out.h -@@ -0,0 +1,47 @@ -+/* -+ * arch/ubicom32/include/asm/a.out.h -+ * Definitions for Ubicom32 a.out executable format. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_A_OUT_H -+#define _ASM_UBICOM32_A_OUT_H -+ -+struct exec -+{ -+ unsigned long a_info; /* Use macros N_MAGIC, etc for access */ -+ unsigned a_text; /* length of text, in bytes */ -+ unsigned a_data; /* length of data, in bytes */ -+ unsigned a_bss; /* length of uninitialized data area for file, in bytes */ -+ unsigned a_syms; /* length of symbol table data in file, in bytes */ -+ unsigned a_entry; /* start address */ -+ unsigned a_trsize; /* length of relocation info for text, in bytes */ -+ unsigned a_drsize; /* length of relocation info for data, in bytes */ -+}; -+ -+#define N_TRSIZE(a) ((a).a_trsize) -+#define N_DRSIZE(a) ((a).a_drsize) -+#define N_SYMSIZE(a) ((a).a_syms) -+ -+#endif /* _ASM_UBICOM32_A_OUT_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/auxvec.h -@@ -0,0 +1,32 @@ -+/* -+ * arch/ubicom32/include/asm/auxvec.h -+ * Symbolic values for the entries in the auxiliary table -+ * put on the initial stack. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_AUXVEC_H -+#define _ASM_UBICOM32_AUXVEC_H -+ -+#endif /* _ASM_UBICOM32_AUXVEC_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/bitops.h -@@ -0,0 +1,41 @@ -+/* -+ * arch/ubicom32/include/asm/bitops.h -+ * Bit manipulation definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_BITOPS_H -+#define _ASM_UBICOM32_BITOPS_H -+ -+/* -+ * Copyright 1992, Linus Torvalds. -+ */ -+ -+#include -+#include /* swab32 */ -+ -+#include -+#include -+ -+#endif /* _ASM_UBICOM32_BITOPS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/board.h -@@ -0,0 +1,34 @@ -+/* -+ * arch/ubicom32/include/asm/board.h -+ * Board init and revision definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_BOARD_H -+#define _ASM_UBICOM32_BOARD_H -+ -+extern const char *board_get_revision(void); -+extern void __init board_init(void); -+ -+#endif /* _ASM_UBICOM32_BOARD_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/byteorder.h -@@ -0,0 +1,35 @@ -+/* -+ * arch/ubicom32/include/asm/byteorder.h -+ * Byte order swapping utility routines. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_BYTEORDER_H -+#define _ASM_UBICOM32_BYTEORDER_H -+ -+#include -+#include -+ -+#endif /* _ASM_UBICOM32_BYTEORDER_H */ -+ ---- /dev/null -+++ b/arch/ubicom32/include/asm/elf.h -@@ -0,0 +1,167 @@ -+/* -+ * arch/ubicom32/include/asm/elf.h -+ * Definitions for elf executable format for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_ELF_H -+#define _ASM_UBICOM32_ELF_H -+ -+/* -+ * ELF register definitions.. -+ */ -+ -+#include -+#include -+ -+/* -+ * Processor specific flags for the ELF header e_flags field. -+ */ -+#define EF_UBICOM32_V3 0x00000001 /* -fmarch=ubicom32v3 */ -+#define EF_UBICOM32_V4 0x00000002 /* -fmarch=ubicom32v4 */ -+#define EF_UBICOM32_PIC 0x80000000 /* -fpic */ -+#define EF_UBICOM32_FDPIC 0x40000000 /* -mfdpic */ -+ -+/* -+ * Ubicom32 ELF relocation types -+ */ -+#define R_UBICOM32_NONE 0 -+#define R_UBICOM32_16 1 -+#define R_UBICOM32_32 2 -+#define R_UBICOM32_LO16 3 -+#define R_UBICOM32_HI16 4 -+#define R_UBICOM32_21_PCREL 5 -+#define R_UBICOM32_24_PCREL 6 -+#define R_UBICOM32_HI24 7 -+#define R_UBICOM32_LO7_S 8 -+#define R_UBICOM32_LO7_2_S 9 -+#define R_UBICOM32_LO7_4_S 10 -+#define R_UBICOM32_LO7_D 11 -+#define R_UBICOM32_LO7_2_D 12 -+#define R_UBICOM32_LO7_4_D 13 -+#define R_UBICOM32_32_HARVARD 14 -+#define R_UBICOM32_LO7_CALLI 15 -+#define R_UBICOM32_LO16_CALLI 16 -+#define R_UBICOM32_GOT_HI24 17 -+#define R_UBICOM32_GOT_LO7_S 18 -+#define R_UBICOM32_GOT_LO7_2_S 19 -+#define R_UBICOM32_GOT_LO7_4_S 20 -+#define R_UBICOM32_GOT_LO7_D 21 -+#define R_UBICOM32_GOT_LO7_2_D 22 -+#define R_UBICOM32_GOT_LO7_4_D 23 -+#define R_UBICOM32_FUNCDESC_GOT_HI24 24 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_S 25 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_2_S 26 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_4_S 27 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_D 28 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_2_D 29 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_4_D 30 -+#define R_UBICOM32_GOT_LO7_CALLI 31 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_CALLI 32 -+#define R_UBICOM32_FUNCDESC_VALUE 33 -+#define R_UBICOM32_FUNCDESC 34 -+#define R_UBICOM32_GOTOFFSET_LO 35 -+#define R_UBICOM32_GOTOFFSET_HI 36 -+#define R_UBICOM32_FUNCDESC_GOTOFFSET_LO 37 -+#define R_UBICOM32_FUNCDESC_GOTOFFSET_HI 38 -+#define R_UBICOM32_GNU_VTINHERIT 200 -+#define R_UBICOM32_GNU_VTENTRY 201 -+ -+typedef unsigned long elf_greg_t; -+ -+#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) -+typedef elf_greg_t elf_gregset_t[ELF_NGREG]; -+ -+typedef struct user_ubicom32fp_struct elf_fpregset_t; -+ -+/* -+ * This is used to ensure we don't load something for the wrong architecture. -+ */ -+#define elf_check_arch(x) ((x)->e_machine == EM_UBICOM32) -+ -+#define elf_check_fdpic(x) ((x)->e_flags & EF_UBICOM32_FDPIC) -+ -+#define elf_check_const_displacement(x) ((x)->e_flags & EF_UBICOM32_PIC) -+ -+/* -+ * These are used to set parameters in the core dumps. -+ */ -+#define ELF_CLASS ELFCLASS32 -+#define ELF_DATA ELFDATA2MSB -+#define ELF_ARCH EM_UBICOM32 -+ -+/* For SVR4/m68k the function pointer to be registered with `atexit' is -+ passed in %a1. Although my copy of the ABI has no such statement, it -+ is actually used on ASV. */ -+#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 -+ -+#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, \ -+ _dynamic_addr) \ -+ do { \ -+ _regs->dn[1] = _exec_map_addr; \ -+ _regs->dn[2] = _interp_map_addr; \ -+ _regs->dn[3] = _dynamic_addr; \ -+ _regs->an[1] = 0; /* dl_fini will be set by ldso */ \ -+ } while (0) -+ -+#define USE_ELF_CORE_DUMP -+#define ELF_EXEC_PAGESIZE 4096 -+ -+#ifdef __KERNEL__ -+#ifdef CONFIG_UBICOM32_V4 -+#define ELF_FDPIC_CORE_EFLAGS (EF_UBICOM32_FDPIC | EF_UBICOM32_V4) -+#elif defined CONFIG_UBICOM32_V3 -+#define ELF_FDPIC_CORE_EFLAGS (EF_UBICOM32_FDPIC | EF_UBICOM32_V3) -+#else -+#error Unknown/Unsupported ubicom32 architecture. -+#endif -+#endif -+ -+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical -+ use of this is to invoke "./ld.so someprog" to test out a new version of -+ the loader. We need to make sure that it is out of the way of the program -+ that it will "exec", and that there is sufficient room for the brk. */ -+ -+#define ELF_ET_DYN_BASE 0xD0000000UL -+ -+/* -+ * For Ubicom32, the elf_gregset_t and struct pt_regs are the same size -+ * data structure so a copy is performed instead of providing the -+ * ELF_CORE_COPY_REGS macro. -+ */ -+ -+/* This yields a mask that user programs can use to figure out what -+ instruction set this cpu supports. */ -+ -+#define ELF_HWCAP (0) -+ -+/* This yields a string that ld.so will use to load implementation -+ specific libraries for optimization. This is more specific in -+ intent than poking at uname or /proc/cpuinfo. */ -+ -+#define ELF_PLATFORM (NULL) -+ -+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) -+ -+#endif /* _ASM_UBICOM32_ELF_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/errno.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/errno.h -+ * Generic errno.h for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_ERRNO_H -+#define _ASM_UBICOM32_ERRNO_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_ERRNO_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/fcntl.h -@@ -0,0 +1,38 @@ -+/* -+ * arch/ubicom32/include/asm/fcntl.h -+ * File control bit definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_FCNTL_H -+#define _ASM_UBICOM32_FCNTL_H -+ -+#define O_DIRECTORY 040000 /* must be a directory */ -+#define O_NOFOLLOW 0100000 /* don't follow links */ -+#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ -+#define O_LARGEFILE 0400000 -+ -+#include -+ -+#endif /* _ASM_UBICOM32_FCNTL_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/flat.h -@@ -0,0 +1,73 @@ -+/* -+ * arch/ubicom32/include/asm/flat.h -+ * Definitions to support flat-format executables. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+ -+#ifndef _ASM_UBICOM32_FLAT_H -+#define _ASM_UBICOM32_FLAT_H -+ -+#define ARCH_FLAT_ALIGN 0x80 -+#define ARCH_FLAT_ALIGN_TEXT 1 -+ -+#define R_UBICOM32_32 2 -+#define R_UBICOM32_HI24 7 -+#define R_UBICOM32_LO7_S 8 -+#define R_UBICOM32_LO7_2_S 9 -+#define R_UBICOM32_LO7_4_S 10 -+#define R_UBICOM32_LO7_D 11 -+#define R_UBICOM32_LO7_2_D 12 -+#define R_UBICOM32_LO7_4_D 13 -+#define R_UBICOM32_LO7_CALLI 15 -+#define R_UBICOM32_LO16_CALLI 16 -+ -+extern void ubicom32_flat_put_addr_at_rp(unsigned long *rp, u32_t val, u32_t rval, unsigned long *p); -+extern unsigned long ubicom32_flat_get_addr_from_rp(unsigned long *rp, u32_t relval, u32_t flags, unsigned long *p); -+ -+#define flat_stack_align(sp) /* nothing needed */ -+#define flat_argvp_envp_on_stack() 1 -+#define flat_old_ram_flag(flags) (flags) -+#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) -+#define flat_get_addr_from_rp(rp, relval, flags, p) (ubicom32_flat_get_addr_from_rp(rp, relval,flags, p)) -+#define flat_put_addr_at_rp(rp, val, relval) do {ubicom32_flat_put_addr_at_rp(rp, val, relval, &persistent);} while(0) -+#define flat_get_relocate_addr(rel) ((persistent) ? (persistent & 0x07ffffff) : (rel & 0x07ffffff)) -+ -+static inline int flat_set_persistent(unsigned int relval, unsigned long *p) -+{ -+ if (*p) { -+ return 0; -+ } else { -+ if ((relval >> 27) != R_UBICOM32_32) { -+ /* -+ * Something other than UBICOM32_32. The next entry has the relocation. -+ */ -+ *p = relval; -+ return 1; -+ } -+ } -+ return 0; -+} -+ -+#endif /* _ASM_UBICOM32_FLAT_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/fpu.h -@@ -0,0 +1,37 @@ -+/* -+ * arch/ubicom32/include/asm/fpu.h -+ * Floating point state definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_FPU_H -+#define _ASM_UBICOM32_FPU_H -+ -+/* -+ * MAX floating point unit state size (FSAVE/FRESTORE) -+ */ -+/* No FP unit present then... */ -+#define FPSTATESIZE (2) /* dummy size */ -+ -+#endif /* _ASM_UBICOM32_FPU_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/futex.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/futex.h -+ * Generic futex.h for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_FUTEX_H -+#define _ASM_UBICOM32_FUTEX_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_FUTEX_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/ioctl.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/ioctl.h -+ * Generic ioctl.h for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_IOCTL_H -+#define _ASM_UBICOM32_IOCTL_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_IOCTL_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/ioctls.h -@@ -0,0 +1,111 @@ -+/* -+ * arch/ubicom32/include/asm/ioctls.h -+ * Definitions of ioctls for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_IOCTLS_H -+#define _ASM_UBICOM32_IOCTLS_H -+ -+#include -+ -+/* 0x54 is just a magic number to make these relatively unique ('T') */ -+ -+#define TCGETS 0x5401 -+#define TCSETS 0x5402 -+#define TCSETSW 0x5403 -+#define TCSETSF 0x5404 -+#define TCGETA 0x5405 -+#define TCSETA 0x5406 -+#define TCSETAW 0x5407 -+#define TCSETAF 0x5408 -+#define TCSBRK 0x5409 -+#define TCXONC 0x540A -+#define TCFLSH 0x540B -+#define TIOCEXCL 0x540C -+#define TIOCNXCL 0x540D -+#define TIOCSCTTY 0x540E -+#define TIOCGPGRP 0x540F -+#define TIOCSPGRP 0x5410 -+#define TIOCOUTQ 0x5411 -+#define TIOCSTI 0x5412 -+#define TIOCGWINSZ 0x5413 -+#define TIOCSWINSZ 0x5414 -+#define TIOCMGET 0x5415 -+#define TIOCMBIS 0x5416 -+#define TIOCMBIC 0x5417 -+#define TIOCMSET 0x5418 -+#define TIOCGSOFTCAR 0x5419 -+#define TIOCSSOFTCAR 0x541A -+#define FIONREAD 0x541B -+#define TIOCINQ FIONREAD -+#define TIOCLINUX 0x541C -+#define TIOCCONS 0x541D -+#define TIOCGSERIAL 0x541E -+#define TIOCSSERIAL 0x541F -+#define TIOCPKT 0x5420 -+#define FIONBIO 0x5421 -+#define TIOCNOTTY 0x5422 -+#define TIOCSETD 0x5423 -+#define TIOCGETD 0x5424 -+#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -+#define TIOCSBRK 0x5427 /* BSD compatibility */ -+#define TIOCCBRK 0x5428 /* BSD compatibility */ -+#define TIOCGSID 0x5429 /* Return the session ID of FD */ -+#define TCGETS2 _IOR('T',0x2A, struct termios2) -+#define TCSETS2 _IOW('T',0x2B, struct termios2) -+#define TCSETSW2 _IOW('T',0x2C, struct termios2) -+#define TCSETSF2 _IOW('T',0x2D, struct termios2) -+#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -+#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -+ -+#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -+#define FIOCLEX 0x5451 -+#define FIOASYNC 0x5452 -+#define TIOCSERCONFIG 0x5453 -+#define TIOCSERGWILD 0x5454 -+#define TIOCSERSWILD 0x5455 -+#define TIOCGLCKTRMIOS 0x5456 -+#define TIOCSLCKTRMIOS 0x5457 -+#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -+#define TIOCSERGETLSR 0x5459 /* Get line status register */ -+#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -+#define TIOCSERSETMULTI 0x545B /* Set multiport config */ -+ -+#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -+#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -+#define FIOQSIZE 0x545E -+ -+/* Used for packet mode */ -+#define TIOCPKT_DATA 0 -+#define TIOCPKT_FLUSHREAD 1 -+#define TIOCPKT_FLUSHWRITE 2 -+#define TIOCPKT_STOP 4 -+#define TIOCPKT_START 8 -+#define TIOCPKT_NOSTOP 16 -+#define TIOCPKT_DOSTOP 32 -+ -+#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ -+ -+#endif /* _ASM_UBICOM32_IOCTLS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/ipcbuf.h -@@ -0,0 +1,55 @@ -+/* -+ * arch/ubicom32/include/asm/ipcbuf.h -+ * Definition of ipc64_perm struct for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_IPCBUF_H -+#define _ASM_UBICOM32_IPCBUF_H -+ -+/* -+ * The user_ipc_perm structure for m68k architecture. -+ * Note extra padding because this structure is passed back and forth -+ * between kernel and user space. -+ * -+ * Pad space is left for: -+ * - 32-bit mode_t and seq -+ * - 2 miscellaneous 32-bit values -+ */ -+struct ipc64_perm -+{ -+ __kernel_key_t key; -+ __kernel_uid32_t uid; -+ __kernel_gid32_t gid; -+ __kernel_uid32_t cuid; -+ __kernel_gid32_t cgid; -+ __kernel_mode_t mode; -+ unsigned short __pad1; -+ unsigned short seq; -+ unsigned short __pad2; -+ unsigned long __unused1; -+ unsigned long __unused2; -+}; -+ -+#endif /* _ASM_UBICOM32_IPCBUF_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/irqflags.h -@@ -0,0 +1,94 @@ -+/* -+ * arch/ubicom32/include/asm/irqflags.h -+ * Raw implementation of local IRQ functions. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_IRQFLAGS_H -+#define _ASM_UBICOM32_IRQFLAGS_H -+ -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_PREEMPT) -+#error Not supported by Ubicom32 irq handling, yet! -+#endif -+ -+/* -+ * raw_local_irq_enable() -+ * Enable interrupts for this thread. -+ */ -+static inline void raw_local_irq_enable(void) -+{ -+ ldsr_local_irq_enable(); -+} -+ -+/* -+ * raw_local_irq_disable() -+ * Disable interrupts for this thread. -+ */ -+static inline void raw_local_irq_disable(void) -+{ -+ ldsr_local_irq_disable(); -+} -+ -+/* -+ * raw_local_save_flags() -+ * Get the current IRQ state. -+ */ -+#define raw_local_save_flags(flags) \ -+do { \ -+ (flags) = ldsr_local_irq_is_disabled(); \ -+} while (0) -+ -+/* -+ * raw_local_irq_save() -+ * Save the current interrupt state and disable interrupts. -+ */ -+#define raw_local_irq_save(flags) \ -+do { \ -+ (flags) = ldsr_local_irq_save(); \ -+} while (0) -+ -+/* -+ * raw_local_irq_restore() -+ * Restore the IRQ state back to flags. -+ */ -+static inline void raw_local_irq_restore(unsigned long flags) -+{ -+ ldsr_local_irq_restore(flags); -+} -+ -+/* -+ * raw_irqs_disabled_flags() -+ * Return true if the flags indicate that IRQ(s) are disabled. -+ */ -+static inline int raw_irqs_disabled_flags(unsigned long flags) -+{ -+ return (flags); -+} -+ -+#endif /* _ASM_UBICOM32_IRQFLAGS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/Kbuild -@@ -0,0 +1 @@ -+include include/asm-generic/Kbuild.asm ---- /dev/null -+++ b/arch/ubicom32/include/asm/kdebug.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/kdebug.h -+ * Generic kdebug.h for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_KDEBUG_H -+#define _ASM_UBICOM32_KDEBUG_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_KDEBUG_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/linkage.h -@@ -0,0 +1,34 @@ -+/* -+ * arch/ubicom32/include/asm/linkage.h -+ * Definition of Ubicom32 architecture specific linkage types. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_LINKAGE_H -+#define _ASM_UBICOM32_LINKAGE_H -+ -+#define __ocm_text __section(.ocm_text) -+#define __ocm_data __section(.ocm_data) -+ -+#endif /* _ASM_UBICOM32_LINKAGE_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/local.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/local.h -+ * Generic local.h for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_LOCAL_H -+#define _ASM_UBICOM32_LOCAL_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_LOCAL_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/mman.h -@@ -0,0 +1,44 @@ -+/* -+ * arch/ubicom32/include/asm/mman.h -+ * Memory mapping definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_MMAN_H -+#define _ASM_UBICOM32_MMAN_H -+ -+#include -+ -+#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -+#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -+#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -+#define MAP_LOCKED 0x2000 /* pages are locked */ -+#define MAP_NORESERVE 0x4000 /* don't check for reservations */ -+#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ -+#define MAP_NONBLOCK 0x10000 /* do not block on IO */ -+ -+#define MCL_CURRENT 1 /* lock all current mappings */ -+#define MCL_FUTURE 2 /* lock all future mappings */ -+ -+#endif /* _ASM_UBICOM32_MMAN_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/msgbuf.h -@@ -0,0 +1,58 @@ -+/* -+ * arch/ubicom32/include/asm/msgbuf.h -+ * Definition of msqid64_ds struct for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_MSGBUF_H -+#define _ASM_UBICOM32_MSGBUF_H -+ -+/* -+ * The msqid64_ds structure for ubicom32 architecture. -+ * Note extra padding because this structure is passed back and forth -+ * between kernel and user space. -+ * -+ * Pad space is left for: -+ * - 64-bit time_t to solve y2038 problem -+ * - 2 miscellaneous 32-bit values -+ */ -+ -+struct msqid64_ds { -+ struct ipc64_perm msg_perm; -+ __kernel_time_t msg_stime; /* last msgsnd time */ -+ unsigned long __unused1; -+ __kernel_time_t msg_rtime; /* last msgrcv time */ -+ unsigned long __unused2; -+ __kernel_time_t msg_ctime; /* last change time */ -+ unsigned long __unused3; -+ unsigned long msg_cbytes; /* current number of bytes on queue */ -+ unsigned long msg_qnum; /* number of messages in queue */ -+ unsigned long msg_qbytes; /* max number of bytes on queue */ -+ __kernel_pid_t msg_lspid; /* pid of last msgsnd */ -+ __kernel_pid_t msg_lrpid; /* last receive pid */ -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+#endif /* _ASM_UBICOM32_MSGBUF_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/namei.h -@@ -0,0 +1,38 @@ -+/* -+ * arch/ubicom32/include/asm/namei.h -+ * Definition of __emul_prefix() for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_NAMEI_H -+#define _ASM_UBICOM32_NAMEI_H -+ -+/* This dummy routine maybe changed to something useful -+ * for /usr/gnemul/ emulation stuff. -+ * Look at asm-sparc/namei.h for details. -+ */ -+ -+#define __emul_prefix() NULL -+ -+#endif /* _ASM_UBICOM32_NAMEI_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/page.h -@@ -0,0 +1,106 @@ -+/* -+ * arch/ubicom32/include/asm/page.h -+ * Memory page related operations and definitions. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_PAGE_H -+#define _ASM_UBICOM32_PAGE_H -+ -+/* PAGE_SHIFT determines the page size */ -+ -+#define PAGE_SHIFT 12 -+#define PAGE_SIZE (1 << PAGE_SHIFT) -+#define PAGE_MASK (~(PAGE_SIZE-1)) -+ -+#include -+ -+#ifndef __ASSEMBLY__ -+ -+#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -+#define free_user_page(page, addr) free_page(addr) -+ -+#define clear_page(page) memset((page), 0, PAGE_SIZE) -+#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) -+ -+#define clear_user_page(page, vaddr, pg) clear_page(page) -+#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) -+ -+#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ -+ alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) -+#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE -+ -+/* -+ * These are used to make use of C type-checking.. -+ */ -+typedef struct { unsigned long pte; } pte_t; -+typedef struct { unsigned long pmd[16]; } pmd_t; -+typedef struct { unsigned long pgd; } pgd_t; -+typedef struct { unsigned long pgprot; } pgprot_t; -+typedef struct page *pgtable_t; -+ -+#define pte_val(x) ((x).pte) -+#define pmd_val(x) ((&x)->pmd[0]) -+#define pgd_val(x) ((x).pgd) -+#define pgprot_val(x) ((x).pgprot) -+ -+#define __pte(x) ((pte_t) { (x) } ) -+#define __pmd(x) ((pmd_t) { (x) } ) -+#define __pgd(x) ((pgd_t) { (x) } ) -+#define __pgprot(x) ((pgprot_t) { (x) } ) -+ -+extern unsigned long memory_start; -+extern unsigned long memory_end; -+ -+#endif /* !__ASSEMBLY__ */ -+ -+#include -+ -+#define PAGE_OFFSET (PAGE_OFFSET_RAW) -+ -+#ifndef __ASSEMBLY__ -+ -+#define __pa(vaddr) virt_to_phys((void *)(vaddr)) -+#define __va(paddr) phys_to_virt((unsigned long)(paddr)) -+ -+#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) -+#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) -+ -+#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) -+#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) -+ -+#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) -+#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) -+#define pfn_valid(pfn) ((pfn) < max_mapnr) -+ -+#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ -+ ((void *)(kaddr) < (void *)memory_end)) -+ -+#endif /* __ASSEMBLY__ */ -+ -+#ifdef __KERNEL__ -+#include -+#endif -+ -+#endif /* _ASM_UBICOM32_PAGE_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/page_offset.h -@@ -0,0 +1,35 @@ -+/* -+ * arch/ubicom32/include/asm/page_offset.h -+ * Definition of PAGE_OFFSET_RAW for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+ -+#ifndef _ASM_UBICOM32_PAGE_OFFSET_H -+#define _ASM_UBICOM32_PAGE_OFFSET_H -+ -+/* This handles the memory map.. */ -+#define PAGE_OFFSET_RAW 0x3ffc0000 -+ -+#endif /* _ASM_UBICOM32_PAGE_OFFSET_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/param.h -@@ -0,0 +1,49 @@ -+/* -+ * arch/ubicom32/include/asm/param.h -+ * Definition of miscellaneous constants, including HZ. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_PARAM_H -+#define _ASM_UBICOM32_PARAM_H -+ -+#ifdef __KERNEL__ -+#define HZ CONFIG_HZ -+#define USER_HZ HZ -+#define CLOCKS_PER_SEC (USER_HZ) -+#endif -+ -+#ifndef HZ -+#define HZ 100 -+#endif -+ -+#define EXEC_PAGESIZE 4096 -+ -+#ifndef NOGROUP -+#define NOGROUP (-1) -+#endif -+ -+#define MAXHOSTNAMELEN 64 /* max length of hostname */ -+ -+#endif /* _ASM_UBICOM32_PARAM_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/poll.h -@@ -0,0 +1,36 @@ -+/* -+ * arch/ubicom32/include/asm/poll.h -+ * Ubicom32 specific poll() related flags definitions. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_POLL_H -+#define _ASM_UBICOM32_POLL_H -+ -+#define POLLWRNORM POLLOUT -+#define POLLWRBAND 0x0100 -+ -+#include -+ -+#endif /* _ASM_UBICOM32_POLL_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/posix_types.h -@@ -0,0 +1,93 @@ -+/* -+ * arch/ubicom32/include/asm/posix_types.h -+ * Ubicom32 architecture posix types. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * Copyright (C) 2004 Microtronix Datacom Ltd -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef __ARCH_UBICOM32_POSIX_TYPES_H -+#define __ARCH_UBICOM32_POSIX_TYPES_H -+ -+/* -+ * This file is generally used by user-level software, so you need to -+ * be a little careful about namespace pollution etc. Also, we cannot -+ * assume GCC is being used. -+ */ -+ -+typedef unsigned long __kernel_ino_t; -+typedef unsigned short __kernel_mode_t; -+typedef unsigned short __kernel_nlink_t; -+typedef long __kernel_off_t; -+typedef int __kernel_pid_t; -+typedef unsigned short __kernel_ipc_pid_t; -+typedef unsigned short __kernel_uid_t; -+typedef unsigned short __kernel_gid_t; -+typedef unsigned int __kernel_size_t; -+typedef int __kernel_ssize_t; -+typedef int __kernel_ptrdiff_t; -+typedef long __kernel_time_t; -+typedef long __kernel_suseconds_t; -+typedef long __kernel_clock_t; -+typedef int __kernel_timer_t; -+typedef int __kernel_clockid_t; -+typedef int __kernel_daddr_t; -+typedef char * __kernel_caddr_t; -+typedef unsigned short __kernel_uid16_t; -+typedef unsigned short __kernel_gid16_t; -+typedef unsigned int __kernel_uid32_t; -+typedef unsigned int __kernel_gid32_t; -+ -+typedef unsigned short __kernel_old_uid_t; -+typedef unsigned short __kernel_old_gid_t; -+typedef unsigned short __kernel_old_dev_t; -+ -+#ifdef __GNUC__ -+typedef long long __kernel_loff_t; -+#endif -+ -+typedef struct { -+#if defined(__KERNEL__) || defined(__USE_ALL) -+ int val[2]; -+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -+ int __val[2]; -+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -+} __kernel_fsid_t; -+ -+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) -+ -+#undef __FD_SET -+#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) -+ -+#undef __FD_CLR -+#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) -+ -+#undef __FD_ISSET -+#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) -+ -+#undef __FD_ZERO -+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -+ -+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ -+ -+#endif ---- /dev/null -+++ b/arch/ubicom32/include/asm/ptrace.h -@@ -0,0 +1,177 @@ -+/* -+ * arch/ubicom32/include/asm/ptrace.h -+ * Ubicom32 architecture ptrace support. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_PTRACE_H -+#define _ASM_UBICOM32_PTRACE_H -+ -+#ifndef __ASSEMBLY__ -+ -+/* -+ * We use hard coded constants because this is shared with user -+ * space and the values are NOT allowed to change. Only fields -+ * that are intended to be exposed get values. -+ */ -+#define PT_D0 0 -+#define PT_D1 4 -+#define PT_D2 8 -+#define PT_D3 12 -+#define PT_D4 16 -+#define PT_D5 20 -+#define PT_D6 24 -+#define PT_D7 28 -+#define PT_D8 32 -+#define PT_D9 36 -+#define PT_D10 40 -+#define PT_D11 44 -+#define PT_D12 48 -+#define PT_D13 52 -+#define PT_D14 56 -+#define PT_D15 60 -+#define PT_A0 64 -+#define PT_A1 68 -+#define PT_A2 72 -+#define PT_A3 76 -+#define PT_A4 80 -+#define PT_A5 84 -+#define PT_A6 88 -+#define PT_A7 92 -+#define PT_SP 92 -+#define PT_ACC0HI 96 -+#define PT_ACC0LO 100 -+#define PT_MAC_RC16 104 -+#define PT_ACC1HI 108 -+#define PT_ACC1LO 112 -+#define PT_SOURCE3 116 -+#define PT_INST_CNT 120 -+#define PT_CSR 124 -+#define PT_DUMMY_UNUSED 128 -+#define PT_INT_MASK0 132 -+#define PT_INT_MASK1 136 -+#define PT_TRAP_CAUSE 140 -+#define PT_PC 144 -+#define PT_ORIGINAL_D0 148 -+#define PT_FRAME_TYPE 152 -+ -+/* -+ * The following 'registers' are not registers at all but are used -+ * locate the relocated sections. -+ */ -+#define PT_TEXT_ADDR 200 -+#define PT_TEXT_END_ADDR 204 -+#define PT_DATA_ADDR 208 -+#define PT_EXEC_FDPIC_LOADMAP 212 -+#define PT_INTERP_FDPIC_LOADMAP 216 -+ -+/* -+ * This struct defines the way the registers are stored on the -+ * stack during a system call. -+ */ -+enum thread_type { -+ NORMAL_THREAD, -+ KERNEL_THREAD, -+}; -+ -+#define UBICOM32_FRAME_TYPE_SYSCALL -1 /* System call frame */ -+#define UBICOM32_FRAME_TYPE_INVALID 0 /* Invalid frame, no longer in use */ -+#define UBICOM32_FRAME_TYPE_INTERRUPT 1 /* Interrupt frame */ -+#define UBICOM32_FRAME_TYPE_TRAP 2 /* Trap frame */ -+#define UBICOM32_FRAME_TYPE_SIGTRAMP 3 /* Signal trampoline frame. */ -+#define UBICOM32_FRAME_TYPE_NEW_THREAD 4 /* New Thread. */ -+ -+struct pt_regs { -+ /* -+ * Data Registers -+ */ -+ unsigned long dn[16]; -+ -+ /* -+ * Address Registers -+ */ -+ unsigned long an[8]; -+ -+ /* -+ * Per thread misc registers. -+ */ -+ unsigned long acc0[2]; -+ unsigned long mac_rc16; -+ unsigned long acc1[2]; -+ unsigned long source3; -+ unsigned long inst_cnt; -+ unsigned long csr; -+ unsigned long dummy_unused; -+ unsigned long int_mask0; -+ unsigned long int_mask1; -+ unsigned long trap_cause; -+ unsigned long pc; -+ unsigned long original_dn_0; -+ -+ /* -+ * Frame type. Syscall frames are -1. For other types look above. -+ */ -+ unsigned long frame_type; -+ -+ /* -+ * These fields are not exposed to ptrace. -+ */ -+ unsigned long previous_pc; -+ long nesting_level; /* When the kernel in in user space this -+ * will be -1. */ -+ unsigned long thread_type; /* This indicates if this is a kernel -+ * thread. */ -+}; -+ -+/* -+ * This is the extended stack used by signal handlers and the context -+ * switcher: it's pushed after the normal "struct pt_regs". -+ */ -+struct switch_stack { -+ unsigned long dummy; -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -+#define PTRACE_GETREGS 12 -+#define PTRACE_SETREGS 13 -+ -+#ifndef PS_S -+#define PS_S (0x2000) -+#define PS_M (0x1000) -+#endif -+ -+extern int __user_mode(unsigned long sp); -+ -+#define user_mode(regs) (__user_mode((regs->an[7]))) -+#define user_stack(regs) ((regs)->an[7]) -+#define instruction_pointer(regs) ((regs)->pc) -+#define profile_pc(regs) instruction_pointer(regs) -+extern void show_regs(struct pt_regs *); -+#endif /* __KERNEL__ */ -+ -+#endif /* __ASSEMBLY__ */ -+ -+#endif /* _ASM_UBICOM32_PTRACE_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/resource.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/resource.h -+ * Generic definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_RESOURCE_H -+#define _ASM_UBICOM32_RESOURCE_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_RESOURCE_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/sections.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/sections.h -+ * Generic sections.h definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SECTIONS_H -+#define _ASM_UBICOM32_SECTIONS_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_SECTIONS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/segment.h -@@ -0,0 +1,78 @@ -+/* -+ * arch/ubicom32/include/asm/segment.h -+ * Memory segment definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SEGMENT_H -+#define _ASM_UBICOM32_SEGMENT_H -+ -+/* define constants */ -+/* Address spaces (FC0-FC2) */ -+#define USER_DATA (1) -+#ifndef __USER_DS -+#define __USER_DS (USER_DATA) -+#endif -+#define USER_PROGRAM (2) -+#define SUPER_DATA (5) -+#ifndef __KERNEL_DS -+#define __KERNEL_DS (SUPER_DATA) -+#endif -+#define SUPER_PROGRAM (6) -+#define CPU_SPACE (7) -+ -+#ifndef __ASSEMBLY__ -+ -+typedef struct { -+ unsigned long seg; -+} mm_segment_t; -+ -+#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) -+#define USER_DS MAKE_MM_SEG(__USER_DS) -+#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) -+ -+/* -+ * Get/set the SFC/DFC registers for MOVES instructions -+ */ -+ -+static inline mm_segment_t get_fs(void) -+{ -+ return USER_DS; -+} -+ -+static inline mm_segment_t get_ds(void) -+{ -+ /* return the supervisor data space code */ -+ return KERNEL_DS; -+} -+ -+static inline void set_fs(mm_segment_t val) -+{ -+} -+ -+#define segment_eq(a,b) ((a).seg == (b).seg) -+ -+#endif /* __ASSEMBLY__ */ -+ -+#endif /* _ASM_UBICOM32_SEGMENT_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/sembuf.h -@@ -0,0 +1,52 @@ -+/* -+ * arch/ubicom32/include/asm/sembuf.h -+ * The semid64_ds structure for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SEMBUF_H -+#define _ASM_UBICOM32_SEMBUF_H -+ -+/* -+ * The semid64_ds structure for ubicom32 architecture. -+ * Note extra padding because this structure is passed back and forth -+ * between kernel and user space. -+ * -+ * Pad space is left for: -+ * - 64-bit time_t to solve y2038 problem -+ * - 2 miscellaneous 32-bit values -+ */ -+ -+struct semid64_ds { -+ struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ -+ __kernel_time_t sem_otime; /* last semop time */ -+ unsigned long __unused1; -+ __kernel_time_t sem_ctime; /* last change time */ -+ unsigned long __unused2; -+ unsigned long sem_nsems; /* no. of semaphores in array */ -+ unsigned long __unused3; -+ unsigned long __unused4; -+}; -+ -+#endif /* _ASM_UBICOM32_SEMBUF_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/setup.h -@@ -0,0 +1,35 @@ -+/* -+ * arch/ubicom32/include/asm/setup.h -+ * Kernel command line length definition. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * Copyright (C) 2004, Microtronix Datacom Ltd., All rights reserved. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+ -+#ifndef _ASM_UBICOM32_SETUP_H -+#define _ASM_UBICOM32_SETUP_H -+ -+#define COMMAND_LINE_SIZE 512 -+ -+#endif /* _ASM_UBICOM32_SETUP_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/shmbuf.h -@@ -0,0 +1,69 @@ -+/* -+ * arch/ubicom32/include/asm/shmbuf.h -+ * The shmid64_ds structure for the Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SHMBUF_H -+#define _ASM_UBICOM32_SHMBUF_H -+ -+/* -+ * The shmid64_ds structure for m68k architecture. -+ * Note extra padding because this structure is passed back and forth -+ * between kernel and user space. -+ * -+ * Pad space is left for: -+ * - 64-bit time_t to solve y2038 problem -+ * - 2 miscellaneous 32-bit values -+ */ -+ -+struct shmid64_ds { -+ struct ipc64_perm shm_perm; /* operation perms */ -+ size_t shm_segsz; /* size of segment (bytes) */ -+ __kernel_time_t shm_atime; /* last attach time */ -+ unsigned long __unused1; -+ __kernel_time_t shm_dtime; /* last detach time */ -+ unsigned long __unused2; -+ __kernel_time_t shm_ctime; /* last change time */ -+ unsigned long __unused3; -+ __kernel_pid_t shm_cpid; /* pid of creator */ -+ __kernel_pid_t shm_lpid; /* pid of last operator */ -+ unsigned long shm_nattch; /* no. of current attaches */ -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+struct shminfo64 { -+ unsigned long shmmax; -+ unsigned long shmmin; -+ unsigned long shmmni; -+ unsigned long shmseg; -+ unsigned long shmall; -+ unsigned long __unused1; -+ unsigned long __unused2; -+ unsigned long __unused3; -+ unsigned long __unused4; -+}; -+ -+#endif /* _ASM_UBICOM32_SHMBUF_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/shmparam.h -@@ -0,0 +1,35 @@ -+/* -+ * arch/ubicom32/include/asm/shmparam.h -+ * Shared memory definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * Copyright (C) 2004 Microtronix Datacom Ltd -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ * Alpha, ix86, M68K, Sparc, ...et al -+ */ -+#ifndef _ASM_UBICOM32_SHMPARAM_H -+#define _ASM_UBICOM32_SHMPARAM_H -+ -+#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ -+ -+#endif /* _ASM_UBICOM32_SHMPARAM_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/sigcontext.h -@@ -0,0 +1,37 @@ -+/* -+ * arch/ubicom32/include/asm/sigcontext.h -+ * Definition of sigcontext struct for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SIGCONTEXT_H -+#define _ASM_UBICOM32_SIGCONTEXT_H -+ -+#include -+ -+struct sigcontext { -+ struct pt_regs sc_regs; -+}; -+ -+#endif /* _ASM_UBICOM32_SIGCONTEXT_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/siginfo.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/siginfo.h -+ * Generic siginfo.h definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SIGINFO_H -+#define _ASM_UBICOM32_SIGINFO_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_SIGINFO_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/signal.h -@@ -0,0 +1,180 @@ -+/* -+ * arch/ubicom32/include/asm/signal.h -+ * Signal related definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SIGNAL_H -+#define _ASM_UBICOM32_SIGNAL_H -+ -+#include -+ -+/* Avoid too many header ordering problems. */ -+struct siginfo; -+ -+#ifdef __KERNEL__ -+/* Most things should be clean enough to redefine this at will, if care -+ is taken to make libc match. */ -+ -+#define _NSIG 64 -+#define _NSIG_BPW 32 -+#define _NSIG_WORDS (_NSIG / _NSIG_BPW) -+ -+typedef unsigned long old_sigset_t; /* at least 32 bits */ -+ -+typedef struct { -+ unsigned long sig[_NSIG_WORDS]; -+} sigset_t; -+ -+#endif /* __KERNEL__ */ -+ -+#define SIGHUP 1 -+#define SIGINT 2 -+#define SIGQUIT 3 -+#define SIGILL 4 -+#define SIGTRAP 5 -+#define SIGABRT 6 -+#define SIGIOT 6 -+#define SIGBUS 7 -+#define SIGFPE 8 -+#define SIGKILL 9 -+#define SIGUSR1 10 -+#define SIGSEGV 11 -+#define SIGUSR2 12 -+#define SIGPIPE 13 -+#define SIGALRM 14 -+#define SIGTERM 15 -+#define SIGSTKFLT 16 -+#define SIGCHLD 17 -+#define SIGCONT 18 -+#define SIGSTOP 19 -+#define SIGTSTP 20 -+#define SIGTTIN 21 -+#define SIGTTOU 22 -+#define SIGURG 23 -+#define SIGXCPU 24 -+#define SIGXFSZ 25 -+#define SIGVTALRM 26 -+#define SIGPROF 27 -+#define SIGWINCH 28 -+#define SIGIO 29 -+#define SIGPOLL SIGIO -+/* -+#define SIGLOST 29 -+*/ -+#define SIGPWR 30 -+#define SIGSYS 31 -+#define SIGUNUSED 31 -+ -+/* These should not be considered constants from userland. */ -+#define SIGRTMIN 32 -+#define SIGRTMAX _NSIG -+ -+/* -+ * SA_FLAGS values: -+ * -+ * SA_ONSTACK indicates that a registered stack_t will be used. -+ * SA_RESTART flag to get restarting signals (which were the default long ago) -+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. -+ * SA_RESETHAND clears the handler when the signal is delivered. -+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. -+ * SA_NODEFER prevents the current signal from being masked in the handler. -+ * -+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single -+ * Unix names RESETHAND and NODEFER respectively. -+ */ -+#define SA_NOCLDSTOP 0x00000001 -+#define SA_NOCLDWAIT 0x00000002 -+#define SA_SIGINFO 0x00000004 -+#define SA_ONSTACK 0x08000000 -+#define SA_RESTART 0x10000000 -+#define SA_NODEFER 0x40000000 -+#define SA_RESETHAND 0x80000000 -+ -+#define SA_NOMASK SA_NODEFER -+#define SA_ONESHOT SA_RESETHAND -+ -+/* -+ * sigaltstack controls -+ */ -+#define SS_ONSTACK 1 -+#define SS_DISABLE 2 -+ -+#define MINSIGSTKSZ 2048 -+#define SIGSTKSZ 8192 -+ -+#include -+ -+#ifdef __KERNEL__ -+struct old_sigaction { -+ __sighandler_t sa_handler; -+ old_sigset_t sa_mask; -+ unsigned long sa_flags; -+ void (*sa_restorer)(void); -+}; -+ -+struct sigaction { -+ __sighandler_t sa_handler; -+ unsigned long sa_flags; -+ void (*sa_restorer)(void); -+ sigset_t sa_mask; /* mask last for extensibility */ -+}; -+ -+struct k_sigaction { -+ struct sigaction sa; -+}; -+#else -+/* Here we must cater to libcs that poke about in kernel headers. */ -+ -+struct sigaction { -+ union { -+ __sighandler_t _sa_handler; -+ void (*_sa_sigaction)(int, struct siginfo *, void *); -+ } _u; -+ sigset_t sa_mask; -+ unsigned long sa_flags; -+ void (*sa_restorer)(void); -+}; -+ -+#define sa_handler _u._sa_handler -+#define sa_sigaction _u._sa_sigaction -+ -+#endif /* __KERNEL__ */ -+ -+typedef struct sigaltstack { -+ void *ss_sp; -+ int ss_flags; -+ size_t ss_size; -+} stack_t; -+ -+#ifdef __KERNEL__ -+ -+#include -+#undef __HAVE_ARCH_SIG_BITOPS -+ -+#define ptrace_signal_deliver(regs, cookie) do { } while (0) -+ -+#endif /* __KERNEL__ */ -+ -+#endif /* _ASM_UBICOM32_SIGNAL_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/socket.h -@@ -0,0 +1,84 @@ -+/* -+ * arch/ubicom32/include/asm/socket.h -+ * Socket options definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SOCKET_H -+#define _ASM_UBICOM32_SOCKET_H -+ -+#include -+ -+/* For setsockopt(2) */ -+#define SOL_SOCKET 1 -+ -+#define SO_DEBUG 1 -+#define SO_REUSEADDR 2 -+#define SO_TYPE 3 -+#define SO_ERROR 4 -+#define SO_DONTROUTE 5 -+#define SO_BROADCAST 6 -+#define SO_SNDBUF 7 -+#define SO_RCVBUF 8 -+#define SO_SNDBUFFORCE 32 -+#define SO_RCVBUFFORCE 33 -+#define SO_KEEPALIVE 9 -+#define SO_OOBINLINE 10 -+#define SO_NO_CHECK 11 -+#define SO_PRIORITY 12 -+#define SO_LINGER 13 -+#define SO_BSDCOMPAT 14 -+/* To add :#define SO_REUSEPORT 15 */ -+#define SO_PASSCRED 16 -+#define SO_PEERCRED 17 -+#define SO_RCVLOWAT 18 -+#define SO_SNDLOWAT 19 -+#define SO_RCVTIMEO 20 -+#define SO_SNDTIMEO 21 -+ -+/* Security levels - as per NRL IPv6 - don't actually do anything */ -+#define SO_SECURITY_AUTHENTICATION 22 -+#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -+#define SO_SECURITY_ENCRYPTION_NETWORK 24 -+ -+#define SO_BINDTODEVICE 25 -+ -+/* Socket filtering */ -+#define SO_ATTACH_FILTER 26 -+#define SO_DETACH_FILTER 27 -+ -+#define SO_PEERNAME 28 -+#define SO_TIMESTAMP 29 -+#define SCM_TIMESTAMP SO_TIMESTAMP -+ -+#define SO_ACCEPTCONN 30 -+ -+#define SO_PEERSEC 31 -+#define SO_PASSSEC 34 -+#define SO_TIMESTAMPNS 35 -+#define SCM_TIMESTAMPNS SO_TIMESTAMPNS -+ -+#define SO_MARK 36 -+ -+#endif /* _ASM_UBICOM32_SOCKET_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/sockios.h -@@ -0,0 +1,40 @@ -+/* -+ * arch/ubicom32/include/asm/sockios.h -+ * Socket-level ioctl definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SOCKIOS_H -+#define _ASM_UBICOM32_SOCKIOS_H -+ -+/* Socket-level I/O control calls. */ -+#define FIOSETOWN 0x8901 -+#define SIOCSPGRP 0x8902 -+#define FIOGETOWN 0x8903 -+#define SIOCGPGRP 0x8904 -+#define SIOCATMARK 0x8905 -+#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -+#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ -+ -+#endif /* _ASM_UBICOM32_SOCKIOS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/statfs.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/statfs.h -+ * Generic statfs.h definitions -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_STATFS_H -+#define _ASM_UBICOM32_STATFS_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_STATFS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/stat.h -@@ -0,0 +1,104 @@ -+/* -+ * arch/ubicom32/include/asm/stat.h -+ * File status definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_STAT_H -+#define _ASM_UBICOM32_STAT_H -+ -+struct __old_kernel_stat { -+ unsigned short st_dev; -+ unsigned short st_ino; -+ unsigned short st_mode; -+ unsigned short st_nlink; -+ unsigned short st_uid; -+ unsigned short st_gid; -+ unsigned short st_rdev; -+ unsigned long st_size; -+ unsigned long st_atime; -+ unsigned long st_mtime; -+ unsigned long st_ctime; -+}; -+ -+struct stat { -+ unsigned short st_dev; -+ unsigned short __pad1; -+ unsigned long st_ino; -+ unsigned short st_mode; -+ unsigned short st_nlink; -+ unsigned short st_uid; -+ unsigned short st_gid; -+ unsigned short st_rdev; -+ unsigned short __pad2; -+ unsigned long st_size; -+ unsigned long st_blksize; -+ unsigned long st_blocks; -+ unsigned long st_atime; -+ unsigned long __unused1; -+ unsigned long st_mtime; -+ unsigned long __unused2; -+ unsigned long st_ctime; -+ unsigned long __unused3; -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+/* This matches struct stat64 in glibc2.1, hence the absolutely -+ * insane amounts of padding around dev_t's. -+ */ -+struct stat64 { -+ unsigned long long st_dev; -+ unsigned char __pad1[2]; -+ -+#define STAT64_HAS_BROKEN_ST_INO 1 -+ unsigned long __st_ino; -+ -+ unsigned int st_mode; -+ unsigned int st_nlink; -+ -+ unsigned long st_uid; -+ unsigned long st_gid; -+ -+ unsigned long long st_rdev; -+ unsigned char __pad3[2]; -+ -+ long long st_size; -+ unsigned long st_blksize; -+ -+ unsigned long long st_blocks; /* Number 512-byte blocks allocated. */ -+ -+ unsigned long st_atime; -+ unsigned long st_atime_nsec; -+ -+ unsigned long st_mtime; -+ unsigned long st_mtime_nsec; -+ -+ unsigned long st_ctime; -+ unsigned long st_ctime_nsec; -+ -+ unsigned long long st_ino; -+}; -+ -+#endif /* _ASM_UBICOM32_STAT_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/swab.h -@@ -0,0 +1,46 @@ -+/* -+ * arch/ubicom32/include/asm/swab.h -+ * Byte order swapping utility routines. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_SWAB_H -+#define _ASM_UBICOM32_SWAB_H -+ -+#include -+ -+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) -+# define __BYTEORDER_HAS_U64__ -+# define __SWAB_64_THRU_32__ -+#endif -+ -+#if defined(IP7000) || defined(IP7000_REV2) -+ -+#define __arch__swab16 __builtin_ubicom32_swapb_2 -+#define __arch__swab32 __builtin_ubicom32_swapb_4 -+ -+#endif /* IP7000 */ -+ -+#endif /* _ASM_UBICOM32_SWAB_H */ -+ ---- /dev/null -+++ b/arch/ubicom32/include/asm/termbits.h -@@ -0,0 +1,227 @@ -+/* -+ * arch/ubicom32/include/asm/termbits.h -+ * Terminal/serial port definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_TERMBITS_H -+#define _ASM_UBICOM32_TERMBITS_H -+ -+#include -+ -+typedef unsigned char cc_t; -+typedef unsigned int speed_t; -+typedef unsigned int tcflag_t; -+ -+#define NCCS 19 -+struct termios { -+ tcflag_t c_iflag; /* input mode flags */ -+ tcflag_t c_oflag; /* output mode flags */ -+ tcflag_t c_cflag; /* control mode flags */ -+ tcflag_t c_lflag; /* local mode flags */ -+ cc_t c_line; /* line discipline */ -+ cc_t c_cc[NCCS]; /* control characters */ -+}; -+ -+struct termios2 { -+ tcflag_t c_iflag; /* input mode flags */ -+ tcflag_t c_oflag; /* output mode flags */ -+ tcflag_t c_cflag; /* control mode flags */ -+ tcflag_t c_lflag; /* local mode flags */ -+ cc_t c_line; /* line discipline */ -+ cc_t c_cc[NCCS]; /* control characters */ -+ speed_t c_ispeed; /* input speed */ -+ speed_t c_ospeed; /* output speed */ -+}; -+ -+struct ktermios { -+ tcflag_t c_iflag; /* input mode flags */ -+ tcflag_t c_oflag; /* output mode flags */ -+ tcflag_t c_cflag; /* control mode flags */ -+ tcflag_t c_lflag; /* local mode flags */ -+ cc_t c_line; /* line discipline */ -+ cc_t c_cc[NCCS]; /* control characters */ -+ speed_t c_ispeed; /* input speed */ -+ speed_t c_ospeed; /* output speed */ -+}; -+ -+/* c_cc characters */ -+#define VINTR 0 -+#define VQUIT 1 -+#define VERASE 2 -+#define VKILL 3 -+#define VEOF 4 -+#define VTIME 5 -+#define VMIN 6 -+#define VSWTC 7 -+#define VSTART 8 -+#define VSTOP 9 -+#define VSUSP 10 -+#define VEOL 11 -+#define VREPRINT 12 -+#define VDISCARD 13 -+#define VWERASE 14 -+#define VLNEXT 15 -+#define VEOL2 16 -+ -+ -+/* c_iflag bits */ -+#define IGNBRK 0000001 -+#define BRKINT 0000002 -+#define IGNPAR 0000004 -+#define PARMRK 0000010 -+#define INPCK 0000020 -+#define ISTRIP 0000040 -+#define INLCR 0000100 -+#define IGNCR 0000200 -+#define ICRNL 0000400 -+#define IUCLC 0001000 -+#define IXON 0002000 -+#define IXANY 0004000 -+#define IXOFF 0010000 -+#define IMAXBEL 0020000 -+#define IUTF8 0040000 -+ -+/* c_oflag bits */ -+#define OPOST 0000001 -+#define OLCUC 0000002 -+#define ONLCR 0000004 -+#define OCRNL 0000010 -+#define ONOCR 0000020 -+#define ONLRET 0000040 -+#define OFILL 0000100 -+#define OFDEL 0000200 -+#define NLDLY 0000400 -+#define NL0 0000000 -+#define NL1 0000400 -+#define CRDLY 0003000 -+#define CR0 0000000 -+#define CR1 0001000 -+#define CR2 0002000 -+#define CR3 0003000 -+#define TABDLY 0014000 -+#define TAB0 0000000 -+#define TAB1 0004000 -+#define TAB2 0010000 -+#define TAB3 0014000 -+#define XTABS 0014000 -+#define BSDLY 0020000 -+#define BS0 0000000 -+#define BS1 0020000 -+#define VTDLY 0040000 -+#define VT0 0000000 -+#define VT1 0040000 -+#define FFDLY 0100000 -+#define FF0 0000000 -+#define FF1 0100000 -+ -+/* c_cflag bit meaning */ -+#define CBAUD 0010017 -+#define B0 0000000 /* hang up */ -+#define B50 0000001 -+#define B75 0000002 -+#define B110 0000003 -+#define B134 0000004 -+#define B150 0000005 -+#define B200 0000006 -+#define B300 0000007 -+#define B600 0000010 -+#define B1200 0000011 -+#define B1800 0000012 -+#define B2400 0000013 -+#define B4800 0000014 -+#define B9600 0000015 -+#define B19200 0000016 -+#define B38400 0000017 -+#define EXTA B19200 -+#define EXTB B38400 -+#define CSIZE 0000060 -+#define CS5 0000000 -+#define CS6 0000020 -+#define CS7 0000040 -+#define CS8 0000060 -+#define CSTOPB 0000100 -+#define CREAD 0000200 -+#define PARENB 0000400 -+#define PARODD 0001000 -+#define HUPCL 0002000 -+#define CLOCAL 0004000 -+#define CBAUDEX 0010000 -+#define BOTHER 0010000 -+#define B57600 0010001 -+#define B115200 0010002 -+#define B230400 0010003 -+#define B460800 0010004 -+#define B500000 0010005 -+#define B576000 0010006 -+#define B921600 0010007 -+#define B1000000 0010010 -+#define B1152000 0010011 -+#define B1500000 0010012 -+#define B2000000 0010013 -+#define B2500000 0010014 -+#define B3000000 0010015 -+#define B3500000 0010016 -+#define B4000000 0010017 -+#define CIBAUD 002003600000 /* input baud rate */ -+#define CMSPAR 010000000000 /* mark or space (stick) parity */ -+#define CRTSCTS 020000000000 /* flow control */ -+ -+#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ -+ -+/* c_lflag bits */ -+#define ISIG 0000001 -+#define ICANON 0000002 -+#define XCASE 0000004 -+#define ECHO 0000010 -+#define ECHOE 0000020 -+#define ECHOK 0000040 -+#define ECHONL 0000100 -+#define NOFLSH 0000200 -+#define TOSTOP 0000400 -+#define ECHOCTL 0001000 -+#define ECHOPRT 0002000 -+#define ECHOKE 0004000 -+#define FLUSHO 0010000 -+#define PENDIN 0040000 -+#define IEXTEN 0100000 -+ -+ -+/* tcflow() and TCXONC use these */ -+#define TCOOFF 0 -+#define TCOON 1 -+#define TCIOFF 2 -+#define TCION 3 -+ -+/* tcflush() and TCFLSH use these */ -+#define TCIFLUSH 0 -+#define TCOFLUSH 1 -+#define TCIOFLUSH 2 -+ -+/* tcsetattr uses these */ -+#define TCSANOW 0 -+#define TCSADRAIN 1 -+#define TCSAFLUSH 2 -+ -+#endif /* _ASM_UBICOM32_TERMBITS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/termios.h -@@ -0,0 +1,119 @@ -+/* -+ * arch/ubicom32/include/asm/termios.h -+ * Ubicom32 termio definitions. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_TERMIOS_H -+#define _ASM_UBICOM32_TERMIOS_H -+ -+#include -+#include -+ -+struct winsize { -+ unsigned short ws_row; -+ unsigned short ws_col; -+ unsigned short ws_xpixel; -+ unsigned short ws_ypixel; -+}; -+ -+#define NCC 8 -+struct termio { -+ unsigned short c_iflag; /* input mode flags */ -+ unsigned short c_oflag; /* output mode flags */ -+ unsigned short c_cflag; /* control mode flags */ -+ unsigned short c_lflag; /* local mode flags */ -+ unsigned char c_line; /* line discipline */ -+ unsigned char c_cc[NCC]; /* control characters */ -+}; -+ -+#ifdef __KERNEL__ -+/* intr=^C quit=^| erase=del kill=^U -+ eof=^D vtime=\0 vmin=\1 sxtc=\0 -+ start=^Q stop=^S susp=^Z eol=\0 -+ reprint=^R discard=^U werase=^W lnext=^V -+ eol2=\0 -+*/ -+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" -+#endif -+ -+/* modem lines */ -+#define TIOCM_LE 0x001 -+#define TIOCM_DTR 0x002 -+#define TIOCM_RTS 0x004 -+#define TIOCM_ST 0x008 -+#define TIOCM_SR 0x010 -+#define TIOCM_CTS 0x020 -+#define TIOCM_CAR 0x040 -+#define TIOCM_RNG 0x080 -+#define TIOCM_DSR 0x100 -+#define TIOCM_CD TIOCM_CAR -+#define TIOCM_RI TIOCM_RNG -+#define TIOCM_OUT1 0x2000 -+#define TIOCM_OUT2 0x4000 -+#define TIOCM_LOOP 0x8000 -+ -+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Translate a "termio" structure into a "termios". Ugh. -+ */ -+#define user_termio_to_kernel_termios(termios, termio) \ -+({ \ -+ unsigned short tmp; \ -+ get_user(tmp, &(termio)->c_iflag); \ -+ (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ -+ get_user(tmp, &(termio)->c_oflag); \ -+ (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ -+ get_user(tmp, &(termio)->c_cflag); \ -+ (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ -+ get_user(tmp, &(termio)->c_lflag); \ -+ (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ -+ get_user((termios)->c_line, &(termio)->c_line); \ -+ copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -+}) -+ -+/* -+ * Translate a "termios" structure into a "termio". Ugh. -+ */ -+#define kernel_termios_to_user_termio(termio, termios) \ -+({ \ -+ put_user((termios)->c_iflag, &(termio)->c_iflag); \ -+ put_user((termios)->c_oflag, &(termio)->c_oflag); \ -+ put_user((termios)->c_cflag, &(termio)->c_cflag); \ -+ put_user((termios)->c_lflag, &(termio)->c_lflag); \ -+ put_user((termios)->c_line, &(termio)->c_line); \ -+ copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -+}) -+ -+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) -+ -+#endif /* __KERNEL__ */ -+ -+#endif /* _ASM_UBICOM32_TERMIOS_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/thread_info.h -@@ -0,0 +1,134 @@ -+/* -+ * arch/ubicom32/include/asm/thread_info.h -+ * Ubicom32 architecture low-level thread information. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * Adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com) -+ * Copyright (C) 2002 David Howells (dhowells@redhat.com) -+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+ -+#ifndef _ASM_UBICOM32_THREAD_INFO_H -+#define _ASM_UBICOM32_THREAD_INFO_H -+ -+#include -+ -+/* -+ * Size of kernel stack for each process. This must be a power of 2... -+ */ -+#ifdef CONFIG_4KSTACKS -+#define THREAD_SIZE_ORDER (0) -+#else -+#define THREAD_SIZE_ORDER (1) -+#endif -+ -+/* -+ * for asm files, THREAD_SIZE is now generated by asm-offsets.c -+ */ -+#define THREAD_SIZE (PAGE_SIZE< preemptable, <0 => BUG */ -+ int interrupt_nesting; /* Interrupt nesting level. */ -+ struct restart_block restart_block; -+}; -+ -+/* -+ * macros/functions for gaining access to the thread information structure -+ */ -+#define INIT_THREAD_INFO(tsk) \ -+{ \ -+ .task = &tsk, \ -+ .exec_domain = &default_exec_domain, \ -+ .flags = 0, \ -+ .cpu = 0, \ -+ .interrupt_nesting = 0, \ -+ .restart_block = { \ -+ .fn = do_no_restart_syscall, \ -+ }, \ -+} -+ -+#define init_thread_info (init_thread_union.thread_info) -+#define init_stack (init_thread_union.stack) -+ -+ -+/* how to get the thread information struct from C */ -+static inline struct thread_info *current_thread_info(void) -+{ -+ struct thread_info *ti; -+ -+ asm ( -+ "and.4 %0, sp, %1\n\t" -+ : "=&r" (ti) -+ : "d" (~(THREAD_SIZE-1)) -+ : "cc" -+ ); -+ -+ return ti; -+} -+ -+#define STACK_WARN (THREAD_SIZE / 8) -+ -+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 1 -+ -+/* thread information allocation */ -+#define alloc_thread_info(tsk) ((struct thread_info *) \ -+ __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER)) -+#define free_thread_info(ti) free_pages((unsigned long) (ti), THREAD_SIZE_ORDER) -+#endif /* __ASSEMBLY__ */ -+ -+#define PREEMPT_ACTIVE 0x4000000 -+ -+/* -+ * thread information flag bit numbers -+ */ -+#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -+#define TIF_SIGPENDING 1 /* signal pending */ -+#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -+#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling -+ TIF_NEED_RESCHED */ -+#define TIF_MEMDIE 4 -+ -+/* as above, but as bit values */ -+#define _TIF_SYSCALL_TRACE (1<. -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_TYPES_H -+#define _ASM_UBICOM32_TYPES_H -+ -+/* -+ * This file is never included by application software unless -+ * explicitly requested (e.g., via linux/types.h) in which case the -+ * application is Linux specific so (user-) name space pollution is -+ * not a major issue. However, for interoperability, libraries still -+ * need to be careful to avoid a name clashes. -+ */ -+ -+#include -+ -+#ifndef __ASSEMBLY__ -+ -+typedef unsigned short umode_t; -+ -+#endif /* __ASSEMBLY__ */ -+ -+/* -+ * These aren't exported outside the kernel to avoid name space clashes -+ */ -+#ifdef __KERNEL__ -+ -+#define BITS_PER_LONG 32 -+ -+#ifndef __ASSEMBLY__ -+ -+/* DMA addresses are always 32-bits wide */ -+ -+typedef u32 dma_addr_t; -+typedef u32 dma64_addr_t; -+ -+/* -+ * XXX These are "Ubicom style" typedefs. They should be removed in all files used by linux. -+ */ -+typedef u32 u32_t; -+typedef s32 s32_t; -+typedef u16 u16_t; -+typedef s16 s16_t; -+typedef u8 u8_t; -+typedef s8 s8_t; -+ -+#endif /* __ASSEMBLY__ */ -+ -+#endif /* __KERNEL__ */ -+ -+#endif /* _ASM_UBICOM32_TYPES_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/ucontext.h -@@ -0,0 +1,39 @@ -+/* -+ * arch/ubicom32/include/asm/ucontext.h -+ * Definition of ucontext structure for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_UCONTEXT_H -+#define _ASM_UBICOM32_UCONTEXT_H -+ -+struct ucontext { -+ unsigned long uc_flags; -+ struct ucontext *uc_link; -+ stack_t uc_stack; -+ struct sigcontext uc_mcontext; -+ sigset_t uc_sigmask; /* mask last for extensibility */ -+}; -+ -+#endif /* _ASM_UBICOM32_UCONTEXT_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/unistd.h -@@ -0,0 +1,400 @@ -+/* -+ * arch/ubicom32/include/asm/unistd.h -+ * Ubicom32 architecture syscall definitions. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_UNISTD_H -+#define _ASM_UBICOM32_UNISTD_H -+ -+/* -+ * This file contains the system call numbers. -+ */ -+ -+#define __NR_restart_syscall 0 -+#define __NR_exit 1 -+#define __NR_fork 2 -+#define __NR_read 3 -+#define __NR_write 4 -+#define __NR_open 5 -+#define __NR_close 6 -+#define __NR_waitpid 7 -+#define __NR_creat 8 -+#define __NR_link 9 -+#define __NR_unlink 10 -+#define __NR_execve 11 -+#define __NR_chdir 12 -+#define __NR_time 13 -+#define __NR_mknod 14 -+#define __NR_chmod 15 -+#define __NR_chown 16 -+#define __NR_break 17 -+#define __NR_oldstat 18 -+#define __NR_lseek 19 -+#define __NR_getpid 20 -+#define __NR_mount 21 -+#define __NR_umount 22 -+#define __NR_setuid 23 -+#define __NR_getuid 24 -+#define __NR_stime 25 -+#define __NR_ptrace 26 -+#define __NR_alarm 27 -+#define __NR_oldfstat 28 -+#define __NR_pause 29 -+#define __NR_utime 30 -+#define __NR_stty 31 -+#define __NR_gtty 32 -+#define __NR_access 33 -+#define __NR_nice 34 -+#define __NR_ftime 35 -+#define __NR_sync 36 -+#define __NR_kill 37 -+#define __NR_rename 38 -+#define __NR_mkdir 39 -+#define __NR_rmdir 40 -+#define __NR_dup 41 -+#define __NR_pipe 42 -+#define __NR_times 43 -+#define __NR_prof 44 -+#define __NR_brk 45 -+#define __NR_setgid 46 -+#define __NR_getgid 47 -+#define __NR_signal 48 -+#define __NR_geteuid 49 -+#define __NR_getegid 50 -+#define __NR_acct 51 -+#define __NR_umount2 52 -+#define __NR_lock 53 -+#define __NR_ioctl 54 -+#define __NR_fcntl 55 -+#define __NR_mpx 56 -+#define __NR_setpgid 57 -+#define __NR_ulimit 58 -+#define __NR_oldolduname 59 -+#define __NR_umask 60 -+#define __NR_chroot 61 -+#define __NR_ustat 62 -+#define __NR_dup2 63 -+#define __NR_getppid 64 -+#define __NR_getpgrp 65 -+#define __NR_setsid 66 -+#define __NR_sigaction 67 -+#define __NR_sgetmask 68 -+#define __NR_ssetmask 69 -+#define __NR_setreuid 70 -+#define __NR_setregid 71 -+#define __NR_sigsuspend 72 -+#define __NR_sigpending 73 -+#define __NR_sethostname 74 -+#define __NR_setrlimit 75 -+#define __NR_getrlimit 76 -+#define __NR_getrusage 77 -+#define __NR_gettimeofday 78 -+#define __NR_settimeofday 79 -+#define __NR_getgroups 80 -+#define __NR_setgroups 81 -+#define __NR_select 82 -+#define __NR_symlink 83 -+#define __NR_oldlstat 84 -+#define __NR_readlink 85 -+#define __NR_uselib 86 -+#define __NR_swapon 87 -+#define __NR_reboot 88 -+#define __NR_readdir 89 -+#define __NR_mmap 90 -+#define __NR_munmap 91 -+#define __NR_truncate 92 -+#define __NR_ftruncate 93 -+#define __NR_fchmod 94 -+#define __NR_fchown 95 -+#define __NR_getpriority 96 -+#define __NR_setpriority 97 -+#define __NR_profil 98 -+#define __NR_statfs 99 -+#define __NR_fstatfs 100 -+#define __NR_ioperm 101 -+#define __NR_socketcall 102 -+#define __NR_syslog 103 -+#define __NR_setitimer 104 -+#define __NR_getitimer 105 -+#define __NR_stat 106 -+#define __NR_lstat 107 -+#define __NR_fstat 108 -+#define __NR_olduname 109 -+#define __NR_iopl /* 110 */ not supported -+#define __NR_vhangup 111 -+#define __NR_idle /* 112 */ Obsolete -+#define __NR_vm86 /* 113 */ not supported -+#define __NR_wait4 114 -+#define __NR_swapoff 115 -+#define __NR_sysinfo 116 -+#define __NR_ipc 117 -+#define __NR_fsync 118 -+#define __NR_sigreturn 119 -+#define __NR_clone 120 -+#define __NR_setdomainname 121 -+#define __NR_uname 122 -+#define __NR_cacheflush 123 -+#define __NR_adjtimex 124 -+#define __NR_mprotect 125 -+#define __NR_sigprocmask 126 -+#define __NR_create_module 127 -+#define __NR_init_module 128 -+#define __NR_delete_module 129 -+#define __NR_get_kernel_syms 130 -+#define __NR_quotactl 131 -+#define __NR_getpgid 132 -+#define __NR_fchdir 133 -+#define __NR_bdflush 134 -+#define __NR_sysfs 135 -+#define __NR_personality 136 -+#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -+#define __NR_setfsuid 138 -+#define __NR_setfsgid 139 -+#define __NR__llseek 140 -+#define __NR_getdents 141 -+#define __NR__newselect 142 -+#define __NR_flock 143 -+#define __NR_msync 144 -+#define __NR_readv 145 -+#define __NR_writev 146 -+#define __NR_getsid 147 -+#define __NR_fdatasync 148 -+#define __NR__sysctl 149 -+#define __NR_mlock 150 -+#define __NR_munlock 151 -+#define __NR_mlockall 152 -+#define __NR_munlockall 153 -+#define __NR_sched_setparam 154 -+#define __NR_sched_getparam 155 -+#define __NR_sched_setscheduler 156 -+#define __NR_sched_getscheduler 157 -+#define __NR_sched_yield 158 -+#define __NR_sched_get_priority_max 159 -+#define __NR_sched_get_priority_min 160 -+#define __NR_sched_rr_get_interval 161 -+#define __NR_nanosleep 162 -+#define __NR_mremap 163 -+#define __NR_setresuid 164 -+#define __NR_getresuid 165 -+#define __NR_getpagesize 166 -+#define __NR_query_module 167 -+#define __NR_poll 168 -+#define __NR_nfsservctl 169 -+#define __NR_setresgid 170 -+#define __NR_getresgid 171 -+#define __NR_prctl 172 -+#define __NR_rt_sigreturn 173 -+#define __NR_rt_sigaction 174 -+#define __NR_rt_sigprocmask 175 -+#define __NR_rt_sigpending 176 -+#define __NR_rt_sigtimedwait 177 -+#define __NR_rt_sigqueueinfo 178 -+#define __NR_rt_sigsuspend 179 -+#define __NR_pread64 180 -+#define __NR_pwrite64 181 -+#define __NR_lchown 182 -+#define __NR_getcwd 183 -+#define __NR_capget 184 -+#define __NR_capset 185 -+#define __NR_sigaltstack 186 -+#define __NR_sendfile 187 -+#define __NR_getpmsg 188 /* some people actually want streams */ -+#define __NR_putpmsg 189 /* some people actually want streams */ -+#define __NR_vfork 190 -+#define __NR_ugetrlimit 191 -+#define __NR_mmap2 192 -+#define __NR_truncate64 193 -+#define __NR_ftruncate64 194 -+#define __NR_stat64 195 -+#define __NR_lstat64 196 -+#define __NR_fstat64 197 -+#define __NR_chown32 198 -+#define __NR_getuid32 199 -+#define __NR_getgid32 200 -+#define __NR_geteuid32 201 -+#define __NR_getegid32 202 -+#define __NR_setreuid32 203 -+#define __NR_setregid32 204 -+#define __NR_getgroups32 205 -+#define __NR_setgroups32 206 -+#define __NR_fchown32 207 -+#define __NR_setresuid32 208 -+#define __NR_getresuid32 209 -+#define __NR_setresgid32 210 -+#define __NR_getresgid32 211 -+#define __NR_lchown32 212 -+#define __NR_setuid32 213 -+#define __NR_setgid32 214 -+#define __NR_setfsuid32 215 -+#define __NR_setfsgid32 216 -+#define __NR_pivot_root 217 -+#define __NR_getdents64 220 -+#define __NR_gettid 221 -+#define __NR_tkill 222 -+#define __NR_setxattr 223 -+#define __NR_lsetxattr 224 -+#define __NR_fsetxattr 225 -+#define __NR_getxattr 226 -+#define __NR_lgetxattr 227 -+#define __NR_fgetxattr 228 -+#define __NR_listxattr 229 -+#define __NR_llistxattr 230 -+#define __NR_flistxattr 231 -+#define __NR_removexattr 232 -+#define __NR_lremovexattr 233 -+#define __NR_fremovexattr 234 -+#define __NR_futex 235 -+#define __NR_sendfile64 236 -+#define __NR_mincore 237 -+#define __NR_madvise 238 -+#define __NR_fcntl64 239 -+#define __NR_readahead 240 -+#define __NR_io_setup 241 -+#define __NR_io_destroy 242 -+#define __NR_io_getevents 243 -+#define __NR_io_submit 244 -+#define __NR_io_cancel 245 -+#define __NR_fadvise64 246 -+#define __NR_exit_group 247 -+#define __NR_lookup_dcookie 248 -+#define __NR_epoll_create 249 -+#define __NR_epoll_ctl 250 -+#define __NR_epoll_wait 251 -+#define __NR_remap_file_pages 252 -+#define __NR_set_tid_address 253 -+#define __NR_timer_create 254 -+#define __NR_timer_settime 255 -+#define __NR_timer_gettime 256 -+#define __NR_timer_getoverrun 257 -+#define __NR_timer_delete 258 -+#define __NR_clock_settime 259 -+#define __NR_clock_gettime 260 -+#define __NR_clock_getres 261 -+#define __NR_clock_nanosleep 262 -+#define __NR_statfs64 263 -+#define __NR_fstatfs64 264 -+#define __NR_tgkill 265 -+#define __NR_utimes 266 -+#define __NR_fadvise64_64 267 -+#define __NR_mbind 268 -+#define __NR_get_mempolicy 269 -+#define __NR_set_mempolicy 270 -+#define __NR_mq_open 271 -+#define __NR_mq_unlink 272 -+#define __NR_mq_timedsend 273 -+#define __NR_mq_timedreceive 274 -+#define __NR_mq_notify 275 -+#define __NR_mq_getsetattr 276 -+#define __NR_waitid 277 -+#define __NR_vserver 278 -+#define __NR_add_key 279 -+#define __NR_request_key 280 -+#define __NR_keyctl 281 -+#define __NR_ioprio_set 282 -+#define __NR_ioprio_get 283 -+#define __NR_inotify_init 284 -+#define __NR_inotify_add_watch 285 -+#define __NR_inotify_rm_watch 286 -+#define __NR_migrate_pages 287 -+#define __NR_openat 288 -+#define __NR_mkdirat 289 -+#define __NR_mknodat 290 -+#define __NR_fchownat 291 -+#define __NR_futimesat 292 -+#define __NR_fstatat64 293 -+#define __NR_unlinkat 294 -+#define __NR_renameat 295 -+#define __NR_linkat 296 -+#define __NR_symlinkat 297 -+#define __NR_readlinkat 298 -+#define __NR_fchmodat 299 -+#define __NR_faccessat 300 -+#define __NR_pselect6 301 -+#define __NR_ppoll 302 -+#define __NR_unshare 303 -+#define __NR_set_robust_list 304 -+#define __NR_get_robust_list 305 -+#define __NR_splice 306 -+#define __NR_sync_file_range 307 -+#define __NR_tee 308 -+#define __NR_vmsplice 309 -+#define __NR_move_pages 310 -+#define __NR_sched_setaffinity 311 -+#define __NR_sched_getaffinity 312 -+#define __NR_kexec_load 313 -+#define __NR_getcpu 314 -+#define __NR_epoll_pwait 315 -+#define __NR_utimensat 316 -+#define __NR_signalfd 317 -+#define __NR_timerfd_create 318 -+#define __NR_eventfd 319 -+#define __NR_fallocate 320 -+#define __NR_timerfd_settime 321 -+#define __NR_timerfd_gettime 322 -+#define __NR_signalfd4 323 -+#define __NR_eventfd2 324 -+#define __NR_epoll_create1 325 -+#define __NR_dup3 326 -+#define __NR_pipe2 327 -+#define __NR_inotify_init1 328 -+ -+#ifdef __KERNEL__ -+ -+#define NR_syscalls 329 -+ -+#define __ARCH_WANT_IPC_PARSE_VERSION -+#define __ARCH_WANT_OLD_READDIR -+#define __ARCH_WANT_OLD_STAT -+#define __ARCH_WANT_STAT64 -+#define __ARCH_WANT_SYS_ALARM -+#define __ARCH_WANT_SYS_GETHOSTNAME -+#define __ARCH_WANT_SYS_PAUSE -+#define __ARCH_WANT_SYS_SGETMASK -+#define __ARCH_WANT_SYS_SIGNAL -+#define __ARCH_WANT_SYS_TIME -+#define __ARCH_WANT_SYS_UTIME -+#define __ARCH_WANT_SYS_WAITPID -+#define __ARCH_WANT_SYS_SOCKETCALL -+#define __ARCH_WANT_SYS_FADVISE64 -+#define __ARCH_WANT_SYS_GETPGRP -+#define __ARCH_WANT_SYS_LLSEEK -+#define __ARCH_WANT_SYS_NICE -+#define __ARCH_WANT_SYS_OLD_GETRLIMIT -+#define __ARCH_WANT_SYS_OLDUMOUNT -+#define __ARCH_WANT_SYS_SIGPENDING -+#define __ARCH_WANT_SYS_SIGPROCMASK -+#define __ARCH_WANT_SYS_RT_SIGACTION -+ -+/* -+ * "Conditional" syscalls -+ * -+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))), -+ * but it doesn't work on all toolchains, so we just do it by hand -+ */ -+//#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") -+#define cond_syscall(x) long x(void) __attribute__((weak,alias("sys_ni_syscall"))) -+#endif /* __KERNEL__ */ -+ -+#endif /* _ASM_UBICOM32_UNISTD_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/user.h -@@ -0,0 +1,82 @@ -+/* -+ * arch/ubicom32/include/asm/user.h -+ * Ubicom32 architecture core file definitions. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_USER_H -+#define _ASM_UBICOM32_USER_H -+ -+#include -+#include -+/* -+ * Adapted from -+ * -+ * Core file format: The core file is written in such a way that gdb -+ * can understand it and provide useful information to the user (under -+ * linux we use the `trad-core' bfd, NOT the osf-core). The file contents -+ * are as follows: -+ * -+ * upage: 1 page consisting of a user struct that tells gdb -+ * what is present in the file. Directly after this is a -+ * copy of the task_struct, which is currently not used by gdb, -+ * but it may come in handy at some point. All of the registers -+ * are stored as part of the upage. The upage should always be -+ * only one page long. -+ * data: The data segment follows next. We use current->end_text to -+ * current->brk to pick up all of the user variables, plus any memory -+ * that may have been sbrk'ed. No attempt is made to determine if a -+ * page is demand-zero or if a page is totally unused, we just cover -+ * the entire range. All of the addresses are rounded in such a way -+ * that an integral number of pages is written. -+ * stack: We need the stack information in order to get a meaningful -+ * backtrace. We need to write the data from usp to -+ * current->start_stack, so we round each of these in order to be able -+ * to write an integer number of pages. -+ */ -+ -+struct user_ubicom32fp_struct { -+}; -+ -+struct user { -+ struct pt_regs regs; /* entire machine state */ -+ size_t u_tsize; /* text size (pages) */ -+ size_t u_dsize; /* data size (pages) */ -+ size_t u_ssize; /* stack size (pages) */ -+ unsigned long start_code; /* text starting address */ -+ unsigned long start_data; /* data starting address */ -+ unsigned long start_stack; /* stack starting address */ -+ long int signal; /* signal causing core dump */ -+ unsigned long u_ar0; /* help gdb find registers */ -+ unsigned long magic; /* identifies a core file */ -+ char u_comm[32]; /* user command name */ -+}; -+ -+#define NBPG PAGE_SIZE -+#define UPAGES 1 -+#define HOST_TEXT_START_ADDR (u.start_code) -+#define HOST_DATA_START_ADDR (u.start_data) -+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) -+ -+#endif /* _ASM_UBICOM32_USER_H */ ---- /dev/null -+++ b/arch/ubicom32/include/asm/xor.h -@@ -0,0 +1,33 @@ -+/* -+ * arch/ubicom32/include/asm/xor.h -+ * Generic xor.h definitions for Ubicom32 architecture. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+#ifndef _ASM_UBICOM32_XOR_H -+#define _ASM_UBICOM32_XOR_H -+ -+#include -+ -+#endif /* _ASM_UBICOM32_XOR_H */ ---- /dev/null -+++ b/arch/ubicom32/Kconfig -@@ -0,0 +1,455 @@ -+# -+# For a description of the syntax of this configuration file, -+# see Documentation/kbuild/kconfig-language.txt. -+# -+ -+mainmenu "uClinux/ubicom32 (w/o MMU) Kernel Configuration" -+ -+config RAMBASE -+ hex -+ default "0x40000000" -+ help -+ Define the address that RAM starts at. -+ -+config UBICOM32 -+ bool -+ select HAVE_OPROFILE -+ default y -+ -+config RAMKERNEL -+ bool -+ default y -+ -+config CPU_BIG_ENDIAN -+ bool -+ default y -+ -+config FORCE_MAX_ZONEORDER -+ int -+ default "14" -+ -+config HAVE_CLK -+ bool -+ default y -+ -+config MMU -+ bool -+ default n -+ -+config FPU -+ bool -+ default n -+ -+config ZONE_DMA -+ bool -+ default y -+ -+config RWSEM_GENERIC_SPINLOCK -+ bool -+ default y -+ -+config RWSEM_XCHGADD_ALGORITHM -+ bool -+ default n -+ -+config ARCH_HAS_ILOG2_U32 -+ bool -+ default n -+ -+config ARCH_HAS_ILOG2_U64 -+ bool -+ default n -+ -+config GENERIC_FIND_NEXT_BIT -+ bool -+ default y -+ -+config GENERIC_GPIO -+ bool -+ default y -+ -+config GPIOLIB -+ bool -+ default y -+ -+config GENERIC_HWEIGHT -+ bool -+ default y -+ -+config GENERIC_HARDIRQS -+ bool -+ default y -+ -+config STACKTRACE_SUPPORT -+ bool -+ default y -+ -+config LOCKDEP_SUPPORT -+ bool -+ default y -+ -+config GENERIC_CALIBRATE_DELAY -+ bool -+ default y -+ -+config GENERIC_TIME -+ bool -+ default y -+ -+config TIME_LOW_RES -+ bool -+ default y -+ -+config GENERIC_CLOCKEVENTS -+ bool -+ default y -+ -+config GENERIC_CLOCKEVENTS_BROADCAST -+ bool -+ depends on GENERIC_CLOCKEVENTS -+ default y if SMP && !LOCAL_TIMERS -+ -+config NO_IOPORT -+ def_bool y -+ -+config ARCH_SUPPORTS_AOUT -+ def_bool y -+ -+config IRQ_PER_CPU -+ bool -+ default y -+ -+config SCHED_NO_NO_OMIT_FRAME_POINTER -+ bool -+ default y -+ -+menu "Processor type and features" -+ -+config BRD_32MB -+ bool -+ depends on IP5160EVAL -+ help -+ Board has 32MB of RAM on it. It is a hidden option used to select default for size of RAM -+ default n -+ -+config BRD_64MB -+ bool -+ depends on IP7145DPF || IP7160RGW || IP7160BRINGUP || IP7160DPF || IP5170DPF || IP5160DEV -+ help -+ Board has 64MB of RAM on it. It is a hidden option used to select default for size of RAM -+ default n -+ -+config BRD_128MB -+ bool -+ depends on IP7500MODULE || IP7500AV || IP7500MEDIA -+ help -+ Board has 128MB of RAM on it. It is a hidden option used to select default for size of RAM -+ default n -+ -+comment "Processor type will be selected by Board" -+ -+config UBICOM32_V3 -+ bool -+ help -+ Ubicom IP5xxx series processor support. -+ -+config UBICOM32_V4 -+ bool -+ help -+ Ubicom IP7xxx series processor support. -+ -+comment "Board" -+choice -+ prompt "Board type" -+ help -+ Select your board. -+ -+config NOBOARD -+ bool "No board selected" -+ help -+ Default. Don't select any board specific config. Will not build unless you change! -+ -+# Add your boards here -+source "arch/ubicom32/mach-ip5k/Kconfig" -+source "arch/ubicom32/mach-ip7k/Kconfig" -+ -+endchoice -+ -+comment "Kernel Options" -+config SMP -+ bool "Symmetric multi-processing support" -+ select USE_GENERIC_SMP_HELPERS -+ default n -+ help -+ Enables multithreading support. Enabling SMP support increases -+ the size of system data structures. SMP support can have either -+ positive or negative impact on performance depending on workloads. -+ -+ If you do not know what to do here, say N. -+ -+config NR_CPUS -+ int "Number of configured CPUs" -+ range 2 32 -+ default 2 -+ depends on SMP -+ help -+ Upper bound on the number of CPUs. Space is reserved -+ at compile time for this many CPUs. -+ -+config LOCAL_TIMERS -+ bool "Use local timer interrupts" -+ depends on SMP -+ default y -+ help -+ Enable support for local timers on SMP platforms, rather then the -+ legacy IPI broadcast method. Local timers allows the system -+ accounting to be spread across the timer interval, preventing a -+ "thundering herd" at every timer tick. A physical timer is allocated -+ per cpu. -+ -+config TIMER_EXTRA_ALLOC -+ int "Number of additional physical timer events to create" -+ depends on GENERIC_CLOCKEVENTS -+ default 0 -+ help -+ The Ubicom32 processor has a number of event timers that can be wrapped -+ in Linux clock event structures (assuming that the timers are not being -+ used for another purpose). Based on the value of LOCAL_TIMERS, either -+ 2 timers will be used or a timer will be used for every CPU. This value -+ allows the programmer to select additional timers over that amount. -+ -+config IRQSTACKS -+ bool "Create separate stacks for interrupt handling" -+ default n -+ help -+ Selecting this causes interrupts to be created on a separate -+ stack instead of nesting the interrupts on the kernel stack. -+ -+config IRQSTACKS_USEOCM -+ bool "Use OCM for interrupt stacks" -+ default n -+ depends on IRQSTACKS -+ help -+ Selecting this cause the interrupt stacks to be placed in OCM -+ reducing cache misses at the expense of using the OCM for servicing -+ interrupts. -+ -+menu "OCM Instruction Heap" -+ -+config OCM_MODULES_RESERVATION -+ int "OCM Instruction heap reservation. 0-192 kB" -+ range 0 192 -+ default "0" -+ help -+ The minimum amount of OCM memory to reserve for kernel loadable module -+ code. If you are not using this memory it cannot be used for anything -+ else. Leave it as 0 if you have prebuilt modules that are compiled with -+ OCM support. -+ -+config OCM_MODULES_MAY_CONSUME_REMAINING_CODESPACE -+ bool "Give all unused ocm code space to the ocm instruction heap." -+ default n -+ help -+ Allow the OCM instruction heap allocation to consume any remaining -+ unused OCM code space. The result of this is that you will not have -+ and deterministic results, but you will not have any waste either. -+ -+config OCM_MODULES_FALLBACK_TO_DDR -+ bool "Loadable Modules requiring OCM may fallback to use DDR." -+ default n -+ help -+ If a module cannot get the OCM code it requires allow DDR to -+ be used instead. -+endmenu -+ -+config HZ -+ int "Frequency of 'jiffies' (for polling)" -+ default 1000 -+ help -+ 100 is common for embedded systems, but 1000 allows -+ you to do more drivers without actually having -+ interrupts working properly. -+ -+comment "RAM configuration" -+ -+if BRD_32MB -+ -+config RAMSIZE -+ hex "Size of RAM (in bytes)" -+ range 0x00000000 0x02000000 -+ default "0x02000000" -+ help -+ Define the size of the system RAM. If you select 0 then the -+ kernel will try to probe the RAM size at runtime. This is not -+ supported on all CPU types. -+ -+endif -+ -+if BRD_64MB -+ -+config RAMSIZE -+ hex "Size of RAM (in bytes)" -+ range 0x00000000 0x04000000 -+ default "0x04000000" -+ help -+ Define the size of the system RAM. If you select 0 then the -+ kernel will try to probe the RAM size at runtime. This is not -+ supported on all CPU types. -+ -+endif -+ -+if BRD_128MB -+ -+config RAMSIZE -+ hex "Size of RAM (in bytes)" -+ range 0x00000000 0x08000000 -+ default "0x08000000" -+ help -+ Define the size of the system RAM. If you select 0 then the -+ kernel will try to probe the RAM size at runtime. This is not -+ supported on all CPU types. -+ -+endif -+ -+config KERNELBASE -+ hex "Address of the base of kernel code" -+ default "0x40400000" -+ help -+ For the time being we are going to start the Kernel at a 4 meg offset. -+ -+comment "Build options" -+config LINKER_RELAXATION -+ bool "Linker Relaxation" -+ default y -+ help -+ Turns on linker relaxation that will produce smaller -+ faster code. Increases link time. -+ -+comment "Driver options" -+menu "PCI Bus" -+config PCI -+ bool "PCI bus" -+ default true -+ help -+ Enable/Disable PCI bus -+ source "drivers/pci/Kconfig" -+ -+ -+config PCI_DEV0_IDSEL -+ hex "slot 0 address" -+ depends on PCI -+ default "0x01000000" -+ help -+ Slot 0 address. This address should correspond to the address line -+ which the IDSEL bit for this slot is connected to. -+ -+config PCI_DEV1_IDSEL -+ hex "slot 1 address" -+ depends on PCI -+ default "0x02000000" -+ help -+ Slot 1 address. This address should correspond to the address line -+ which the IDSEL bit for this slot is connected to. -+endmenu -+# End PCI -+ -+menu "Input devices" -+config UBICOM_INPUT -+ bool "Ubicom polled GPIO input driver" -+ select INPUT -+ select INPUT_POLLDEV -+ help -+ Polling input driver, much like the GPIO input driver, except that it doesn't -+ rely on interrupts. It will report events via the input subsystem. -+ default n -+ -+config UBICOM_INPUT_I2C -+ bool "Ubicom polled GPIO input driver over I2C" -+ select INPUT -+ select INPUT_POLLDEV -+ help -+ Polling input driver, much like the PCA953x driver, it can support a variety of -+ different I2C I/O expanders. This device polls the I2C I/O expander for events -+ and reports them via the input subsystem. -+ default n -+endmenu -+# Input devices -+ -+menu "Misc devices" -+config UBICOM_HID -+ bool "Ubicom HID driver" -+ select INPUT -+ select INPUT_POLLDEV -+ select LCD_CLASS_DEVICE -+ help -+ Driver for HID chip found on some Ubicom reference designs. This chip handles -+ PWM, button input, and IR remote control. It registers as an input device and -+ a backlight device. -+ default n -+endmenu -+# Misc devices -+ -+config CMDLINE_BOOL -+ bool "Built-in kernel command line" -+ default n -+ help -+ Allow for specifying boot arguments to the kernel at -+ build time. On some systems (e.g. embedded ones), it is -+ necessary or convenient to provide some or all of the -+ kernel boot arguments with the kernel itself (that is, -+ to not rely on the boot loader to provide them.) -+ -+ To compile command line arguments into the kernel, -+ set this option to 'Y', then fill in the -+ the boot arguments in CONFIG_CMDLINE. -+ -+ Systems with fully functional boot loaders (i.e. non-embedded) -+ should leave this option set to 'N'. -+ -+config CMDLINE -+ string "Built-in kernel command string" -+ depends on CMDLINE_BOOL -+ default "" -+ help -+ Enter arguments here that should be compiled into the kernel -+ image and used at boot time. If the boot loader provides a -+ command line at boot time, it is appended to this string to -+ form the full kernel command line, when the system boots. -+ -+ However, you can use the CONFIG_CMDLINE_OVERRIDE option to -+ change this behavior. -+ -+ In most cases, the command line (whether built-in or provided -+ by the boot loader) should specify the device for the root -+ file system. -+ -+config CMDLINE_OVERRIDE -+ bool "Built-in command line overrides boot loader arguments" -+ default n -+ depends on CMDLINE_BOOL -+ help -+ Set this option to 'Y' to have the kernel ignore the boot loader -+ command line, and use ONLY the built-in command line. -+ -+ This is used to work around broken boot loaders. This should -+ be set to 'N' under normal conditions. -+ -+endmenu -+# End Processor type and features -+ -+source "arch/ubicom32/Kconfig.debug" -+ -+menu "Executable file formats" -+source "fs/Kconfig.binfmt" -+endmenu -+ -+source "init/Kconfig" -+source "kernel/Kconfig.preempt" -+source "kernel/time/Kconfig" -+source "mm/Kconfig" -+source "net/Kconfig" -+source "drivers/Kconfig" -+source "fs/Kconfig" -+source "security/Kconfig" -+source "crypto/Kconfig" -+source "lib/Kconfig" ---- /dev/null -+++ b/arch/ubicom32/Kconfig.debug -@@ -0,0 +1,117 @@ -+menu "Kernel hacking" -+ -+config TRACE_IRQFLAGS_SUPPORT -+ def_bool y -+ -+config PROTECT_KERNEL -+ default y -+ bool 'Enable Kernel range register Protection' -+ help -+ Adds code to enable/disable range registers to protect static -+ kernel code/data from userspace. Currently the ranges covered -+ do no protect kernel loadable modules or dynamically allocated -+ kernel data. -+ -+config NO_KERNEL_MSG -+ bool "Suppress Kernel BUG Messages" -+ help -+ Do not output any debug BUG messages within the kernel. -+ -+config EARLY_PRINTK -+ bool "Use the driver that you selected as console also for early printk (to debug kernel bootup)." -+ default n -+ help -+ If you want to use the serdes driver (console=ttyUS0) for -+ early printk, you must also supply an additional kernel boot -+ parameter like this: -+ -+ serdes=ioportaddr,irq,clockrate,baud -+ -+ For an IP7160RGW eval board, you could use this: -+ -+ serdes=0x2004000,61,250000000,57600 -+ -+ which will let you see early printk output at 57600 baud. -+ -+config STOP_ON_TRAP -+ bool "Enable stopping at the LDSR for all traps" -+ default n -+ help -+ Cause the LDSR to stop all threads whenever a trap is about to be serviced -+ -+config STOP_ON_BUG -+ bool "Enable stopping on failed BUG_ON()" -+ default n -+ help -+ Cause all BUG_ON failures to stop all threads -+ -+config DEBUG_IRQMEASURE -+ bool "Enable IRQ handler measurements" -+ default n -+ help -+ When enabled each IRQ's min/avg/max times will be printed. If the handler -+ re-enables interrupt, the times will show the full time including to service -+ nested interrupts. See /proc/irq_measurements. -+ -+config DEBUG_PCIMEASURE -+ bool "Enable PCI transaction measurements" -+ default n -+ help -+ When enabled the system will measure the min/avg/max timer for each PCI transactions. -+ See /proc/pci_measurements. -+ -+config ACCESS_OK_CHECKS_ENABLED -+ bool "Enable user space access checks" -+ default n -+ help -+ Enabling this check causes the kernel to verify that addresses passed -+ to the kernel by the user space code are within the processes -+ address space. On a no-mmu system, this is done by examining the -+ processes memory data structures (adversly affecting performance) but -+ ensuring that a process does not ask the kernel to violate another -+ processes address space. Sadly, the kernel uses access_ok() for -+ address that are in the kernel which results in a large volume of -+ false positives. -+ -+choice -+ prompt "Unaligned Access Support" -+ default UNALIGNED_ACCESS_ENABLED -+ help -+ Kernel / Userspace unaligned access handling. -+ -+config UNALIGNED_ACCESS_ENABLED -+ bool "Kernel and Userspace" -+ help -+ -+config UNALIGNED_ACCESS_USERSPACE_ONLY -+ bool "Userspace Only" -+ help -+ -+config UNALIGNED_ACCESS_DISABLED -+ bool "Disabled" -+ help -+ -+endchoice -+ -+config DEBUG_STACKOVERFLOW -+ bool "Check for stack overflows" -+ default n -+ depends on DEBUG_KERNEL -+ help -+ This option will cause messages to be printed if free kernel stack space -+ drops below a certain limit (THREAD_SIZE /8). -+ -+config DEBUG_STACK_USAGE -+ bool "Stack utilization instrumentation" -+ default n -+ depends on DEBUG_KERNEL -+ help -+ Enables the display of the minimum amount of free kernel stack which each -+ task has ever had available in the sysrq-T and sysrq-P debug output. -+ -+ This option will slow down process creation somewhat. -+ -+source "lib/Kconfig.debug" -+ -+endmenu -+ ---- /dev/null -+++ b/arch/ubicom32/Makefile -@@ -0,0 +1,103 @@ -+# -+# arch/ubicom32/Makefile -+# -+# -+# (C) Copyright 2009, Ubicom, Inc. -+# -+# This file is part of the Ubicom32 Linux Kernel Port. -+# -+# The Ubicom32 Linux Kernel Port is free software: you can redistribute -+# it and/or modify it under the terms of the GNU General Public License -+# as published by the Free Software Foundation, either version 2 of the -+# License, or (at your option) any later version. -+# -+# The Ubicom32 Linux Kernel Port is distributed in the hope that it -+# will be useful, but WITHOUT ANY WARRANTY; without even the implied -+# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+# the GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with the Ubicom32 Linux Kernel Port. If not, -+# see . -+# -+# Ubicom32 implementation derived from (with many thanks): -+# arch/m68knommu -+# arch/blackfin -+# arch/parisc -+# -+ -+KBUILD_DEFCONFIG := -+ -+# setup the machine name and machine dependent settings -+machine-$(CONFIG_UBICOM32_V3) := ip5k -+machine-$(CONFIG_UBICOM32_V4) := ip7k -+MACHINE := $(machine-y) -+export MACHINE -+ -+model-$(CONFIG_RAMKERNEL) := ram -+model-$(CONFIG_ROMKERNEL) := rom -+MODEL := $(model-y) -+export MODEL -+ -+CPUCLASS := $(cpuclass-y) -+ -+export CPUCLASS -+ -+# -+# We want the core kernel built using the fastcall ABI but modules need -+# to be built using the slower calling convention because they could be -+# loaded out of range for fast calls. -+# -+CFLAGS_KERNEL += -mfastcall -+CFLAGS_MODULE += -mno-fastcall -+ -+# -+# Some CFLAG additions based on specific CPU type. -+# -+cflags-$(CONFIG_UBICOM32_V3) := -march=ubicom32v3 -mno-fdpic -DIP5000 -+cflags-$(CONFIG_UBICOM32_V4) := -march=ubicom32v4 -mno-fdpic -DIP7000 -+ -+ldflags-$(CONFIG_LINKER_RELAXATION) := --relax -+LDFLAGS_vmlinux := $(ldflags-y) -+ -+GCCLIBDIR := $(dir $(shell $(CC) $(cflags-y) -print-libgcc-file-name)) -+ -+KBUILD_CFLAGS += $(cflags-y) -ffunction-sections -+KBUILD_AFLAGS += $(cflags-y) -+ -+KBUILD_CFLAGS += -D__linux__ -Dlinux -+KBUILD_CFLAGS += -DUTS_SYSNAME=\"uClinux\" -+ -+# include any machine specific directory -+ifneq ($(machine-y),) -+core-y += arch/$(ARCH)/mach-$(MACHINE)/ -+endif -+ -+head-y := arch/$(ARCH)/kernel/head.o -+ -+core-y += arch/$(ARCH)/kernel/ \ -+ arch/$(ARCH)/mm/ \ -+ arch/$(ARCH)/crypto/ \ -+ arch/$(ARCH)/mach-common/ -+ -+drivers-$(CONFIG_OPROFILE) += arch/ubicom32/oprofile/ -+ -+libs-y += arch/$(ARCH)/lib/ -+ -+archclean: -+ -+# make sure developer has selected a valid board -+ifeq ($(CONFIG_NOBOARD),y) -+# $(error have to select a valid board file $(CONFIG_NOBOARD), please run kernel config again) -+_all: config_board_error -+endif -+ -+config_board_error: -+ @echo "*************************************************" -+ @echo "You have not selected a proper board." -+ @echo "Please run menuconfig (or config) against your" -+ @echo "kernel and choose your board under Processor" -+ @echo "options" -+ @echo "*************************************************" -+ @exit 1 -+ ---- /dev/null -+++ b/arch/ubicom32/kernel/asm-offsets.c -@@ -0,0 +1,162 @@ -+/* -+ * arch/ubicom32/kernel/asm-offsets.c -+ * Ubicom32 architecture definitions needed by assembly language modules. -+ * -+ * (C) Copyright 2009, Ubicom, Inc. -+ * -+ * This file is part of the Ubicom32 Linux Kernel Port. -+ * -+ * The Ubicom32 Linux Kernel Port is free software: you can redistribute -+ * it and/or modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation, either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * The Ubicom32 Linux Kernel Port is distributed in the hope that it -+ * will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ * the GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with the Ubicom32 Linux Kernel Port. If not, -+ * see . -+ * -+ * Ubicom32 implementation derived from (with many thanks): -+ * arch/m68knommu -+ * arch/blackfin -+ * arch/parisc -+ */ -+/* -+ * This program is used to generate definitions needed by -+ * assembly language modules. -+ * -+ * We use the technique used in the OSF Mach kernel code: -+ * generate asm statements containing #defines, -+ * compile this file to assembler, and then extract the -+ * #defines from the assembly-language output. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DEFINE(sym, val) \ -+ asm volatile("\n->" #sym " %0 " #val : : "i" (val)) -+ -+#define BLANK() asm volatile("\n->" : : ) -+ -+int main(void) -+{ -+ /* offsets into the task struct */ -+ DEFINE(TASK_STATE, offsetof(struct task_struct, state)); -+ DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags)); -+ DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace)); -+ DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked)); -+ DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); -+ DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack)); -+ DEFINE(TASK_MM, offsetof(struct task_struct, mm)); -+ DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); -+ -+ /* offsets into the kernel_stat struct */ -+ DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs)); -+ -+ /* offsets into the irq_cpustat_t struct */ -+ DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); -+ -+ /* offsets into the thread struct */ -+ DEFINE(THREAD_D10, offsetof(struct thread_struct, d10)); -+ DEFINE(THREAD_D11, offsetof(struct thread_struct, d11)); -+ DEFINE(THREAD_D12, offsetof(struct thread_struct, d12)); -+ DEFINE(THREAD_D13, offsetof(struct thread_struct, d13)); -+ DEFINE(THREAD_A1, offsetof(struct thread_struct, a1)); -+ DEFINE(THREAD_A2, offsetof(struct thread_struct, a2)); -+ DEFINE(THREAD_A5, offsetof(struct thread_struct, a5)); -+ DEFINE(THREAD_A6, offsetof(struct thread_struct, a6)); -+ DEFINE(THREAD_SP, offsetof(struct thread_struct, sp)); -+ -+ /* offsets into the pt_regs */ -+ DEFINE(PT_D0, offsetof(struct pt_regs, dn[0])); -+ DEFINE(PT_D1, offsetof(struct pt_regs, dn[1])); -+ DEFINE(PT_D2, offsetof(struct pt_regs, dn[2])); -+ DEFINE(PT_D3, offsetof(struct pt_regs, dn[3])); -+ DEFINE(PT_D4, offsetof(struct pt_regs, dn[4])); -+ DEFINE(PT_D5, offsetof(struct pt_regs, dn[5])); -+ DEFINE(PT_D6, offsetof(struct pt_regs, dn[6])); -+ DEFINE(PT_D7, offsetof(struct pt_regs, dn[7])); -+ DEFINE(PT_D8, offsetof(struct pt_regs, dn[8])); -+ DEFINE(PT_D9, offsetof(struct pt_regs, dn[9])); -+ DEFINE(PT_D10, offsetof(struct pt_regs, dn[10])); -+ DEFINE(PT_D11, offsetof(struct pt_regs, dn[11])); -+ DEFINE(PT_D12, offsetof(struct pt_regs, dn[12])); -+ DEFINE(PT_D13, offsetof(struct pt_regs, dn[13])); -+ DEFINE(PT_D14, offsetof(struct pt_regs, dn[14])); -+ DEFINE(PT_D15, offsetof(struct pt_regs, dn[15])); -+ DEFINE(PT_A0, offsetof(struct pt_regs, an[0])); -+ DEFINE(PT_A1, offsetof(struct pt_regs, an[1])); -+ DEFINE(PT_A2, offsetof(struct pt_regs, an[2])); -+ DEFINE(PT_A3, offsetof(struct pt_regs, an[3])); -+ DEFINE(PT_A4, offsetof(struct pt_regs, an[4])); -+ DEFINE(PT_A5, offsetof(struct pt_regs, an[5])); -+ DEFINE(PT_A6, offsetof(struct pt_regs, an[6])); -+ DEFINE(PT_A7, offsetof(struct pt_regs, an[7])); -+ DEFINE(PT_SP, offsetof(struct pt_regs, an[7])); -+ -+ DEFINE(PT_ACC0HI, offsetof(struct pt_regs, acc0[0])); -+ DEFINE(PT_ACC0LO, offsetof(struct pt_regs, acc0[1])); -+ DEFINE(PT_MAC_RC16, offsetof(struct pt_regs, mac_rc16)); -+ -+ DEFINE(PT_ACC1HI, offsetof(struct pt_regs, acc1[0])); -+ DEFINE(PT_ACC1LO, offsetof(struct pt_regs, acc1[1])); -+ -+ DEFINE(PT_SOURCE3, offsetof(struct pt_regs, source3)); -+ DEFINE(PT_INST_CNT, offsetof(struct pt_regs, inst_cnt)); -+ DEFINE(PT_CSR, offsetof(struct pt_regs, csr)); -+ DEFINE(PT_DUMMY_UNUSED, offsetof(struct pt_regs, dummy_unused)); -+ -+ DEFINE(PT_INT_MASK0, offsetof(struct pt_regs, int_mask0)); -+ DEFINE(PT_INT_MASK1, offsetof(struct pt_regs, int_mask1)); -+ -+ DEFINE(PT_PC, offsetof(struct pt_regs, pc)); -+ -+ DEFINE(PT_TRAP_CAUSE, offsetof(struct pt_regs, trap_cause)); -+ -+ DEFINE(PT_SIZE, sizeof(struct pt_regs)); -+ -+ DEFINE(PT_FRAME_TYPE, offsetof(struct pt_regs, frame_type)); -+ -+ DEFINE(PT_ORIGINAL_D0, offsetof(struct pt_regs, original_dn_0)); -+ DEFINE(PT_PREVIOUS_PC, offsetof(struct pt_regs, previous_pc)); -+ -+ /* offsets into the kernel_stat struct */ -+ DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs)); -+ -+ /* signal defines */ -+ DEFINE(SIGSEGV, SIGSEGV); -+ //DEFINE(SEGV_MAPERR, SEGV_MAPERR); -+ DEFINE(SIGTRAP, SIGTRAP); -+ //DEFINE(TRAP_TRACE, TRAP_TRACE); -+ -+ DEFINE(PT_PTRACED, PT_PTRACED); -+ DEFINE(PT_DTRACE, PT_DTRACE); -+ -+ DEFINE(ASM_THREAD_SIZE, THREAD_SIZE); -+ -+ /* Offsets in thread_info structure */ -+ DEFINE(TI_TASK, offsetof(struct thread_info, task)); -+ DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain)); -+ DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); -+ DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count)); -+ DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); -+ DEFINE(TI_INTR_NESTING, offsetof(struct thread_info, interrupt_nesting)); -+ DEFINE(ASM_TIF_NEED_RESCHED, TIF_NEED_RESCHED); -+ DEFINE(ASM_TIF_SYSCALL_TRACE, TIF_SYSCALL_TRACE); -+ DEFINE(ASM_TIF_SIGPENDING, TIF_SIGPENDING); -+ -+ DEFINE(ASM_RAM_END, (CONFIG_RAMBASE + CONFIG_RAMSIZE)); -+ return 0; -+} ---- /dev/null -+++ b/arch/ubicom32/kernel/Makefile -@@ -0,0 +1,64 @@ -+# -+# arch/ubicom32/kernel/Makefile -+# Main Makefile for the Ubicom32 arch directory. -+# -+# (C) Copyright 2009, Ubicom, Inc. -+# -+# This file is part of the Ubicom32 Linux Kernel Port. -+# -+# The Ubicom32 Linux Kernel Port is free software: you can redistribute -+# it and/or modify it under the terms of the GNU General Public License -+# as published by the Free Software Foundation, either version 2 of the -+# License, or (at your option) any later version. -+# -+# The Ubicom32 Linux Kernel Port is distributed in the hope that it -+# will be useful, but WITHOUT ANY WARRANTY; without even the implied -+# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+# the GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with the Ubicom32 Linux Kernel Port. If not, -+# see . -+# -+# Ubicom32 implementation derived from (with many thanks): -+# arch/m68knommu -+# arch/blackfin -+# arch/parisc -+# -+ -+extra-y := head.o vmlinux.lds -+ -+obj-y += \ -+ devtree.o \ -+ dma.o \ -+ flat.o \ -+ init_task.o \ -+ irq.o \ -+ ldsr.o \ -+ os_node.o \ -+ process.o \ -+ processor.o \ -+ ptrace.o \ -+ setup.o \ -+ signal.o \ -+ stacktrace.o \ -+ sys_ubicom32.o \ -+ syscalltable.o \ -+ thread.o \ -+ time.o \ -+ traps.o \ -+ ubicom32_context_switch.o \ -+ ubicom32_ksyms.o \ -+ ubicom32_syscall.o \ -+ unaligned_trap.o -+ -+obj-$(CONFIG_MODULES) += module.o -+obj-$(CONFIG_COMEMPCI) += comempci.o -+obj-$(CONFIG_SMP) += smp.o topology.o -+obj-$(CONFIG_ACCESS_OK_CHECKS_ENABLED) += uaccess.o -+obj-$(CONFIG_GENERIC_CLOCKEVENTS) += timer_device.o -+obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += timer_broadcast.o -+ -+ifndef CONFIG_GENERIC_CLOCKEVENTS -+obj-y += timer_tick.o -+endif ---- /dev/null -+++ b/arch/ubicom32/mach-ip5k/Kconfig -@@ -0,0 +1,32 @@ -+ -+config IP5170DPF -+ bool "IP5170DPF" -+ select UBICOM32_V3 -+ select I2C -+ select I2C_GPIO -+ select FB -+ select FB_UBICOM32 -+ select BACKLIGHT_LCD_SUPPORT -+ select BACKLIGHT_CLASS_DEVICE -+ select UBICOM_HID -+ select NEW_LEDS -+ select LEDS_CLASS -+ select LEDS_GPIO -+ select BRD_64MB -+ help -+ IP5170 Digital Picture Frame board, 8005-1113, IP5K-BEV-0011-13 v1.3 -+ -+config IP5160DEV -+ bool "IP5160Dev_Ver1Dot1" -+ select UBICOM32_V3 -+ select BRD_64MB -+ help -+ Ubicom StreamEngine 5000 Development Board, IP5K-BDV-0004-11 v1.1 -+ -+config IP5160EVAL -+ bool "IP5160RGWEval_Ver2Rev2" -+ select UBICOM32_V3 -+ select BRD_32MB -+ help -+ Ubicom StreamEngine 5000 RGW Evaluation Board, IP5K-RGW-0004-11 v2.2 -+ ---- /dev/null -+++ b/arch/ubicom32/mach-ip7k/Kconfig -@@ -0,0 +1,132 @@ -+config IP7145DPF -+ bool "IP7145DPF" -+ select UBICOM32_V4 -+ select UBICOM_INPUT -+ select UBICOM_INPUT_I2C -+ select RTC_CLASS -+ select RTC_DRV_S35390A -+ select I2C -+ select I2C_GPIO -+ select GPIO_PCA953X -+ select FB -+ select FB_UBICOM32 -+ select BACKLIGHT_LCD_SUPPORT -+ select LCD_CLASS_DEVICE -+ select LCD_UBICOM32 -+ select BACKLIGHT_CLASS_DEVICE -+ select BACKLIGHT_UBICOM32 -+ select SND_UBI32 -+ select MMC_UBICOM32 -+ select MMC -+ select MMC_BLOCK -+ select BRD_64MB -+ help -+ IP7145 Digital Picture Frame reference design, supports: -+ 8007-0410 v1.0 -+ -+config IP7160RGW -+ bool "IP7160RGW" -+ select UBICOM32_V4 -+ select UBICOM_INPUT -+ select NEW_LEDS -+ select LEDS_CLASS -+ select LEDS_GPIO -+ select BRD_64MB -+ select SPI -+ select SPI_UBICOM32_GPIO -+ select VLAN_8021Q -+ select UBICOM_SWITCH -+ select UBICOM_SWITCH_BCM539X -+ help -+ Ubicom IP7160 RGW Eval, supports: -+ 8007-0110 v1.0 -+ 8007-0111 v1.1 -+ 8007-0112 v1.2 -+ -+config IP7160BRINGUP -+ bool "IP7160BRINGUP" -+ select UBICOM32_V4 -+ select NEW_LEDS -+ select LEDS_CLASS -+ select LEDS_GPIO -+ select BRD_64MB -+ help -+ Ubicom IP7160 Bringup, supports: -+ 8007-0010 v1.0 -+ -+config IP7160DPF -+ bool "IP7160DPF" -+ select UBICOM32_V4 -+ select I2C -+ select I2C_GPIO -+ select FB -+ select FB_UBICOM32 -+ select BACKLIGHT_LCD_SUPPORT -+ select BACKLIGHT_CLASS_DEVICE -+ select SND_UBI32 -+ select SND_UBI32_AUDIO_CS4350 -+ select UBICOM_HID -+ select BRD_64MB -+ help -+ IP7160 Digital Picture Frame board, supports: -+ 8007-0211 Rev 1.1 -+ -+config IP7500MODULE -+ bool "IP7500MODULE" -+ select UBICOM32_V4 -+ select BRD_128MB -+ help -+ Ubicom IP7500 CPU Module board, supports: -+ 8007-0510 v1.0 -+ 8007-0510A v1.0 -+ -+ Please see ip7500module.c for more details. -+ -+config IP7500AV -+ bool "IP7500AV" -+ select UBICOM32_V4 -+ select BRD_128MB -+ select I2C -+ select I2C_GPIO -+ select SND_UBI32 -+ select SND_UBI32_AUDIO_CS4384 -+ select FB -+ select FB_UBICOM32 -+ help -+ Ubicom IP7500 Audio Video board, supports: -+ 8007-0810 v1.0 -+ -+ With Ubicom IP7500 CPU Module board: -+ 8007-0510 v1.0 -or- -+ 8007-0510A v1.0 -+ -+ Please see ip7500av.c for more details. -+ -+config IP7500MEDIA -+ bool "IP7500MEDIA" -+ select UBICOM32_V4 -+ select UBICOM_INPUT_I2C -+ select RTC_CLASS -+ select RTC_DRV_S35390A -+ select I2C -+ select I2C_GPIO -+ select GPIO_PCA953X -+ select FB -+ select FB_UBICOM32 -+ select BACKLIGHT_LCD_SUPPORT -+ select LCD_CLASS_DEVICE -+ select LCD_UBICOM32 -+ select BACKLIGHT_CLASS_DEVICE -+ select BACKLIGHT_UBICOM32 -+ select SND_UBI32 -+ select SND_UBI32_AUDIO_CS4350 -+ select MMC_UBICOM32 -+ select MMC -+ select MMC_BLOCK -+ select BRD_128MB -+ help -+ IP7500 Media Board w/ IP7500 CPU Module board, supports: -+ 8007-0610 v1.0 w/ 8007-0510 v1.0 -+ -+ Please see ip7500media.c for more details. -+ ---- a/fs/Kconfig.binfmt -+++ b/fs/Kconfig.binfmt -@@ -30,7 +30,7 @@ config COMPAT_BINFMT_ELF - config BINFMT_ELF_FDPIC - bool "Kernel support for FDPIC ELF binaries" - default y -- depends on (FRV || BLACKFIN || (SUPERH32 && !MMU)) -+ depends on (FRV || BLACKFIN || (SUPERH32 && !MMU) || UBICOM32) - help - ELF FDPIC binaries are based on ELF, but allow the individual load - segments of a binary to be located in memory independently of each - diff --git a/toolchain/uClibc/config-0.9.33.2/common b/toolchain/uClibc/config-0.9.33.2/common index d6b3d2c44c..4e4da3e37e 100644 --- a/toolchain/uClibc/config-0.9.33.2/common +++ b/toolchain/uClibc/config-0.9.33.2/common @@ -76,7 +76,6 @@ TARGET_SUBARCH="" # TARGET_sh is not set # TARGET_sh64 is not set # TARGET_sparc is not set -# TARGET_ubicom32 is not set # TARGET_v850 is not set # TARGET_vax is not set # TARGET_x86_64 is not set diff --git a/toolchain/uClibc/config-0.9.33.2/ubicom32 b/toolchain/uClibc/config-0.9.33.2/ubicom32 deleted file mode 100644 index 6277fc380a..0000000000 --- a/toolchain/uClibc/config-0.9.33.2/ubicom32 +++ /dev/null @@ -1,36 +0,0 @@ -ARCH_BIG_ENDIAN=y -ARCH_HAS_NO_MMU=y -COMPAT_ATEXIT=y -# CONFIG_UC_UBICOM32_V3 is not set -CONFIG_UC_UBICOM32_V4=y -# DOSTRIP is not set -EXCLUDE_BRK=y -FORCE_SHAREABLE_TEXT_SEGMENTS=y -LDSO_PRELOAD_FILE_SUPPORT=y -LINUXTHREADS_OLD=y -MALLOC=y -# MALLOC_STANDARD is not set -PTHREADS_DEBUG_SUPPORT=y -SUPPORT_LD_DEBUG=y -TARGET_ARCH="ubicom32" -TARGET_ubicom32=y -# UCLIBC_FORMAT_ELF is not set -UCLIBC_FORMAT_FDPIC_ELF=y -# UCLIBC_FORMAT_FLAT is not set -# UCLIBC_FORMAT_FLAT_SEP_DATA is not set -# UCLIBC_FORMAT_SHARED_FLAT is not set -UCLIBC_HAS_FOPEN_LARGEFILE_MODE=y -UCLIBC_HAS_FPU=y -# UCLIBC_HAS_GETPT is not set -UCLIBC_HAS_OBSOLETE_BSD_SIGNAL=y -UCLIBC_HAS_OBSOLETE_SYSV_SIGNAL=y -UCLIBC_HAS_PROFILING=y -UCLIBC_HAS_REENTRANT_RPC=y -UCLIBC_HAS_STUBS=y -# UCLIBC_HAS_THREADS_NATIVE is not set -UCLIBC_HAS_XATTR=y -UCLIBC_NTP_LEGACY=y -UCLIBC_STATIC_LDCONFIG=y -UCLIBC_SV4_DEPRECATED=y -UCLIBC_UCLINUX_BROKEN_MUNMAP=y -UNIX98PTY_ONLY=y diff --git a/toolchain/uClibc/patches-0.9.33.2/600-ubicom32-uClibc.patch b/toolchain/uClibc/patches-0.9.33.2/600-ubicom32-uClibc.patch deleted file mode 100644 index 6e8fc8a89e..0000000000 --- a/toolchain/uClibc/patches-0.9.33.2/600-ubicom32-uClibc.patch +++ /dev/null @@ -1,4305 +0,0 @@ ---- a/Rules.mak -+++ b/Rules.mak -@@ -524,6 +524,17 @@ ifeq ($(TARGET_ARCH),i960) - SYMBOL_PREFIX=_ - endif - -+ifeq ($(TARGET_ARCH),ubicom32) -+ OPTIMIZATION+=-fstrict-aliasing -+ CPU_CFLAGS-$(CONFIG_UBICOM32_V3)+=-march=ubicom32v3 -+ CPU_CFLAGS-$(CONFIG_UBICOM32_V4)+=-march=ubicom32v4 -+ifeq ($(UCLIBC_FORMAT_FDPIC_ELF),y) -+ CPU_CFLAGS-y:=-mfdpic -+ CPU_LDFLAGS-y += -Wl,-melf32ubicom32fdpic -+endif -+ -+endif -+ - ifeq ($(TARGET_ARCH),v850) - SYMBOL_PREFIX=_ - endif ---- a/extra/Configs/Config.in -+++ b/extra/Configs/Config.in -@@ -102,6 +102,9 @@ config TARGET_sh64 - config TARGET_sparc - bool "sparc" - -+config TARGET_ubicom32 -+ bool "ubicom32" -+ - config TARGET_v850 - bool "v850 (BROKEN)" - -@@ -206,6 +209,10 @@ if TARGET_sparc - source "extra/Configs/Config.sparc" - endif - -+if TARGET_ubicom32 -+source "extra/Configs/Config.ubicom32" -+endif -+ - if TARGET_v850 - source "extra/Configs/Config.v850" - endif ---- a/extra/Configs/Config.in.arch -+++ b/extra/Configs/Config.in.arch -@@ -152,7 +152,7 @@ config UCLIBC_HAS_SOFT_FLOAT - config DO_C99_MATH - bool "Enable full C99 math library support" - depends on UCLIBC_HAS_FLOATS -- default n -+ default y - help - If you want the uClibc math library to contain the full set C99 - math library features, then answer Y. If you leave this set to ---- /dev/null -+++ b/extra/Configs/Config.ubicom32 -@@ -0,0 +1,44 @@ -+# -+# For a description of the syntax of this configuration file, -+# see extra/config/Kconfig-language.txt -+# -+ -+config TARGET_ARCH -+ string -+ default "ubicom32" -+ -+config FORCE_OPTIONS_FOR_ARCH -+ bool -+ default y -+ select ARCH_BIG_ENDIAN -+ select ARCH_HAS_NO_MMU -+ -+choice -+ prompt "Target Processor Architecture" -+ default CONFIG_UC_UBICOM32_V3 -+ help -+ This selects the instruction set architecture of your Ubicom32 CPU. This -+ information is used for optimizing purposes. To build a library that -+ will run on any Ubicom32 CPU, you can specify "v3" here. -+ If you pick anything other than "v3," there is no -+ guarantee that uClibc will even run on anything other than the -+ selected processor type. -+ -+ You should probably select the Ubicom32 ISA that best matches the -+ CPU you will be using on your device. uClibc will be tuned -+ for that architecture. -+ -+ If you don't know what to do, choose "v3" -+ -+config CONFIG_UC_UBICOM32_V3 -+ bool "ISA v3" -+ -+config CONFIG_UC_UBICOM32_V4 -+ bool "ISA v4" -+endchoice -+ -+config ARCH_CFLAGS -+ string -+ -+config CROSS -+ string ---- a/include/elf.h -+++ b/include/elf.h -@@ -338,6 +338,8 @@ typedef struct - - #define EM_XSTORMY16 0xad45 - -+#define EM_UBICOM32 0xde3d /* Ubicom32; no ABI */ -+ - /* FRV magic number - no EABI available??. */ - #define EM_CYGNUS_FRV 0x5441 - -@@ -3141,6 +3143,55 @@ typedef Elf32_Addr Elf32_Conflict; - #define R_MICROBLAZE_COPY 21 /* runtime copy */ - #define R_MICROBLAZE_NUM 22 - -+/* Ubicom32 ELF relocation types */ -+#define R_UBICOM32_NONE 0 -+#define R_UBICOM32_16 1 -+#define R_UBICOM32_32 2 -+#define R_UBICOM32_LO16 3 -+#define R_UBICOM32_HI16 4 -+#define R_UBICOM32_21_PCREL 5 -+#define R_UBICOM32_24_PCREL 6 -+#define R_UBICOM32_HI24 7 -+#define R_UBICOM32_LO7_S 8 -+#define R_UBICOM32_LO7_2_S 9 -+#define R_UBICOM32_LO7_4_S 10 -+#define R_UBICOM32_LO7_D 11 -+#define R_UBICOM32_LO7_2_D 12 -+#define R_UBICOM32_LO7_4_D 13 -+#define R_UBICOM32_32_HARVARD 14 -+#define R_UBICOM32_LO7_CALLI 15 -+#define R_UBICOM32_LO16_CALLI 16 -+#define R_UBICOM32_GOT_HI24 17 -+#define R_UBICOM32_GOT_LO7_S 18 -+#define R_UBICOM32_GOT_LO7_2_S 19 -+#define R_UBICOM32_GOT_LO7_4_S 20 -+#define R_UBICOM32_GOT_LO7_D 21 -+#define R_UBICOM32_GOT_LO7_2_D 22 -+#define R_UBICOM32_GOT_LO7_4_D 23 -+#define R_UBICOM32_FUNCDESC_GOT_HI24 24 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_S 25 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_2_S 26 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_4_S 27 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_D 28 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_2_D 29 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_4_D 30 -+#define R_UBICOM32_GOT_LO7_CALLI 31 -+#define R_UBICOM32_FUNCDESC_GOT_LO7_CALLI 32 -+#define R_UBICOM32_FUNCDESC_VALUE 33 -+#define R_UBICOM32_FUNCDESC 34 -+#define R_UBICOM32_GOTOFFSET_LO 35 -+#define R_UBICOM32_GOTOFFSET_HI 36 -+#define R_UBICOM32_FUNCDESC_GOTOFFSET_LO 37 -+#define R_UBICOM32_FUNCDESC_GOTOFFSET_HI 38 -+#define R_UBICOM32_GNU_VTINHERIT 200 -+#define R_UBICOM32_GNU_VTENTRY 201 -+ -+/* Ubicom32 Flags. */ -+#define EF_UBICOM32_V3 0x00000001 /* -fmarch=ubicom32v3 */ -+#define EF_UBICOM32_V4 0x00000002 /* -fmarch=ubicom32v4 */ -+#define EF_UBICOM32_PIC 0x80000000 /* -fpic */ -+#define EF_UBICOM32_FDPIC 0x40000000 /* -mfdpic */ -+ - #ifdef __cplusplus - } - #endif ---- a/include/features.h -+++ b/include/features.h -@@ -448,4 +448,10 @@ uClibc was built without large file supp - # include - #endif - -+#ifndef libc_hidden_proto -+#define libc_hidden_proto(name, attrs...) -+#endif -+#ifndef libm_hidden_proto -+#define libm_hidden_proto(name, attrs...) -+#endif - #endif /* features.h */ ---- /dev/null -+++ b/ldso/ldso/ubicom32/dl-debug.h -@@ -0,0 +1,72 @@ -+/* vi: set sw=4 ts=4: */ -+/* Ubicom32 ELF shared library loader suppport -+ * -+ * Copyright (c) 2009 Ubicom Inc. -+ * Copyright (c) 1994-2000 Eric Youngdale, Peter MacDonald, -+ * David Engel, Hongjiu Lu and Mitch D'Souza -+ * Copyright (C) 2001-2004 Erik Andersen -+ * -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. The name of the above contributors may not be -+ * used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+static const char *_dl_reltypes_tab[] = -+{ -+ "R_UBICOM32_NONE", /* 0 */ -+ "R_UBICOM32_16", -+ "R_UBICOM32_32", -+ "R_UBICOM32_LO16", -+ "R_UBICOM32_HI16", -+ "R_UBICOM32_21_PCREL", /* 5 */ -+ "R_UBICOM32_24_PCREL", -+ "R_UBICOM32_HI24", -+ "R_UBICOM32_LO7_S", -+ "R_UBICOM32_LO7_2_S", -+ "R_UBICOM32_LO7_4_S", /* 10 */ -+ "R_UBICOM32_LO7_D", -+ "R_UBICOM32_LO7_2_D", -+ "R_UBICOM32_LO7_4_D", -+ "R_UBICOM32_32_HARVARD", -+ "R_UBICOM32_LO7_CALLI", /* 15 */ -+ "R_UBICOM32_LO16_CALLI", -+ "R_UBICOM32_GOT_HI24", -+ "R_UBICOM32_GOT_LO7_S", -+ "R_UBICOM32_GOT_LO7_2_S" -+ "R_UBICOM32_GOT_LO7_4_S", /* 20 */ -+ "R_UBICOM32_GOT_LO7_D", -+ "R_UBICOM32_GOT_LO7_2_D", -+ "R_UBICOM32_GOT_LO7_4_D", -+ "R_UBICOM32_FUNCDESC_GOT_HI24 24", -+ "R_UBICOM32_FUNCDESC_GOT_LO7_S", /* 25 */ -+ "R_UBICOM32_FUNCDESC_GOT_LO7_2_S", -+ "R_UBICOM32_FUNCDESC_GOT_LO7_4_S", -+ "R_UBICOM32_FUNCDESC_GOT_LO7_D", -+ "R_UBICOM32_FUNCDESC_GOT_LO7_2_D", -+ "R_UBICOM32_FUNCDESC_GOT_LO7_4_D", /* 30 */ -+ "R_UBICOM32_GOT_LO7_CALLI", -+ "R_UBICOM32_FUNCDESC_VALUE", -+ "R_UBICOM32_FUNCDESC", -+#if 1 -+ [200] "R_UBICOM32_GNU_VTINHERIT" , "R_UBICOM32_GNU_VTENTRY" -+#endif -+}; ---- /dev/null -+++ b/ldso/ldso/ubicom32/dl-inlines.h -@@ -0,0 +1,582 @@ -+ /* Copyright (C) 2003, 2004 Red Hat, Inc. -+ Contributed by Alexandre Oliva -+ -+This file is part of uClibc. -+ -+uClibc is free software; you can redistribute it and/or modify it -+under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+uClibc is distributed in the hope that it will be useful, but WITHOUT -+ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with uClibc; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, -+USA. */ -+ -+//#include -+#define SRAM_TEST(x) 0 -+#ifndef _dl_assert -+# define _dl_assert(expr) -+#endif -+ -+/* Initialize a DL_LOADADDR_TYPE given a got pointer and a complete -+ load map. */ -+static __always_inline void -+__dl_init_loadaddr_map (struct elf32_fdpic_loadaddr *loadaddr, Elf32_Addr dl_boot_got_pointer, -+ struct elf32_fdpic_loadmap *map) -+{ -+ if (map->version != 0) -+ { -+ SEND_EARLY_STDERR ("Invalid loadmap version number\n"); -+ _dl_exit(-1); -+ } -+ if (map->nsegs == 0) -+ { -+ SEND_EARLY_STDERR ("Invalid segment count in loadmap\n"); -+ _dl_exit(-1); -+ } -+ loadaddr->got_value = (void*)dl_boot_got_pointer; -+ loadaddr->map = map; -+} -+ -+/* Figure out how many LOAD segments there are in the given headers, -+ and allocate a block for the load map big enough for them. -+ got_value will be properly initialized later on, with INIT_GOT. */ -+static __always_inline int -+__dl_init_loadaddr (struct elf32_fdpic_loadaddr *loadaddr, Elf32_Phdr *ppnt, -+ int pcnt) -+{ -+ int count = 0, i; -+ size_t size; -+ -+ for (i = 0; i < pcnt; i++) -+ if (ppnt[i].p_type == PT_LOAD) -+ count++; -+ -+ loadaddr->got_value = 0; -+ -+ size = sizeof (struct elf32_fdpic_loadmap) -+ + sizeof (struct elf32_fdpic_loadseg) * count; -+ loadaddr->map = _dl_malloc (size); -+ if (! loadaddr->map) -+ _dl_exit (-1); -+ -+ loadaddr->map->version = 0; -+ loadaddr->map->nsegs = 0; -+ -+ return count; -+} -+ -+#if defined (__SUPPORT_LD_DEBUG__) -+extern char *_dl_debug; -+extern int _dl_debug_file; -+#endif -+ -+/* Incrementally initialize a load map. */ -+static __always_inline void -+__dl_init_loadaddr_hdr (struct elf32_fdpic_loadaddr loadaddr, void *addr, -+ Elf32_Phdr *phdr, int maxsegs) -+{ -+ struct elf32_fdpic_loadseg *segdata; -+ -+ if (loadaddr.map->nsegs == maxsegs) -+ _dl_exit (-1); -+ -+ segdata = &loadaddr.map->segs[loadaddr.map->nsegs++]; -+ segdata->addr = (Elf32_Addr) addr; -+ segdata->p_vaddr = phdr->p_vaddr; -+ segdata->p_memsz = phdr->p_memsz; -+ -+#if defined (__SUPPORT_LD_DEBUG__) -+ { -+ if (_dl_debug) -+ _dl_dprintf(_dl_debug_file, "%i: mapped %x at %x, size %x\n", -+ loadaddr.map->nsegs-1, -+ segdata->p_vaddr, segdata->addr, segdata->p_memsz); -+ } -+#endif -+} -+ -+static __always_inline void __dl_loadaddr_unmap -+(struct elf32_fdpic_loadaddr loadaddr, struct funcdesc_ht *funcdesc_ht); -+ -+/* Figure out whether the given address is in one of the mapped -+ segments. */ -+static __always_inline int -+__dl_addr_in_loadaddr (void *p, struct elf32_fdpic_loadaddr loadaddr) -+{ -+ struct elf32_fdpic_loadmap *map = loadaddr.map; -+ int c; -+ -+ for (c = 0; c < map->nsegs; c++) -+ if ((void*)map->segs[c].addr <= p -+ && (char*)p < (char*)map->segs[c].addr + map->segs[c].p_memsz) -+ return 1; -+ -+ return 0; -+} -+ -+static __always_inline void * _dl_funcdesc_for (void *entry_point, void *got_value); -+ -+/* The hashcode handling code below is heavily inspired in libiberty's -+ hashtab code, but with most adaptation points and support for -+ deleting elements removed. -+ -+ Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. -+ Contributed by Vladimir Makarov (vmakarov@cygnus.com). */ -+ -+static __always_inline unsigned long -+higher_prime_number (unsigned long n) -+{ -+ /* These are primes that are near, but slightly smaller than, a -+ power of two. */ -+ static const unsigned long primes[] = { -+ (unsigned long) 7, -+ (unsigned long) 13, -+ (unsigned long) 31, -+ (unsigned long) 61, -+ (unsigned long) 127, -+ (unsigned long) 251, -+ (unsigned long) 509, -+ (unsigned long) 1021, -+ (unsigned long) 2039, -+ (unsigned long) 4093, -+ (unsigned long) 8191, -+ (unsigned long) 16381, -+ (unsigned long) 32749, -+ (unsigned long) 65521, -+ (unsigned long) 131071, -+ (unsigned long) 262139, -+ (unsigned long) 524287, -+ (unsigned long) 1048573, -+ (unsigned long) 2097143, -+ (unsigned long) 4194301, -+ (unsigned long) 8388593, -+ (unsigned long) 16777213, -+ (unsigned long) 33554393, -+ (unsigned long) 67108859, -+ (unsigned long) 134217689, -+ (unsigned long) 268435399, -+ (unsigned long) 536870909, -+ (unsigned long) 1073741789, -+ (unsigned long) 2147483647, -+ /* 4294967291L */ -+ ((unsigned long) 2147483647) + ((unsigned long) 2147483644), -+ }; -+ -+ const unsigned long *low = &primes[0]; -+ const unsigned long *high = &primes[sizeof(primes) / sizeof(primes[0])]; -+ -+ while (low != high) -+ { -+ const unsigned long *mid = low + (high - low) / 2; -+ if (n > *mid) -+ low = mid + 1; -+ else -+ high = mid; -+ } -+ -+#if 0 -+ /* If we've run out of primes, abort. */ -+ if (n > *low) -+ { -+ fprintf (stderr, "Cannot find prime bigger than %lu\n", n); -+ abort (); -+ } -+#endif -+ -+ return *low; -+} -+ -+struct funcdesc_ht -+{ -+ /* Table itself. */ -+ struct funcdesc_value **entries; -+ -+ /* Current size (in entries) of the hash table */ -+ size_t size; -+ -+ /* Current number of elements. */ -+ size_t n_elements; -+}; -+ -+static __always_inline int -+hash_pointer (const void *p) -+{ -+ return (int) ((long)p >> 3); -+} -+ -+static __always_inline struct funcdesc_ht * -+htab_create (void) -+{ -+ struct funcdesc_ht *ht = _dl_malloc (sizeof (struct funcdesc_ht)); -+ -+ if (! ht) -+ return NULL; -+ ht->size = 3; -+ ht->entries = _dl_malloc (sizeof (struct funcdesc_ht_value *) * ht->size); -+ if (! ht->entries) -+ return NULL; -+ -+ ht->n_elements = 0; -+ -+ _dl_memset (ht->entries, 0, sizeof (struct funcdesc_ht_value *) * ht->size); -+ -+ return ht; -+} -+ -+/* This is only called from _dl_loadaddr_unmap, so it's safe to call -+ _dl_free(). See the discussion below. */ -+static __always_inline void -+htab_delete (struct funcdesc_ht *htab) -+{ -+ int i; -+ -+ for (i = htab->size - 1; i >= 0; i--) -+ if (htab->entries[i]) -+ _dl_free (htab->entries[i]); -+ -+ _dl_free (htab->entries); -+ _dl_free (htab); -+} -+ -+/* Similar to htab_find_slot, but without several unwanted side effects: -+ - Does not call htab->eq_f when it finds an existing entry. -+ - Does not change the count of elements/searches/collisions in the -+ hash table. -+ This function also assumes there are no deleted entries in the table. -+ HASH is the hash value for the element to be inserted. */ -+ -+static __always_inline struct funcdesc_value ** -+find_empty_slot_for_expand (struct funcdesc_ht *htab, int hash) -+{ -+ size_t size = htab->size; -+ unsigned int index = hash % size; -+ struct funcdesc_value **slot = htab->entries + index; -+ int hash2; -+ -+ if (! *slot) -+ return slot; -+ -+ hash2 = 1 + hash % (size - 2); -+ for (;;) -+ { -+ index += hash2; -+ if (index >= size) -+ index -= size; -+ -+ slot = htab->entries + index; -+ if (! *slot) -+ return slot; -+ } -+} -+ -+/* The following function changes size of memory allocated for the -+ entries and repeatedly inserts the table elements. The occupancy -+ of the table after the call will be about 50%. Naturally the hash -+ table must already exist. Remember also that the place of the -+ table entries is changed. If memory allocation failures are allowed, -+ this function will return zero, indicating that the table could not be -+ expanded. If all goes well, it will return a non-zero value. */ -+ -+static __always_inline int -+htab_expand (struct funcdesc_ht *htab) -+{ -+ struct funcdesc_value **oentries; -+ struct funcdesc_value **olimit; -+ struct funcdesc_value **p; -+ struct funcdesc_value **nentries; -+ size_t nsize; -+ -+ oentries = htab->entries; -+ olimit = oentries + htab->size; -+ -+ /* Resize only when table after removal of unused elements is either -+ too full or too empty. */ -+ if (htab->n_elements * 2 > htab->size) -+ nsize = higher_prime_number (htab->n_elements * 2); -+ else -+ nsize = htab->size; -+ -+ nentries = _dl_malloc (sizeof (struct funcdesc_value *) * nsize); -+ _dl_memset (nentries, 0, sizeof (struct funcdesc_value *) * nsize); -+ if (nentries == NULL) -+ return 0; -+ htab->entries = nentries; -+ htab->size = nsize; -+ -+ p = oentries; -+ do -+ { -+ if (*p) -+ *find_empty_slot_for_expand (htab, hash_pointer ((*p)->entry_point)) -+ = *p; -+ -+ p++; -+ } -+ while (p < olimit); -+ -+#if 0 /* We can't tell whether this was allocated by the _dl_malloc() -+ built into ld.so or malloc() in the main executable or libc, -+ and calling free() for something that wasn't malloc()ed could -+ do Very Bad Things (TM). Take the conservative approach -+ here, potentially wasting as much memory as actually used by -+ the hash table, even if multiple growths occur. That's not -+ so bad as to require some overengineered solution that would -+ enable us to keep track of how it was allocated. */ -+ _dl_free (oentries); -+#endif -+ return 1; -+} -+ -+/* This function searches for a hash table slot containing an entry -+ equal to the given element. To delete an entry, call this with -+ INSERT = 0, then call htab_clear_slot on the slot returned (possibly -+ after doing some checks). To insert an entry, call this with -+ INSERT = 1, then write the value you want into the returned slot. -+ When inserting an entry, NULL may be returned if memory allocation -+ fails. */ -+ -+static __always_inline struct funcdesc_value ** -+htab_find_slot (struct funcdesc_ht *htab, void *ptr, int insert) -+{ -+ unsigned int index; -+ int hash, hash2; -+ size_t size; -+ struct funcdesc_value **entry; -+ -+ if (htab->size * 3 <= htab->n_elements * 4 -+ && htab_expand (htab) == 0) -+ return NULL; -+ -+ hash = hash_pointer (ptr); -+ -+ size = htab->size; -+ index = hash % size; -+ -+ entry = &htab->entries[index]; -+ if (!*entry) -+ goto empty_entry; -+ else if ((*entry)->entry_point == ptr) -+ return entry; -+ -+ hash2 = 1 + hash % (size - 2); -+ for (;;) -+ { -+ index += hash2; -+ if (index >= size) -+ index -= size; -+ -+ entry = &htab->entries[index]; -+ if (!*entry) -+ goto empty_entry; -+ else if ((*entry)->entry_point == ptr) -+ return entry; -+ } -+ -+ empty_entry: -+ if (!insert) -+ return NULL; -+ -+ htab->n_elements++; -+ return entry; -+} -+ -+void * -+_dl_funcdesc_for (void *entry_point, void *got_value) -+{ -+ struct elf_resolve *tpnt = ((void**)got_value)[2]; -+ struct funcdesc_ht *ht = tpnt->funcdesc_ht; -+ struct funcdesc_value **entry; -+ -+ _dl_assert (got_value == tpnt->loadaddr.got_value); -+ -+ if (! ht) -+ { -+ ht = htab_create (); -+ if (! ht) -+ return (void*)-1; -+ tpnt->funcdesc_ht = ht; -+ } -+ -+ entry = htab_find_slot (ht, entry_point, 1); -+ if (*entry) -+ { -+ _dl_assert ((*entry)->entry_point == entry_point); -+ return _dl_stabilize_funcdesc (*entry); -+ } -+ -+ *entry = _dl_malloc (sizeof (struct funcdesc_value)); -+ (*entry)->entry_point = entry_point; -+ (*entry)->got_value = got_value; -+ -+ return _dl_stabilize_funcdesc (*entry); -+} -+ -+static __always_inline void const * -+_dl_lookup_address (void const *address) -+{ -+ struct elf_resolve *rpnt; -+ struct funcdesc_value const *fd; -+ -+ /* Make sure we don't make assumptions about its alignment. */ -+ __asm__ ("" : "+r" (address)); -+ -+ if ((Elf32_Addr)address & 7) -+ /* It's not a function descriptor. */ -+ return address; -+ -+ fd = (struct funcdesc_value const *)address; -+ -+ for (rpnt = _dl_loaded_modules; rpnt; rpnt = rpnt->next) -+ { -+ if (! rpnt->funcdesc_ht) -+ continue; -+ -+ if (fd->got_value != rpnt->loadaddr.got_value) -+ continue; -+ -+ address = htab_find_slot (rpnt->funcdesc_ht, (void*)fd->entry_point, 0); -+ -+ if (address && *(struct funcdesc_value *const*)address == fd) -+ { -+ address = (*(struct funcdesc_value *const*)address)->entry_point; -+ break; -+ } -+ else -+ address = fd; -+ } -+ -+ return address; -+} -+ -+void -+__dl_loadaddr_unmap (struct elf32_fdpic_loadaddr loadaddr, -+ struct funcdesc_ht *funcdesc_ht) -+{ -+ int i; -+ -+ for (i = 0; i < loadaddr.map->nsegs; i++) -+ { -+ struct elf32_fdpic_loadseg *segdata; -+ ssize_t offs; -+ segdata = loadaddr.map->segs + i; -+ -+#if 0 /* SRAM */ -+ /* FIXME: -+ A more cleaner way is to add type for struct elf32_fdpic_loadseg, -+ and release the memory according to the type. -+ Currently, we hardcode the memory address of L1 SRAM. */ -+ if ((segdata->addr & 0xff800000) == 0xff800000) -+ { -+ _dl_sram_free ((void *)segdata->addr); -+ continue; -+ } -+#endif -+ offs = (segdata->p_vaddr & ADDR_ALIGN); -+ _dl_munmap ((void*)segdata->addr - offs, -+ segdata->p_memsz + offs); -+ } -+ /* _dl_unmap is only called for dlopen()ed libraries, for which -+ calling free() is safe, or before we've completed the initial -+ relocation, in which case calling free() is probably pointless, -+ but still safe. */ -+ _dl_free (loadaddr.map); -+ if (funcdesc_ht) -+ htab_delete (funcdesc_ht); -+} -+ -+#if 0 /* XXX TODO will look at enabling this if we decide to add support for OCM -+ * code/data */ -+// OLD BLACKFIN CODE -+static __always_inline int -+__dl_is_special_segment (Elf32_Ehdr *epnt, -+ Elf32_Phdr *ppnt) -+{ -+ if (ppnt->p_type != PT_LOAD) -+ return 0; -+ -+ if ((epnt->e_flags & EF_BFIN_CODE_IN_L1) -+ && !(ppnt->p_flags & PF_W) -+ && (ppnt->p_flags & PF_X)) -+ return 1; -+ -+ if ((epnt->e_flags & EF_BFIN_DATA_IN_L1) -+ && (ppnt->p_flags & PF_W) -+ && !(ppnt->p_flags & PF_X)) -+ return 1; -+ -+ /* 0xff700000, 0xff800000, 0xff900000 and 0xffa00000 are also used in -+ GNU ld and linux kernel. They need to be keep synchronized. */ -+ if (ppnt->p_vaddr == 0xff700000 -+ || ppnt->p_vaddr == 0xff800000 -+ || ppnt->p_vaddr == 0xff900000 -+ || ppnt->p_vaddr == 0xffa00000) -+ return 1; -+ -+ return 0; -+} -+ -+static __always_inline char * -+__dl_map_segment (Elf32_Ehdr *epnt, -+ Elf32_Phdr *ppnt, -+ int infile, -+ int flags) -+{ -+ char *status, *tryaddr, *l1addr; -+ size_t size; -+ -+ -+ if (((epnt->e_flags & EF_BFIN_CODE_IN_L1) || ppnt->p_vaddr == 0xffa00000) -+ && !(ppnt->p_flags & PF_W) -+ && (ppnt->p_flags & PF_X)) { -+ status = (char *) _dl_mmap -+ (tryaddr = 0, -+ size = (ppnt->p_vaddr & ADDR_ALIGN) + ppnt->p_filesz, -+ LXFLAGS(ppnt->p_flags), -+ flags | MAP_EXECUTABLE | MAP_DENYWRITE, -+ infile, ppnt->p_offset & OFFS_ALIGN); -+ if (_dl_mmap_check_error(status) -+ || (tryaddr && tryaddr != status)) -+ return NULL; -+ l1addr = (char *) _dl_sram_alloc (ppnt->p_filesz, L1_INST_SRAM); -+ if (l1addr != NULL) -+ _dl_dma_memcpy (l1addr, status + (ppnt->p_vaddr & ADDR_ALIGN), ppnt->p_filesz); -+ _dl_munmap (status, size); -+ if (l1addr == NULL) -+ _dl_dprintf(2, "%s:%i: L1 allocation failed\n", _dl_progname, __LINE__); -+ return l1addr; -+ } -+ -+ if (((epnt->e_flags & EF_BFIN_DATA_IN_L1) -+ || ppnt->p_vaddr == 0xff700000 -+ || ppnt->p_vaddr == 0xff800000 -+ || ppnt->p_vaddr == 0xff900000) -+ && (ppnt->p_flags & PF_W) -+ && !(ppnt->p_flags & PF_X)) { -+ if (ppnt->p_vaddr == 0xff800000) -+ l1addr = (char *) _dl_sram_alloc (ppnt->p_memsz, L1_DATA_A_SRAM); -+ else if (ppnt->p_vaddr == 0xff900000) -+ l1addr = (char *) _dl_sram_alloc (ppnt->p_memsz, L1_DATA_B_SRAM); -+ else -+ l1addr = (char *) _dl_sram_alloc (ppnt->p_memsz, L1_DATA_SRAM); -+ if (l1addr == NULL) { -+ _dl_dprintf(2, "%s:%i: L1 allocation failed\n", _dl_progname, __LINE__); -+ } else { -+ if (_DL_PREAD (infile, l1addr, ppnt->p_filesz, ppnt->p_offset) != ppnt->p_filesz) { -+ _dl_sram_free (l1addr); -+ return NULL; -+ } -+ if (ppnt->p_filesz < ppnt->p_memsz) -+ _dl_memset (l1addr + ppnt->p_filesz, 0, ppnt->p_memsz - ppnt->p_filesz); -+ } -+ return l1addr; -+ } -+ return 0; -+} -+#endif ---- /dev/null -+++ b/ldso/ldso/ubicom32/dl-startup.h -@@ -0,0 +1,232 @@ -+/* -+ Copyright (C) 2009 Ubicom, Inc. -+ Copyright (C) 2003 Red Hat, Inc. -+ Contributed by Alexandre Oliva -+ -+This file is part of uClibc. -+ -+uClibc is free software; you can redistribute it and/or modify it -+under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+uClibc is distributed in the hope that it will be useful, but WITHOUT -+ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with uClibc; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, -+USA. */ -+ -+/* Any assembly language/system dependent hacks needed to setup -+ * boot1.c so it will work as expected and cope with whatever platform -+ * specific wierdness is needed for this architecture. -+ -+ * We override the default _dl_boot function, and replace it with a -+ * bit of asm. Then call the real _dl_boot function, which is now -+ * named _dl_boot2. */ -+ -+/* At program start-up, p0 contains a pointer to a -+ elf32_fdpic_loadmap that describes how the executable was loaded -+ into memory. p1 contains a pointer to the interpreter (our!) -+ loadmap, if there is an interpreter, or 0 if we're being run as an -+ executable. p2 holds a pointer to the interpreter's dynamic -+ section, if there is an interpreter, or to the executable's dynamic -+ section, otherwise. If the executable is not dynamic, gr18 is 0. -+ -+ We rely on the fact that the linker adds a pointer to the -+ _GLOBAL_OFFSET_TABLE_ as the last ROFIXUP entry, and that -+ __self_reloc returns the relocated pointer to us, so that we can -+ use this value to initialize the PIC register. */ -+ -+ -+/* -+ * _dl_boot is the entry point for ldso. -+ * -+ * The kernel leaves the main apps args on the stack (positive offsets), and -+ * communicates the load maps as follows -+ * -+ * - d1 is set to the exec_map_addr (struct elf32_fdpic_loadmap *), which is the -+ * current state of the mapped application. -+ * -+ * - d2 is set to interp_map_addr (struct elf32_fdpic_loadmap *), which is use -+ * by ldso to relocate itself. -+ * -+ * - d3 is dynamic_addr which as far as I can tell is the stack pointer. -+ * -+ * - a1 is set to zero and will later be initialised to ldso _dl_fini funcdesc -+ */ -+ -+__asm__( -+ " .text \n\t" -+ " .global _start \n\t" -+ " .type _start,@function \n\t" -+ "_start:\n\t" -+ /* -+ * Jump to .Lcall storing the location .Lcall in a5 -+ */ -+ " call a5, .Lcall \n\t" -+ ".Lcall: \n\t" -+ /* -+ * Reserve and Push inputs to stack. -+ * 32 byte stack layout as follows -+ * offset 0 exec_map_addr -+ * 4 interp_map_addr -+ * 8 dynamic_addr -+ * 12 not used -+ * 16 dl_main_funcdesc structure for _dl_boot -+ * (12 bytes sizeof funcdesc_value) -+ * 28 reserved -+ * 32 start of &original stack -+ */ -+ " pdec sp, 32(sp); reserve stack space \n\t" -+ " move.4 0(sp), d1 ; exec_map_addr \n\t" -+ " move.4 4(sp), d2 ; interp_map_addr \n\t" -+ " move.4 8(sp), d3; dynamic_addr \n\t" -+ -+ /* -+ * Load linker version of .Lcall in to d0 -+ */ -+ " moveai a3, #%hi(.Lcall) \n\t" -+ " lea.1 d0, %lo(.Lcall)(a3) \n\t" -+ -+ /* -+ * Determine the offset from loaded .Lcall and put it in d0. -+ */ -+ " sub.4 d0, a5, d0 \n\t" -+ -+ /* -+ * Load linker version of __ROFIXUP_LIST__ and __ROFIXUP_END__ in to d1 -+ * and d2. -+ */ -+ " moveai a3, #%hi(__ROFIXUP_LIST__) \n\t" -+ " lea.1 d1, %lo(__ROFIXUP_LIST__)(a3) \n\t" -+ " moveai a3, #%hi(__ROFIXUP_END__) \n\t" -+ " lea.1 d2, %lo(__ROFIXUP_END__)(a3) \n\t" -+ /* -+ * Use offset determined above to find the loaded versions. -+ */ -+ " add.4 d1, d1, d0 \n\t" -+ " add.4 d2, d2, d0 \n\t" -+ -+ /* -+ * Load interp_map_addr into d0, if interp_map_addr is null use -+ * exec_map_addr. -+ */ -+ " move.4 d0, 4(sp) ; load interp_map_addr \n\t" -+ " cmpi d0, #0 \n\t" -+ " jmpne.f 1f \n\t" -+ " move.4 d0, 0(sp) ; load exec_map_addr \n\t" -+ -+ /* -+ * call __self_reloc(map, void ***p, void ***e) -+ * it returns the the GOT in d0. -+ */ -+ "1: call a5, __self_reloc ; returns a0 in d0 \n\t" -+ " move.4 a0, d0 ; set GOT \n\t" -+ " move.4 a2, d0 ; save GOT \n\t" -+ -+ /* -+ * now setup to call -+ * _dl_start (Elf32_Addr dl_boot_got_pointer, (d0) -+ * struct elf32_fdpic_loadmap *dl_boot_progmap, (d1) -+ * struct elf32_fdpic_loadmap *dl_boot_ldsomap, (d2) -+ * Elf32_Dyn *dl_boot_ldso_dyn_pointer, (d3) -+ * struct funcdesc_value *dl_main_funcdesc, (d4) -+ * unsigned long args (d5) -+ * -+ * NOTE: for dl_main_funcdesc we reserved space on the stack for this -+ * structure. -+ */ -+ " move.4 d1, 0(sp) ; d1 = exec_map_addr \n\t" -+ " move.4 d2, 4(sp) ; d2 = interp_map_addr \n\t" -+ " move.4 d3, 8(sp) ; d3 = dynamic_addr \n\t" -+ " lea.1 d4, 16(sp) ; d4 = &dl_main_funcdesc \n\t" -+ " lea.1 d5, 32(sp) ; d5 = original stack ptr (args)\n\t" -+ " call a5, _dl_start \n\t" -+ -+ /* -+ * Setup to call the main entry point, starting with passing our FINI -+ * ptr() to the user in a1 (remember we saved the got in a2) -+ */ -+ " movei d15, #%got_funcdesc_lo(_dl_fini) \n\t" -+ " move.4 a1, (a2, d15) \n\t" -+ -+ /* -+ * restore the load map from the kernel. -+ */ -+ " move.4 d1, 0(sp) ; restore exec_map_addr \n\t" -+ " move.4 d2, 4(sp) ; restore interp_map_addr \n\t" -+ " move.4 d3, 8(sp) ; restore dynamic_addr \n\t" -+ -+ /* -+ * _dl_start returned the main apps entry point in dl_main_funcdesc, -+ * load that information now. -+ */ -+ " move.4 a5, 16(sp) ; a5 = dl_main_funcdesc.entry_point \n\t" -+ " move.4 a0, 20(sp) ; a0 = dl_main_funcdesc.got_value \n\t" -+ " lea.1 sp, 32(sp); restore original stack ptr (args) \n\t" -+ " calli a5, 0(a5) \n\t" -+ " bkpt -1; should never get here \n\t" -+ " .size _start, . - _start \n\t" -+); -+ -+#undef DL_START -+#define DL_START(X) \ -+static void __attribute__ ((used)) \ -+_dl_start (Elf32_Addr dl_boot_got_pointer, \ -+ struct elf32_fdpic_loadmap *dl_boot_progmap, \ -+ struct elf32_fdpic_loadmap *dl_boot_ldsomap, \ -+ Elf32_Dyn *dl_boot_ldso_dyn_pointer, \ -+ struct funcdesc_value *dl_main_funcdesc, \ -+ X) -+ -+struct elf32_fdpic_loadmap; -+ -+/* -+ * Get a pointer to the argv array. On many platforms this can be just -+ * the address if the first argument, on other platforms we need to -+ * do something a little more subtle here. -+ */ -+#define GET_ARGV(ARGVP, ARGS) ARGVP = (((unsigned long*) ARGS) + 1) -+ -+/* -+ * Here is a macro to perform a relocation. This is only used when -+ * bootstrapping the dynamic loader. RELP is the relocation that we -+ * are performing, REL is the pointer to the address we are relocating. -+ * SYMBOL is the symbol involved in the relocation, and LOAD is the -+ * load address. -+ */ -+#define PERFORM_BOOTSTRAP_RELOC(RELP,REL,SYMBOL,LOAD,SYMTAB) \ -+ switch(ELF32_R_TYPE((RELP)->r_info)){ \ -+ case R_UBICOM32_32: \ -+ *(REL) += (SYMBOL); \ -+ break; \ -+ case R_UBICOM32_FUNCDESC_VALUE: \ -+ { \ -+ struct funcdesc_value fv = { \ -+ (void*)((SYMBOL) + *(REL)), \ -+ (LOAD).got_value \ -+ }; \ -+ *(struct funcdesc_value volatile *)(REL) = fv; \ -+ break; \ -+ } \ -+ default: \ -+ _dl_exit(1); \ -+ } -+ -+/* -+ * Transfer control to the user's application, once the dynamic loader -+ * is done. We return the address of the function's entry point to -+ * _dl_boot, see boot1_arch.h. -+ */ -+#define START() do { \ -+ struct elf_resolve *exec_mod = _dl_loaded_modules; \ -+ dl_main_funcdesc->entry_point = _dl_elf_main; \ -+ while (exec_mod->libtype != elf_executable) \ -+ exec_mod = exec_mod->next; \ -+ dl_main_funcdesc->got_value = exec_mod->loadaddr.got_value; \ -+ return; \ -+} while (0) ---- /dev/null -+++ b/ldso/ldso/ubicom32/dl-syscalls.h -@@ -0,0 +1,206 @@ -+/* Copyright (C) 2003, 2004 Red Hat, Inc. -+ Contributed by Alexandre Oliva -+ -+This file is part of uClibc. -+ -+uClibc is free software; you can redistribute it and/or modify it -+under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+uClibc is distributed in the hope that it will be useful, but WITHOUT -+ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with uClibc; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, -+USA. */ -+ -+/* We can't use the real errno in ldso, since it has not yet -+ * been dynamicly linked in yet. */ -+#include "sys/syscall.h" -+extern int _dl_errno; -+#undef __set_errno -+#define __set_errno(X) {(_dl_errno) = (X);} -+#include -+ -+/* The code below is extracted from libc/sysdeps/linux/frv/_mmap.c */ -+ -+#if defined(DYNAMIC_LOADER_IN_SIMULATOR) && DYNAMIC_LOADER_IN_SIMULATOR -+#define __NR___syscall_mmap2 __NR_mmap2 -+static __inline__ _syscall6(__ptr_t, __syscall_mmap2, __ptr_t, addr, -+ size_t, len, int, prot, int, flags, int, fd, off_t, offset); -+ -+/* Make sure we don't get another definition of _dl_mmap from the -+ machine-independent code. */ -+#undef __NR_mmap -+#undef __NR_mmap2 -+ -+/* This is always 12, even on architectures where PAGE_SHIFT != 12. */ -+# ifndef MMAP2_PAGE_SHIFT -+# define MMAP2_PAGE_SHIFT 12 -+# endif -+ -+#include /* for PAGE_SIZE */ -+static __always_inline void *_dl_memset(void*,int,size_t); -+static __always_inline ssize_t _dl_pread(int fd, void *buf, size_t count, off_t offset); -+ -+static __ptr_t -+_dl_mmap(__ptr_t addr, size_t len, int prot, int flags, int fd, __off_t offset) -+{ -+ size_t plen = (len + PAGE_SIZE - 1) & -PAGE_SIZE; -+ -+/* This is a hack to enable the dynamic loader to run within a -+ simulator that doesn't support mmap, with a number of very ugly -+ tricks. Also, it's not as useful as it sounds, since only dynamic -+ executables without DT_NEEDED dependencies can be run. AFAIK, they -+ can only be created with -pie. This trick suffices to enable the -+ dynamic loader to obtain a blank page that it maps early in the -+ bootstrap. */ -+ if ((flags & MAP_FIXED) == 0) -+ { -+ void *_dl_mmap_base = 0; -+ __ptr_t *ret = 0; -+ -+ if (! _dl_mmap_base) -+ { -+ void *stack; -+ __asm__ ("mov sp, %0" : "=r" (stack)); -+ _dl_mmap_base = (void *)(((long)stack + 2 * PAGE_SIZE) & -PAGE_SIZE); -+ retry: -+ if (((void **)_dl_mmap_base)[0] == _dl_mmap_base -+ && ((void **)_dl_mmap_base)[1023] == _dl_mmap_base -+ && (((void **)_dl_mmap_base)[177] -+ == ((void **)_dl_mmap_base)[771])) -+ { -+ while (((void**)_dl_mmap_base)[177]) -+ { -+ _dl_mmap_base = ((void**)_dl_mmap_base)[177]; -+ if (!(((void **)_dl_mmap_base)[0] == _dl_mmap_base -+ && ((void **)_dl_mmap_base)[1023] == _dl_mmap_base -+ && (((void **)_dl_mmap_base)[177] -+ == ((void**)_dl_mmap_base)[771]))) -+ ((void(*)())0)(); -+ } -+ } -+ else -+ { -+ int i; -+ for (i = 0; i < (int)PAGE_SIZE; i++) -+ if (*(char*)(_dl_mmap_base + i)) -+ break; -+ if (i != PAGE_SIZE) -+ { -+ _dl_mmap_base = (void*)((long)_dl_mmap_base + PAGE_SIZE); -+ goto retry; -+ } -+ ((void**)_dl_mmap_base)[-1] = -+ ((void**)_dl_mmap_base)[0] = -+ ((void**)_dl_mmap_base)[1023] = -+ _dl_mmap_base; -+ } -+ } -+ -+ if (_dl_mmap_base) -+ { -+ if (!(((void **)_dl_mmap_base)[0] == _dl_mmap_base -+ && ((void **)_dl_mmap_base)[1023] == _dl_mmap_base -+ && (((void **)_dl_mmap_base)[177] -+ == ((void**)_dl_mmap_base)[771]))) -+ ((void(*)())0)(); -+ ret = (__ptr_t)((char*)_dl_mmap_base + PAGE_SIZE); -+ _dl_mmap_base = -+ ((void**)_dl_mmap_base)[177] = -+ ((void**)_dl_mmap_base)[771] = -+ (char*)_dl_mmap_base + plen + PAGE_SIZE; -+ ((void**)_dl_mmap_base)[0] = -+ ((void**)_dl_mmap_base)[1023] = -+ _dl_mmap_base; -+ } -+ -+ if ((flags & MAP_ANONYMOUS) != 0) -+ { -+ _dl_memset (ret, 0, plen); -+ return ret; -+ } -+ -+ flags |= MAP_FIXED; -+ addr = ret; -+ } -+ if (offset & ((1 << MMAP2_PAGE_SHIFT) - 1)) { -+#if 0 -+ __set_errno (EINVAL); -+#endif -+ return MAP_FAILED; -+ } -+ if ((flags & MAP_FIXED) != 0) -+ { -+ if (_dl_pread(fd, addr, len, offset) != (ssize_t)len) -+ return (void*)MAP_FAILED; -+ if (plen != len) -+ _dl_memset (addr + len, 0, plen - len); -+ return addr; -+ } -+ return(__syscall_mmap2(addr, len, prot, flags, fd, (off_t) (offset >> MMAP2_PAGE_SHIFT))); -+} -+#endif -+ -+#ifdef __NR_pread64 -+#ifdef DYNAMIC_LOADER_IN_SIMULATOR -+#include -+ -+#define __NR___syscall_lseek __NR_lseek -+static __always_inline unsigned long _dl_read(int fd, const void *buf, unsigned long count); -+ -+static __always_inline _syscall3(__off_t, __syscall_lseek, int, fd, __off_t, offset, -+ int, whence); -+static __always_inline ssize_t -+_dl_pread(int fd, void *buf, size_t count, off_t offset) -+{ -+ __off_t orig = __syscall_lseek (fd, 0, SEEK_CUR); -+ ssize_t ret; -+ -+ if (orig == -1) -+ return -1; -+ -+ if (__syscall_lseek (fd, offset, SEEK_SET) != offset) -+ return -1; -+ -+ ret = _dl_read (fd, buf, count); -+ -+ if (__syscall_lseek (fd, orig, SEEK_SET) != orig) -+ ((void(*)())0)(); -+ -+ return ret; -+} -+#else -+#define __NR___syscall_pread __NR_pread64 -+static __always_inline _syscall5(ssize_t, __syscall_pread, int, fd, void *, buf, -+ size_t, count, off_t, offset_hi, off_t, offset_lo); -+ -+static __always_inline ssize_t -+_dl_pread(int fd, void *buf, size_t count, off_t offset) -+{ -+ return(__syscall_pread(fd,buf,count,__LONG_LONG_PAIR (offset >> 31, offset))); -+} -+#endif -+#endif -+ -+#ifdef __NR_sram_alloc -+#define __NR__dl_sram_alloc __NR_sram_alloc -+static __always_inline _syscall2(__ptr_t, _dl_sram_alloc, -+ size_t, len, unsigned long, flags); -+#endif -+ -+#ifdef __NR_sram_free -+#define __NR__dl_sram_free __NR_sram_free -+static __always_inline _syscall1(int, _dl_sram_free, __ptr_t, addr); -+#endif -+ -+#ifdef __NR_dma_memcpy -+#define __NR__dl_dma_memcpy __NR_dma_memcpy -+static __always_inline _syscall3(__ptr_t, _dl_dma_memcpy, -+ __ptr_t, dest, __ptr_t, src, size_t, len); -+#endif ---- /dev/null -+++ b/ldso/ldso/ubicom32/dl-sysdep.h -@@ -0,0 +1,243 @@ -+ /* Copyright (C) 2003, 2004 Red Hat, Inc. -+ Contributed by Alexandre Oliva -+ Based on ../i386/dl-sysdep.h -+ -+This file is part of uClibc. -+ -+uClibc is free software; you can redistribute it and/or modify it -+under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+uClibc is distributed in the hope that it will be useful, but WITHOUT -+ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with uClibc; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, -+USA. */ -+ -+/* -+ * Various assembly language/system dependent hacks that are required -+ * so that we can minimize the amount of platform specific code. -+ */ -+ -+/* -+ * Define this if the system uses RELOCA. -+ */ -+#undef ELF_USES_RELOCA -+ -+/* JMPREL relocs are inside the DT_RELA table. */ -+#define ELF_MACHINE_PLTREL_OVERLAP -+ -+#define DL_NO_COPY_RELOCS -+ -+#define HAVE_DL_INLINES_H -+ -+/* -+ * Initialization sequence for a GOT. Copy the resolver function -+ * descriptor and the pointer to the elf_resolve/link_map data -+ * structure. Initialize the got_value in the module while at that. -+ */ -+#define INIT_GOT(GOT_BASE,MODULE) \ -+{ \ -+ (MODULE)->loadaddr.got_value = (GOT_BASE); \ -+ GOT_BASE[0] = ((unsigned long *)&_dl_linux_resolve)[0]; \ -+ GOT_BASE[1] = ((unsigned long *)&_dl_linux_resolve)[1]; \ -+ GOT_BASE[2] = (unsigned long) MODULE; \ -+} -+ -+/* Here we define the magic numbers that this dynamic loader should accept */ -+#define MAGIC1 EM_UBICOM32 -+#undef MAGIC2 -+ -+/* Used for error messages */ -+#define ELF_TARGET "UBICOM32" -+ -+struct elf_resolve; -+ -+struct funcdesc_value -+{ -+ void *entry_point; -+ void *got_value; -+/*int relocation; not sure if this required, but it does exist */ -+}; -+ -+extern int _dl_linux_resolve(void) __attribute__((__visibility__("hidden"))); -+extern struct funcdesc_value volatile *__attribute__((__visibility__("hidden"))) -+ _dl_linux_resolver (struct elf_resolve *tpnt, int reloc_entry); -+ -+/* 4KiB page alignment. Should perhaps be made dynamic using -+ getpagesize(), based on AT_PAGESZ from auxvt? */ -+#define PAGE_ALIGN 0xfffff000 -+#define ADDR_ALIGN 0xfff -+#define OFFS_ALIGN 0x7ffff000 -+ -+struct funcdesc_ht; -+ -+/* -+ * This asm does a quick relcation of string S (which is stored in the text -+ * section as thats all we can use -+ */ -+#undef SEND_EARLY_STDERR -+#define SEND_EARLY_STDERR(S) \ -+do { \ -+ static const char __attribute__((section(".text"))) __s[] = (S); \ -+ const char *__p, *__scratch; \ -+ __asm__ ( \ -+ " call a3, 1f; \n\t" \ -+ "1: movei %0, #%%got_lo(1b) \n\t" \ -+ " move.4 %0, (%3, %0) \n\t" \ -+ " sub.4 %1, a3, %0; \n\t" \ -+ " add.4 %1, %1, %2; \n\t" \ -+ : "=&d" (__scratch), "=&d" (__p) \ -+ : "d" (__s), "a" (dl_boot_got_pointer) \ -+ : "a3", "a4", "d15"); \ -+ SEND_STDERR (__p); \ -+ { int __t; \ -+ for (__t = 0; __t < 0x100000; __t++) __asm__ __volatile__ (""); } \ -+} while (0) -+ -+#define DL_LOADADDR_TYPE struct elf32_fdpic_loadaddr -+ -+#define DL_RELOC_ADDR(LOADADDR, ADDR) \ -+ ((ElfW(Addr))__reloc_pointer ((void*)(ADDR), (LOADADDR).map)) -+ -+#define DL_ADDR_TO_FUNC_PTR(ADDR, LOADADDR) \ -+ ((void(*)(void)) _dl_funcdesc_for ((void*)(ADDR), (LOADADDR).got_value)) -+ -+#define _dl_stabilize_funcdesc(val) \ -+ ({ __asm__ ("" : "+m" (*(val))); (val); }) -+ -+#define DL_CALL_FUNC_AT_ADDR(ADDR, LOADADDR, SIGNATURE, ...) \ -+ ({ struct funcdesc_value fd = { (void*)(ADDR), (LOADADDR).got_value }; \ -+ void (*pf)(void) = (void*) _dl_stabilize_funcdesc (&fd); \ -+ (* SIGNATURE pf)(__VA_ARGS__); }) -+ -+#define DL_INIT_LOADADDR_BOOT(LOADADDR, BASEADDR) \ -+ (__dl_init_loadaddr_map (&(LOADADDR), dl_boot_got_pointer, \ -+ dl_boot_ldsomap ?: dl_boot_progmap)) -+ -+#define DL_INIT_LOADADDR_PROG(LOADADDR, BASEADDR) \ -+ (__dl_init_loadaddr_map (&(LOADADDR), 0, dl_boot_progmap)) -+ -+#define DL_INIT_LOADADDR_EXTRA_DECLS \ -+ int dl_init_loadaddr_load_count; -+#define DL_INIT_LOADADDR(LOADADDR, BASEADDR, PHDR, PHDRCNT) \ -+ (dl_init_loadaddr_load_count = \ -+ __dl_init_loadaddr (&(LOADADDR), (PHDR), (PHDRCNT))) -+#define DL_INIT_LOADADDR_HDR(LOADADDR, ADDR, PHDR) \ -+ (__dl_init_loadaddr_hdr ((LOADADDR), (ADDR), (PHDR), \ -+ dl_init_loadaddr_load_count)) -+#define DL_LOADADDR_UNMAP(LOADADDR, LEN) \ -+ (__dl_loadaddr_unmap ((LOADADDR), (NULL))) -+#define DL_LIB_UNMAP(LIB, LEN) \ -+ (__dl_loadaddr_unmap ((LIB)->loadaddr, (LIB)->funcdesc_ht)) -+#define DL_LOADADDR_BASE(LOADADDR) \ -+ ((LOADADDR).got_value) -+ -+/* This is called from dladdr(), such that we map a function -+ descriptor's address to the function's entry point before trying to -+ find in which library it's defined. */ -+#define DL_LOOKUP_ADDRESS(ADDRESS) (_dl_lookup_address (ADDRESS)) -+ -+#define DL_ADDR_IN_LOADADDR(ADDR, TPNT, TFROM) \ -+ (! (TFROM) && __dl_addr_in_loadaddr ((void*)(ADDR), (TPNT)->loadaddr)) -+ -+/* -+ * Compute the GOT address. On several platforms, we use assembly -+ * here. on FR-V FDPIC, there's no way to compute the GOT address, -+ * since the offset between text and data is not fixed, so we arrange -+ * for the assembly _dl_boot to pass this value as an argument to -+ * _dl_boot. */ -+#define DL_BOOT_COMPUTE_GOT(got) ((got) = dl_boot_got_pointer) -+ -+#define DL_BOOT_COMPUTE_DYN(dpnt, got, load_addr) \ -+ ((dpnt) = dl_boot_ldso_dyn_pointer) -+ -+/* We only support loading FDPIC independently-relocatable shared -+ libraries. It probably wouldn't be too hard to support loading -+ shared libraries that require relocation by the same amount, but we -+ don't know that they exist or would be useful, and the dynamic -+ loader code could leak the whole-library map unless we keeping a -+ bit more state for DL_LOADADDR_UNMAP and DL_LIB_UNMAP, so let's -+ keep things simple for now. */ -+#define DL_CHECK_LIB_TYPE(epnt, piclib, _dl_progname, libname) \ -+do \ -+{ \ -+ if (((epnt)->e_flags & EF_UBICOM32_FDPIC) && ! ((epnt)->e_flags & EF_UBICOM32_PIC)) \ -+ (piclib) = 2; \ -+ else \ -+ { \ -+ _dl_internal_error_number = LD_ERROR_NOTDYN; \ -+ _dl_dprintf(2, "%s: '%s' is not an FDPIC shared library" \ -+ "\n", (_dl_progname), (libname)); \ -+ _dl_close(infile); \ -+ return NULL; \ -+ } \ -+\ -+} \ -+while (0) -+ -+/* We want want to apply all relocations in the interpreter during -+ bootstrap. Because of this, we have to skip the interpreter -+ relocations in _dl_parse_relocation_information(), see -+ elfinterp.c. */ -+#define DL_SKIP_BOOTSTRAP_RELOC(SYMTAB, INDEX, STRTAB) 0 -+ -+#ifdef __NR_pread64 -+#define _DL_PREAD(FD, BUF, SIZE, OFFSET) \ -+ (_dl_pread((FD), (BUF), (SIZE), (OFFSET))) -+#endif -+ -+/* We want to return to dlsym() a function descriptor if the symbol -+ turns out to be a function. */ -+#define DL_FIND_HASH_VALUE(TPNT, TYPE_CLASS, SYM) \ -+ (((TYPE_CLASS) & ELF_RTYPE_CLASS_DLSYM) \ -+ && ELF32_ST_TYPE((SYM)->st_info) == STT_FUNC \ -+ ? _dl_funcdesc_for ((void *)DL_RELOC_ADDR ((TPNT)->loadaddr, (SYM)->st_value), \ -+ (TPNT)->loadaddr.got_value) \ -+ : DL_RELOC_ADDR ((TPNT)->loadaddr, (SYM)->st_value)) -+ -+#if 0 /* XXX TODO will look at enabling this if we decide to add support for OCM -+ * code/data */ -+ -+#define DL_IS_SPECIAL_SEGMENT(EPNT, PPNT) \ -+ __dl_is_special_segment(EPNT, PPNT) -+#define DL_MAP_SEGMENT(EPNT, PPNT, INFILE, FLAGS) \ -+ __dl_map_segment (EPNT, PPNT, INFILE, FLAGS) -+ -+#endif -+ -+ -+#define DL_GET_READY_TO_RUN_EXTRA_PARMS \ -+ , struct elf32_fdpic_loadmap *dl_boot_progmap, Elf32_Addr dl_boot_got_pointer -+#define DL_GET_READY_TO_RUN_EXTRA_ARGS \ -+ , dl_boot_progmap, dl_boot_got_pointer -+ -+ -+#ifdef __USE_GNU -+# include -+#else -+# define __USE_GNU -+# include -+# undef __USE_GNU -+#endif -+ -+#include -+static __inline__ void -+elf_machine_relative (DL_LOADADDR_TYPE load_off, const Elf32_Addr rel_addr, -+ Elf32_Word relative_count) -+{ -+#if 0 -+ Elf32_Rel * rpnt = (void *) rel_addr; -+ --rpnt; -+ do { -+ Elf32_Addr *const reloc_addr = (void *) (load_off + (++rpnt)->r_offset); -+ -+ *reloc_addr = DL_RELOC_ADDR (load_off, *reloc_addr); -+ } while (--relative_count); -+#endif -+} ---- /dev/null -+++ b/ldso/ldso/ubicom32/elfinterp.c -@@ -0,0 +1,366 @@ -+/* Blackfin ELF shared library loader suppport -+ Copyright (C) 2003, 2004 Red Hat, Inc. -+ Contributed by Alexandre Oliva -+ Lots of code copied from ../i386/elfinterp.c, so: -+ Copyright (c) 1994-2000 Eric Youngdale, Peter MacDonald, -+ David Engel, Hongjiu Lu and Mitch D'Souza -+ Copyright (C) 2001-2002, Erik Andersen -+ All rights reserved. -+ -+This file is part of uClibc. -+ -+uClibc is free software; you can redistribute it and/or modify it -+under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+uClibc is distributed in the hope that it will be useful, but WITHOUT -+ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with uClibc; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, -+USA. */ -+ -+#include /* __attribute_used__ */ -+ -+/* Program to load an ELF binary on a linux system, and run it. -+ References to symbols in sharable libraries can be resolved by either -+ an ELF sharable library or a linux style of shared library. */ -+ -+/* Disclaimer: I have never seen any AT&T source code for SVr4, nor have -+ I ever taken any courses on internals. This program was developed using -+ information available through the book "UNIX SYSTEM V RELEASE 4, -+ Programmers guide: Ansi C and Programming Support Tools", which did -+ a more than adequate job of explaining everything required to get this -+ working. */ -+extern int _dl_ubicom32_resolve_pending(void) __attribute__((__visibility__("hidden"))); -+ -+struct funcdesc_value volatile *__attribute__((__visibility__("hidden"))) -+_dl_linux_resolver (struct elf_resolve *tpnt, int reloc_entry) -+{ -+ int reloc_type; -+ ELF_RELOC *this_reloc; -+ char *strtab; -+ ElfW(Sym) *symtab; -+ int symtab_index; -+ char *rel_addr; -+ struct elf_resolve *new_tpnt; -+ char *new_addr; -+ struct funcdesc_value funcval; -+ struct funcdesc_value volatile *got_entry; -+ char *symname; -+ -+ rel_addr = (char *)tpnt->dynamic_info[DT_JMPREL]; -+ -+ this_reloc = (ELF_RELOC *)(intptr_t)(rel_addr + reloc_entry); -+ reloc_type = ELF_R_TYPE(this_reloc->r_info); -+ symtab_index = ELF_R_SYM(this_reloc->r_info); -+ -+ symtab = (Elf32_Sym *) tpnt->dynamic_info[DT_SYMTAB]; -+ strtab = (char *) tpnt->dynamic_info[DT_STRTAB]; -+ symname= strtab + symtab[symtab_index].st_name; -+ -+ if (reloc_type != R_UBICOM32_FUNCDESC_VALUE) { -+ _dl_dprintf(2, "%s: Incorrect relocation type in jump relocations\n", -+ _dl_progname); -+ _dl_exit(1); -+ } -+ -+ /* Address of GOT entry fix up */ -+ got_entry = (struct funcdesc_value *) DL_RELOC_ADDR(tpnt->loadaddr, this_reloc->r_offset); -+ -+ /* Get the address to be used to fill in the GOT entry. */ -+ new_addr = _dl_lookup_hash(symname, tpnt->symbol_scope, NULL, 0, &new_tpnt); -+ if (!new_addr) { -+ new_addr = _dl_lookup_hash(symname, NULL, NULL, 0, &new_tpnt); -+ if (!new_addr) { -+ _dl_dprintf(2, "%s: can't resolve symbol '%s'\n", -+ _dl_progname, symname); -+ _dl_exit(1); -+ } -+ } -+ -+ funcval.entry_point = new_addr; -+ funcval.got_value = new_tpnt->loadaddr.got_value; -+ -+#if defined (__SUPPORT_LD_DEBUG__) -+ if (_dl_debug_bindings) { -+ _dl_dprintf(_dl_debug_file, "\nresolve function: %s", symname); -+ if (_dl_debug_detail) -+ _dl_dprintf(_dl_debug_file, -+ "\n\tpatched (%x,%x) ==> (%x,%x) @ %x\n", -+ got_entry->entry_point, got_entry->got_value, -+ funcval.entry_point, funcval.got_value, -+ got_entry); -+ } -+ if (1 || !_dl_debug_nofixups) { -+ got_entry->entry_point = ((unsigned long *)&_dl_ubicom32_resolve_pending)[0]; -+ got_entry->got_value = funcval.got_value; -+ got_entry->entry_point = funcval.entry_point; -+ } -+#else -+ /* -+ * initially set the entry point to resolve pending before starting -+ * the update. This has the effect of putting all other requests in a -+ * holding pattern until the resolution is completed. -+ */ -+ got_entry->entry_point = ((unsigned long *)&_dl_ubicom32_resolve_pending)[0]; -+ got_entry->got_value = funcval.got_value; -+ got_entry->entry_point = funcval.entry_point; -+#endif -+ -+ return got_entry; -+} -+ -+static int -+_dl_parse(struct elf_resolve *tpnt, struct dyn_elf *scope, -+ unsigned long rel_addr, unsigned long rel_size, -+ int (*reloc_fnc) (struct elf_resolve *tpnt, struct dyn_elf *scope, -+ ELF_RELOC *rpnt, ElfW(Sym) *symtab, char *strtab)) -+{ -+ unsigned int i; -+ char *strtab; -+ ElfW(Sym) *symtab; -+ ELF_RELOC *rpnt; -+ int symtab_index; -+ -+ /* Now parse the relocation information */ -+ rpnt = (ELF_RELOC *) rel_addr; -+ rel_size = rel_size / sizeof(ELF_RELOC); -+ -+ symtab = (ElfW(Sym) *) tpnt->dynamic_info[DT_SYMTAB]; -+ strtab = (char *) tpnt->dynamic_info[DT_STRTAB]; -+ -+ for (i = 0; i < rel_size; i++, rpnt++) { -+ int res; -+ -+ symtab_index = ELF_R_SYM(rpnt->r_info); -+ debug_sym(symtab,strtab,symtab_index); -+ debug_reloc(symtab,strtab,rpnt); -+ -+ res = reloc_fnc (tpnt, scope, rpnt, symtab, strtab); -+ -+ if (res==0) continue; -+ -+ _dl_dprintf(2, "\n%s: ",_dl_progname); -+ -+ if (symtab_index) -+ _dl_dprintf(2, "symbol '%s': ", strtab + symtab[symtab_index].st_name); -+ -+ if (res <0) { -+ int reloc_type = ELF_R_TYPE(rpnt->r_info); -+#if defined (__SUPPORT_LD_DEBUG__) -+ _dl_dprintf(2, "can't handle reloc type %s\n ", _dl_reltypes(reloc_type)); -+#else -+ _dl_dprintf(2, "can't handle reloc type %x\n", reloc_type); -+#endif -+ _dl_exit(-res); -+ } else if (res >0) { -+ _dl_dprintf(2, "can't resolve symbol\n"); -+ return res; -+ } -+ } -+ return 0; -+} -+ -+static int -+_dl_do_reloc (struct elf_resolve *tpnt,struct dyn_elf *scope, -+ ELF_RELOC *rpnt, ElfW(Sym) *symtab, char *strtab) -+{ -+ int reloc_type; -+ int symtab_index; -+ char *symname; -+ unsigned long reloc_value = 0, *reloc_addr; -+ struct { unsigned long v; } __attribute__((__packed__)) -+ *reloc_addr_packed; -+ unsigned long symbol_addr; -+ struct elf_resolve *symbol_tpnt; -+ struct funcdesc_value funcval; -+#if defined (__SUPPORT_LD_DEBUG__) -+ unsigned long old_val; -+#endif -+ -+ reloc_addr = (unsigned long *) DL_RELOC_ADDR(tpnt->loadaddr, rpnt->r_offset); -+ __asm__ ("" : "=r" (reloc_addr_packed) : "0" (reloc_addr)); -+ reloc_type = ELF_R_TYPE(rpnt->r_info); -+ symtab_index = ELF_R_SYM(rpnt->r_info); -+ symbol_addr = 0; -+ symname = strtab + symtab[symtab_index].st_name; -+ -+ if (ELF_ST_BIND (symtab[symtab_index].st_info) == STB_LOCAL) { -+ symbol_addr = (unsigned long) DL_RELOC_ADDR(tpnt->loadaddr, symtab[symtab_index].st_value); -+ symbol_tpnt = tpnt; -+ } else { -+ -+ symbol_addr = (unsigned long) -+ _dl_lookup_hash(symname, scope, NULL, 0, &symbol_tpnt); -+ -+ /* -+ * We want to allow undefined references to weak symbols - this might -+ * have been intentional. We should not be linking local symbols -+ * here, so all bases should be covered. -+ */ -+ -+ if (!symbol_addr && ELF_ST_BIND(symtab[symtab_index].st_info) != STB_WEAK) { -+ _dl_dprintf (2, "%s: can't resolve symbol '%s'\n", -+ _dl_progname, strtab + symtab[symtab_index].st_name); -+ _dl_exit (1); -+ } -+ } -+ -+#if defined (__SUPPORT_LD_DEBUG__) -+ if (_dl_debug_reloc && _dl_debug_detail) -+ { -+ if ((long)reloc_addr_packed & 3) -+ old_val = reloc_addr_packed->v; -+ else -+ old_val = *reloc_addr; -+ } -+ else -+ old_val = 0; -+#endif -+ switch (reloc_type) { -+ case R_UBICOM32_NONE: -+ break; -+ case R_UBICOM32_32: -+ if ((long)reloc_addr_packed & 3) -+ reloc_value = reloc_addr_packed->v += symbol_addr; -+ else -+ reloc_value = *reloc_addr += symbol_addr; -+ break; -+ case R_UBICOM32_FUNCDESC_VALUE: -+ funcval.entry_point = (void*)symbol_addr; -+ /* The addend of FUNCDESC_VALUE -+ relocations referencing global -+ symbols must be ignored, because it -+ may hold the address of a lazy PLT -+ entry. */ -+ if (ELF_ST_BIND(symtab[symtab_index].st_info) == STB_LOCAL) -+ funcval.entry_point += *reloc_addr; -+ reloc_value = (unsigned long)funcval.entry_point; -+ if (symbol_addr) -+ funcval.got_value -+ = symbol_tpnt->loadaddr.got_value; -+ else -+ funcval.got_value = 0; -+ -+/// XXX this is my best guess as to what I should be doing, but I'm -+/// putting a break-point here so I can inspect the first time this is -+/// used. -+ __asm__ ( -+ " move.4 4(%0), 4(%1) \n\t" -+ " move.4 0(%0), 0(%1) \n\t" /* Must to entry_point last */ -+ : -+ : "a" (reloc_addr), "a" (&funcval) -+ : "memory" ); -+ break; -+ case R_UBICOM32_FUNCDESC: -+ if ((long)reloc_addr_packed & 3) -+ reloc_value = reloc_addr_packed->v; -+ else -+ reloc_value = *reloc_addr; -+ if (symbol_addr) -+ reloc_value = (unsigned long)_dl_funcdesc_for -+ ((char *)symbol_addr + reloc_value, -+ symbol_tpnt->loadaddr.got_value); -+ else -+ reloc_value = 0; -+ if ((long)reloc_addr_packed & 3) -+ reloc_addr_packed->v = reloc_value; -+ else -+ *reloc_addr = reloc_value; -+ break; -+ default: -+ return -1; -+ } -+#if defined (__SUPPORT_LD_DEBUG__) -+ if (_dl_debug_reloc && _dl_debug_detail) { -+ _dl_dprintf(_dl_debug_file, "\tpatched: %x ==> %x @ %x", old_val, reloc_value, reloc_addr); -+ switch (reloc_type) { -+ case R_UBICOM32_FUNCDESC_VALUE: -+ _dl_dprintf(_dl_debug_file, " got %x", ((struct funcdesc_value *)reloc_value)->got_value); -+ break; -+ case R_UBICOM32_FUNCDESC: -+ if (! reloc_value) -+ break; -+ _dl_dprintf(_dl_debug_file, " funcdesc (%x,%x)", -+ ((struct funcdesc_value *)reloc_value)->entry_point, -+ ((struct funcdesc_value *)reloc_value)->got_value); -+ break; -+ } -+ } -+#endif -+ -+ return 0; -+} -+ -+static int -+_dl_do_lazy_reloc (struct elf_resolve *tpnt, -+ struct dyn_elf *scope __attribute__((unused)), -+ ELF_RELOC *rpnt, ElfW(Sym) *symtab __attribute__((unused)), -+ char *strtab __attribute__((unused))) -+{ -+ int reloc_type; -+ struct funcdesc_value volatile *reloc_addr; -+ struct funcdesc_value funcval; -+#if defined (__SUPPORT_LD_DEBUG__) -+ unsigned long old_val; -+#endif -+ -+ reloc_addr = (struct funcdesc_value *) DL_RELOC_ADDR(tpnt->loadaddr, rpnt->r_offset); -+ reloc_type = ELF_R_TYPE(rpnt->r_info); -+ -+#if defined (__SUPPORT_LD_DEBUG__) -+ old_val = (unsigned long)reloc_addr->entry_point; -+#endif -+ switch (reloc_type) { -+ case R_UBICOM32_NONE: -+ break; -+ case R_UBICOM32_FUNCDESC_VALUE: -+ funcval = *reloc_addr; -+ funcval.entry_point = (void*)DL_RELOC_ADDR(tpnt->loadaddr, funcval.entry_point); -+ funcval.got_value = tpnt->loadaddr.got_value; -+ *reloc_addr = funcval; -+ break; -+ default: -+ return -1; -+ } -+#if defined (__SUPPORT_LD_DEBUG__) -+ if (_dl_debug_reloc && _dl_debug_detail) -+ _dl_dprintf(_dl_debug_file, "\tpatched: %x ==> %x @ %x", old_val, reloc_addr->entry_point, reloc_addr); -+#endif -+ return 0; -+ -+} -+ -+void -+_dl_parse_lazy_relocation_information -+(struct dyn_elf *rpnt, unsigned long rel_addr, unsigned long rel_size) -+{ -+ _dl_parse(rpnt->dyn, NULL, rel_addr, rel_size, _dl_do_lazy_reloc); -+} -+ -+int -+_dl_parse_relocation_information -+(struct dyn_elf *rpnt, unsigned long rel_addr, unsigned long rel_size) -+{ -+ return _dl_parse(rpnt->dyn, rpnt->dyn->symbol_scope, rel_addr, rel_size, _dl_do_reloc); -+} -+ -+#if 0 -+/* We don't have copy relocs. */ -+int -+_dl_parse_copy_information -+(struct dyn_elf *rpnt __attribute__((unused)), -+ unsigned long rel_addr __attribute__((unused)), -+ unsigned long rel_size __attribute__((unused))) -+{ -+ return 0; -+} -+#endif -+#ifndef IS_IN_libdl -+# include "../../libc/sysdeps/linux/ubicom32/crtreloc.c" -+#endif ---- /dev/null -+++ b/ldso/ldso/ubicom32/resolve.S -@@ -0,0 +1,161 @@ -+ /* Copyright (C) 2003 Red Hat, Inc. -+ Contributed by Alexandre Oliva -+ -+ Copyright (C) 2009 Ubicom Inc. -+ Ported to Ubicom32 by Ubicom Inc. -+ -+This file is part of uClibc. -+ -+uClibc is free software; you can redistribute it and/or modify it -+under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+uClibc is distributed in the hope that it will be useful, but WITHOUT -+ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with uClibc; see the file COPYING.LIB. If not, write to -+the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, -+USA. */ -+ -+ -+/* -+ * The function below is tail-called by resolver stubs when a lazily-bound * -+ * function is called. It must preserve all registers that could * be used to -+ * pass arguments to the actual function. -+ * -+ * On entry to the function d0-d13 contain parameters to the actual function of -+ * interest -+ * -+ * a5 contains the return address -+ * a0 is pointing to the GOT table for the original function -+ * (a0) _dl_linux_resolve -+ * 4(a0) GOT for _dl_linux_resolve -+ * 8(a0) is pointer to "structure elf_resolve" of the module where the call -+ * originated from -+ * -+ * a3 is pointing to the function descriptor in the GOT table, and 8(a3) the -+ * resolver lookup information. -+ * -+ * _dl_linux_resolve calls _dl_linux_resolver passing it pointer to -+ * struct elf_resolve and the relocation entry. -+ * -+ * _dl_linux_resolver() figures out where the jump symbol is _really_ supposed -+ * to have jumped to and returns that to us. Once we have that, we prepare to -+ * tail-call the actual function, clean up after ourselves, restoring the -+ * original arguments, then jump to the fixed up address. -+ */ -+ -+#if 0 -+ /* -+ * Here is what the linker will use for the PLT. -+ */ -+sample_PLT_functionX: /* (at entry a0 contains GOT for this library) */ -+ movei d15, # -%lo(got_funcdescX) ; load offset for GOT -+ lea.4 a3, (a0, d15) ; a4 is now the function descriptor -+ move.4 a4, 0(a3) ; get entry_point -+ move.4 a0, 4(a3) ; set new GOT -+ -+ /* -+ * jump to resovled function OR PLT_trampoline Nat had some code here -+ * that uses the stack instead of a3 to reduces hazards. -+ */ -+ calli a4, 0(a4) -+ -+ -+sample_PLT_trampoline: -+ /* -+ * find the old got by undoing what was done above. An alternative -+ * could have been to ‘save’ the old got in say d14 but that would add 1 -+ * instruction to every PLT and there is only 1 PLT trampoline per library. -+ */ -+ ret (a0) ; jump to _dl_linux_resolve -+#endif -+ -+ .text -+ .p2align 4 -+ -+ .hidden _dl_linux_resolve -+ .global _dl_linux_resolve -+ .type _dl_linux_resolve,@function -+_dl_linux_resolve: -+ /* Preserve arguments and return address */ -+ move.4 -4(sp)++, d0 -+ move.4 -4(sp)++, d1 -+ move.4 -4(sp)++, d2 -+ move.4 -4(sp)++, d3 -+ move.4 -4(sp)++, d4 -+ move.4 -4(sp)++, d5 -+ move.4 -4(sp)++, d6 -+ move.4 -4(sp)++, d7 -+ move.4 -4(sp)++, d8 -+ move.4 -4(sp)++, d9 -+ move.4 -4(sp)++, d10 -+ move.4 -4(sp)++, d11 -+ move.4 -4(sp)++, d12 -+ move.4 -4(sp)++, d13 -+ move.4 -4(sp)++, a5 -+ -+ /* Prepare to call _dl_linux_resolver. */ -+ move.4 d0, 8(a0) ; reference to elf_resolve -+ /* Not aligned for space reasons. */ -+ move.4 d1, mac_hi ; reference to GOT table entry which -+ ; contains the relocation information. -+ -+ move.4 a0, 4(a0) ; switch to GOT for _dl_linux_resolve -+ call a5, _dl_linux_resolver; -+ -+ /* Move aside return value that contains the FUNCDESC_VALUE. */ -+ ;P3 = R0; -+ move.4 a3, d0; -+ -+ /* Restore arguments. */ -+ move.4 a5, (sp)4++ -+ move.4 d13, (sp)4++ -+ move.4 d12, (sp)4++ -+ move.4 d11, (sp)4++ -+ move.4 d10, (sp)4++ -+ move.4 d9, (sp)4++ -+ move.4 d8, (sp)4++ -+ move.4 d7, (sp)4++ -+ move.4 d6, (sp)4++ -+ move.4 d5, (sp)4++ -+ move.4 d4, (sp)4++ -+ move.4 d3, (sp)4++ -+ move.4 d2, (sp)4++ -+ move.4 d1, (sp)4++ -+ move.4 d0, (sp)4++ -+ -+ /* Now jump to the actual function. */ -+ /* a3 contains func_desc resolution */ -+ move.4 a4, 0(a3) ; address of function X -+ move.4 a0, 4(a3) ; switch to GOT for function X -+ calli a4, 0(a4) ; call through a4, a5 remains -+ -+ .size _dl_linux_resolve, . - _dl_linux_resolve -+ -+ .hidden _dl_ubicom32_resolve_pending -+ .global _dl_ubicom32_resolve_pending -+ .type _dl_ubicom32_resolve_pending,@function -+ -+_dl_ubicom32_resolve_pending: -+ /* -+ * A special function that is used to ensure thread saftly when the fd -+ * for a particular resolution is being updated. -+ * -+ * At entry, a3 must point to the FD. While the FD is being updated the -+ * entry_point will continue to point to _dl_ubicom32_resolve_pending so -+ * we will effectively spin until the resolver update is complete. -+ */ -+ -+ move.4 a4, 0(a3) ; get entry_point -+ move.4 a0, 4(a3) ; set new GOT -+ -+ /* -+ * jump to resovled function or back to _dl_ubicom32_resolve_pending. -+ */ -+ calli a4, 0(a4) -+ .size _dl_ubicom32_resolve_pending, . - _dl_ubicom32_resolve_pending ---- a/libc/misc/Makefile.in -+++ b/libc/misc/Makefile.in -@@ -12,7 +12,9 @@ include $(top_srcdir)libc/misc/assert/Ma - include $(top_srcdir)libc/misc/ctype/Makefile.in - include $(top_srcdir)libc/misc/dirent/Makefile.in - include $(top_srcdir)libc/misc/error/Makefile.in -+ifneq ($(ARCH_HAS_NO_LDSO),y) - include $(top_srcdir)libc/misc/elf/Makefile.in -+endif - include $(top_srcdir)libc/misc/file/Makefile.in - include $(top_srcdir)libc/misc/fnmatch/Makefile.in - include $(top_srcdir)libc/misc/ftw/Makefile.in ---- a/libc/misc/elf/dl-iterate-phdr.c -+++ b/libc/misc/elf/dl-iterate-phdr.c -@@ -14,7 +14,7 @@ - - #include - #include -- -+#include - /* we want this in libc but nowhere else */ - #ifdef __USE_GNU - ---- a/libc/stdlib/malloc/malloc.c -+++ b/libc/stdlib/malloc/malloc.c -@@ -23,7 +23,7 @@ - - /* The malloc heap. We provide a bit of initial static space so that - programs can do a little mallocing without mmaping in more space. */ --HEAP_DECLARE_STATIC_FREE_AREA (initial_fa, 256); -+HEAP_DECLARE_STATIC_FREE_AREA (initial_fa, 32768); - struct heap_free_area *__malloc_heap = HEAP_INIT_WITH_FA (initial_fa); - #ifdef HEAP_USE_LOCKING - malloc_mutex_t __malloc_heap_lock = PTHREAD_MUTEX_INITIALIZER; ---- /dev/null -+++ b/libc/string/ubicom32/Makefile -@@ -0,0 +1,13 @@ -+# Makefile for uClibc -+# -+# Copyright (C) 2000-2005 Erik Andersen -+# -+# Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball. -+# -+ -+top_srcdir:=../../../ -+top_builddir:=../../../ -+all: objs -+include $(top_builddir)Rules.mak -+include ../Makefile.in -+include $(top_srcdir)Makerules ---- /dev/null -+++ b/libc/string/ubicom32/memcpy.c -@@ -0,0 +1,152 @@ -+/* Copy memory to memory until the specified number of bytes -+ has been copied. Overlap is NOT handled correctly. -+ Copyright (C) 1991, 1997, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Torbjorn Granlund (tege@sics.se). -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+typedef unsigned long addr_t; -+ -+libc_hidden_proto(memcpy) -+ -+void *memcpy (void *dest, const void *src, size_t n) -+{ -+ void *dest_ret = dest; -+ void *aligned_start; -+ -+ if (likely((((addr_t)dest ^ (addr_t)src) & 3) == 0) && likely(n > 6)) { -+ size_t m; -+ n -= (4 - (addr_t)dest) & 0x03; -+ m = n >> 2; -+ __asm__ volatile ( -+ " call %4, 99f \n\t" // load %4 with address of 99 -+ "99: movei d15, #%%lo(1f-99b) \n\t" // load d15 with offset to 1 from 99 -+ " add.4 %4, %4, d15 \n\t" // add difference -+ -+ " sub.4 d15, #0, %2 \n\t" // set up for jump table -+ " and.4 d15, #(32-1), d15 \n\t" // d15 = (-m) & (32 - 1) -+ " lea.4 %4, (%4,d15) \n\t" -+ -+ " bfextu d15, %0, #2 \n\t" // d15 = (dest & 3) -+ " jmpne.w.f 100f \n\t" -+ " calli %4, 0(%4) \n\t" // 4-byte alignment -+ -+ "100: cmpi d15, #2 \n\t" -+ " jmpne.s.f 101f \n\t" -+ " move.2 (%0)2++, (%1)2++ \n\t" -+ " calli %4, 0(%4) \n\t" // 2-byte alignment -+ -+ "101: move.1 (%0)1++, (%1)1++ \n\t" -+ " jmpgt.s.f 102f \n\t" // 3-byte alignment -+ " move.2 (%0)2++, (%1)2++ \n\t" // 1-byte alignment -+ "102: calli %4, 0(%4) \n\t" -+ -+ "200: cmpi %3, #2 \n\t" -+ " jmplt.s.f 201f \n\t" -+ " move.2 (%0)2++, (%1)2++ \n\t" -+ " jmpeq.s.t 2f \n\t" -+ "201: move.1 (%0)1++, (%1)1++ \n\t" -+ " jmpt.w.t 2f \n\t" -+ -+ "1: .rept 25 \n\t" -+ " movea (%0)4++, (%1)4++ \n\t" -+ " .endr \n\t" -+ " .rept 7 \n\t" -+ " move.4 (%0)4++, (%1)4++ \n\t" -+ " .endr \n\t" -+ " add.4 %2, #-32, %2 \n\t" -+ " jmpgt.w.f 1b \n\t" -+ -+ " and.4 %3, #3, %3 \n\t" // check n -+ " jmpne.w.f 200b \n\t" -+ "2: \n\t" -+ : "+a"(dest), "+a"(src), "+d"(m), "+d"(n), "=a"(aligned_start) -+ : -+ : "d15", "memory", "cc" -+ ); -+ -+ return dest_ret; -+ } -+ -+ if (likely((((addr_t)dest ^ (addr_t)src) & 1) == 0) && likely(n > 2)) { -+ size_t m; -+ n -= (addr_t)dest & 0x01; -+ m = n >> 1; -+ __asm__ volatile ( -+ " call %4, 99f \n\t" // load %4 with address of 99 -+ "99: movei d15, #%%lo(1f-99b) \n\t" // load d15 with offset to 1 from 99 -+ " add.4 %4, %4, d15 \n\t" // add difference -+ -+ " sub.4 d15, #0, %2 \n\t" // set up for jump table -+ " and.4 d15, #(32-1), d15 \n\t" // d15 = (-m) & (32 - 1) -+ " lea.4 %4, (%4,d15) \n\t" -+ -+ " btst %0, #0 \n\t" // check bit 0 -+ " jmpne.w.f 100f \n\t" -+ " calli %4, 0(%4) \n\t" // 4-byte alignment -+ -+ "100: move.1 (%0)1++, (%1)1++ \n\t" -+ " calli %4, 0(%4) \n\t" -+ -+ "200: move.1 (%0)1++, (%1)1++ \n\t" -+ " jmpt.w.t 2f \n\t" -+ -+ "1: .rept 32 \n\t" -+ " move.2 (%0)2++, (%1)2++ \n\t" -+ " .endr \n\t" -+ " add.4 %2, #-32, %2 \n\t" -+ " jmpgt.w.f 1b \n\t" -+ -+ " and.4 %3, #1, %3 \n\t" // check n -+ " jmpne.w.f 200b \n\t" -+ "2: \n\t" -+ -+ : "+a"(dest), "+a"(src), "+d"(m), "+d"(n), "=a"(aligned_start) -+ : -+ : "d15", "memory", "cc" -+ ); -+ return dest_ret; -+ } -+ -+ __asm__ volatile ( -+ " call %3, 99f \n\t" // load %3 with address of 99 -+ "99: movei d15, #%%lo(1f-99b) \n\t" // load d15 with offset to 1 from 99 -+ " add.4 %3, %3, d15 \n\t" // add difference -+ -+ " sub.4 d15, #0, %2 \n\t" -+ " jmpeq.w.f 2f \n\t" -+ " and.4 d15, #(16-1), d15 \n\t" // d15 = (-n) & (16 - 1) -+ " lea.4 %3, (%3,d15) \n\t" -+ " calli %3, 0(%3) \n\t" -+ -+ "1: .rept 16 \n\t" -+ " move.1 (%0)1++, (%1)1++ \n\t" -+ " .endr \n\t" -+ " add.4 %2, #-16, %2 \n\t" -+ " jmpgt.w.f 1b \n\t" -+ "2: \n\t" -+ -+ : "+a"(dest), "+a"(src), "+d"(n), "=a"(aligned_start) -+ : -+ : "d15", "memory", "cc" -+ ); -+ -+ return dest_ret; -+} -+libc_hidden_def(memcpy) ---- /dev/null -+++ b/libc/string/ubicom32/memset.c -@@ -0,0 +1,107 @@ -+/* Copyright (C) 1991, 1997, 2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+typedef unsigned long addr_t; -+ -+libc_hidden_proto(memset) -+void *memset (void *s, int c, size_t n) -+{ -+ void *s_ret = s; -+ void *aligned_start; -+ if (likely(n > 6)) { -+ size_t m; -+ n -= (4 - (addr_t)s) & 0x03; -+ m = n >> 2; -+ __asm__ volatile ( -+ " call %4, 99f \n\t" // load %4 with address of 99 -+ "99: movei d15, #%%lo(1f-99b) \n\t" // load d15 with offset to 1 from 99 -+ " add.4 %4, %4, d15 \n\t" // add difference -+ -+ " sub.4 d15, #0, %2 \n\t" // set up for jump table -+ " and.4 d15, #(32-1), d15 \n\t" // d15 = (-m) & (32 - 1) -+ " shmrg.1 %1, %1, %1 \n\t" -+ " shmrg.2 %1, %1, %1 \n\t" // %1 = (c<<24)|(c<<16)|(c<<8)|c -+ " lea.4 %4, (%4,d15) \n\t" -+ -+ " bfextu d15, %0, #2 \n\t" // d15 = (s & 3) -+ " jmpne.w.f 100f \n\t" -+ " calli %4, 0(%4) \n\t" // 4-byte alignment -+ -+ "100: cmpi d15, #2 \n\t" -+ " jmpne.s.f 101f \n\t" -+ " move.2 (%0)2++, %1 \n\t" -+ " calli %4, 0(%4) \n\t" // 2-byte alignment -+ -+ "101: move.1 (%0)1++, %1 \n\t" -+ " jmpgt.s.f 102f \n\t" // 3-byte alignment -+ " move.2 (%0)2++, %1 \n\t" // 1-byte alignment -+ "102: calli %4, 0(%4) \n\t" -+ -+ "200: cmpi %3, #2 \n\t" -+ " jmplt.s.f 201f \n\t" -+ " move.2 (%0)2++, %1 \n\t" -+ " jmpeq.s.t 2f \n\t" -+ "201: move.1 (%0)1++, %1 \n\t" -+ " jmpt.w.t 2f \n\t" -+ -+ "1: .rept 25 \n\t" -+ " movea (%0)4++, %1 \n\t" -+ " .endr \n\t" -+ " .rept 7 \n\t" -+ " move.4 (%0)4++, %1 \n\t" -+ " .endr \n\t" -+ " add.4 %2, #-32, %2 \n\t" -+ " jmpgt.w.f 1b \n\t" -+ -+ " and.4 %3, #3, %3 \n\t" // test bit 1 of n -+ " jmpne.w.f 200b \n\t" -+ "2: \n\t" -+ : "+a"(s), "+d"(c), "+d"(m), "+d"(n), "=a"(aligned_start) -+ : -+ : "d15", "memory", "cc" -+ ); -+ -+ return s_ret; -+ } -+ -+ __asm__ volatile ( -+ " call %3, 99f \n\t" // load %3 with address of 99 -+ "99: movei d15, #%%lo(1f-99b) \n\t" // load d15 with offset to 1 from 99 -+ " add.4 %3, %3, d15 \n\t" // add difference -+ -+ " sub.4 d15, #0, %2 \n\t" -+ " jmpeq.w.f 2f \n\t" -+ " and.4 d15, #(8-1), d15 \n\t" // d15 = (-%2) & (16 - 1) -+ " lea.4 %3, (%3,d15) \n\t" -+ " calli %3, 0(%3) \n\t" -+ -+ "1: .rept 8 \n\t" -+ " move.1 (%0)1++, %1 \n\t" -+ " .endr \n\t" -+ "2: \n\t" -+ -+ : "+a"(s), "+d"(c), "+d"(n), "=a"(aligned_start) -+ : -+ : "d15", "memory", "cc" -+ ); -+ -+ return s_ret; -+} -+libc_hidden_def(memset) ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/Makefile -@@ -0,0 +1,13 @@ -+# Makefile for uClibc -+# -+# Copyright (C) 2000-2006 Erik Andersen -+# -+# Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball. -+# -+ -+top_srcdir=../../../../ -+top_builddir=../../../../ -+all: objs -+include $(top_builddir)Rules.mak -+include Makefile.arch -+include $(top_srcdir)Makerules ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/Makefile.arch -@@ -0,0 +1,28 @@ -+# Makefile for uClibc -+# -+# Copyright (C) 2000-2006 Erik Andersen -+# -+# Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball. -+# -+ -+#CSRC := \ -+# brk.c \ -+# crtbegin.c \ -+# crtend.c -+# -+#SSRC := \ -+# __longjmp.S \ -+# bsd-_setjmp.S \ -+# bsd-setjmp.S \ -+# setjmp.S \ -+# clone.S \ -+# vfork.S -+ -+CSRC := \ -+ syscall.c __syscall_error.c -+ -+SSRC := \ -+ clone.S setjmp.S vfork.S -+ -+ARCH_CFLAGS := $(CPU_CFLAGS-y) -+include $(top_srcdir)libc/sysdeps/linux/Makefile.commonarch ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/__syscall_error.c -@@ -0,0 +1,11 @@ -+#include -+#include -+ -+/* This routine is jumped to by some of the syscall handlers, to stash -+ * an error number into errno. */ -+int __syscall_error(int err_no) attribute_hidden; -+int __syscall_error(int err_no) -+{ -+ __set_errno(err_no); -+ return -1; -+} ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/elf-fdpic.h -@@ -0,0 +1,115 @@ -+/* Copyright 2003, 2004 Free Software Foundation, Inc. -+This file is part of the GNU C Library. -+ -+The GNU C Library is free software; you can redistribute it and/or -+modify it under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+In addition to the permissions in the GNU Lesser General Public -+License, the Free Software Foundation gives you unlimited -+permission to link the compiled version of this file with other -+programs, and to distribute those programs without any restriction -+coming from the use of this file. (The GNU Lesser General Public -+License restrictions do apply in other respects; for example, they -+cover modification of the file, and distribution when not linked -+into another program.) -+ -+The GNU C Library is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with the GNU C Library; see the file COPYING.LIB. If -+not, write to the Free Software Foundation, Inc., 675 Mass Ave, -+Cambridge, MA 02139, USA. */ -+ -+#ifndef _BITS_ELF_FDPIC_H -+#define _BITS_ELF_FDPIC_H -+ -+/* These data structures are described in the FDPIC ABI extension. -+ The kernel passes a process a memory map, such that for every LOAD -+ segment there is an elf32_fdpic_loadseg entry. A pointer to an -+ elf32_fdpic_loadmap is passed in d8 at start-up, and a pointer to -+ an additional such map is passed in d9 for the interpreter, when -+ there is one. */ -+ -+#include -+ -+/* This data structure represents a PT_LOAD segment. */ -+struct elf32_fdpic_loadseg -+{ -+ /* Core address to which the segment is mapped. */ -+ Elf32_Addr addr; -+ /* VMA recorded in the program header. */ -+ Elf32_Addr p_vaddr; -+ /* Size of this segment in memory. */ -+ Elf32_Word p_memsz; -+}; -+ -+struct elf32_fdpic_loadmap { -+ /* Protocol version number, must be zero. */ -+ Elf32_Half version; -+ /* Number of segments in this map. */ -+ Elf32_Half nsegs; -+ /* The actual memory map. */ -+ struct elf32_fdpic_loadseg segs[/*nsegs*/]; -+}; -+ -+struct elf32_fdpic_loadaddr { -+ struct elf32_fdpic_loadmap *map; -+ void *got_value; -+}; -+ -+/* Map a pointer's VMA to its corresponding address according to the -+ load map. */ -+static __always_inline void * -+__reloc_pointer (void *p, -+ const struct elf32_fdpic_loadmap *map) -+{ -+ int c; -+ -+#if 0 -+ if (map->version != 0) -+ /* Crash. */ -+ ((void(*)())0)(); -+#endif -+ -+ /* No special provision is made for NULL. We don't want NULL -+ addresses to go through relocation, so they shouldn't be in -+ .rofixup sections, and, if they're present in dynamic -+ relocations, they shall be mapped to the NULL address without -+ undergoing relocations. */ -+ -+ for (c = 0; -+ /* Take advantage of the fact that the loadmap is ordered by -+ virtual addresses. In general there will only be 2 entries, -+ so it's not profitable to do a binary search. */ -+ c < map->nsegs && p >= (void*)map->segs[c].p_vaddr; -+ c++) -+ { -+ /* This should be computed as part of the pointer comparison -+ above, but we want to use the carry in the comparison, so we -+ can't convert it to an integer type beforehand. */ -+ unsigned long offset = p - (void*)map->segs[c].p_vaddr; -+ /* We only check for one-past-the-end for the last segment, -+ assumed to be the data segment, because other cases are -+ ambiguous in the absence of padding between segments, and -+ rofixup already serves as padding between text and data. -+ Unfortunately, unless we special-case the last segment, we -+ fail to relocate the _end symbol. */ -+ if (offset < map->segs[c].p_memsz -+ || (offset == map->segs[c].p_memsz && c + 1 == map->nsegs)) -+ return (char*)map->segs[c].addr + offset; -+ } -+ -+ /* We might want to crash instead. */ -+ return (void*)-1; -+} -+ -+# define __RELOC_POINTER(ptr, loadaddr) \ -+ (__reloc_pointer ((void*)(ptr), \ -+ (loadaddr).map)) -+ -+#endif /* _BITS_ELF_FDPIC_H */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/endian.h -@@ -0,0 +1,7 @@ -+/* Ubicom32 is big-endian. */ -+ -+#ifndef _ENDIAN_H -+# error "Never use directly; include instead." -+#endif -+ -+#define __BYTE_ORDER __BIG_ENDIAN ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/fcntl.h -@@ -0,0 +1,226 @@ -+/* O_*, F_*, FD_* bit values for Linux. -+ Copyright (C) 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _FCNTL_H -+# error "Never use directly; include instead." -+#endif -+ -+ -+#include -+#ifdef __USE_GNU -+# include -+#endif -+ -+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files -+ located on an ext2 file system */ -+#define O_ACCMODE 0003 -+#define O_RDONLY 00 -+#define O_WRONLY 01 -+#define O_RDWR 02 -+#define O_CREAT 0100 /* not fcntl */ -+#define O_EXCL 0200 /* not fcntl */ -+#define O_NOCTTY 0400 /* not fcntl */ -+#define O_TRUNC 01000 /* not fcntl */ -+#define O_APPEND 02000 -+#define O_NONBLOCK 04000 -+#define O_NDELAY O_NONBLOCK -+#define O_SYNC 010000 -+#define O_FSYNC O_SYNC -+#define O_ASYNC 020000 -+ -+#ifdef __USE_GNU -+# define O_DIRECTORY 040000 /* Must be a directory. */ -+# define O_NOFOLLOW 0100000 /* Do not follow links. */ -+# define O_DIRECT 0200000 /* Direct disk access. */ -+# define O_NOATIME 01000000 /* Do not set atime. */ -+# define O_CLOEXEC 02000000 /* set close_on_exec */ -+# define O_STREAMING 04000000 /* streaming access */ -+#endif -+ -+/* For now Linux has synchronisity options for data and read operations. -+ We define the symbols here but let them do the same as O_SYNC since -+ this is a superset. */ -+#if defined __USE_POSIX199309 || defined __USE_UNIX98 -+# define O_DSYNC O_SYNC /* Synchronize data. */ -+# define O_RSYNC O_SYNC /* Synchronize read operations. */ -+#endif -+ -+#ifdef __USE_LARGEFILE64 -+# define O_LARGEFILE 0400000 -+#endif -+ -+/* Values for the second argument to `fcntl'. */ -+#define F_DUPFD 0 /* Duplicate file descriptor. */ -+#define F_GETFD 1 /* Get file descriptor flags. */ -+#define F_SETFD 2 /* Set file descriptor flags. */ -+#define F_GETFL 3 /* Get file status flags. */ -+#define F_SETFL 4 /* Set file status flags. */ -+#ifndef __USE_FILE_OFFSET64 -+# define F_GETLK 5 /* Get record locking info. */ -+# define F_SETLK 6 /* Set record locking info (non-blocking). */ -+# define F_SETLKW 7 /* Set record locking info (blocking). */ -+#else -+# define F_GETLK F_GETLK64 /* Get record locking info. */ -+# define F_SETLK F_SETLK64 /* Set record locking info (non-blocking).*/ -+# define F_SETLKW F_SETLKW64 /* Set record locking info (blocking). */ -+#endif -+#define F_GETLK64 12 /* Get record locking info. */ -+#define F_SETLK64 13 /* Set record locking info (non-blocking). */ -+#define F_SETLKW64 14 /* Set record locking info (blocking). */ -+ -+#if defined __USE_BSD || defined __USE_XOPEN2K -+# define F_SETOWN 8 /* Get owner of socket (receiver of SIGIO). */ -+# define F_GETOWN 9 /* Set owner of socket (receiver of SIGIO). */ -+#endif -+ -+#ifdef __USE_GNU -+# define F_SETSIG 10 /* Set number of signal to be sent. */ -+# define F_GETSIG 11 /* Get number of signal to be sent. */ -+#endif -+ -+#ifdef __USE_GNU -+# define F_SETLEASE 1024 /* Set a lease. */ -+# define F_GETLEASE 1025 /* Enquire what lease is active. */ -+# define F_NOTIFY 1026 /* Request notfications on a directory. */ -+#endif -+ -+/* For F_[GET|SET]FL. */ -+#define FD_CLOEXEC 1 /* actually anything with low bit set goes */ -+ -+/* For posix fcntl() and `l_type' field of a `struct flock' for lockf(). */ -+#define F_RDLCK 0 /* Read lock. */ -+#define F_WRLCK 1 /* Write lock. */ -+#define F_UNLCK 2 /* Remove lock. */ -+ -+/* For old implementation of bsd flock(). */ -+#define F_EXLCK 4 /* or 3 */ -+#define F_SHLCK 8 /* or 4 */ -+ -+#ifdef __USE_BSD -+/* Operations for bsd flock(), also used by the kernel implementation. */ -+# define LOCK_SH 1 /* shared lock */ -+# define LOCK_EX 2 /* exclusive lock */ -+# define LOCK_NB 4 /* or'd with one of the above to prevent -+ blocking */ -+# define LOCK_UN 8 /* remove lock */ -+#endif -+ -+#ifdef __USE_GNU -+# define LOCK_MAND 32 /* This is a mandatory flock: */ -+# define LOCK_READ 64 /* ... which allows concurrent read operations. */ -+# define LOCK_WRITE 128 /* ... which allows concurrent write operations. */ -+# define LOCK_RW 192 /* ... Which allows concurrent read & write operations. */ -+#endif -+ -+#ifdef __USE_GNU -+/* Types of directory notifications that may be requested with F_NOTIFY. */ -+# define DN_ACCESS 0x00000001 /* File accessed. */ -+# define DN_MODIFY 0x00000002 /* File modified. */ -+# define DN_CREATE 0x00000004 /* File created. */ -+# define DN_DELETE 0x00000008 /* File removed. */ -+# define DN_RENAME 0x00000010 /* File renamed. */ -+# define DN_ATTRIB 0x00000020 /* File changed attibutes. */ -+# define DN_MULTISHOT 0x80000000 /* Don't remove notifier. */ -+#endif -+ -+struct flock -+ { -+ short int l_type; /* Type of lock: F_RDLCK, F_WRLCK, or F_UNLCK. */ -+ short int l_whence; /* Where `l_start' is relative to (like `lseek'). */ -+#ifndef __USE_FILE_OFFSET64 -+ __off_t l_start; /* Offset where the lock begins. */ -+ __off_t l_len; /* Size of the locked area; zero means until EOF. */ -+#else -+ __off64_t l_start; /* Offset where the lock begins. */ -+ __off64_t l_len; /* Size of the locked area; zero means until EOF. */ -+#endif -+ __pid_t l_pid; /* Process holding the lock. */ -+ }; -+ -+#ifdef __USE_LARGEFILE64 -+struct flock64 -+ { -+ short int l_type; /* Type of lock: F_RDLCK, F_WRLCK, or F_UNLCK. */ -+ short int l_whence; /* Where `l_start' is relative to (like `lseek'). */ -+ __off64_t l_start; /* Offset where the lock begins. */ -+ __off64_t l_len; /* Size of the locked area; zero means until EOF. */ -+ __pid_t l_pid; /* Process holding the lock. */ -+ }; -+#endif -+ -+/* Define some more compatibility macros to be backward compatible with -+ BSD systems which did not managed to hide these kernel macros. */ -+#ifdef __USE_BSD -+# define FAPPEND O_APPEND -+# define FFSYNC O_FSYNC -+# define FASYNC O_ASYNC -+# define FNONBLOCK O_NONBLOCK -+# define FNDELAY O_NDELAY -+#endif /* Use BSD. */ -+ -+/* Advise to `posix_fadvise'. */ -+#ifdef __USE_XOPEN2K -+# define POSIX_FADV_NORMAL 0 /* No further special treatment. */ -+# define POSIX_FADV_RANDOM 1 /* Expect random page references. */ -+# define POSIX_FADV_SEQUENTIAL 2 /* Expect sequential page references. */ -+# define POSIX_FADV_WILLNEED 3 /* Will need these pages. */ -+# define POSIX_FADV_DONTNEED 4 /* Don't need these pages. */ -+# define POSIX_FADV_NOREUSE 5 /* Data will be accessed once. */ -+#endif -+ -+#ifdef __USE_GNU -+# define SYNC_FILE_RANGE_WAIT_BEFORE 1 /* Wait upon writeout of all pages -+ in the range before performing the -+ write. */ -+# define SYNC_FILE_RANGE_WRITE 2 /* Initiate writeout of all those -+ dirty pages in the range which are -+ not presently under writeback. */ -+# define SYNC_FILE_RANGE_WAIT_AFTER 4 /* Wait upon writeout of all pages in -+ the range after performing the -+ write. */ -+#endif -+ -+__BEGIN_DECLS -+ -+#ifdef __USE_GNU -+ -+/* Provide kernel hint to read ahead. */ -+extern ssize_t readahead (int __fd, __off64_t __offset, size_t __count) -+ __THROW; -+ -+/* Selective file content synch'ing. */ -+extern int sync_file_range (int __fd, __off64_t __from, __off64_t __to, -+ unsigned int __flags); -+ -+/* Splice address range into a pipe. */ -+extern ssize_t vmsplice (int __fdout, const struct iovec *__iov, -+ size_t __count, unsigned int __flags); -+ -+/* Splice two files together. */ -+extern ssize_t splice (int __fdin, __off64_t *__offin, int __fdout, -+ __off64_t *__offout, size_t __len, -+ unsigned int __flags); -+ -+/* In-kernel implementation of tee for pipe buffers. */ -+extern ssize_t tee (int __fdin, int __fdout, size_t __len, -+ unsigned int __flags); -+ -+#endif -+ -+__END_DECLS ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/kernel_stat.h -@@ -0,0 +1,55 @@ -+#ifndef _BITS_STAT_STRUCT_H -+#define _BITS_STAT_STRUCT_H -+ -+#ifndef _LIBC -+#error bits/kernel_stat.h is for internal uClibc use only! -+#endif -+ -+/* This file provides whatever this particular arch's kernel thinks -+ * struct kernel_stat should look like... It turns out each arch has a -+ * different opinion on the subject... */ -+ -+struct kernel_stat { -+ unsigned short st_dev; -+ unsigned short __pad1; -+ unsigned long st_ino; -+ unsigned short st_mode; -+ unsigned short st_nlink; -+ unsigned short st_uid; -+ unsigned short st_gid; -+ unsigned short st_rdev; -+ unsigned short __pad2; -+ unsigned long st_size; -+ unsigned long st_blksize; -+ unsigned long st_blocks; -+ struct timespec st_atim; -+ struct timespec st_mtim; -+ struct timespec st_ctim; -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+struct kernel_stat64 { -+ unsigned char __pad0[6]; -+ unsigned short st_dev; -+ unsigned char __pad1[4]; -+#define _HAVE_STAT64___ST_INO -+ unsigned long __st_ino; -+ unsigned int st_mode; -+ unsigned int st_nlink; -+ unsigned long st_uid; -+ unsigned long st_gid; -+ unsigned char __pad2[6]; -+ unsigned short st_rdev; -+ unsigned char __pad3[4]; -+ long long st_size; -+ unsigned long st_blksize; -+ unsigned long st_blocks; /* Number 512-byte blocks allocated. */ -+ unsigned long __pad4; /* future possible st_blocks high bits */ -+ struct timespec st_atim; -+ struct timespec st_mtim; -+ struct timespec st_ctim; -+ unsigned long long st_ino; -+}; -+ -+#endif /* _BITS_STAT_STRUCT_H */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/kernel_types.h -@@ -0,0 +1,44 @@ -+/* Note that we use the exact same include guard #define names -+ * as asm/posix_types.h. This will avoid gratuitous conflicts -+ * with the posix_types.h kernel header, and will ensure that -+ * our private content, and not the kernel header, will win. -+ * -Erik -+ */ -+#ifndef __ARCH_UBICOM32_POSIX_TYPES_H -+#define __ARCH_UBICOM32_POSIX_TYPES_H -+ -+typedef unsigned long __kernel_dev_t; -+typedef unsigned long __kernel_ino_t; -+typedef unsigned short __kernel_mode_t; -+typedef unsigned short __kernel_nlink_t; -+typedef long __kernel_off_t; -+typedef int __kernel_pid_t; -+typedef unsigned short __kernel_ipc_pid_t; -+typedef unsigned short __kernel_uid_t; -+typedef unsigned short __kernel_gid_t; -+typedef unsigned int __kernel_size_t; -+typedef int __kernel_ssize_t; -+typedef int __kernel_ptrdiff_t; -+typedef long __kernel_time_t; -+typedef long __kernel_suseconds_t; -+typedef long __kernel_clock_t; -+typedef int __kernel_daddr_t; -+typedef char * __kernel_caddr_t; -+typedef unsigned short __kernel_uid16_t; -+typedef unsigned short __kernel_gid16_t; -+typedef unsigned int __kernel_uid32_t; -+typedef unsigned int __kernel_gid32_t; -+typedef unsigned short __kernel_old_uid_t; -+typedef unsigned short __kernel_old_gid_t; -+typedef unsigned short __kernel_old_dev_t; -+typedef long long __kernel_loff_t; -+ -+typedef struct { -+#ifdef __USE_ALL -+ int val[2]; -+#else -+ int __val[2]; -+#endif -+} __kernel_fsid_t; -+ -+#endif /* __ARCH_UBICOM32_POSIX_TYPES_H */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/mman.h -@@ -0,0 +1,103 @@ -+/* Definitions for POSIX memory map interface. Linux/m68k version. -+ Copyright (C) 1997, 2000, 2003, 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_MMAN_H -+# error "Never use directly; include instead." -+#endif -+ -+/* The following definitions basically come from the kernel headers. -+ But the kernel header is not namespace clean. */ -+ -+ -+/* Protections are chosen from these bits, OR'd together. The -+ implementation does not necessarily support PROT_EXEC or PROT_WRITE -+ without PROT_READ. The only guarantees are that no writing will be -+ allowed without PROT_WRITE and no access will be allowed for PROT_NONE. */ -+ -+#define PROT_READ 0x1 /* Page can be read. */ -+#define PROT_WRITE 0x2 /* Page can be written. */ -+#define PROT_EXEC 0x4 /* Page can be executed. */ -+#define PROT_NONE 0x0 /* Page can not be accessed. */ -+#define PROT_GROWSDOWN 0x01000000 /* Extend change to start of -+ growsdown vma (mprotect only). */ -+#define PROT_GROWSUP 0x02000000 /* Extend change to start of -+ growsup vma (mprotect only). */ -+ -+/* Sharing types (must choose one and only one of these). */ -+#define MAP_SHARED 0x01 /* Share changes. */ -+#define MAP_PRIVATE 0x02 /* Changes are private. */ -+#ifdef __USE_MISC -+# define MAP_TYPE 0x0f /* Mask for type of mapping. */ -+#endif -+ -+/* Other flags. */ -+#define MAP_FIXED 0x10 /* Interpret addr exactly. */ -+#ifdef __USE_MISC -+# define MAP_FILE 0 -+# define MAP_ANONYMOUS 0x20 /* Don't use a file. */ -+# define MAP_ANON MAP_ANONYMOUS -+#endif -+ -+/* These are Linux-specific. */ -+#ifdef __USE_MISC -+# define MAP_GROWSDOWN 0x0000100 /* Stack-like segment. */ -+# define MAP_DENYWRITE 0x0000800 /* ETXTBSY */ -+# define MAP_EXECUTABLE 0x0001000 /* Mark it as an executable. */ -+# define MAP_LOCKED 0x0002000 /* Lock the mapping. */ -+# define MAP_NORESERVE 0x0004000 /* Don't check for reservations. */ -+# define MAP_POPULATE 0x0008000 /* Populate (prefault) pagetables. */ -+# define MAP_NONBLOCK 0x0010000 /* Do not block on IO. */ -+# define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could be uninitialized. */ -+#endif -+ -+/* Flags to `msync'. */ -+#define MS_ASYNC 1 /* Sync memory asynchronously. */ -+#define MS_SYNC 4 /* Synchronous memory sync. */ -+#define MS_INVALIDATE 2 /* Invalidate the caches. */ -+ -+/* Flags for `mlockall'. */ -+#define MCL_CURRENT 1 /* Lock all currently mapped pages. */ -+#define MCL_FUTURE 2 /* Lock all additions to address -+ space. */ -+ -+/* Flags for `mremap'. */ -+#ifdef __USE_GNU -+# define MREMAP_MAYMOVE 1 -+# define MREMAP_FIXED 2 -+#endif -+ -+/* Advice to `madvise'. */ -+#ifdef __USE_BSD -+# define MADV_NORMAL 0 /* No further special treatment. */ -+# define MADV_RANDOM 1 /* Expect random page references. */ -+# define MADV_SEQUENTIAL 2 /* Expect sequential page references. */ -+# define MADV_WILLNEED 3 /* Will need these pages. */ -+# define MADV_DONTNEED 4 /* Don't need these pages. */ -+# define MADV_DONTFORK 10 /* Do not inherit across fork. */ -+# define MADV_DOFORK 11 /* Do inherit across fork. */ -+#endif -+ -+/* The POSIX people had to invent similar names for the same things. */ -+#ifdef __USE_XOPEN2K -+# define POSIX_MADV_NORMAL 0 /* No further special treatment. */ -+# define POSIX_MADV_RANDOM 1 /* Expect random page references. */ -+# define POSIX_MADV_SEQUENTIAL 2 /* Expect sequential page references. */ -+# define POSIX_MADV_WILLNEED 3 /* Will need these pages. */ -+# define POSIX_MADV_DONTNEED 4 /* Don't need these pages. */ -+#endif ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/setjmp.h -@@ -0,0 +1,52 @@ -+/* Define the machine-dependent type `jmp_buf'. Ubicom32 version. -+ Copyright (C) 1992,93,95,97,2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _BITS_SETJMP_H -+#define _BITS_SETJMP_H 1 -+ -+#if !defined _SETJMP_H && !defined _PTHREAD_H -+# error "Never include directly; use instead." -+#endif -+ -+#ifndef _ASM -+/* -+ * This is the structure where we are going to save D10-D13, A0, A1, A2, A5, A6 and SP(A7). -+ * A5 is the return address. Call to setjmp will save these. Call to longjmp will return -+ * Control to the address in A5. -+ */ -+typedef struct setjmp_save_struct { -+ unsigned long d10; /* D10 */ -+ unsigned long d11; /* D11 */ -+ unsigned long d12; /* D12 */ -+ unsigned long d13; /* D13 */ -+ unsigned long a1; /* A1 */ -+ unsigned long a2; /* A2 */ -+ unsigned long a5; /* A5 return address. */ -+ unsigned long a6; /* A6 */ -+ unsigned long sp; /* A7 stack pointer. */ -+} __jmp_buf[1]; -+ -+#endif -+ -+/* Test if longjmp to JMPBUF would unwind the frame -+ containing a local variable at ADDRESS. */ -+#define _JMPBUF_UNWINDS(jmpbuf, address) \ -+ ((void *) (address) < (void*)(jmpbuf)->sp) -+ -+#endif /* bits/setjmp.h */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/stackinfo.h -@@ -0,0 +1,28 @@ -+/* Copyright (C) 1999 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+/* This file contains a bit of information about the stack allocation -+ of the processor. */ -+ -+#ifndef _STACKINFO_H -+#define _STACKINFO_H 1 -+ -+/* On Ubicom32 the stack grows down. */ -+#define _STACK_GROWS_DOWN 1 -+ -+#endif /* stackinfo.h */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/syscalls.h -@@ -0,0 +1,81 @@ -+#ifndef _BITS_SYSCALLS_H -+#define _BITS_SYSCALLS_H -+#ifndef _SYSCALL_H -+# error "Never use directly; include instead." -+#endif -+ -+/* m68k headers does stupid stuff with __NR_iopl / __NR_vm86: -+ * #define __NR_iopl not supported -+ * #define __NR_vm86 not supported -+ */ -+#undef __NR_iopl -+#undef __NR_vm86 -+ -+#ifndef __ASSEMBLER__ -+ -+#include -+ -+/* Linux takes system call arguments in registers: -+ -+ syscall number %d8 -+ arg 1 %d0 -+ arg 2 %d1 -+ arg 3 %d2 -+ arg 4 %d3 -+ arg 5 %d4 -+ arg 6 %d5 -+*/ -+ -+#define __loadargs_0(name, dummy) \ -+ d8 = (long int)name -+ -+#define __loadargs_1(name, __arg1) \ -+ __loadargs_0(name, 0); \ -+ d0_retval = (long int) __arg1 -+ -+#define __loadargs_2(name, __arg1, __arg2) \ -+ __loadargs_1(name, __arg1); \ -+ d1 = (long int) __arg2 -+ -+#define __loadargs_3(name, __arg1, __arg2, __arg3) \ -+ __loadargs_2(name, __arg1, __arg2); \ -+ d2 = (long int) __arg3 -+ -+#define __loadargs_4(name, __arg1, __arg2, __arg3, __arg4) \ -+ __loadargs_3(name, __arg1, __arg2, __arg3); \ -+ d3 = (long int)__arg4 -+ -+#define __loadargs_5(name, __arg1, __arg2, __arg3, __arg4, __arg5) \ -+ __loadargs_4(name, __arg1, __arg2, __arg3, __arg4); \ -+ d4 = (long int)__arg5 -+ -+#define __loadargs_6(name, __arg1, __arg2, __arg3, __arg4, __arg5, __arg6) \ -+ __loadargs_5(name, __arg1, __arg2, __arg3, __arg4, __arg5); \ -+ d5 = (long int)__arg6 -+ -+#define INTERNAL_SYSCALL_NCS(name, err, nr, args...) \ -+({ \ -+ register long int d0_retval __asm__ ("d0"); \ -+ register long int d1 __asm__ ("d1"); \ -+ register long int d2 __asm__ ("d2"); \ -+ register long int d3 __asm__ ("d3"); \ -+ register long int d4 __asm__ ("d4"); \ -+ register long int d5 __asm__ ("d5"); \ -+ register long int d8 __asm__ ("d8"); \ -+ __loadargs_##nr (name, args); \ -+ __asm__ __volatile__ ( \ -+ " moveai a5, #%%hi(0x40400000)\n\t" \ -+ " calli a5, 16(a5)\n\t" \ -+ : "+r" (d0_retval), "+r" (d1), "+r" (d2), "+r" (d3), \ -+ "+r" (d4), "+r" (d5), "+r" (d8) : \ -+ : "cc", "memory", \ -+ "acc0_lo", "acc0_hi", "acc1_lo", "acc1_hi", \ -+ "source3", \ -+ "a0", "a3", "a4", "a5", \ -+ "d6", "d7", "d9", "d14", "d15" \ -+ ); \ -+ d0_retval; \ -+}) -+ -+#endif /* __ASSEMBLER__ */ -+#endif /* _BITS_SYSCALLS_H */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/uClibc_arch_features.h -@@ -0,0 +1,45 @@ -+/* -+ * Track misc arch-specific features that aren't config options -+ */ -+ -+#ifndef _BITS_UCLIBC_ARCH_FEATURES_H -+#define _BITS_UCLIBC_ARCH_FEATURES_H -+ -+/* instruction used when calling abort() to kill yourself */ -+/*#define __UCLIBC_ABORT_INSTRUCTION__ "asm instruction"*/ -+#undef __UCLIBC_ABORT_INSTRUCTION__ -+ -+/* can your target use syscall6() for mmap ? */ -+#undef __UCLIBC_MMAP_HAS_6_ARGS__ -+ -+/* does your target use syscall4() for truncate64 ? (32bit arches only) */ -+#undef __UCLIBC_TRUNCATE64_HAS_4_ARGS__ -+ -+/* does your target have a broken create_module() ? */ -+#undef __UCLIBC_BROKEN_CREATE_MODULE__ -+ -+/* does your target have to worry about older [gs]etrlimit() ? */ -+#undef __UCLIBC_HANDLE_OLDER_RLIMIT__ -+ -+/* does your target prefix all symbols with an _ ? */ -+#define __UCLIBC_NO_UNDERSCORES__ -+ -+/* does your target have an asm .set ? */ -+#define __UCLIBC_HAVE_ASM_SET_DIRECTIVE__ -+ -+/* define if target doesn't like .global */ -+#undef __UCLIBC_ASM_GLOBAL_DIRECTIVE__ -+ -+/* define if target supports .weak */ -+#define __UCLIBC_HAVE_ASM_WEAK_DIRECTIVE__ -+ -+/* define if target supports .weakext */ -+#undef __UCLIBC_HAVE_ASM_WEAKEXT_DIRECTIVE__ -+ -+/* needed probably only for ppc64 */ -+#undef __UCLIBC_HAVE_ASM_GLOBAL_DOT_NAME__ -+ -+/* define if target supports IEEE signed zero floats */ -+#define __UCLIBC_HAVE_SIGNED_ZERO__ -+ -+#endif /* _BITS_UCLIBC_ARCH_FEATURES_H */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/bits/wordsize.h -@@ -0,0 +1,19 @@ -+/* Copyright (C) 1999 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#define __WORDSIZE 32 ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/clone.S -@@ -0,0 +1,71 @@ -+#include -+ -+ .global __syscall_error -+ -+/* int _clone(int (*fn)(void *arg), void *child_stack, int flags, void *arg); */ -+ .text -+ .type clone,@function -+ .global clone -+clone: -+ /* Sanity check arguments. */ -+ sub.4 #0, #0, d0 /* Test if fn is zero. */ -+ jmpeq.f 1f /* arg bad */ -+ sub.4 #0, #0, d1 /* Test if child_stack is zero. */ -+ jmpeq.f 1f /* arg bad */ -+ -+ /* Set up child_stack frame.. arg and fn */ -+ move.4 a3, d1 -+ move.4 -4(a3)++, d3 /* push 'arg' to child stack */ -+ move.4 -4(a3)++, d0 /* push fn to child stack, this will become a5 -+ * on new child */ -+ move.4 d1, a3 -+ move.4 -4(sp)++, a5 /* push a5 to our stack */ -+ -+ /* -+ * The syscall clone is clone(int flags, void *child_stack) so we set -+ * that up now -+ */ -+ move.4 d0, d2 /* Move flags to d0 */ -+ -+ /* Do Clone syscall */ -+ movei d8, #__NR_clone -+ moveai a5, #%hi(0x40400000) -+ calli a5, 0x10(a5) -+ move.4 a5, (sp)4++ /* pop a5 from stack */ -+ -+ /* Clone Complete */ -+ cmpi d0, #0 /* Test if d0 is less than zero. If it is we -+ * return the error */ -+ jmplt.f 2f /* If return is less than we had an error */ -+ jmpeq.f 3f /* If return is 0 we are in the clone, jump to -+ * thread start */ -+ ret a5 /* d0 is pid */ -+ -+ /* Invalid Value */ -+1: movei d0, #-22 /* EINVAL */ -+ -+ /* Call syscall Error */ -+2: sub.4 d0, #0, d0 /* d0 = -d0 */ -+#if defined(__UBICOM32_FDPIC__) -+ call a3, __syscall_error -+#else -+ moveai a3, #%hi(__syscall_error) -+ calli a3, %lo(__syscall_error)(a3) -+#endif -+ /* Child Thread Start */ -+3: -+#if defined(__UBICOM32_FDPIC__) -+ /* a5 actually contains a function descriptor for fdpic */ -+ move.4 a0, 4(a5) /* set GOT for this function */ -+ move.4 a5, 0(a5) /* get address of entry point */ -+#endif -+ move.4 d0, (sp)4++ /* pop 'arg' to stack */ -+ calli a5, 0(a5) -+ movei d8, #__NR_exit -+ moveai a3, #%hi(0x40400000) -+ calli a3, 0x10(a3) -+ -+ .size clone, . - clone -+ .global __GI_clone -+ .hidden __GI_clone -+ .set __GI_clone,clone ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/crt1.S -@@ -0,0 +1,179 @@ -+/* Startup code compliant to the ELF m68k ABI. -+ Copyright (C) 1996, 1997, 1998, 2001, 2002 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ In addition to the permissions in the GNU Lesser General Public -+ License, the Free Software Foundation gives you unlimited -+ permission to link the compiled version of this file with other -+ programs, and to distribute those programs without any restriction -+ coming from the use of this file. (The GNU Lesser General Public -+ License restrictions do apply in other respects; for example, they -+ cover modification of the file, and distribution when not linked -+ into another program.) -+ -+ Note that people who make modified versions of this file are not -+ obligated to grant this special exception for their modified -+ versions; it is their choice whether to do so. The GNU Lesser -+ General Public License gives permission to release a modified -+ version without this exception; this exception also makes it -+ possible to release a modified version which carries forward this -+ exception. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#include -+ -+/* This is the canonical entry point, usually the first thing in the text -+ segment. The SVR4/m68k ABI says that when the entry point runs, -+ most registers' values are unspecified, except for: -+ -+ %a1 Contains a function pointer to be registered with `atexit'. -+ This is how the dynamic linker arranges to have DT_FINI -+ functions called for shared libraries that have been loaded -+ before this code runs. -+ -+ %sp The stack contains the arguments and environment: -+ 0(%sp) argc -+ 4(%sp) argv[0] -+ ... -+ (4*argc)(%sp) NULL -+ (4*(argc+1))(%sp) envp[0] -+ ... -+ NULL -+ -+ The uclinux conventions are different. %a1 is not defined on entry -+ and the stack is laid out as follows: -+ -+ 0(%sp) argc -+ 4(%sp) argv -+ 8(%sp) envp -+*/ -+ -+ -+ .text -+ .type main,@function -+ .type _init,%function -+ .type _fini,%function -+#ifndef __UCLIBC_CTOR_DTOR__ -+ .weak _init -+ .weak _fini -+#endif -+ .globl _start -+ .global __uClibc_main; -+ .type __uClibc_main,@function; -+ .type _start,@function -+_start: -+ -+#if defined(__UBICOM32_FDPIC__) && !defined(L_Scrt1) -+ /* P0 contains a pointer to the program's load map. */ -+ call a3, .Lcall; -+.Lcall: -+ move.4 d0, d1 ; load exec_map_addr -+ moveai a4, #%hi(.Lcall) -+ lea.1 d15, %lo(.Lcall)(a4) -+ sub.4 d15, a3, d15 ; difference between .Lcall and actual address of .Lcall -+ moveai a3, #%hi(__ROFIXUP_LIST__) -+ lea.1 d1, %lo(__ROFIXUP_LIST__)(a3) -+ moveai a3, #%hi(__ROFIXUP_END__) -+ lea.1 d2, %lo(__ROFIXUP_END__)(a3) -+ add.4 d1, d1, d15 -+ add.4 d2, d2, d15 -+ call a5, __self_reloc ; returns GOT in d0 -+ move.4 a0, d0 ; set GOT -+#endif -+ -+/* -+ all this is setup to make the following call. -+ -+ void __uClibc_main( -+ d0 - int (*main)(int, char **, char **), -+ d1 - int argc, (d1) -+ d2 - char **argv, -+ d3 - void (*app_init)(void), -+ d4 - void (*app_fini)(void), -+ d5 - void (*rtld_fini)(void), -+ d6 - void *stack_end -+ ); -+ */ -+ -+ /* -+ * Load pointer to main into d0 -+ */ -+#ifdef __UBICOM32_FDPIC__ -+ movei d0, #%got_funcdesc_lo(main) -+ move.4 d0, (a0, d0) -+#else -+ moveai a3, #%hi(main) -+ lea.1 d0, %lo(main)(a3) -+#endif -+ -+ /* -+ * Grab the environment stuff from stack and set up d1, d2 with it. -+ */ -+ move.4 d1, (sp) -+#ifdef __UBICOM32_FDPIC__ -+ /* For FDPIC the calling convention is different than flat */ -+ lea.1 d2, 4(sp) -+#else -+ move.4 d2, 4(sp) -+#endif -+ -+#ifdef __UCLIBC_CTOR_DTOR__ -+ /* -+ * Load pointer to _init into d3 -+ */ -+#ifdef __UBICOM32_FDPIC__ -+ movei d3, #%got_funcdesc_lo(_init) -+ move.4 d3, (a0, d3) -+#else -+ moveai a3, #%hi(_init) -+ lea.1 d3, %lo(_init)(a3) -+#endif -+ -+ /* -+ * Load pointer to _fini into d4 -+ */ -+#ifdef __UBICOM32_FDPIC__ -+ movei d4, #%got_funcdesc_lo(_fini) -+ move.4 d4, (a0, d4) -+#else -+ moveai a3, #%hi(_fini) -+ lea.1 d4, %lo(_fini)(a3) -+#endif -+ -+#else /* !__UCLIBC_CTOR_DTOR__ */ -+ move.4 d3, #0 ; _init -+ move.4 d4, #0 ; _fini -+#endif -+ -+#ifdef __UBICOM32_FDPIC__ -+ move.4 d5, a1 ; ldso _fini funcdesc (see dl-startup.h) -+#else -+ movei d5, #0 ; rtld_fini (not used) -+#endif -+ -+ move.4 d6, sp ; Stack End. -+ -+ /* Call the user's main function, and exit with its value. But -+ let the libc call main. */ -+#ifdef __UBICOM32_FDPIC__ -+ call a5, __uClibc_main -+#else -+ moveai a5, #%hi(__uClibc_main) -+ calli a5, %lo(__uClibc_main)(a5) -+#endif -+ -+ bkpt #-1 ; Crash if somehow `exit' does return. ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/crti.S -@@ -0,0 +1,54 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file just supplies function prologues for the .init and .fini -+ * sections. It is linked in before crtbegin.o. -+ */ -+ .file "crti.o" -+ .ident "GNU C crti.o" -+ -+ .section .init -+ .align 2 -+ .globl _init -+ .type _init, @function -+_init: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif -+ -+ .section .fini -+ .align 2 -+ .globl _fini -+ .type _fini, @function -+_fini: -+ move.4 -4(sp)++, a5 -+#ifdef __UBICOM32_FDPIC__ -+ move.4 -4(sp)++, a0 -+#endif ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/crtn.S -@@ -0,0 +1,47 @@ -+/* Specialized code needed to support construction and destruction of -+ file-scope objects in C++ and Java code, and to support exception handling. -+ Copyright (C) 1999 Free Software Foundation, Inc. -+ Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca). -+ -+This file is part of GCC. -+ -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. -+ -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. */ -+ -+/* -+ * This file supplies function epilogues for the .init and .fini sections. -+ * It is linked in after all other files. -+ */ -+ -+ .file "crtn.o" -+ .ident "GNU C crtn.o" -+ -+ .section .init -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ -+ -+ .section .fini -+#ifdef __UBICOM32_FDPIC__ -+ move.4 a0, (sp)4++ -+#endif -+ ret (sp)4++ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/crtreloc.c -@@ -0,0 +1,145 @@ -+/* Copyright (C) 2003, 2004 Free Software Foundation, Inc. -+ written by Alexandre Oliva -+This file is part of the GNU C Library. -+ -+The GNU C Library is free software; you can redistribute it and/or -+modify it under the terms of the GNU Lesser General Public License as -+published by the Free Software Foundation; either version 2.1 of the -+License, or (at your option) any later version. -+ -+In addition to the permissions in the GNU Lesser General Public -+License, the Free Software Foundation gives you unlimited -+permission to link the compiled version of this file with other -+programs, and to distribute those programs without any restriction -+coming from the use of this file. (The GNU Lesser General Public -+License restrictions do apply in other respects; for example, they -+cover modification of the file, and distribution when not linked -+into another program.) -+ -+The GNU C Library is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+Library General Public License for more details. -+ -+You should have received a copy of the GNU Lesser General Public -+License along with the GNU C Library; see the file COPYING.LIB. If -+not, write to the Free Software Foundation, Inc., 675 Mass Ave, -+Cambridge, MA 02139, USA. */ -+ -+#ifdef __UBICOM32_FDPIC__ -+ -+#include -+#include -+ -+/* This file is to be compiled into crt object files, to enable -+ executables to easily self-relocate. */ -+ -+union word { -+ char c[4]; -+ void *v; -+}; -+ -+/* Compute the runtime address of pointer in the range [p,e), and then -+ map the pointer pointed by it. */ -+static __always_inline void *** -+reloc_range_indirect (void ***p, void ***e, -+ const struct elf32_fdpic_loadmap *map) -+{ -+ while (p < e) -+ { -+ if (*p != (void **)-1) -+ { -+ void *ptr = __reloc_pointer (*p, map); -+ if (ptr != (void *)-1) -+ { -+ void *pt; -+ if ((long)ptr & 3) -+ { -+ unsigned char *c = ptr; -+ int i; -+ unsigned long v = 0; -+ for (i = 0; i < 4; i++) -+ v |= c[i] << 8 * i; -+ pt = (void *)v; -+ } -+ else -+ pt = *(void**)ptr; -+ pt = __reloc_pointer (pt, map); -+ if ((long)ptr & 3) -+ { -+ unsigned char *c = ptr; -+ int i; -+ unsigned long v = (unsigned long)pt; -+ for (i = 0; i < 4; i++, v >>= 8) -+ c[i] = v; -+ } -+ else -+ *(void**)ptr = pt; -+ } -+ } -+ p++; -+ } -+ return p; -+} -+ -+/* Call __reloc_range_indirect for the given range except for the last -+ entry, whose contents are only relocated. It's expected to hold -+ the GOT value. */ -+void* attribute_hidden -+__self_reloc (const struct elf32_fdpic_loadmap *map, -+ void ***p, void ***e) -+{ -+ p = reloc_range_indirect (p, e-1, map); -+ -+ if (p >= e) -+ return (void*)-1; -+ -+ return __reloc_pointer (*p, map); -+} -+ -+#if 0 -+/* These are other functions that might be useful, but that we don't -+ need. */ -+ -+/* Remap pointers in [p,e). */ -+static __always_inline void** -+reloc_range (void **p, void **e, -+ const struct elf32_fdpic_loadmap *map) -+{ -+ while (p < e) -+ { -+ *p = __reloc_pointer (*p, map); -+ p++; -+ } -+ return p; -+} -+ -+/* Remap p, adjust e by the same offset, then map the pointers in the -+ range determined by them. */ -+void attribute_hidden -+__reloc_range (const struct elf32_fdpic_loadmap *map, -+ void **p, void **e) -+{ -+ void **old = p; -+ -+ p = __reloc_pointer (p, map); -+ e += p - old; -+ reloc_range (p, e, map); -+} -+ -+/* Remap p, adjust e by the same offset, then map pointers referenced -+ by the (unadjusted) pointers in the range. Return the relocated -+ value of the last pointer in the range. */ -+void* attribute_hidden -+__reloc_range_indirect (const struct elf32_fdpic_loadmap *map, -+ void ***p, void ***e) -+{ -+ void ***old = p; -+ -+ p = __reloc_pointer (p, map); -+ e += p - old; -+ return reloc_range_indirect (p, e, map); -+} -+#endif -+ -+#endif /* __UBICOM32_FDPIC__ */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/setjmp.S -@@ -0,0 +1,72 @@ -+/* Setjmp for Ubicom32 */ -+ .text -+ .global _setjmp -+ .type _setjmp,@function -+_setjmp: -+ movea a3, d0 ; A3 now holds the jmp buf that was passed in. -+ move.4 (a3)4++, d10 -+ move.4 (a3)4++, d11 -+ move.4 (a3)4++, d12 -+ move.4 (a3)4++, d13 -+ move.4 (a3)4++, a1 -+ move.4 (a3)4++, a2 -+ move.4 (a3)4++, a5 -+ move.4 (a3)4++, a6 -+ move.4 (a3)4++, a7 -+ move.4 d0, #0 -+ -+ calli a5, 0(a5) -+ .size _setjmp, . - _setjmp -+ -+/* -+ * __sigsetjmp for Ubicom32 -+ * d0 holds sigjmp_buf and d1 holds the savemask. We will save the frame and then just call __sigjmp_save to do the mask save. -+ */ -+ .global __sigsetjmp -+ .type __sigsetjmp,@function -+__sigsetjmp: -+ movea a3, d0 ; A3 now holds the jmp buf that was passed in. -+ move.4 (a3)4++, d10 -+ move.4 (a3)4++, d11 -+ move.4 (a3)4++, d12 -+ move.4 (a3)4++, d13 -+ move.4 (a3)4++, a1 -+ move.4 (a3)4++, a2 -+ move.4 (a3)4++, a5 -+ move.4 (a3)4++, a6 -+ move.4 (a3)4++, a7 -+ -+ ;; The frame has been saved. Call _sigjmp_save to get sigmask saved. a5 still has the return address and it will go back to that. -+#if defined(__UBICOM32_FDPIC__) -+ call a3, __sigjmp_save -+#else -+ moveai a3, #%hi(__sigjmp_save) -+ calli a3, %lo(__sigjmp_save)(a3) -+#endif -+ .size __sigjmp_save, . - __sigjmp_save -+ -+ .global __longjmp -+ .type __longjmp,@function -+__longjmp: -+ movea a3, d0 ; A3 now holds the jmp buf that was passed in. -+ move.4 d10, (a3)4++ -+ move.4 d11, (a3)4++ -+ move.4 d12, (a3)4++ -+ move.4 d13, (a3)4++ -+ move.4 a1 , (a3)4++ -+ move.4 a2 , (a3)4++ -+ move.4 a5 , (a3)4++ -+ move.4 a6 , (a3)4++ -+ move.4 a7 , (a3)4++ -+ -+ sub.4 #0, #0, d1 ; Test if d1 is zero. If it is we have to return 1 other wise return content of d1 -+ jmpeq.t 2f -+ move.4 d0, d1 ; d1 is non zero load it into d0 -+ jmpt.t 3f -+ -+2: move.4 d0, #1 -+3: calli a5, 0(a5) -+ .size __longjmp, . - __longjmp -+ .global __GI___longjmp -+ .hidden __GI___longjmp -+ .set __GI___longjmp,__longjmp ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/sys/procfs.h -@@ -0,0 +1,122 @@ -+/* Copyright (C) 1996, 1997, 1999, 2000 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_PROCFS_H -+#define _SYS_PROCFS_H 1 -+ -+/* This is somehow modelled after the file of the same name on SysVr4 -+ systems. It provides a definition of the core file format for ELF -+ used on Linux. */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+__BEGIN_DECLS -+ -+#define ELF_NGREG 38 -+ -+typedef struct -+ { -+ union -+ { -+ unsigned long pr_regs[32]; -+ double pr_dregs[16]; -+ } pr_fr; -+ unsigned long __unused; -+ unsigned long pr_fsr; -+ unsigned char pr_qcnt; -+ unsigned char pr_q_entrysize; -+ unsigned char pr_en; -+ unsigned int pr_q[64]; -+ } elf_fpregset_t; -+ -+typedef unsigned long elf_greg_t; -+typedef elf_greg_t elf_gregset_t[ELF_NGREG]; -+ -+struct elf_siginfo -+ { -+ int si_signo; /* Signal number. */ -+ int si_code; /* Extra code. */ -+ int si_errno; /* Errno. */ -+ }; -+ -+/* Definitions to generate Intel SVR4-like core files. These mostly -+ have the same names as the SVR4 types with "elf_" tacked on the -+ front to prevent clashes with linux definitions, and the typedef -+ forms have been avoided. This is mostly like the SVR4 structure, -+ but more Linuxy, with things that Linux does not support and which -+ gdb doesn't really use excluded. Fields present but not used are -+ marked with "XXX". */ -+struct elf_prstatus -+ { -+ struct elf_siginfo pr_info; /* Info associated with signal. */ -+ short int pr_cursig; /* Current signal. */ -+ unsigned long int pr_sigpend; /* Set of pending signals. */ -+ unsigned long int pr_sighold; /* Set of held signals. */ -+ __pid_t pr_pid; -+ __pid_t pr_ppid; -+ __pid_t pr_pgrp; -+ __pid_t pr_sid; -+ struct timeval pr_utime; /* User time. */ -+ struct timeval pr_stime; /* System time. */ -+ struct timeval pr_cutime; /* Cumulative user time. */ -+ struct timeval pr_cstime; /* Cumulative system time. */ -+ elf_gregset_t pr_reg; /* GP registers. */ -+ int pr_fpvalid; /* True if math copro being used. */ -+ }; -+ -+ -+#define ELF_PRARGSZ (80) /* Number of chars for args */ -+ -+struct elf_prpsinfo -+ { -+ char pr_state; /* Numeric process state. */ -+ char pr_sname; /* Char for pr_state. */ -+ char pr_zomb; /* Zombie. */ -+ char pr_nice; /* Nice val. */ -+ unsigned long int pr_flag; /* Flags. */ -+ unsigned short int pr_uid; -+ unsigned short int pr_gid; -+ int pr_pid, pr_ppid, pr_pgrp, pr_sid; -+ /* Lots missing */ -+ char pr_fname[16]; /* Filename of executable. */ -+ char pr_psargs[ELF_PRARGSZ]; /* Initial part of arg list. */ -+ }; -+ -+/* Addresses. */ -+typedef void *psaddr_t; -+ -+/* Register sets. Linux has different names. */ -+typedef elf_gregset_t prgregset_t; -+typedef elf_fpregset_t prfpregset_t; -+ -+/* We don't have any differences between processes and threads, -+ therefore have only one PID type. */ -+typedef __pid_t lwpid_t; -+ -+ -+typedef struct elf_prstatus prstatus_t; -+typedef struct elf_prpsinfo prpsinfo_t; -+ -+__END_DECLS -+ -+#endif /* sys/procfs.h */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/sys/ucontext.h -@@ -0,0 +1,104 @@ -+/* Copyright (C) 1998, 1999 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_UCONTEXT_H -+#define _SYS_UCONTEXT_H 1 -+ -+#include -+#include -+/* -+ * Location of the users' stored registers relative to R0. -+ * Usage is as an index into a gregset_t array or as u.u_ar0[XX]. -+ */ -+#define REG_PSR (0) -+#define REG_PC (1) -+#define REG_SPARE (2) -+#define REG_WVALID (3) -+#define REG_G1 (4) -+#define REG_G2 (5) -+#define REG_G3 (6) -+#define REG_G4 (7) -+#define REG_G5 (8) -+#define REG_G6 (9) -+#define REG_G7 (10) -+#define REG_O0 (11) -+#define REG_O1 (12) -+#define REG_O2 (13) -+#define REG_O3 (14) -+#define REG_O4 (15) -+#define REG_O5 (16) -+#define REG_O6 (17) -+#define REG_O7 (18) -+#define REG_GLOBALS (19) -+ -+/* -+ * A gregset_t is defined as an array type for compatibility with the reference -+ * source. This is important due to differences in the way the C language -+ * treats arrays and structures as parameters. -+ * -+ * Note that NGREG is really (sizeof (struct regs) / sizeof (greg_t)), -+ * but that the ABI defines it absolutely to be 21 (resp. 19). -+ */ -+ -+#define NGREG 20 -+typedef int greg_t; -+ -+typedef greg_t gregset_t[NGREG]; -+ -+/* -+ * The following structures define how a register window can appear on the -+ * stack. This structure is available (when required) through the `gwins' -+ * field of an mcontext (nested within ucontext). NIOS_MAXWINDOW is the -+ * maximum number of outstanding register windows defined in the NIOS -+ * architecture (*not* implementation). -+ */ -+#define NIOS_MAXREGWINDOW 31 /* max windows in NIOS arch. */ -+struct rwindow -+ { -+ greg_t rw_local[8]; /* locals */ -+ greg_t rw_in[8]; /* ins */ -+ }; -+ -+#define rw_fp rw_in[6] /* frame pointer */ -+#define rw_rtn rw_in[7] /* return address */ -+ -+typedef struct gwindows -+ { -+ int wbcnt; -+ int *spbuf[NIOS_MAXREGWINDOW]; -+ struct rwindow wbuf[NIOS_MAXREGWINDOW]; -+ } gwindows_t; -+ -+typedef struct -+ { -+ gregset_t gregs; /* general register set */ -+ gwindows_t *gwins; /* POSSIBLE pointer to register windows */ -+ } mcontext_t; -+ -+ -+/* Userlevel context. */ -+typedef struct ucontext -+ { -+ unsigned long uc_flags; -+ struct ucontext *uc_link; -+ __sigset_t uc_sigmask; -+ stack_t uc_stack; -+ mcontext_t uc_mcontext; -+ } ucontext_t; -+ -+#endif /* sys/ucontext.h */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/syscall.c -@@ -0,0 +1,32 @@ -+/* vi: set sw=4 ts=4: */ -+/* syscall for ubicom32/uClibc -+ * -+ * Copyright (C) 2008 by Ubicom Inc. -+ * Copyright (C) 2002 by Erik Andersen -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU Library General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU Library General Public License -+ * along with this program; if not, write to the Free Software Foundation, -+ * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+ -+extern long syscall(long sysnum, long a, long b, long c, long d, long e, long f); -+long syscall(long sysnum, long a, long b, long c, long d, long e, long f) -+{ -+ int __NR_syscall_number = sysnum; -+ return (long) INLINE_SYSCALL(syscall_number, 6, a, b, c, d, e, f); -+} ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/vfork.S -@@ -0,0 +1,35 @@ -+#include -+ -+ .text -+ .type vfork,@function -+ .global vfork -+vfork: -+ move.4 -4(sp)++, a5 ; Save return address on the stack. -+ movei d8, #__NR_vfork -+ moveai a3, #%hi(0x40400000) -+ calli a5, 0x10(a3) -+ -+ /* -+ * You get here only if the syscall bombed. If things had worked out the -+ * parent and child would have both returned to the instruction after -+ * the vfork call. -+ */ -+ move.4 a5, (sp)4++ ; Pop the return address off the stack. -+ movei d1, #-125 -+ sub.4 #0, d0, d1 -+ jmplt.t 1f -+ -+ ;; We have an error. -+ sub.4 d0, #0, d0 ; d0 = -res. Call __set_errno with that. -+#if defined(__UBICOM32_FDPIC__) -+ call a3, __syscall_error -+#else -+ moveai a3, #%hi(__syscall_error) -+ calli a3, %lo(__syscall_error)(a3) ; __syscall_error will return -1 and not come back here. -+#endif -+1: -+ calli a5, 0(a5) -+ .size vfork, . - vfork -+ .global __GI_vfork -+ .hidden __GI_vfork -+ .set __GI_vfork,vfork ---- a/libpthread/linuxthreads.old/pthread.c -+++ b/libpthread/linuxthreads.old/pthread.c -@@ -391,6 +391,10 @@ void __pthread_initialize_minimal(void) - #endif - - __libc_multiple_threads_ptr = __libc_pthread_init (ptr_pthread_functions); -+#ifndef __ARCH_USE_MMU__ -+ __pthread_initial_thread_tos = -+ (char *)(((long)CURRENT_STACK_FRAME + getpagesize()) & ~(getpagesize() - 1)); -+#endif /* __ARCH_USE_MMU__ */ - } - - -@@ -467,7 +471,8 @@ static void pthread_initialize(void) - * for a few more details. - */ - __pthread_initial_thread_mid = CURRENT_STACK_FRAME; -- __pthread_initial_thread_tos = (char *) -1; -+ if (__pthread_initial_thread_tos == NULL) -+ __pthread_initial_thread_tos = (char *) -1; - __pthread_initial_thread_bos = (char *) 1; /* set it non-zero so we know we have been here */ - PDEBUG("initial thread stack bounds: bos=%p, tos=%p\n", - __pthread_initial_thread_bos, __pthread_initial_thread_tos); ---- /dev/null -+++ b/libpthread/linuxthreads.old/sysdeps/ubicom32/pt-machine.h -@@ -0,0 +1,68 @@ -+/* Machine-dependent pthreads configuration and inline functions. -+ -+ Copyright (C) 1996, 1997, 1998, 2000, 2002, 2003, 2004 -+ Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ Contributed by Ralf Baechle . -+ Based on the Alpha version by Richard Henderson . -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public License as -+ published by the Free Software Foundation; either version 2.1 of the -+ License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; see the file COPYING.LIB. If -+ not, write to the Free Software Foundation, Inc., -+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+#ifndef _PT_MACHINE_H -+#define _PT_MACHINE_H 1 -+ -+#include -+ -+/* -+ * XXX try to make this inline -+ */ -+extern long int testandset (int *spinlock); -+ -+#ifndef PT_EI -+#define PT_EI -+#else -+/* Spinlock implementation; required. */ -+ -+/* -+ * testandset() is the basis for the pthread spin lock. -+ * -+ * This implementation only requires that we 'set' the state of *spinlock. As -+ * bset is allows us to atomically 'testandset' a single bit define our 'set' is -+ * such that we will set bit 0 (ignoring all other bits, which should also be -+ * zero). -+ * Return value of 1 implies that the bit was already set and is still -+ * set. -+ * Return value of 0 implies that the bit was not previously set but it -+ * now is. -+ */ -+long int -+testandset (int *spinlock) -+{ -+ int ret; -+ __asm__ volatile ( -+ " move.4 %0, #0 \n\t" /* Assume that the bit is not currently set */ -+ " bset %1, %1, #0 \n\t" /* Attempt to 'set' bit 0 */ -+ " jmpeq.t 1f \n\t" -+ " move.4 %0, #1 \n\t" /* Bit was already set, so return 1 */ -+ " 1: \n\t" -+ : "=r"(ret), "+U4"(*spinlock) -+ : -+ : "memory", "cc" -+ ); -+ return ret; -+} -+#endif -+#endif /* pt-machine.h */ ---- /dev/null -+++ b/libpthread/linuxthreads.old/sysdeps/ubicom32/tls.h -@@ -0,0 +1,26 @@ -+/* Definitions for thread-local data handling. linuxthreads/MIPS version. -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _TLS_H -+#define _TLS_H -+#ifdef HAVE_TLS_SUPPORT -+#warning no tls support -+#undef USE_TLS -+#endif -+#endif /* tls.h */ ---- /dev/null -+++ b/libc/sysdeps/linux/ubicom32/sys/user.h -@@ -0,0 +1,40 @@ -+/* Copyright (C) 1998 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _SYS_USER_H -+#define _SYS_USER_H 1 -+ -+#include -+ -+#include -+ -+struct user { -+ struct pt_regs regs; /* entire machine state */ -+ size_t u_tsize; /* text size (pages) */ -+ size_t u_dsize; /* data size (pages) */ -+ size_t u_ssize; /* stack size (pages) */ -+ unsigned long start_code; /* text starting address */ -+ unsigned long start_data; /* data starting address */ -+ unsigned long start_stack; /* stack starting address */ -+ long int signal; /* signal causing core dump */ -+ struct regs * u_ar0; /* help gdb find registers */ -+ unsigned long magic; /* identifies a core file */ -+ char u_comm[32]; /* user command name */ -+}; -+ -+#endif /* _SYS_USER_H */ diff --git a/toolchain/uClibc/patches-0.9.33.2/601-ubicom32_uClibc_fixes.patch b/toolchain/uClibc/patches-0.9.33.2/601-ubicom32_uClibc_fixes.patch deleted file mode 100644 index d2bfdc72b4..0000000000 --- a/toolchain/uClibc/patches-0.9.33.2/601-ubicom32_uClibc_fixes.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/ldso/include/dl-elf.h -+++ b/ldso/include/dl-elf.h -@@ -45,6 +45,10 @@ extern int _dl_linux_resolve(void); - extern int _dl_fixup(struct dyn_elf *rpnt, struct r_scope_elem *scope, int flag); - extern void _dl_protect_relro (struct elf_resolve *l); - -+#ifndef DL_LOADADDR_ISSET(_loadaddr) -+#define DL_LOADADDR_ISSET(_loadaddr) ((_loadaddr) != 0) -+#endif -+ - /* - * Bitsize related settings for things ElfW() - * does not handle already -@@ -206,7 +210,7 @@ unsigned int __dl_parse_dynamic_info(Elf - we'd have to walk all the loadsegs to find out if it was - actually unnecessary, so skip this optimization. */ - #if !defined __FDPIC__ && !defined __DSBT__ -- if (load_off != 0) -+ if (DL_LOADADDR_ISSET(load_off)) - #endif - { - ADJUST_DYN_INFO(DT_HASH, load_off); ---- a/ldso/ldso/ubicom32/dl-sysdep.h -+++ b/ldso/ldso/ubicom32/dl-sysdep.h -@@ -101,6 +101,7 @@ do { \ - } while (0) - - #define DL_LOADADDR_TYPE struct elf32_fdpic_loadaddr -+#define DL_LOADADDR_ISSET(_loadaddr) ((_loadaddr).map != NULL) - - #define DL_RELOC_ADDR(LOADADDR, ADDR) \ - ((ElfW(Addr))__reloc_pointer ((void*)(ADDR), (LOADADDR).map))