From: Bjorn Helgaas Date: Wed, 31 Jan 2018 16:10:32 +0000 (-0600) Subject: Merge branch 'pci/misc' into next X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=412ee7cd3dc581a37b7d15a5147a556e45445be1;p=openwrt%2Fstaging%2Fblogic.git Merge branch 'pci/misc' into next * pci/misc: PCI: Add dummy pci_irqd_intx_xlate() for CONFIG_PCI=n build PCI: Add wrappers for dev_printk() PCI: Remove unnecessary messages for memory allocation failures PCI: Add #defines for Completion Timeout Disable feature hinic: Replace PCI pool old API net: e100: Replace PCI pool old API block: DAC960: Replace PCI pool old API MAINTAINERS: Include more PCI files PCI: Remove unneeded kallsyms include powerpc/pci: Unroll two pass loop when scanning bridges powerpc/pci: Use for_each_pci_bridge() helper --- 412ee7cd3dc581a37b7d15a5147a556e45445be1 diff --cc drivers/pci/quirks.c index 24e9a148e734,e5cccc64940c..78047dc89213 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@@ -2699,10 -2696,9 +2696,10 @@@ static void __nv_msi_ht_cap_quirk(struc * HT MSI mapping should be disabled on devices that are below * a non-Hypertransport host bridge. Locate the host bridge... */ - host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); + host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, + PCI_DEVFN(0, 0)); if (host_bridge == NULL) { - dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); + pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); return; } diff --cc include/uapi/linux/pci_regs.h index c8586db4fb07,9dc67643fc18..0c79eac5e9b8 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@@ -622,11 -622,10 +622,12 @@@ * safely. */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ + #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */ #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ -#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */ +#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ +#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ +#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */