From: Markus Stockhausen <markus.stockhausen@gmx.de>
Date: Sun, 18 Sep 2022 18:30:39 +0000 (+0200)
Subject: realtek: use upstream recommendation for secondary CPU start
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=3f41360eb70c775764408b6dd353d83fa6cab943;p=openwrt%2Fstaging%2Fxback.git

realtek: use upstream recommendation for secondary CPU start

Currently we fix interrupts/timers for the secondary CPU by patching
vsmp_init_secondary(). Get a little bit more generic and use the
upstream recommended way instead. Additionally avoid a check around
register_cps_smp_ops() because it does that itself.

See https://lkml.org/lkml/2022/9/12/522

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
---

diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c
index ad8c2d75f2..ae768f9338 100644
--- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c
+++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c
@@ -29,6 +29,28 @@ extern const char __appended_dtb;
 struct rtl83xx_soc_info soc_info;
 const void *fdt;
 
+#ifdef CONFIG_MIPS_MT_SMP
+extern const struct plat_smp_ops vsmp_smp_ops;
+
+static void rtl_init_secondary(void)
+{
+/*
+ * MIPS timer interrupt might fire like crazy if not used or initialized
+ * properly. Silence it by setting the maximum possible interval.
+ */
+	write_c0_compare(0);
+/*
+ * Enable all CPU interrupts, as everything is managed by the external
+ * controller. TODO: Standard vsmp_init_secondary() has special treatment for
+ * Malta if external GIC is available. Maybe we need this too.
+ */
+	if (mips_gic_present())
+		pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__);
+	else
+		set_c0_status(ST0_IM);
+}
+#endif
+
 const char *get_system_type(void)
 {
 	return soc_info.name;
@@ -193,15 +215,19 @@ void __init prom_init(void)
 
 	prom_init_cmdline();
 
-#ifdef  CONFIG_MIPS_CPS
-	if (!register_cps_smp_ops()) {
+	if (!register_cps_smp_ops())
 		return;
-	}
-#endif
+
 #ifdef CONFIG_MIPS_MT_SMP
-	if (!register_vsmp_smp_ops()) {
+	if (cpu_has_mipsmt) {
+		struct plat_smp_ops rtl_smp_ops;
+
+		rtl_smp_ops = vsmp_smp_ops;
+		rtl_smp_ops.init_secondary = rtl_init_secondary;
+		register_smp_ops(&rtl_smp_ops);
 		return;
 	}
 #endif
+
 	register_up_smp_ops();
 }
diff --git a/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch
index 6a0038d86b..2b9102633e 100644
--- a/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch
+++ b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch
@@ -31,24 +31,3 @@
  #ifdef CONFIG_CEVT_R4K
  	return r4k_clockevent_init();
  #else
---- a/arch/mips/kernel/smp-mt.c
-+++ b/arch/mips/kernel/smp-mt.c
-@@ -108,12 +108,18 @@ static void __init smvp_tc_init(unsigned
- static void vsmp_init_secondary(void)
- {
- 	/* This is Malta specific: IPI,performance and timer interrupts */
-+
-+	/* RTL9300 Clear internal timer interrupt */
-+	write_c0_compare(0);
-+
- 	if (mips_gic_present())
- 		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
- 					 STATUSF_IP4 | STATUSF_IP5 |
- 					 STATUSF_IP6 | STATUSF_IP7);
- 	else
- 		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
-+					 STATUSF_IP2 | STATUSF_IP3 |
-+					 STATUSF_IP4 | STATUSF_IP5 |
- 					 STATUSF_IP6 | STATUSF_IP7);
- }
-