From: Florian Fainelli <florian@openwrt.org>
Date: Fri, 19 Dec 2008 17:05:09 +0000 (+0000)
Subject: add experimental support for bcm6338
X-Git-Tag: reboot~24953
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=3dd67d64f49db4fd0e01dcd737e806620ea9cd9e;p=openwrt%2Fstaging%2Fchunkeey.git

add experimental support for bcm6338

SVN-Revision: 13691
---

diff --git a/target/linux/brcm63xx/config-2.6.27 b/target/linux/brcm63xx/config-2.6.27
index e9b6555303..4b7d1d87e9 100644
--- a/target/linux/brcm63xx/config-2.6.27
+++ b/target/linux/brcm63xx/config-2.6.27
@@ -14,6 +14,7 @@ CONFIG_AUDIT_GENERIC=y
 CONFIG_BASE_SMALL=0
 # CONFIG_BCM47XX is not set
 CONFIG_BCM63XX=y
+CONFIG_BCM63XX_CPU_6338=y
 CONFIG_BCM63XX_CPU_6348=y
 CONFIG_BCM63XX_CPU_6358=y
 CONFIG_BCM63XX_ENET=y
diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig b/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
index 8c192e747c..325f69afa5 100644
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
@@ -1,6 +1,13 @@
 menu "CPU support"
 	depends on BCM63XX
 
+config BCM63XX_CPU_6338
+	bool "support 6338 CPU"
+	select HW_HAS_PCI
+	select USB_ARCH_HAS_OHCI
+	select USB_OHCI_BIG_ENDIAN_DESC
+	select USB_OHCI_BIG_ENDIAN_MMIO
+
 config BCM63XX_CPU_6348
 	bool "support 6348 CPU"
 	select HW_HAS_PCI
diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
index 0a403dd07c..b7c041f60d 100644
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
@@ -25,6 +25,29 @@ static u16 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
+/*
+ * 6338 register sets and irqs
+ */
+
+static const unsigned long bcm96338_regs_base[] = {
+	[RSET_PERF]		= BCM_6338_PERF_BASE,
+	[RSET_TIMER]		= BCM_6338_TIMER_BASE,
+	[RSET_WDT]		= BCM_6338_WDT_BASE,
+	[RSET_UART0]		= BCM_6338_UART0_BASE,
+	[RSET_GPIO]		= BCM_6338_GPIO_BASE,
+	[RSET_SPI]		= BCM_6338_SPI_BASE,
+};
+
+static const int bcm96338_irqs[] = {
+	[IRQ_TIMER]		= BCM_6338_TIMER_IRQ,
+	[IRQ_UART0]		= BCM_6338_UART0_IRQ,
+	[IRQ_DSL]		= BCM_6338_DSL_IRQ,
+	[IRQ_ENET0]		= BCM_6338_ENET0_IRQ,
+	[IRQ_ENET_PHY]		= BCM_6338_ENET_PHY_IRQ,
+	[IRQ_ENET0_RXDMA]	= BCM_6338_ENET0_RXDMA_IRQ,
+	[IRQ_ENET0_TXDMA]	= BCM_6338_ENET0_TXDMA_IRQ,
+};
+
 /*
  * 6348 register sets and irqs
  */
@@ -137,6 +160,10 @@ static unsigned int detect_cpu_clock(void)
 {
 	unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 
+	if (BCMCPU_IS_6338()) {
+		return 240000000;
+	}
+
 	/*
 	 * frequency depends on PLL configuration:
 	 */
@@ -170,7 +197,7 @@ static unsigned int detect_memory_size(void)
 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 	u32 val;
 
-	if (BCMCPU_IS_6348()) {
+	if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 		val = bcm_sdram_readl(SDRAM_CFG_REG);
 		rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 		cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
@@ -204,6 +231,11 @@ void __init bcm63xx_cpu_init(void)
 	expected_cpu_id = 0;
 
 	switch (c->cputype) {
+	case CPU_BCM6338:
+		expected_cpu_id = BCM6338_CPU_ID;
+		bcm63xx_regs_base = bcm96338_regs_base;
+		bcm63xx_irqs = bcm96338_irqs;
+		break;
 	case CPU_BCM6348:
 		expected_cpu_id = BCM6348_CPU_ID;
 		bcm63xx_regs_base = bcm96348_regs_base;
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 4c8c3fd8b8..560da0b292 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */
+#define BCM6338_CPU_ID		0x6338
 #define BCM6348_CPU_ID		0x6348
 #define BCM6358_CPU_ID		0x6358
 
@@ -17,6 +18,19 @@ u16 __bcm63xx_get_cpu_id(void);
 u16 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 
+#ifdef CONFIG_BCM63XX_CPU_6338
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()	BCM6338_CPU_ID
+# endif
+# define BCMCPU_IS_6338()	(bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+#else
+# define BCMCPU_IS_6338()	(0)
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6348
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
@@ -87,6 +101,19 @@ enum bcm63xx_regs_set {
 #define RSET_EHCI_SIZE			256
 #define RSET_PCMCIA_SIZE		12
 
+/*
+ * 6338 register sets base address
+ */
+
+#define BCM_6338_PERF_BASE		(0xfffe0000)
+#define BCM_6338_TIMER_BASE		(0xfffe0000)
+#define BCM_6338_WDT_BASE		(0xfffe001c)
+#define BCM_6338_UART0_BASE		(0xfffe0300)
+#define BCM_6338_GPIO_BASE		(0xfffe0400)
+#define BCM_6338_SPI_BASE		(0xfffe0c00)
+#define BCM_6338_SAR_BASE		(0xfffe2000)
+#define BCM_6338_MEMC_BASE		(0xfffe3100)
+
 /*
  * 6348 register sets base address
  */
@@ -147,6 +174,24 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef BCMCPU_RUNTIME_DETECT
 	return bcm63xx_regs_base[set];
 #else
+#ifdef CONFIG_BCM63XX_CPU_6338
+	switch (set) {
+	case RSET_PERF:
+		return BCM_6338_PERF_BASE;
+	case RSET_TIMER:
+		return BCM_6338_TIMER_BASE;
+	case RSET_WDT:
+		return BCM_6338_WDT_BASE;
+	case RSET_UART0:
+		return BCM_6338_UART0_BASE;
+	case RSET_GPIO:
+		return BCM_6338_GPIO_BASE;
+	case RSET_SPI:
+		return BCM_6338_SPI_BASE;
+	case RSET_MEMC:
+		return BCM_6338_MEMC_BASE;
+	}
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6348
 	switch (set) {
 	case RSET_DSL_LMEM:
@@ -266,6 +311,27 @@ enum bcm63xx_irq {
 	IRQ_PCMCIA,
 };
 
+/*
+ * 6338 irqs
+ */
+#define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IR			(IRQ_INTERNAL_BASE + 1)
+#define BCM_6338_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
+#define BCM_6338_DG_IRQ			(IRQ_INTERNAL_BASE + 4)
+#define BCM_6338_DSL_IRQ		(IRQ_INTERNAL_BASE + 5)
+#define BCM_6338_ATM_IRQ		(IRQ_INTERNAL_BASE + 6)
+#define BCM_6338_USBS_IRQ		(IRQ_INTERNAL_BASE + 7)
+#define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
+#define BCM_6338_SDRAM_IRQ		(IRQ_INTERNAL_BASE + 10)
+#define BCM_6338_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 11)
+#define BCM_6338_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 12)
+#define BCM_6338_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13)
+#define BCM_6338_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 14)
+#define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
+#define BCM_6338_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
+#define BCM_6338_SDIO_IRQ		(IRQ_INTERNAL_BASE + 17)
+
 /*
  * 6348 irqs
  */
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
index d628601ab4..cdc44fc4cb 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,15 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG			0x4
 
+#define CKCTL_6338_ENET_EN		(1 << 4)
+#define CKCTL_6338_USBS_EN		(1 << 4)
+#define CKCTL_6338_SAR_EN		(1 << 5)
+#define CKCTL_6338_SPI_EN		(1 << 9)
+
+#define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ENET_EN |		\
+					CKCTL_6338_SAR_EN |		\
+					CKCTL_6338_SPI_EN)
+
 #define CKCTL_6348_ADSLPHY_EN		(1 << 0)
 #define CKCTL_6348_MPI_EN		(1 << 1)
 #define CKCTL_6348_SDRAM_EN		(1 << 2)
@@ -83,6 +92,25 @@
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG		0x28
 
+#define SOFTRESET_6338_SPI_MASK		(1 << 0)
+#define SOFTRESET_6338_ENET_MASK	(1 << 2)
+#define SOFTRESET_6338_USBH_MASK	(1 << 3)
+#define SOFTRESET_6338_USBS_MASK	(1 << 4)
+#define SOFTRESET_6338_ADSL_MASK	(1 << 5)
+#define SOFTRESET_6338_DMAMEM_MASK	(1 << 6) 
+#define SOFTRESET_6338_SAR_MASK		(1 << 7)
+#define SOFTRESET_6338_ACLC_MASK	(1 << 8)
+#define SOFTRESET_6338_ADSLMIPSPLL_MASK	(1 << 10)
+#define SOFTRESET_6338_ALL	 (SOFTRESET_6338_SPI_MASK |		\
+				  SOFTRESET_6338_ENET_MASK |		\
+				  SOFTRESET_6338_USBH_MASK |		\
+				  SOFTRESET_6338_USBS_MASK |		\
+				  SOFTRESET_6338_ADSL_MASK |		\
+				  SOFTRESET_6338_DMAMEM_MASK |		\
+				  SOFTRESET_6338_SAR_MASK |		\
+				  SOFTRESET_6338_ACLC_MASK |		\
+				  SOFTRESET_6338_ADSLMIPSPLL_MASK)
+
 #define SOFTRESET_6348_SPI_MASK		(1 << 0)
 #define SOFTRESET_6348_ENET_MASK	(1 << 2)
 #define SOFTRESET_6348_USBH_MASK	(1 << 3)
@@ -763,7 +791,7 @@
 #define SPI_INT_MASK			0x704
 #define SPI_INTR_CMD_DONE		0x01
 #define SPI_INTR_RX_OVERFLOW		0x02
-#define SPI_INTR_INTR_TX_UNDERFLOW	0x04
+#define SPI_INTR_TX_UNDERFLOW		0x04
 #define SPI_INTR_TX_OVERFLOW		0x08
 #define SPI_INTR_RX_UNDERFLOW		0x10
 #define SPI_INTR_CLEAR_ALL		0x1f