From: Kenneth Feng Date: Tue, 14 May 2019 09:08:36 +0000 (+0800) Subject: drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=3a3c51dd9008a5787dae6dd66a322df7e0f8909d;p=openwrt%2Fstaging%2Fblogic.git drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10 on navi10, by default the below four features are enabled. gfxclk deep sleep: enabled and verified fw dstate: enabled and then soc ulv is verified dcefclk deep sleep: enabled and verified. notice that on different boards, due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk deep sleep kicking in. Signed-off-by: Kenneth Feng Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index b7f5a94e3833..f49f2d6ded9a 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -326,7 +326,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) | FEATURE_MASK(FEATURE_MMHUB_PG_BIT) | FEATURE_MASK(FEATURE_ATHUB_PG_BIT) - | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) + | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) + | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) + | FEATURE_MASK(FEATURE_FW_DSTATE_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)