From: Daniel Golle <daniel@makrotopia.org>
Date: Sun, 27 Oct 2024 14:24:47 +0000 (+0000)
Subject: mediatek: mt7988: add DT entries for WED
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=388de64d9fe9919a577f826eab5947e67e5ef34a;p=openwrt%2Fstaging%2Fblocktrron.git

mediatek: mt7988: add DT entries for WED

Add memory regions and devices used for wireless offloading to the
device tree for MT7988.

This allows using WED on devices with MT7988 SoC and MT7995E, MT7996E or
MT7992E wireless controllers.

Devices with 4 GiB of RAM (or more) will still need ajustments to avoid
running out of swiotlb entries.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---

diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 6a15dcff3d..c894253fed 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -195,6 +195,32 @@
 			reg = <0 0x43000000 0 0x50000>;
 			no-map;
 		};
+
+		wmcpu_emi: wmcpu-reserved@47cc0000 {
+			reg = <0 0x47cc0000 0 0x00100000>;
+			no-map;
+		};
+
+		wo_emi0: wo-emi@4f600000 {
+			reg = <0 0x4f600000 0 0x40000>;
+			no-map;
+		};
+
+		wo_emi1: wo-emi@4f640000 {
+			reg = <0 0x4f640000 0 0x40000>;
+			no-map;
+		};
+
+		wo_emi2: wo-emi@4f680000 {
+			reg = <0 0x4f680000 0 0x40000>;
+			no-map;
+		};
+
+		wo_data: wo-data@4f700000 {
+			reg = <0 0x4f700000 0 0x800000>;
+			no-map;
+			shared = <1>;
+		};
 	};
 
 	soc {
@@ -1218,6 +1244,48 @@
 			#size-cells = <1>;
 		};
 
+		wed0: wed@15010000 {
+			compatible = "mediatek,mt7988-wed",
+				     "syscon";
+			reg = <0 0x15010000 0 0x2000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi0>, <&wo_data>;
+			memory-region-names = "wo-emi", "wo-data";
+			mediatek,wo-ccif = <&wo_ccif0>;
+			mediatek,wo-ilm = <&wo_ilm0>;
+			mediatek,wo-dlm = <&wo_dlm0>;
+			mediatek,wo-cpuboot = <&wo_cpuboot0>;
+		};
+
+		wed1: wed@15012000 {
+			compatible = "mediatek,mt7988-wed",
+				     "syscon";
+			reg = <0 0x15012000 0 0x2000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi1>, <&wo_data>;
+			memory-region-names = "wo-emi", "wo-data";
+			mediatek,wo-ccif = <&wo_ccif1>;
+			mediatek,wo-ilm = <&wo_ilm1>;
+			mediatek,wo-dlm = <&wo_dlm1>;
+			mediatek,wo-cpuboot = <&wo_cpuboot1>;
+		};
+
+		wed2: wed@15014000 {
+			compatible = "mediatek,mt7988-wed",
+				     "syscon";
+			reg = <0 0x15014000 0 0x2000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+			memory-region = <&wo_emi2>, <&wo_data>;
+			memory-region-names = "wo-emi", "wo-data";
+			mediatek,wo-ccif = <&wo_ccif2>;
+			mediatek,wo-ilm = <&wo_ilm2>;
+			mediatek,wo-dlm = <&wo_dlm2>;
+			mediatek,wo-cpuboot = <&wo_cpuboot2>;
+		};
+
 		switch: switch@15020000 {
 			compatible = "mediatek,mt7988-switch";
 			reg = <0 0x15020000 0 0x8000>;
@@ -1449,6 +1517,7 @@
 						 <&apmixedsys CLK_APMIXED_SGMPLL>;
 			mediatek,ethsys = <&ethsys>;
 			mediatek,infracfg = <&topmisc>;
+			mediatek,wed = <&wed0>, <&wed1>, <&wed2>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
@@ -1511,6 +1580,72 @@
 			};
 		};
 
+		wo_ccif0: syscon@151a5000 {
+			compatible = "mediatek,mt7988-wo-ccif", "syscon";
+			reg = <0 0x151a5000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_ccif1: syscon@152a5000 {
+			compatible = "mediatek,mt7988-wo-ccif", "syscon";
+			reg = <0 0x152a5000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_ccif2: syscon@153a5000 {
+			compatible = "mediatek,mt7988-wo-ccif", "syscon";
+			reg = <0 0x153a5000 0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wo_ilm0: syscon@151e0000 {
+			compatible = "mediatek,mt7988-wo-ilm", "syscon";
+			reg = <0 0x151e0000 0 0x8000>;
+		};
+
+		wo_ilm1: syscon@152e0000 {
+			compatible = "mediatek,mt7988-wo-ilm", "syscon";
+			reg = <0 0x152e0000 0 0x8000>;
+		};
+
+		wo_ilm2: syscon@153e0000 {
+			compatible = "mediatek,mt7988-wo-ilm", "syscon";
+			reg = <0 0x153e0000 0 0x8000>;
+		};
+
+		wo_dlm0: syscon@151e8000 {
+			compatible = "mediatek,mt7988-wo-dlm", "syscon";
+			reg = <0 0x151e8000 0 0x2000>;
+		};
+
+		wo_dlm1: syscon@152e8000 {
+			compatible = "mediatek,mt7988-wo-dlm", "syscon";
+			reg = <0 0x152e8000 0 0x2000>;
+		};
+
+		wo_dlm2: syscon@153e8000 {
+			compatible = "mediatek,mt7988-wo-dlm", "syscon";
+			reg = <0 0x153e8000 0 0x2000>;
+		};
+
+		wo_cpuboot0: syscon@15194000 {
+			compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+			reg = <0 0x15194000 0 0x1000>;
+		};
+
+		wo_cpuboot1: syscon@15294000 {
+			compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+			reg = <0 0x15294000 0 0x1000>;
+		};
+
+		wo_cpuboot2: syscon@15394000 {
+			compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+			reg = <0 0x15394000 0 0x1000>;
+		};
+
 		crypto: crypto@15600000 {
 			compatible = "inside-secure,safexcel-eip197b";
 			reg = <0 0x15600000 0 0x180000>;