From: Andrew Sharp <tigerand@gmail.com>
Date: Sat, 10 Feb 2007 01:35:28 +0000 (-0800)
Subject: [MIPS] Fix uniprocessor Sibyte builds.
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=366d6aef281a670b32a51d289fc07bf0e5e72d9a;p=openwrt%2Fstaging%2Fblogic.git

[MIPS] Fix uniprocessor Sibyte builds.

Signed-off-by: Andrew Sharp <tigerand@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 3a8afd47feaa..9ea460b16bda 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -259,6 +259,12 @@ static void sb1_flush_cache_data_page(unsigned long addr)
 		on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1);
 }
 #else
+
+static void local_sb1_flush_cache_data_page(unsigned long addr)
+{
+	__sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
+}
+
 void sb1_flush_cache_data_page(unsigned long)
 	__attribute__((alias("local_sb1_flush_cache_data_page")));
 #endif