From: Rafał Miłecki Date: Thu, 18 Nov 2021 15:34:55 +0000 (+0100) Subject: bcm53xx: use more upsteam DT patches from 5.16 / 5.17 X-Git-Tag: v21.02.6~116 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=35e470ad0a4080f44f1be888bf552441df0f5d50;p=openwrt%2Fopenwrt.git bcm53xx: use more upsteam DT patches from 5.16 / 5.17 Signed-off-by: Rafał Miłecki (cherry picked from commit 5901917b936d93c8facda6dfec4c5d77f666cbac) --- diff --git a/target/linux/bcm53xx/patches-5.4/038-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch b/target/linux/bcm53xx/patches-5.4/038-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch new file mode 100644 index 0000000000..fae0f02cdf --- /dev/null +++ b/target/linux/bcm53xx/patches-5.4/038-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch @@ -0,0 +1,104 @@ +From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 28 Oct 2021 09:03:44 +0200 +Subject: [PATCH] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +replaces the bit-banged i2c-gpio provided i2c functionality +with the hardware in the SoC. + +During review of the MR32, Florian Fainelli pointed out that the +SoC has a real I2C-controller. Furthermore, the connected pins +(SDA and SCL) would line up perfectly for use. Back then I couldn't +get it working though and I left it with i2c-gpio (which worked). + +Now we know the reason: the interrupt was incorrectly specified. +(Hence, this patch depends on Florian Fainelli's +"ARM: dts: BCM5301X: Fix I2C controller interrupt" patch). + +Cc: Florian Fainelli +Cc: Rafał Miłecki +Cc: Matthew Hagan +Signed-off-by: Christian Lamparter +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------ + 1 file changed, 28 insertions(+), 34 deletions(-) + +--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts ++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +@@ -84,40 +84,6 @@ + max-brightness = <255>; + }; + }; +- +- i2c { +- /* +- * The platform provided I2C does not budge. +- * This is a replacement until I can figure +- * out what are the missing bits... +- */ +- +- compatible = "i2c-gpio"; +- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; +- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; +- i2c-gpio,delay-us = <10>; /* close to 100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- current_sense: ina219@45 { +- compatible = "ti,ina219"; +- reg = <0x45>; +- shunt-resistor = <60000>; /* = 60 mOhms */ +- }; +- +- eeprom: eeprom@50 { +- compatible = "atmel,24c64"; +- reg = <0x50>; +- pagesize = <32>; +- read-only; +- #address-cells = <1>; +- #size-cells = <1>; +- +- mac_address: mac-address@66 { +- reg = <0x66 0x6>; +- }; +- }; +- }; + }; + + &uart0 { +@@ -228,3 +194,31 @@ + }; + }; + }; ++ ++&i2c0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinmux_i2c>; ++ ++ clock-frequency = <100000>; ++ ++ current_sense: ina219@45 { ++ compatible = "ti,ina219"; ++ reg = <0x45>; ++ shunt-resistor = <60000>; /* = 60 mOhms */ ++ }; ++ ++ eeprom: eeprom@50 { ++ compatible = "atmel,24c64"; ++ reg = <0x50>; ++ pagesize = <32>; ++ read-only; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ mac_address: mac-address@66 { ++ reg = <0x66 0x6>; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-5.4/038-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch b/target/linux/bcm53xx/patches-5.4/038-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch new file mode 100644 index 0000000000..0a817e8fd1 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.4/038-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch @@ -0,0 +1,60 @@ +From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 29 Oct 2021 18:05:23 +0200 +Subject: [PATCH] ARM: dts: BCM5301X: update CRU block description +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This describes CRU in a way matching documentation and fixes: + +arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' + From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml + +Signed-off-by: Rafał Miłecki +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -423,14 +423,14 @@ + #address-cells = <1>; + #size-cells = <1>; + +- cru@100 { +- compatible = "simple-bus"; ++ cru-bus@100 { ++ compatible = "brcm,ns-cru", "simple-mfd"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + +- lcpll0: lcpll0@100 { ++ lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; +@@ -439,7 +439,7 @@ + "sdio", "ddr_phy"; + }; + +- genpll: genpll@140 { ++ genpll: clock-controller@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; +@@ -450,6 +450,11 @@ + "sata1", "sata2"; + }; + ++ syscon@180 { ++ compatible = "brcm,cru-clkset", "syscon"; ++ reg = <0x180 0x4>; ++ }; ++ + pinctrl: pin-controller@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>;