From: Marek Vasut <marek.vasut@gmail.com>
Date: Wed, 4 Oct 2017 01:03:50 +0000 (+0200)
Subject: ARM: rmobile: Fixup ULCB CPLD support after PFC rework
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=3219c77e58a8b6d272a40d87b06361f1e7882712;p=project%2Fbcm63xx%2Fu-boot.git

ARM: rmobile: Fixup ULCB CPLD support after PFC rework

The ULCB CPLD support was not updated during the PFC table rework,
fix up the GPIO numbers until the CPLD support is rewritten to a
proper DM capable and DT probing driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c
index f9384b09ef..a1fecf18e5 100644
--- a/board/renesas/ulcb/cpld.c
+++ b/board/renesas/ulcb/cpld.c
@@ -12,10 +12,10 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
-#define SCLK			GPIO_GP_6_8
-#define SSTBZ			GPIO_GP_2_3
-#define MOSI			GPIO_GP_6_7
-#define MISO			GPIO_GP_6_10
+#define SCLK			(192 + 8)	/* GPIO6 8 */
+#define SSTBZ			(64 + 3)	/* GPIO2 3 */
+#define MOSI			(192 + 7)	/* GPIO6 8 */
+#define MISO			(192 + 10)	/* GPIO6 10 */
 
 #define CPLD_ADDR_MODE		0x00 /* RW */
 #define CPLD_ADDR_MUX		0x02 /* RW */