From: Vikram Kanigiri <vikram.kanigiri@arm.com>
Date: Mon, 24 Mar 2014 11:21:35 +0000 (+0000)
Subject: Fix build by correcting asm helper function usage in TSPD
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=31526cb013af98b2e4bec321f5c799ebf488c037;p=project%2Fbcm63xx%2Fatf.git

Fix build by correcting asm helper function usage in TSPD

This patch fixes a regression failure due to the use of functions by the
TSPD code which access system registers with partially qualified names.
These functions had been removed in an earlier patch. The relevant code
has been updated to access these registers with their fully qualified
names.

Fixes ARM-software/tf-issues#119

Change-Id: Ide1bc5036e1b8164a42f7b7fe86186ad860e0ef9
---

diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c
index 1bfe6967..f9ca6241 100644
--- a/services/spd/tspd/tspd_common.c
+++ b/services/spd/tspd/tspd_common.c
@@ -49,7 +49,7 @@ int32_t tspd_init_secure_context(uint64_t entrypoint,
 				uint64_t mpidr,
 				tsp_context *tsp_ctx)
 {
-	uint32_t scr = read_scr(), sctlr = read_sctlr();
+	uint32_t scr, sctlr;
 	el1_sys_regs *el1_state;
 	uint32_t spsr;
 
@@ -69,6 +69,7 @@ int32_t tspd_init_secure_context(uint64_t entrypoint,
 	memset(tsp_ctx, 0, sizeof(*tsp_ctx));
 
 	/* Set the right security state and register width for the SP */
+	scr = read_scr();
 	scr &= ~SCR_NS_BIT;
 	scr &= ~SCR_RW_BIT;
 	if (rw == TSP_AARCH64)
@@ -78,9 +79,10 @@ int32_t tspd_init_secure_context(uint64_t entrypoint,
 	el1_state = get_sysregs_ctx(&tsp_ctx->cpu_ctx);
 
 	/*
-	 * Program the sctlr to allow execution in S-EL1 with caches
-	 * and mmu off
+	 * Program the SCTLR_EL1 such that upon entry in S-EL1, caches and MMU are
+	 * disabled and exception endianess is set to be the same as EL3
 	 */
+	sctlr = read_sctlr_el3()
 	sctlr &= SCTLR_EE_BIT;
 	sctlr |= SCTLR_EL1_RES1;
 	write_ctx_reg(el1_state, CTX_SCTLR_EL1, sctlr);