From: Birger Koblitz Date: Fri, 31 Dec 2021 17:39:22 +0000 (+0100) Subject: realtek: Fix RTL839x TX CPU-Tag X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=2f51e567ff6704e9354a359410e41b619617b59f;p=openwrt%2Fstaging%2Fnoltari.git realtek: Fix RTL839x TX CPU-Tag Setting bits 20 and 23 in a u16 is obviously wrong. According to https://www.svanheule.net/realtek/cypress/cputag cpu_tag[2] starts at bit 48 in the cpu-tag structure, so bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in cpu_tag[2]. Signed-off-by: Birger Koblitz --- diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index 2021e53c39..fdc2227c19 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -126,8 +126,8 @@ static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio) h->cpu_tag[4] = BIT(dest_port) >> 16; h->cpu_tag[5] = BIT(dest_port) & 0xffff; } - h->cpu_tag[2] |= BIT(20); // Enable destination port mask use - h->cpu_tag[2] |= BIT(23); // Enable L2 Learning + h->cpu_tag[2] |= BIT(5); // Enable destination port mask use + h->cpu_tag[2] |= BIT(8); // Enable L2 Learning // Set internal priority and AS_PRIO if (prio >= 0) h->cpu_tag[1] |= prio | BIT(3);