From: Felix Fietkau Date: Sat, 27 Dec 2014 13:03:12 +0000 (+0000) Subject: oxnas: clk-oxnas: rework pllb enable function X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=2ef587a8fc61b4d6697f567e11023156946ffdf7;p=openwrt%2Fstaging%2Fjow.git oxnas: clk-oxnas: rework pllb enable function kernel lock debugging unveiled that we should not call of_reset_control_get inside a clock's enable operation (see below) move of_reset_control_* previously used in pllb_clk_enable to new pllb_clk_prepare and pllb_clk_unprepare functions. use a container to carry runtime information. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2742 lockdep_trace_alloc+0xb8/0xfc() DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.26 #6 [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x7c/0x94) [] (dump_stack) from [] (warn_slowpath_common+0x68/0x8c) [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) [] (warn_slowpath_fmt) from [] (lockdep_trace_alloc+0xb8/0xfc) [] (lockdep_trace_alloc) from [] (kmem_cache_alloc+0x1c/0xf8) [] (kmem_cache_alloc) from [] (of_reset_control_get+0xe8/0x12c) [] (of_reset_control_get) from [] (pllb_clk_enable+0x14/0xbc) [] (pllb_clk_enable) from [] (__clk_enable+0x54/0xa0) [] (__clk_enable) from [] (clk_enable+0x18/0x2c) [] (clk_enable) from [] (oxnas_pcie_probe+0x3b8/0x6a0) [] (oxnas_pcie_probe) from [] (platform_drv_probe+0x18/0x48) [] (platform_drv_probe) from [] (driver_probe_device+0xd8/0x24c) [] (driver_probe_device) from [] (__driver_attach+0x70/0x94) [] (__driver_attach) from [] (bus_for_each_dev+0x4c/0x98) [] (bus_for_each_dev) from [] (bus_add_driver+0xcc/0x1e8) [] (bus_add_driver) from [] (driver_register+0xa0/0xe8) [] (driver_register) from [] (platform_driver_probe+0x20/0xa4) [] (platform_driver_probe) from [] (do_one_initcall+0x90/0x140) [] (do_one_initcall) from [] (kernel_init_freeable+0x1e4/0x2c0) [] (kernel_init_freeable) from [] (kernel_init+0x8/0x104) [] (kernel_init) from [] (ret_from_fork+0x14/0x2c) ---[ end trace 5f17ed2f61e0683f ]--- Signed-off-by: Daniel Golle SVN-Revision: 43787 --- diff --git a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c index 8d80c4f2b8..00d0f7afe0 100644 --- a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c +++ b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c @@ -28,6 +28,14 @@ #define MHZ (1000 * 1000) +struct clk_oxnas_pllb { + struct clk_hw hw; + struct device_node *devnode; + struct reset_control *rstc; +}; + +#define to_clk_oxnas_pllb(_hw) container_of(_hw, struct clk_oxnas_pllb, hw) + static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -67,48 +75,72 @@ static struct clk_hw plla_hw = { .init = &clk_plla_init, }; -static struct device_node *node_pllb; +static int pllb_clk_is_prepared(struct clk_hw *hw) +{ + struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); + + return !!pllb->rstc; +} -int pllb_clk_enable(struct clk_hw *hw) +static int pllb_clk_prepare(struct clk_hw *hw) { - struct reset_control *rstc; + struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - rstc = of_reset_control_get(node_pllb, NULL); - if (IS_ERR(rstc)) - return PTR_ERR(rstc); + pllb->rstc = of_reset_control_get(pllb->devnode, NULL); + + return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0; +} + +static void pllb_clk_unprepare(struct clk_hw *hw) +{ + struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); + + BUG_ON(IS_ERR(pllb->rstc)); + + reset_control_put(pllb->rstc); + pllb->rstc = NULL; +} + +static int pllb_clk_enable(struct clk_hw *hw) +{ + struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); + + BUG_ON(IS_ERR(pllb->rstc)); /* put PLL into bypass */ oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); wmb(); udelay(10); - reset_control_assert(rstc); + reset_control_assert(pllb->rstc); udelay(10); /* set PLL B control information */ writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV), SEC_CTRL_PLLB_CTRL0); - reset_control_deassert(rstc); - reset_control_put(rstc); + reset_control_deassert(pllb->rstc); udelay(100); oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); return 0; } -void pllb_clk_disable(struct clk_hw *hw) +static void pllb_clk_disable(struct clk_hw *hw) { - struct reset_control *rstc; + struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); + + BUG_ON(IS_ERR(pllb->rstc)); /* put PLL into bypass */ oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); wmb(); udelay(10); - rstc = of_reset_control_get(node_pllb, NULL); - if (!IS_ERR(rstc)) - reset_control_assert(rstc); + reset_control_assert(pllb->rstc); } static struct clk_ops pllb_ops = { + .prepare = pllb_clk_prepare, + .unprepare = pllb_clk_unprepare, + .is_prepared = pllb_clk_is_prepared, .enable = pllb_clk_enable, .disable = pllb_clk_disable, }; @@ -120,9 +152,6 @@ static struct clk_init_data clk_pllb_init = { .num_parents = ARRAY_SIZE(pll_clk_parents), }; -static struct clk_hw pllb_hw = { - .init = &clk_pllb_init, -}; /* standard gate clock */ struct clk_std { @@ -252,10 +281,16 @@ CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); void __init oxnas_init_pllb(struct device_node *np) { struct clk *clk; + struct clk_oxnas_pllb *pllb; + + pllb = kmalloc(sizeof(*pllb), GFP_KERNEL); + BUG_ON(!pllb); - node_pllb = np; + pllb->hw.init = &clk_pllb_init; + pllb->devnode = np; + pllb->rstc = NULL; - clk = clk_register(NULL, &pllb_hw); + clk = clk_register(NULL, &pllb->hw); BUG_ON(IS_ERR(clk)); of_clk_add_provider(np, of_clk_src_simple_get, clk); }