From: Gabor Juhos Date: Mon, 10 Sep 2012 14:32:54 +0000 (+0000) Subject: ar71xx: fix QCA955X_EHCI_SIZE X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=2e0e38ad69c719afd06858daba2f46724c989e1f;p=openwrt%2Fstaging%2Fzorun.git ar71xx: fix QCA955X_EHCI_SIZE SVN-Revision: 33360 --- diff --git a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch index dd79296f60..5a27a9b714 100644 --- a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch +++ b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch @@ -86,7 +86,7 @@ Signed-off-by: Gabor Juhos +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 -+#define QCA955X_EHCI_SIZE 0x1000 ++#define QCA955X_EHCI_SIZE 0x200 + /* * DDR_CTRL block diff --git a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch index 5f88238267..efc354e9d9 100644 --- a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch +++ b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch @@ -67,4 +67,4 @@ Signed-off-by: Gabor Juhos +#define QCA955X_WMAC_SIZE 0x20000 #define QCA955X_EHCI0_BASE 0x1b000000 #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x1000 + #define QCA955X_EHCI_SIZE 0x200 diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch index 84d7166ca1..1d9ec4166a 100644 --- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch @@ -39,7 +39,7 @@ @@ -112,6 +122,8 @@ #define QCA955X_EHCI0_BASE 0x1b000000 #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x1000 + #define QCA955X_EHCI_SIZE 0x200 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40