From: Zoltan HERPAI Date: Sat, 25 May 2024 22:53:22 +0000 (+0200) Subject: d1: remove upstreamed patches and add new patchset X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=2e0b000e0e2695fdfcb2fee7cd56610696e9a076;p=openwrt%2Fstaging%2Fneocturne.git d1: remove upstreamed patches and add new patchset Remove patches that were upstreamed, and backport features from later kernels. Signed-off-by: Zoltan HERPAI --- diff --git a/target/linux/d1/patches-6.6/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch b/target/linux/d1/patches-6.6/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch deleted file mode 100644 index 6636cddde6..0000000000 --- a/target/linux/d1/patches-6.6/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 24 Jul 2022 17:12:07 -0500 -Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS - -RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is -already supported by the hci_uart/btrtl driver. Document the compatible. - -Series-to: Marcel Holtmann -Series-to: Johan Hedberg -Series-to: Luiz Augusto von Dentz -Series-to: David S. Miller -Series-to: Eric Dumazet -Series-to: Jakub Kicinski -Series-to: Paolo Abeni -Series-cc: linux-bluetooth@vger.kernel.org - -Signed-off-by: Samuel Holland ---- - Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml -+++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml -@@ -20,6 +20,7 @@ properties: - enum: - - realtek,rtl8723bs-bt - - realtek,rtl8723cs-bt -+ - realtek,rtl8723ds-bt - - realtek,rtl8822cs-bt - - device-wake-gpios: diff --git a/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch b/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch new file mode 100644 index 0000000000..4652b640fe --- /dev/null +++ b/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch @@ -0,0 +1,64 @@ +From c6fd43b8420f3864ad1cd64d818d9b9abc2cb711 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 28 Aug 2023 12:30:22 +0800 +Subject: [PATCH 01/14] riscv: dts: allwinner: d1: Add PMU event node + +D1 has several pmu events supported by opensbi. +These events can be used by perf for profiling. + +Signed-off-by: Inochi Amaoto +Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf +Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 +Acked-by: Conor Dooley +Acked-by: Jernej Skrabec +Reviewed-by: Guo Ren +--- + arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +@@ -72,4 +72,43 @@ + #interrupt-cells = <2>; + }; + }; ++ ++ pmu { ++ compatible = "riscv,pmu"; ++ riscv,event-to-mhpmcounters = ++ <0x00003 0x00003 0x00000008>, ++ <0x00004 0x00004 0x00000010>, ++ <0x00005 0x00005 0x00000200>, ++ <0x00006 0x00006 0x00000100>, ++ <0x10000 0x10000 0x00004000>, ++ <0x10001 0x10001 0x00008000>, ++ <0x10002 0x10002 0x00010000>, ++ <0x10003 0x10003 0x00020000>, ++ <0x10019 0x10019 0x00000040>, ++ <0x10021 0x10021 0x00000020>; ++ riscv,event-to-mhpmevent = ++ <0x00003 0x00000000 0x00000001>, ++ <0x00004 0x00000000 0x00000002>, ++ <0x00005 0x00000000 0x00000007>, ++ <0x00006 0x00000000 0x00000006>, ++ <0x10000 0x00000000 0x0000000c>, ++ <0x10001 0x00000000 0x0000000d>, ++ <0x10002 0x00000000 0x0000000e>, ++ <0x10003 0x00000000 0x0000000f>, ++ <0x10019 0x00000000 0x00000004>, ++ <0x10021 0x00000000 0x00000003>; ++ riscv,raw-event-to-mhpmcounters = ++ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, ++ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, ++ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, ++ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, ++ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, ++ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, ++ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, ++ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, ++ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, ++ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, ++ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, ++ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; ++ }; + }; diff --git a/target/linux/d1/patches-6.6/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch b/target/linux/d1/patches-6.6/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch deleted file mode 100644 index 22d4885e29..0000000000 --- a/target/linux/d1/patches-6.6/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 7 Aug 2022 20:08:49 -0500 -Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice - -ccu_mp_find_best() already computes a best_rate at the same time as the -best m and p factors. Return it so the caller does not need to duplicate -the division. - -Series-to: Chen-Yu Tsai -Series-to: Jernej Skrabec - -Signed-off-by: Samuel Holland ---- - drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - ---- a/drivers/clk/sunxi-ng/ccu_mp.c -+++ b/drivers/clk/sunxi-ng/ccu_mp.c -@@ -10,9 +10,9 @@ - #include "ccu_gate.h" - #include "ccu_mp.h" - --static void ccu_mp_find_best(unsigned long parent, unsigned long rate, -- unsigned int max_m, unsigned int max_p, -- unsigned int *m, unsigned int *p) -+static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, -+ unsigned int max_m, unsigned int max_p, -+ unsigned int *m, unsigned int *p) - { - unsigned long best_rate = 0; - unsigned int best_m = 0, best_p = 0; -@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo - - *m = best_m; - *p = best_p; -+ -+ return best_rate; - } - - static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw, -@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s - max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); - - if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) { -- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); -- rate = *parent_rate / p / m; -+ rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); - } else { - rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, - max_m, max_p); diff --git a/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch b/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch new file mode 100644 index 0000000000..db3ce3dcca --- /dev/null +++ b/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch @@ -0,0 +1,59 @@ +From 99942611816c117a01f16dbcab54908a49b378c3 Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:39 +0100 +Subject: [PATCH 02/14] riscv: dts: allwinner: Update opp table to allow CPU + frequency scaling + +Two OPPs are currently defined for the D1/D1s; one at 408MHz and +another at 1.08GHz. Switching between these can be done with the +"sun50i-cpufreq-nvmem" driver. This patch populates the opp table +appropriately, inspired by +https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi + +The supply voltages are PWM-controlled, but support for that IP +is still in the works. So stick to a target vdd-cpu supply of 0.9V, +which seems to be the default on most D1 boards. + +Signed-off-by: Brandon Cheo Fusi +--- + arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +@@ -36,16 +36,22 @@ + }; + + opp_table_cpu: opp-table-cpu { +- compatible = "operating-points-v2"; ++ compatible = "allwinner,sun20i-d1-operating-points", ++ "allwinner,sun50i-h6-operating-points"; ++ nvmem-cells = <&cpu_speed_grade>; ++ nvmem-cell-names = "speed"; ++ opp-shared; + + opp-408000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000 900000 1100000>; ++ opp-microvolt-speed0 = <900000 900000 1100000>; + }; + + opp-1080000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1008000000>; +- opp-microvolt = <900000 900000 1100000>; ++ opp-microvolt-speed0 = <900000 900000 1100000>; + }; + }; + +@@ -112,3 +118,9 @@ + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; + }; + }; ++ ++&sid { ++ cpu_speed_grade: cpu-speed-grade@0 { ++ reg = <0x00 0x2>; ++ }; ++}; diff --git a/target/linux/d1/patches-6.6/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch b/target/linux/d1/patches-6.6/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch deleted file mode 100644 index ec3f553b51..0000000000 --- a/target/linux/d1/patches-6.6/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 5 Sep 2022 16:45:44 -0500 -Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property - -Signed-off-by: Samuel Holland ---- - .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -@@ -40,6 +40,9 @@ properties: - clock-names: - const: stmmaceth - -+ phy-supply: -+ description: PHY regulator -+ - syscon: - $ref: /schemas/types.yaml#/definitions/phandle - description: diff --git a/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch b/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch new file mode 100644 index 0000000000..b60551be86 --- /dev/null +++ b/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch @@ -0,0 +1,25 @@ +From e904f32e5fe694ed7b8d1cd914bcf2bfd67e896c Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:40 +0100 +Subject: [PATCH 03/14] dt-bindings: opp: sun50i: Add binding for D1 CPUs + +Add binding for D1 CPU OPPs. + +Signed-off-by: Brandon Cheo Fusi +--- + .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml ++++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml +@@ -23,7 +23,9 @@ allOf: + + properties: + compatible: +- const: allwinner,sun50i-h6-operating-points ++ enum: ++ - allwinner,sun50i-h6-operating-points ++ - allwinner,sun20i-d1-operating-points + + nvmem-cells: + description: | diff --git a/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch b/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch new file mode 100644 index 0000000000..e918156eb1 --- /dev/null +++ b/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch @@ -0,0 +1,23 @@ +From b294def636629cc4d9feff4ed610a0d0c68a58fd Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:41 +0100 +Subject: [PATCH 04/14] cpufreq: sun50i: Add D1 support + +Add support for D1 based devices to the Allwinner H6 cpufreq +driver + +Signed-off-by: Brandon Cheo Fusi +--- + drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c ++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c +@@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpu + + static const struct of_device_id sun50i_cpufreq_match_list[] = { + { .compatible = "allwinner,sun50i-h6" }, ++ { .compatible = "allwinner,sun20i-d1" }, + {} + }; + MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list); diff --git a/target/linux/d1/patches-6.6/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch b/target/linux/d1/patches-6.6/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch deleted file mode 100644 index 9ac335ae3e..0000000000 --- a/target/linux/d1/patches-6.6/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Mon, 5 Sep 2022 16:46:34 -0500 -Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from - dwmac binding - -Signed-off-by: Samuel Holland ---- - .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml -@@ -40,6 +40,9 @@ properties: - clock-names: - const: stmmaceth - -+ resets: true -+ reset-names: true -+ - phy-supply: - description: PHY regulator - -@@ -49,6 +52,8 @@ properties: - Phandle to the device containing the EMAC or GMAC clock - register - -+ mdio: true -+ - required: - - compatible - - reg diff --git a/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch b/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch new file mode 100644 index 0000000000..3127a0e9bb --- /dev/null +++ b/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch @@ -0,0 +1,23 @@ +From 9d78aafd278577ef2a9d92127c9d35b00989c057 Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:42 +0100 +Subject: [PATCH 05/14] cpufreq: dt-platdev: Blocklist allwinner,sun20i-d1 SoC + +The Allwinner D1 uses H6 cpufreq driver. Add it to blocklist +so the "cpufreq-dt" device is not created twice. + +Signed-off-by: Brandon Cheo Fusi +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -104,6 +104,7 @@ static const struct of_device_id allowli + */ + static const struct of_device_id blocklist[] __initconst = { + { .compatible = "allwinner,sun50i-h6", }, ++ { .compatible = "allwinner,sun20i-d1", }, + + { .compatible = "apple,arm-platform", }, + diff --git a/target/linux/d1/patches-6.6/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch b/target/linux/d1/patches-6.6/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch deleted file mode 100644 index 402f291674..0000000000 --- a/target/linux/d1/patches-6.6/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch +++ /dev/null @@ -1,28 +0,0 @@ -From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 13 Aug 2022 10:45:59 -0500 -Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove - #phy-cells - -This device is not a PHY, and none of the nodes using this schema -contain a #phy-cells property. Likely this was a copy/paste error -introduced during the YAML conversion. - -Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas") -Signed-off-by: Samuel Holland ---- - .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 3 --- - 1 file changed, 3 deletions(-) - ---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -@@ -20,9 +20,6 @@ maintainers: - - Maxime Ripard - - properties: -- "#phy-cells": -- const: 0 -- - compatible: - oneOf: - - const: allwinner,sun8i-a83t-dw-hdmi diff --git a/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch b/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch new file mode 100644 index 0000000000..7ff3095ebc --- /dev/null +++ b/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch @@ -0,0 +1,69 @@ +From e4a8ff817e133d84f8a82f78461e0592e5e9d9cc Mon Sep 17 00:00:00 2001 +From: Brandon Cheo Fusi +Date: Mon, 18 Dec 2023 12:05:43 +0100 +Subject: [PATCH 06/14] cpufreq: Make sun50i h6 cpufreq Kconfig option arch + generic + +Move the Allwinner SUN50I cpufreq driver from Kconfig.arm to the +main Kconfig file so it supports other architectures, like RISC-V +in our case, and drop the 'ARM_' prefix. + +Signed-off-by: Brandon Cheo Fusi +--- + drivers/cpufreq/Kconfig | 12 ++++++++++++ + drivers/cpufreq/Kconfig.arm | 12 ------------ + drivers/cpufreq/Makefile | 2 +- + 3 files changed, 13 insertions(+), 13 deletions(-) + +--- a/drivers/cpufreq/Kconfig ++++ b/drivers/cpufreq/Kconfig +@@ -312,5 +312,17 @@ config QORIQ_CPUFREQ + This adds the CPUFreq driver support for Freescale QorIQ SoCs + which are capable of changing the CPU's frequency dynamically. + ++config ALLWINNER_SUN50I_CPUFREQ_NVMEM ++ tristate "Allwinner nvmem based SUN50I CPUFreq driver" ++ depends on ARCH_SUNXI ++ depends on NVMEM_SUNXI_SID ++ select PM_OPP ++ help ++ This adds the nvmem based CPUFreq driver for Allwinner ++ h6/D1 SoCs. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called sun50i-cpufreq-nvmem. ++ + endif + endmenu +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -29,18 +29,6 @@ config ACPI_CPPC_CPUFREQ_FIE + + If in doubt, say N. + +-config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM +- tristate "Allwinner nvmem based SUN50I CPUFreq driver" +- depends on ARCH_SUNXI +- depends on NVMEM_SUNXI_SID +- select PM_OPP +- help +- This adds the nvmem based CPUFreq driver for Allwinner +- h6 SoC. +- +- To compile this driver as a module, choose M here: the +- module will be called sun50i-cpufreq-nvmem. +- + config ARM_APPLE_SOC_CPUFREQ + tristate "Apple Silicon SoC CPUFreq support" + depends on ARCH_APPLE || (COMPILE_TEST && 64BIT) +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -78,7 +78,7 @@ obj-$(CONFIG_ARM_SCMI_CPUFREQ) += scmi- + obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o + obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o + obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o +-obj-$(CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o ++obj-$(CONFIG_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o + obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o + obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o + obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o diff --git a/target/linux/d1/patches-6.6/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch b/target/linux/d1/patches-6.6/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch deleted file mode 100644 index b62e45c09f..0000000000 --- a/target/linux/d1/patches-6.6/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch +++ /dev/null @@ -1,34 +0,0 @@ -From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Thu, 31 Mar 2022 23:43:15 -0500 -Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles - -Allwinner D1 contains a DesignWare HDMI controller with some changes in -platform integration, and a new HDMI PHY. Add their compatibles. - -Signed-off-by: Samuel Holland ---- - .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 1 + - .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml | 1 + - 2 files changed, 2 insertions(+) - ---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml -@@ -29,6 +29,7 @@ properties: - - enum: - - allwinner,sun8i-h3-dw-hdmi - - allwinner,sun8i-r40-dw-hdmi -+ - allwinner,sun20i-d1-dw-hdmi - - allwinner,sun50i-a64-dw-hdmi - - const: allwinner,sun8i-a83t-dw-hdmi - ---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml -+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml -@@ -19,6 +19,7 @@ properties: - - allwinner,sun8i-a83t-hdmi-phy - - allwinner,sun8i-h3-hdmi-phy - - allwinner,sun8i-r40-hdmi-phy -+ - allwinner,sun20i-d1-hdmi-phy - - allwinner,sun50i-a64-hdmi-phy - - allwinner,sun50i-h6-hdmi-phy - diff --git a/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch b/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch new file mode 100644 index 0000000000..ad50d9130c --- /dev/null +++ b/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch @@ -0,0 +1,116 @@ +From 3341f884d75929a009801d4299d219e64c64a33c Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:01 +0300 +Subject: [PATCH 07/14] ASoC: dt-bindings: sun4i-a10-codec: Add binding for + Allwinner D1 SoC + +The Allwinner D1 SoC has a internal audio codec that similar to previous +ones, but it contains a three ADC channels instead of two, and also has +a separate clocks for ADC and DAC modules. + +Signed-off-by: Maksim Kiselev +Reviewed-by: Rob Herring +--- + .../sound/allwinner,sun4i-a10-codec.yaml | 64 ++++++++++++++++--- + 1 file changed, 56 insertions(+), 8 deletions(-) + +--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml ++++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml +@@ -22,6 +22,7 @@ properties: + - allwinner,sun8i-a23-codec + - allwinner,sun8i-h3-codec + - allwinner,sun8i-v3s-codec ++ - allwinner,sun20i-d1-codec + + reg: + maxItems: 1 +@@ -29,15 +30,9 @@ properties: + interrupts: + maxItems: 1 + +- clocks: +- items: +- - description: Bus Clock +- - description: Module Clock ++ clocks: true + +- clock-names: +- items: +- - const: apb +- - const: codec ++ clock-names: true + + dmas: + items: +@@ -106,11 +101,42 @@ allOf: + - if: + properties: + compatible: ++ const: allwinner,sun20i-d1-codec ++ then: ++ properties: ++ clocks: ++ items: ++ - description: Bus Clock ++ - description: ADC Module Clock ++ - description: DAC Module Clock ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: adc ++ - const: dac ++ ++ else: ++ properties: ++ clocks: ++ items: ++ - description: Bus Clock ++ - description: Module Clock ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: codec ++ ++ - if: ++ properties: ++ compatible: + enum: + - allwinner,sun6i-a31-codec + - allwinner,sun8i-a23-codec + - allwinner,sun8i-h3-codec + - allwinner,sun8i-v3s-codec ++ - allwinner,sun20i-d1-codec + + then: + if: +@@ -225,6 +251,28 @@ allOf: + - Headphone + - Headset Mic + - Line In ++ - Line Out ++ - Mic ++ - Speaker ++ ++ - if: ++ properties: ++ compatible: ++ enum: ++ - allwinner,sun20i-d1-codec ++ ++ then: ++ properties: ++ allwinner,audio-routing: ++ items: ++ enum: ++ - HP ++ - LINEIN ++ - MIC3 ++ - MBIAS ++ - Headphone ++ - Headset Mic ++ - Line In + - Line Out + - Mic + - Speaker diff --git a/target/linux/d1/patches-6.6/0007-drm-sun4i-Add-support-for-D1-HDMI.patch b/target/linux/d1/patches-6.6/0007-drm-sun4i-Add-support-for-D1-HDMI.patch deleted file mode 100644 index b55c3a3f20..0000000000 --- a/target/linux/d1/patches-6.6/0007-drm-sun4i-Add-support-for-D1-HDMI.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 30 Mar 2022 21:24:21 -0500 -Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI - -D1's HDMI controller contains some platform integration changes. -It now has no external TMDS clock. The controller also supports HDCP -without an external clock or reset. - -While the maximum HDMI frequency is not explicity stated, the BSP PHY -driver provides PLL configurations only up to 297 MHz, so use that as -the max frequency. - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev - return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl), - "Could not get ctrl reset control\n"); - -- hdmi->clk_tmds = devm_clk_get(dev, "tmds"); -+ hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds"); - if (IS_ERR(hdmi->clk_tmds)) - return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds), - "Couldn't get the tmds clock\n"); -@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks - .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, - }; - -+static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = { -+ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, -+ .use_drm_infoframe = true, -+}; -+ - static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { - .mode_valid = sun8i_dw_hdmi_mode_valid_h6, - .use_drm_infoframe = true, -@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d - .data = &sun8i_a83t_quirks, - }, - { -+ .compatible = "allwinner,sun20i-d1-dw-hdmi", -+ .data = &sun20i_d1_quirks, -+ }, -+ { - .compatible = "allwinner,sun50i-h6-dw-hdmi", - .data = &sun50i_h6_quirks, - }, diff --git a/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch b/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch new file mode 100644 index 0000000000..d25a27de92 --- /dev/null +++ b/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch @@ -0,0 +1,51 @@ +From 64efc9cc704d27c60dc9c96a02d842f22dbdfeae Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:02 +0300 +Subject: [PATCH 08/14] ASoC: dt-bindings: Add schema for + "allwinner,sun20i-d1-codec-analog" + +Add a DT schema to describe the analog part of the Allwinner D1/T113s +internal audio codec. + +Signed-off-by: Maksim Kiselev +--- + .../allwinner,sun20i-d1-codec-analog.yaml | 33 +++++++++++++++++++ + 1 file changed, 33 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml +@@ -0,0 +1,33 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/allwinner,sun20i-d1-codec-analog.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Allwinner D1 Analog Codec ++ ++maintainers: ++ - Maksim Kiselev ++ ++properties: ++ compatible: ++ const: allwinner,sun20i-d1-codec-analog ++ ++ reg: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ ++additionalProperties: false ++ ++examples: ++ - | ++ codec_analog: codec-analog@2030300 { ++ compatible = "allwinner,sun20i-d1-codec-analog"; ++ reg = <0x02030300 0xd00>; ++ }; ++ ++... ++ diff --git a/target/linux/d1/patches-6.6/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch b/target/linux/d1/patches-6.6/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch deleted file mode 100644 index e8007cc5c4..0000000000 --- a/target/linux/d1/patches-6.6/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 3 Apr 2022 15:15:41 -0500 -Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 169 +++++++++++++++++++++++++ - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 32 +++++ - 2 files changed, 201 insertions(+) - ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -145,6 +145,175 @@ - - #define SUN8I_HDMI_PHY_CEC_REG 0x003c - -+#define SUN20I_HDMI_PHY_CTL0_REG 0x0040 -+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN BIT(31) -+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE BIT(30) -+#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN BIT(29) -+#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS BIT(28) -+#define SUN20I_HDMI_PHY_CTL0_ENTX GENMASK(27, 24) -+#define SUN20I_HDMI_PHY_CTL0_ENBI GENMASK(23, 20) -+#define SUN20I_HDMI_PHY_CTL0_ENLDO BIT(18) -+#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS BIT(17) -+#define SUN20I_HDMI_PHY_CTL0_ENCK BIT(16) -+#define SUN20I_HDMI_PHY_CTL0_REG_PLR GENMASK(15, 12) -+#define SUN20I_HDMI_PHY_CTL0_REG_DEN GENMASK(11, 8) -+#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS GENMASK(7, 6) -+#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL BIT(5) -+#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL BIT(4) -+#define SUN20I_HDMI_PHY_CTL0_HPD_EN BIT(2) -+#define SUN20I_HDMI_PHY_CTL0_SCL_EN BIT(1) -+#define SUN20I_HDMI_PHY_CTL0_SDA_EN BIT(0) -+ -+#define SUN20I_HDMI_PHY_CTL1_REG 0x0044 -+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN BIT(31) -+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE BIT(30) -+#define SUN20I_HDMI_PHY_CTL1_RES_S GENMASK(29, 28) -+#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS BIT(27) -+#define SUN20I_HDMI_PHY_CTL1_REG_SWI BIT(26) -+#define SUN20I_HDMI_PHY_CTL1_REG_SVR GENMASK(25, 24) -+#define SUN20I_HDMI_PHY_CTL1_REG_BST2 GENMASK(21, 20) -+#define SUN20I_HDMI_PHY_CTL1_REG_BST1 GENMASK(19, 18) -+#define SUN20I_HDMI_PHY_CTL1_REG_BST0 GENMASK(17, 16) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3 GENMASK(15, 12) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2 GENMASK(11, 8) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1 GENMASK(7, 4) -+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0 GENMASK(3, 0) -+ -+#define SUN20I_HDMI_PHY_CTL2_REG 0x0048 -+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN BIT(31) -+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE BIT(30) -+#define SUN20I_HDMI_PHY_CTL2_REG_RESDI GENMASK(29, 24) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3 GENMASK(23, 19) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2 GENMASK(18, 14) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1 GENMASK(13, 9) -+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0 GENMASK(8, 4) -+#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT GENMASK(3, 0) -+ -+#define SUN20I_HDMI_PHY_CTL3_REG 0x004c -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_3 GENMASK(31, 28) -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_2 GENMASK(27, 24) -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_1 GENMASK(23, 20) -+#define SUN20I_HDMI_PHY_CTL3_REG_P2_0 GENMASK(19, 16) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC3 GENMASK(15, 12) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC2 GENMASK(11, 8) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC1 GENMASK(7, 4) -+#define SUN20I_HDMI_PHY_CTL3_REG_MC0 GENMASK(3, 0) -+ -+#define SUN20I_HDMI_PHY_CTL4_REG 0x0050 -+#define SUN20I_HDMI_PHY_CTL4_REG_SLV GENMASK(31, 29) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_3 GENMASK(28, 24) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_2 GENMASK(20, 16) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_1 GENMASK(12, 8) -+#define SUN20I_HDMI_PHY_CTL4_REG_P1_0 GENMASK(4, 0) -+ -+#define SUN20I_HDMI_PHY_CTL5_REG 0x0054 -+#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT GENMASK(19, 16) -+#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT BIT(12) -+#define SUN20I_HDMI_PHY_CTL5_REG_CALSW BIT(11) -+#define SUN20I_HDMI_PHY_CTL5_ENRESCK BIT(10) -+#define SUN20I_HDMI_PHY_CTL5_ENRES BIT(9) -+#define SUN20I_HDMI_PHY_CTL5_ENRCAL BIT(8) -+#define SUN20I_HDMI_PHY_CTL5_ENP2S GENMASK(7, 4) -+#define SUN20I_HDMI_PHY_CTL5_ENIB BIT(1) -+#define SUN20I_HDMI_PHY_CTL5_ENCALOG BIT(0) -+ -+#define SUN20I_HDMI_PLL_CTL0_REG 0x0058 -+#define SUN20I_HDMI_PLL_CTL0_CKO_SEL GENMASK(31, 30) -+#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL BIT(29) -+#define SUN20I_HDMI_PLL_CTL0_ENVBS BIT(28) -+#define SUN20I_HDMI_PLL_CTL0_SLV GENMASK(26, 24) -+#define SUN20I_HDMI_PLL_CTL0_BCR BIT(23) -+#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH BIT(22) -+#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH GENMASK(21, 20) -+#define SUN20I_HDMI_PLL_CTL0_CUTFB BIT(18) -+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT BIT(17) -+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS BIT(16) -+#define SUN20I_HDMI_PLL_CTL0_DIV_PRE GENMASK(15, 12) -+#define SUN20I_HDMI_PLL_CTL0_DIVX1 BIT(10) -+#define SUN20I_HDMI_PLL_CTL0_SDRVEN BIT(9) -+#define SUN20I_HDMI_PLL_CTL0_VCORANGE BIT(8) -+#define SUN20I_HDMI_PLL_CTL0_N_CNTRL GENMASK(7, 6) -+#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL GENMASK(5, 4) -+#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL GENMASK(2, 0) -+ -+#define SUN20I_HDMI_PLL_CTL1_REG 0x005c -+#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC BIT(31) -+#define SUN20I_HDMI_PLL_CTL1_PCNT_N GENMASK(27, 20) -+#define SUN20I_HDMI_PLL_CTL1_PCNT_EN BIT(19) -+#define SUN20I_HDMI_PLL_CTL1_SDM_EN BIT(18) -+#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP GENMASK(17, 16) -+#define SUN20I_HDMI_PLL_CTL1_PWRON BIT(12) -+#define SUN20I_HDMI_PLL_CTL1_RESET BIT(11) -+#define SUN20I_HDMI_PLL_CTL1_SCKREF BIT(10) -+#define SUN20I_HDMI_PLL_CTL1_SCKFB BIT(9) -+#define SUN20I_HDMI_PLL_CTL1_DRV_ANA BIT(8) -+#define SUN20I_HDMI_PLL_CTL1_FAST_TECH BIT(7) -+#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT BIT(6) -+#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL GENMASK(5, 4) -+#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL GENMASK(2, 0) -+ -+#define SUN20I_HDMI_AFIFO_CFG_REG 0x0060 -+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR BIT(0) -+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET BIT(1) -+ -+#define SUN20I_HDMI_MODULATOR_CFG0_REG 0x0064 -+#define SUN20I_HDMI_MODULATOR_CFG1_REG 0x0068 -+ -+#define SUN20I_HDMI_INDEB_CTRL_REG 0x006c -+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE BIT(29) -+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG BIT(28) -+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE BIT(25) -+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG BIT(24) -+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE BIT(21) -+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG BIT(20) -+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE BIT(17) -+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG BIT(16) -+#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE GENMASK(1, 0) -+ -+#define SUN20I_HDMI_INDBG_TXD0_REG 0x0070 -+#define SUN20I_HDMI_INDBG_TXD1_REG 0x0074 -+#define SUN20I_HDMI_INDBG_TXD2_REG 0x0078 -+#define SUN20I_HDMI_INDBG_TXD3_REG 0x007c -+ -+#define SUN20I_HDMI_PLL_STS_REG 0x0080 -+#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS BIT(31) -+#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS GENMASK(30, 28) -+#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS BIT(27) -+#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS GENMASK(26, 24) -+#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS BIT(23) -+#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS BIT(22) -+#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS BIT(21) -+#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS BIT(20) -+#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS BIT(17) -+#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS BIT(16) -+#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS GENMASK(13, 8) -+#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS BIT(4) -+#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS BIT(1) -+#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS BIT(0) -+ -+#define SUN20I_HDMI_PRBS_CTL_REG 0x0084 -+#define SUN20I_HDMI_PRBS_SEED_GEN_REG 0x0088 -+#define SUN20I_HDMI_PRBS_SEED_CHK_REG 0x008c -+#define SUN20I_HDMI_PRBS_SEED_NUM_REG 0x0090 -+#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG 0x0094 -+ -+#define SUN20I_HDMI_PLL_ODLY_REG 0x0098 -+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET BIT(31) -+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT GENMASK(30, 16) -+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET BIT(15) -+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT GENMASK(14, 0) -+ -+#define SUN20I_HDMI_PHY_CTL6_REG 0x009c -+#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA BIT(31) -+#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT BIT(30) -+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M GENMASK(29, 20) -+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M GENMASK(19, 10) -+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M GENMASK(9, 0) -+ -+#define SUN20I_HDMI_PHY_CTL7_REG 0x00a0 -+#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M GENMASK(21, 12) -+#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M GENMASK(9, 0) -+ - struct sun8i_hdmi_phy; - - struct sun8i_hdmi_phy_variant { ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8 - .setup_hpd = dw_hdmi_phy_setup_hpd, - }; - -+static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, -+ const struct drm_display_info *display, -+ const struct drm_display_mode *mode) -+{ -+ struct sun8i_hdmi_phy *phy = data; -+ -+ return 0; -+} -+ -+static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) -+{ -+ struct sun8i_hdmi_phy *phy = data; -+} -+ -+static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = { -+ .init = sun20i_d1_hdmi_phy_config, -+ .disable = sun20i_d1_hdmi_phy_disable, -+ .read_hpd = dw_hdmi_phy_read_hpd, -+ .update_hpd = dw_hdmi_phy_update_hpd, -+ .setup_hpd = dw_hdmi_phy_setup_hpd, -+}; -+ - static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) - { - /* enable read access to HDMI controller */ -@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i - const struct sun8i_hdmi_phy_variant *variant = phy->variant; - - if (variant->phy_ops) { -+ plat_data->phy_force_vendor = true; - plat_data->phy_ops = variant->phy_ops; - plat_data->phy_name = "sun8i_dw_hdmi_phy"; - plat_data->phy_data = phy; -@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia - .phy_init = &sun8i_hdmi_phy_init_h3, - }; - -+static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = { -+ .phy_ops = &sun20i_d1_hdmi_phy_ops, -+ .phy_init = &sun50i_hdmi_phy_init_h6, -+}; -+ - static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { - .has_phy_clk = true, - .phy_ops = &sun8i_h3_hdmi_phy_ops, -@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h - .data = &sun8i_r40_hdmi_phy, - }, - { -+ .compatible = "allwinner,sun20i-d1-hdmi-phy", -+ .data = &sun20i_d1_hdmi_phy, -+ }, -+ { - .compatible = "allwinner,sun50i-a64-hdmi-phy", - .data = &sun50i_a64_hdmi_phy, - }, diff --git a/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch b/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch new file mode 100644 index 0000000000..242f8f7a0e --- /dev/null +++ b/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch @@ -0,0 +1,614 @@ +From 0963766bc665769aebf370d44ee3a97facfbca57 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:03 +0300 +Subject: [PATCH 09/14] ASoC: sunxi: sun4i-codec: add basic support for D1 + audio codec + +Allwinner D1 has an audio codec similar to earlier ones, but it comes +with 3 channel ADC instead of 2, and many registers are moved. + +Add basic support for it. + +Signed-off-by: Maksim Kiselev +--- + sound/soc/sunxi/sun4i-codec.c | 364 ++++++++++++++++++++++++++++------ + 1 file changed, 300 insertions(+), 64 deletions(-) + +--- a/sound/soc/sunxi/sun4i-codec.c ++++ b/sound/soc/sunxi/sun4i-codec.c +@@ -232,15 +232,65 @@ + + /* TODO H3 DAP (Digital Audio Processing) bits */ + ++/* ++ * sun20i D1 and similar codecs specific registers ++ * ++ * Almost all registers moved on D1, including ADC digital controls, ++ * FIFO and RX data registers. Only DAC control are at the same offset. ++ */ ++ ++#define SUN20I_D1_CODEC_DAC_VOL_CTRL (0x04) ++#define SUN20I_D1_CODEC_DAC_VOL_SEL (16) ++#define SUN20I_D1_CODEC_DAC_VOL_L (8) ++#define SUN20I_D1_CODEC_DAC_VOL_R (0) ++#define SUN20I_D1_CODEC_DAC_FIFOC (0x10) ++#define SUN20I_D1_CODEC_ADC_FIFOC (0x30) ++#define SUN20I_D1_CODEC_ADC_FIFOC_EN_AD (28) ++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (16) ++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (4) ++#define SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN (3) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1 (0x34) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL (16) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL (8) ++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL (0) ++#define SUN20I_D1_CODEC_ADC_RXDATA (0x40) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL (0x50) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN (2) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN (1) ++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN (0) ++#define SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL (0x54) ++ ++/* TODO D1 DAP (Digital Audio Processing) bits */ ++ ++struct sun4i_codec; ++ ++struct sun4i_codec_quirks { ++ const struct regmap_config *regmap_config; ++ const struct snd_soc_component_driver *codec; ++ struct snd_soc_card * (*create_card)(struct device *dev); ++ struct reg_field reg_dac_fifoc; /* used for regmap_field */ ++ struct reg_field reg_adc_fifoc; /* used for regmap_field */ ++ unsigned int adc_drq_en; ++ unsigned int rx_sample_bits; ++ unsigned int rx_trig_level; ++ unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ ++ unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ ++ bool has_reset; ++ bool has_dual_clock; ++}; ++ + struct sun4i_codec { + struct device *dev; + struct regmap *regmap; + struct clk *clk_apb; +- struct clk *clk_module; ++ struct clk *clk_module; /* used for ADC if clocks are separate */ ++ struct clk *clk_module_dac; + struct reset_control *rst; + struct gpio_desc *gpio_pa; ++ const struct sun4i_codec_quirks *quirks; + +- /* ADC_FIFOC register is at different offset on different SoCs */ ++ /* DAC/ADC FIFOC registers are at different offset on different SoCs */ ++ struct regmap_field *reg_dac_fifoc; + struct regmap_field *reg_adc_fifoc; + + struct snd_dmaengine_dai_dma_data capture_dma_data; +@@ -250,33 +300,33 @@ struct sun4i_codec { + static void sun4i_codec_start_playback(struct sun4i_codec *scodec) + { + /* Flush TX FIFO */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); + + /* Enable DAC DRQ */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); + } + + static void sun4i_codec_stop_playback(struct sun4i_codec *scodec) + { + /* Disable DAC DRQ */ +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN)); + } + + static void sun4i_codec_start_capture(struct sun4i_codec *scodec) + { + /* Enable ADC DRQ */ + regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); ++ BIT(scodec->quirks->adc_drq_en)); + } + + static void sun4i_codec_stop_capture(struct sun4i_codec *scodec) + { + /* Disable ADC DRQ */ + regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN)); ++ BIT(scodec->quirks->adc_drq_en)); + } + + static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd, +@@ -325,8 +375,8 @@ static int sun4i_codec_prepare_capture(s + + /* Set RX FIFO trigger level */ + regmap_field_update_bits(scodec->reg_adc_fifoc, +- 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, +- 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL); ++ 0xf << scodec->quirks->rx_trig_level, ++ 0x7 << scodec->quirks->rx_trig_level); + + /* + * FIXME: Undocumented in the datasheet, but +@@ -360,13 +410,13 @@ static int sun4i_codec_prepare_playback( + u32 val; + + /* Flush the TX FIFO */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH)); + + /* Set TX FIFO Empty Trigger Level */ +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL, +- 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL, ++ 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL); + + if (substream->runtime->rate > 32000) + /* Use 64 bits FIR filter */ +@@ -375,13 +425,12 @@ static int sun4i_codec_prepare_playback( + /* Use 32 bits FIR filter */ + val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION); + +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), +- val); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), val); + + /* Send zeros when we have an underrun */ +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT)); + + return 0; + }; +@@ -476,30 +525,32 @@ static int sun4i_codec_hw_params_capture + 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS, + hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS); + +- /* Set the number of channels we want to use */ +- if (params_channels(params) == 1) +- regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); +- else +- regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); ++ if (!scodec->quirks->has_dual_clock) { ++ /* Set the number of channels we want to use */ ++ if (params_channels(params) == 1) ++ regmap_field_set_bits(scodec->reg_adc_fifoc, ++ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); ++ else ++ regmap_field_clear_bits(scodec->reg_adc_fifoc, ++ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN)); ++ } + + /* Set the number of sample bits to either 16 or 24 bits */ + if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { + regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); ++ BIT(scodec->quirks->rx_sample_bits)); + + regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); ++ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); + + scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + } else { + regmap_field_clear_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS)); ++ BIT(scodec->quirks->rx_sample_bits)); + + /* Fill most significant bits with valid data MSB */ + regmap_field_set_bits(scodec->reg_adc_fifoc, +- BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); ++ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE)); + + scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + } +@@ -514,9 +565,9 @@ static int sun4i_codec_hw_params_playbac + u32 val; + + /* Set DAC sample rate */ +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS, +- hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS, ++ hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS); + + /* Set the number of channels we want to use */ + if (params_channels(params) == 1) +@@ -524,27 +575,26 @@ static int sun4i_codec_hw_params_playbac + else + val = 0; + +- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), +- val); ++ regmap_field_update_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), val); + + /* Set the number of sample bits to either 16 or 24 bits */ + if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) { +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); + + /* Set TX FIFO mode to padding the LSBs with 0 */ +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); + + scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + } else { +- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); ++ regmap_field_clear_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS)); + + /* Set TX FIFO mode to repeat the MSB */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE)); + + scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + } +@@ -565,7 +615,11 @@ static int sun4i_codec_hw_params(struct + if (!clk_freq) + return -EINVAL; + +- ret = clk_set_rate(scodec->clk_module, clk_freq); ++ if (scodec->clk_module_dac && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ ret = clk_set_rate(scodec->clk_module_dac, clk_freq); ++ else ++ ret = clk_set_rate(scodec->clk_module, clk_freq); + if (ret) + return ret; + +@@ -607,10 +661,14 @@ static int sun4i_codec_startup(struct sn + * Stop issuing DRQ when we have room for less than 16 samples + * in our TX FIFO + */ +- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC, +- 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT); ++ regmap_field_set_bits(scodec->reg_dac_fifoc, ++ 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT); + +- return clk_prepare_enable(scodec->clk_module); ++ if (scodec->clk_module_dac && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ return clk_prepare_enable(scodec->clk_module_dac); ++ else ++ return clk_prepare_enable(scodec->clk_module); + } + + static void sun4i_codec_shutdown(struct snd_pcm_substream *substream, +@@ -619,7 +677,11 @@ static void sun4i_codec_shutdown(struct + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card); + +- clk_disable_unprepare(scodec->clk_module); ++ if (scodec->clk_module_dac && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ clk_disable_unprepare(scodec->clk_module_dac); ++ else ++ clk_disable_unprepare(scodec->clk_module); + } + + static const struct snd_soc_dai_ops sun4i_codec_dai_ops = { +@@ -1229,6 +1291,55 @@ static const struct snd_soc_component_dr + .endianness = 1, + }; + ++/* sun20i D1 codec */ ++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_dvol_scale, -12000, 75, 1); ++ ++static const struct snd_kcontrol_new sun20i_d1_codec_codec_controls[] = { ++ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC, ++ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1, ++ sun6i_codec_dvol_scale), ++ SOC_DOUBLE_TLV("DAC Front Playback Volume", SUN20I_D1_CODEC_DAC_VOL_CTRL, ++ SUN20I_D1_CODEC_DAC_VOL_L, SUN20I_D1_CODEC_DAC_VOL_R, ++ 0xFF, 0, sun20i_d1_codec_dvol_scale), ++ ++ SOC_SINGLE_TLV("ADC1 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1, ++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL, 0xff, 0, ++ sun20i_d1_codec_dvol_scale), ++ SOC_SINGLE_TLV("ADC2 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1, ++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL, 0xff, 0, ++ sun20i_d1_codec_dvol_scale), ++ SOC_SINGLE_TLV("ADC3 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1, ++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL, 0xff, 0, ++ sun20i_d1_codec_dvol_scale), ++}; ++ ++static const struct snd_soc_dapm_widget sun20i_d1_codec_codec_widgets[] = { ++ /* Digital parts of the ADCs */ ++ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN20I_D1_CODEC_ADC_FIFOC, ++ SUN20I_D1_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("ADC1 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL, ++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("ADC2 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL, ++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("ADC3 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL, ++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN, 0, NULL, 0), ++ /* Digital parts of the DACs */ ++ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC, ++ SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0), ++ SND_SOC_DAPM_SUPPLY("DAC VOL_SEL Enable", SUN20I_D1_CODEC_DAC_VOL_CTRL, ++ SUN20I_D1_CODEC_DAC_VOL_SEL, 0, NULL, 0), ++}; ++ ++static const struct snd_soc_component_driver sun20i_d1_codec_codec = { ++ .controls = sun20i_d1_codec_codec_controls, ++ .num_controls = ARRAY_SIZE(sun20i_d1_codec_codec_controls), ++ .dapm_widgets = sun20i_d1_codec_codec_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun20i_d1_codec_codec_widgets), ++ .idle_bias_on = 1, ++ .use_pmdown_time = 1, ++ .endianness = 1, ++}; ++ + static const struct snd_soc_component_driver sun4i_codec_component = { + .name = "sun4i-codec", + .legacy_dai_naming = 1, +@@ -1532,6 +1643,66 @@ static struct snd_soc_card *sun8i_v3s_co + return card; + }; + ++static const struct snd_soc_dapm_route sun20i_d1_codec_card_routes[] = { ++ /* ADC Routes */ ++ { "ADC1", NULL, "ADC Enable" }, ++ { "ADC2", NULL, "ADC Enable" }, ++ { "ADC3", NULL, "ADC Enable" }, ++ { "ADC1", NULL, "ADC1 CH Enable" }, ++ { "ADC2", NULL, "ADC2 CH Enable" }, ++ { "ADC3", NULL, "ADC3 CH Enable" }, ++ { "Codec Capture", NULL, "ADC1" }, ++ { "Codec Capture", NULL, "ADC2" }, ++ { "Codec Capture", NULL, "ADC3" }, ++ ++ /* DAC Routes */ ++ { "Left DAC", NULL, "DAC Enable" }, ++ { "Right DAC", NULL, "DAC Enable" }, ++ { "Left DAC", NULL, "DAC VOL_SEL Enable" }, ++ { "Right DAC", NULL, "DAC VOL_SEL Enable" }, ++ { "Left DAC", NULL, "Codec Playback" }, ++ { "Right DAC", NULL, "Codec Playback" }, ++}; ++ ++static struct snd_soc_card *sun20i_d1_codec_create_card(struct device *dev) ++{ ++ struct snd_soc_card *card; ++ int ret; ++ ++ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); ++ if (!card) ++ return ERR_PTR(-ENOMEM); ++ ++ aux_dev.dlc.of_node = of_parse_phandle(dev->of_node, ++ "allwinner,codec-analog-controls", ++ 0); ++ if (!aux_dev.dlc.of_node) { ++ dev_err(dev, "Can't find analog controls for codec.\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ card->dai_link = sun4i_codec_create_link(dev, &card->num_links); ++ if (!card->dai_link) ++ return ERR_PTR(-ENOMEM); ++ ++ card->dev = dev; ++ card->owner = THIS_MODULE; ++ card->name = "D1 Audio Codec"; ++ card->dapm_widgets = sun6i_codec_card_dapm_widgets; ++ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); ++ card->dapm_routes = sun20i_d1_codec_card_routes; ++ card->num_dapm_routes = ARRAY_SIZE(sun20i_d1_codec_card_routes); ++ card->aux_dev = &aux_dev; ++ card->num_aux_devs = 1; ++ card->fully_routed = true; ++ ++ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); ++ if (ret) ++ dev_warn(dev, "failed to parse audio-routing: %d\n", ret); ++ ++ return card; ++}; ++ + static const struct regmap_config sun4i_codec_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -1574,21 +1745,22 @@ static const struct regmap_config sun8i_ + .max_register = SUN8I_H3_CODEC_ADC_DBG, + }; + +-struct sun4i_codec_quirks { +- const struct regmap_config *regmap_config; +- const struct snd_soc_component_driver *codec; +- struct snd_soc_card * (*create_card)(struct device *dev); +- struct reg_field reg_adc_fifoc; /* used for regmap_field */ +- unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ +- unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ +- bool has_reset; ++static const struct regmap_config sun20i_d1_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL, + }; + + static const struct sun4i_codec_quirks sun4i_codec_quirks = { + .regmap_config = &sun4i_codec_regmap_config, + .codec = &sun4i_codec_codec, + .create_card = sun4i_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, + }; +@@ -1597,7 +1769,11 @@ static const struct sun4i_codec_quirks s + .regmap_config = &sun6i_codec_regmap_config, + .codec = &sun6i_codec_codec, + .create_card = sun6i_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, +@@ -1607,7 +1783,11 @@ static const struct sun4i_codec_quirks s + .regmap_config = &sun7i_codec_regmap_config, + .codec = &sun7i_codec_codec, + .create_card = sun4i_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA, + }; +@@ -1616,7 +1796,11 @@ static const struct sun4i_codec_quirks s + .regmap_config = &sun8i_a23_codec_regmap_config, + .codec = &sun8i_a23_codec_codec, + .create_card = sun8i_a23_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, +@@ -1631,7 +1815,11 @@ static const struct sun4i_codec_quirks s + */ + .codec = &sun8i_a23_codec_codec, + .create_card = sun8i_h3_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, +@@ -1645,12 +1833,31 @@ static const struct sun4i_codec_quirks s + */ + .codec = &sun8i_a23_codec_codec, + .create_card = sun8i_v3s_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31), + .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, + .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, + .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA, + .has_reset = true, + }; + ++static const struct sun4i_codec_quirks sun20i_d1_codec_quirks = { ++ .regmap_config = &sun20i_d1_codec_regmap_config, ++ .codec = &sun20i_d1_codec_codec, ++ .create_card = sun20i_d1_codec_create_card, ++ .reg_dac_fifoc = REG_FIELD(SUN20I_D1_CODEC_DAC_FIFOC, 0, 31), ++ .reg_adc_fifoc = REG_FIELD(SUN20I_D1_CODEC_ADC_FIFOC, 0, 31), ++ .adc_drq_en = SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN, ++ .rx_sample_bits = SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS, ++ .rx_trig_level = SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL, ++ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA, ++ .reg_adc_rxdata = SUN20I_D1_CODEC_ADC_RXDATA, ++ .has_reset = true, ++ .has_dual_clock = true, ++}; ++ + static const struct of_device_id sun4i_codec_of_match[] = { + { + .compatible = "allwinner,sun4i-a10-codec", +@@ -1676,6 +1883,10 @@ static const struct of_device_id sun4i_c + .compatible = "allwinner,sun8i-v3s-codec", + .data = &sun8i_v3s_codec_quirks, + }, ++ { ++ .compatible = "allwinner,sun20i-d1-codec", ++ .data = &sun20i_d1_codec_quirks, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, sun4i_codec_of_match); +@@ -1704,6 +1915,7 @@ static int sun4i_codec_probe(struct plat + dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); + return -ENODEV; + } ++ scodec->quirks = quirks; + + scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, + quirks->regmap_config); +@@ -1719,10 +1931,24 @@ static int sun4i_codec_probe(struct plat + return PTR_ERR(scodec->clk_apb); + } + +- scodec->clk_module = devm_clk_get(&pdev->dev, "codec"); +- if (IS_ERR(scodec->clk_module)) { +- dev_err(&pdev->dev, "Failed to get the module clock\n"); +- return PTR_ERR(scodec->clk_module); ++ if (quirks->has_dual_clock) { ++ scodec->clk_module = devm_clk_get(&pdev->dev, "adc"); ++ if (IS_ERR(scodec->clk_module)) { ++ dev_err(&pdev->dev, "Failed to get the ADC module clock\n"); ++ return PTR_ERR(scodec->clk_module); ++ } ++ ++ scodec->clk_module_dac = devm_clk_get(&pdev->dev, "dac"); ++ if (IS_ERR(scodec->clk_module_dac)) { ++ dev_err(&pdev->dev, "Failed to get the DAC module clock\n"); ++ return PTR_ERR(scodec->clk_module_dac); ++ } ++ } else { ++ scodec->clk_module = devm_clk_get(&pdev->dev, "codec"); ++ if (IS_ERR(scodec->clk_module)) { ++ dev_err(&pdev->dev, "Failed to get the module clock\n"); ++ return PTR_ERR(scodec->clk_module); ++ } + } + + if (quirks->has_reset) { +@@ -1751,6 +1977,16 @@ static int sun4i_codec_probe(struct plat + dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", + ret); + return ret; ++ } ++ ++ scodec->reg_dac_fifoc = devm_regmap_field_alloc(&pdev->dev, ++ scodec->regmap, ++ quirks->reg_dac_fifoc); ++ if (IS_ERR(scodec->reg_dac_fifoc)) { ++ ret = PTR_ERR(scodec->reg_dac_fifoc); ++ dev_err(&pdev->dev, "Failed to create regmap fields: %d\n", ++ ret); ++ return ret; + } + + /* Enable the bus clock */ diff --git a/target/linux/d1/patches-6.6/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch b/target/linux/d1/patches-6.6/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch deleted file mode 100644 index 85c81d5057..0000000000 --- a/target/linux/d1/patches-6.6/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch +++ /dev/null @@ -1,621 +0,0 @@ -From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 30 Mar 2022 00:46:07 -0500 -Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/sun4i/aw_phy.h | 411 +++++++++++++++++++++++++ - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 + - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++ - 3 files changed, 568 insertions(+) - create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h - ---- /dev/null -+++ b/drivers/gpu/drm/sun4i/aw_phy.h -@@ -0,0 +1,411 @@ -+/* -+ * Allwinner SoCs hdmi2.0 driver. -+ * -+ * Copyright (C) 2016 Allwinner. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef AW_PHY_H_ -+#define AW_PHY_H_ -+ -+#define AW_PHY_TIMEOUT 1000 -+#define LOCK_TIMEOUT 100 -+ -+/* allwinner phy register offset */ -+#define HDMI_PHY_CTL0 0x40 -+#define HDMI_PHY_CTL1 0x44 -+#define HDMI_PHY_CTL2 0x48 -+#define HDMI_PHY_CTL3 0x4C -+#define HDMI_PHY_CTL4 0x50 -+#define HDMI_PHY_CTL5 0x54 -+#define HDMI_PLL_CTL0 0x58 -+#define HDMI_PLL_CTL1 0x5C -+#define HDMI_AFIFO_CFG 0x60 -+#define HDMI_MODULATOR_CFG0 0x64 -+#define HDMI_MODULATOR_CFG1 0x68 -+#define HDMI_PHY_INDEB_CTRL 0x6C -+#define HDMI_PHY_INDBG_TXD0 0x70 -+#define HDMI_PHY_INDBG_TXD1 0x74 -+#define HDMI_PHY_INDBG_TXD2 0x78 -+#define HDMI_PHY_INDBG_TXD3 0x7C -+#define HDMI_PHY_PLL_STS 0x80 -+#define HDMI_PRBS_CTL 0x84 -+#define HDMI_PRBS_SEED_GEN 0x88 -+#define HDMI_PRBS_SEED_CHK 0x8C -+#define HDMI_PRBS_SEED_NUM 0x90 -+#define HDMI_PRBS_CYCLE_NUM 0x94 -+#define HDMI_PHY_PLL_ODLY_CFG 0x98 -+#define HDMI_PHY_CTL6 0x9C -+#define HDMI_PHY_CTL7 0xA0 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 sda_en :1; // Default: 0; -+ u32 scl_en :1; // Default: 0; -+ u32 hpd_en :1; // Default: 0; -+ u32 res0 :1; // Default: 0; -+ u32 reg_ck_sel :1; // Default: 1; -+ u32 reg_ck_test_sel :1; // Default: 1; -+ u32 reg_csmps :2; // Default: 0; -+ u32 reg_den :4; // Default: F; -+ u32 reg_plr :4; // Default: 0; -+ u32 enck :1; // Default: 1; -+ u32 enldo_fs :1; // Default: 1; -+ u32 enldo :1; // Default: 1; -+ u32 res1 :1; // Default: 1; -+ u32 enbi :4; // Default: F; -+ u32 entx :4; // Default: F; -+ u32 async_fifo_autosync_disable :1; // Default: 0; -+ u32 async_fifo_workc_enable :1; // Default: 1; -+ u32 phy_pll_lock_mode :1; // Default: 1; -+ u32 phy_pll_lock_mode_man :1; // Default: 1; -+ } bits; -+} HDMI_PHY_CTL0_t; //=========================== 0x0040 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_sp2_0 : 4 ; // Default: 0; -+ u32 reg_sp2_1 : 4 ; // Default: 0; -+ u32 reg_sp2_2 : 4 ; // Default: 0; -+ u32 reg_sp2_3 : 4 ; // Default: 0; -+ u32 reg_bst0 : 2 ; // Default: 3; -+ u32 reg_bst1 : 2 ; // Default: 3; -+ u32 reg_bst2 : 2 ; // Default: 3; -+ u32 res0 : 2 ; // Default: 0; -+ u32 reg_svr : 2 ; // Default: 2; -+ u32 reg_swi : 1 ; // Default: 0; -+ u32 res_scktmds : 1 ; // Default: 0; -+ u32 res_res_s : 2 ; // Default: 3; -+ u32 phy_rxsense_mode : 1 ; // Default: 0; -+ u32 res_rxsense_mode_man : 1 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL1_t; //===================================================== 0x0044 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_p2opt : 4 ; // Default: 0; -+ u32 reg_sp1_0 : 5 ; // Default: 0; -+ u32 reg_sp1_1 : 5 ; // Default: 0; -+ u32 reg_sp1_2 : 5 ; // Default: 0; -+ u32 reg_sp1_3 : 5 ; // Default: 0; -+ u32 reg_resdi : 6 ; // Default: 18; -+ u32 phy_hpdo_mode : 1 ; // Default: 0; -+ u32 phy_hpdo_mode_man : 1 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL2_t; //===================================================== 0x0048 -+ -+ -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_mc0 : 4 ; // Default: F; -+ u32 reg_mc1 : 4 ; // Default: F; -+ u32 reg_mc2 : 4 ; // Default: F; -+ u32 reg_mc3 : 4 ; // Default: F; -+ u32 reg_p2_0 : 4 ; // Default: F; -+ u32 reg_p2_1 : 4 ; // Default: F; -+ u32 reg_p2_2 : 4 ; // Default: F; -+ u32 reg_p2_3 : 4 ; // Default: F; -+ } bits; -+} HDMI_PHY_CTL3_t; //===================================================== 0x004C -+ -+ -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 reg_p1_0 : 5 ; // Default: 0x10; -+ u32 res0 : 3 ; // Default: 0; -+ u32 reg_p1_1 : 5 ; // Default: 0x10; -+ u32 res1 : 3 ; // Default: 0; -+ u32 reg_p1_2 : 5 ; // Default: 0x10; -+ u32 res2 : 3 ; // Default: 0; -+ u32 reg_p1_3 : 5 ; // Default: 0x10; -+ u32 reg_slv : 3 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL4_t; //===================================================== 0x0050 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 encalog : 1 ; // Default: 0x1; -+ u32 enib : 1 ; // Default: 0x1; -+ u32 res0 : 2 ; // Default: 0; -+ u32 enp2s : 4 ; // Default: 0xF; -+ u32 enrcal : 1 ; // Default: 0x1; -+ u32 enres : 1 ; // Default: 1; -+ u32 enresck : 1 ; // Default: 1; -+ u32 reg_calsw : 1 ; // Default: 0; -+ u32 reg_ckpdlyopt : 1 ; // Default: 0; -+ u32 res1 : 3 ; // Default: 0; -+ u32 reg_p1opt : 4 ; // Default: 0; -+ u32 res2 : 12 ; // Default: 0; -+ } bits; -+} HDMI_PHY_CTL5_t; //===================================================== 0x0054 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prop_cntrl : 3 ; // Default: 0x7; -+ u32 res0 : 1 ; // Default: 0; -+ u32 gmp_cntrl : 2 ; // Default: 1; -+ u32 n_cntrl : 2 ; // Default: 0; -+ u32 vcorange : 1 ; // Default: 0; -+ u32 sdrven : 1 ; // Default: 0; -+ u32 divx1 : 1 ; // Default: 0; -+ u32 res1 : 1 ; // Default: 0; -+ u32 div_pre : 4 ; // Default: 0; -+ u32 div2_cktmds : 1 ; // Default: 1; -+ u32 div2_ckbit : 1 ; // Default: 1; -+ u32 cutfb : 1 ; // Default: 0; -+ u32 res2 : 1 ; // Default: 0; -+ u32 clr_dpth : 2 ; // Default: 0; -+ u32 bypass_clrdpth : 1 ; // Default: 0; -+ u32 bcr : 1 ; // Default: 0; -+ u32 slv : 3 ; // Default: 4; -+ u32 res3 : 1 ; // Default: 0; -+ u32 envbs : 1 ; // Default: 0; -+ u32 bypass_ppll : 1 ; // Default: 0; -+ u32 cko_sel : 2 ; // Default: 0; -+ } bits; -+} HDMI_PLL_CTL0_t; //===================================================== 0x0058 -+ -+ -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 int_cntrl : 3 ; // Default: 0x0; -+ u32 res0 : 1 ; // Default: 0; -+ u32 ref_cntrl : 2 ; // Default: 3; -+ u32 gear_shift : 1 ; // Default: 0; -+ u32 fast_tech : 1 ; // Default: 0; -+ u32 drv_ana : 1 ; // Default: 1; -+ u32 sckfb : 1 ; // Default: 0; -+ u32 sckref : 1 ; // Default: 0; -+ u32 reset : 1 ; // Default: 0; -+ u32 pwron : 1 ; // Default: 0; -+ u32 res1 : 3 ; // Default: 0; -+ u32 pixel_rep : 2 ; // Default: 0; -+ u32 sdm_en : 1 ; // Default: 0; -+ u32 pcnt_en : 1 ; // Default: 0; -+ u32 pcnt_n : 8 ; // Default: 0xE; -+ u32 res2 : 3 ; // Default: 0; -+ u32 ctrl_modle_clksrc : 1 ; // Default: 0; -+ } bits; -+} HDMI_PLL_CTL1_t; //===================================================== 0x005C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 hdmi_afifo_error : 1 ; // Default: 0x0; -+ u32 hdmi_afifo_error_det : 1 ; // Default: 0x0; -+ u32 res0 : 30 ; // Default: 0; -+ } bits; -+} HDMI_AFIFO_CFG_t; //===================================================== 0x0060 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 fnpll_mash_en : 1 ; // Default: 0x0; -+ u32 fnpll_mash_mod : 2 ; // Default: 0x0; -+ u32 fnpll_mash_stp : 9 ; // Default: 0x0; -+ u32 fnpll_mash_m12 : 1 ; // Default: 0x0; -+ u32 fnpll_mash_frq : 2 ; // Default: 0x0; -+ u32 fnpll_mash_bot : 17 ; // Default: 0x0; -+ } bits; -+} HDMI_MODULATOR_CFG0_t; //===================================================== 0x0064 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 fnpll_mash_dth : 1 ; // Default: 0x0; -+ u32 fnpll_mash_fen : 1 ; // Default: 0x0; -+ u32 fnpll_mash_frc : 17 ; // Default: 0x0; -+ u32 fnpll_mash_fnv : 8 ; // Default: 0x0; -+ u32 res0 : 5 ; // Default: 0x0; -+ } bits; -+} HDMI_MODULATOR_CFG1_t; //===================================================== 0x0068 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata_debugmode : 2 ; // Default: 0x0; -+ u32 res0 : 14 ; // Default: 0x0; -+ u32 ceci_debug : 1 ; // Default: 0x0; -+ u32 ceci_debugmode : 1 ; // Default: 0x0; -+ u32 res1 : 2 ; // Default: 0x0; -+ u32 sdai_debug : 1 ; // Default: 0x0; -+ u32 sdai_debugmode : 1 ; // Default: 0x0; -+ u32 res2 : 2 ; // Default: 0x0; -+ u32 scli_debug : 1 ; // Default: 0x0; -+ u32 scli_debugmode : 1 ; // Default: 0x0; -+ u32 res3 : 2 ; // Default: 0x0; -+ u32 hpdi_debug : 1 ; // Default: 0x0; -+ u32 hpdi_debugmode : 1 ; // Default: 0x0; -+ u32 res4 : 2 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_CTRL_t; //================================================== 0x006C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata0_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD0_t; //================================================== 0x0070 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata1_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD1_t; //================================================== 0x0074 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata2_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD2_t; //================================================== 0x0078 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 txdata3_debug_data : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_INDBG_TXD3_t; //================================================== 0x007C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 tx_ready_dly_status : 1 ; // Default: 0x0; -+ u32 rxsense_dly_status : 1 ; // Default: 0x0; -+ u32 res0 : 2 ; // Default: 0x0; -+ u32 pll_lock_status : 1 ; // Default: 0x0; -+ u32 res1 : 3 ; // Default: 0x0; -+ u32 phy_resdo2d_status : 6 ; // Default: 0x0; -+ u32 res2 : 2 ; // Default: 0x0; -+ u32 phy_rcalend2d_status : 1 ; // Default: 0x0; -+ u32 phy_cout2d_status : 1 ; // Default: 0x0; -+ u32 res3 : 2 ; // Default: 0x0; -+ u32 phy_ceco_status : 1 ; // Default: 0x0; -+ u32 phy_sdao_status : 1 ; // Default: 0x0; -+ u32 phy_sclo_status : 1 ; // Default: 0x0; -+ u32 phy_hpdo_status : 1 ; // Default: 0x0; -+ u32 phy_cdetn_status : 3 ; // Default: 0x0; -+ u32 phy_cdetnck_status : 1 ; // Default: 0x0; -+ u32 phy_cdetp_status : 3 ; // Default: 0x0; -+ u32 phy_cdetpck_status : 1 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_PLL_STS_t; //===================================================== 0x0080 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_en : 1 ; // Default: 0x0; -+ u32 prbs_start : 1 ; // Default: 0x0; -+ u32 prbs_seq_gen : 1 ; // Default: 0x0; -+ u32 prbs_seq_chk : 1 ; // Default: 0x0; -+ u32 prbs_mode : 4 ; // Default: 0x0; -+ u32 prbs_type : 2 ; // Default: 0x0; -+ u32 prbs_clk_pol : 1 ; // Default: 0x0; -+ u32 res0 : 21 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_CTL_t; //===================================================== 0x0084 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_seed_gen : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_SEED_GEN_t; //================================================= 0x0088 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_seed_chk : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_SEED_CHK_t; //================================================= 0x008C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_seed_num : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_SEED_NUM_t; //================================================= 0x0090 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 prbs_cycle_num : 32 ; // Default: 0x0; -+ } bits; -+} HDMI_PRBS_CYCLE_NUM_t; //================================================= 0x0094 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 tx_ready_dly_count : 15 ; // Default: 0x0; -+ u32 tx_ready_dly_reset : 1 ; // Default: 0x0; -+ u32 rxsense_dly_count : 15 ; // Default: 0x0; -+ u32 rxsense_dly_reset : 1 ; // Default: 0x0; -+ } bits; -+} HDMI_PHY_PLL_ODLY_CFG_t; //================================================= 0x0098 -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 clk_greate0_340m : 10 ; // Default: 0x3FF; -+ u32 clk_greate1_340m : 10 ; // Default: 0x3FF; -+ u32 clk_greate2_340m : 10 ; // Default: 0x3FF; -+ u32 en_ckdat : 1 ; // Default: 0x3FF; -+ u32 switch_clkch_data_corresponding : 1 ; // Default: 0x3FF; -+ } bits; -+} HDMI_PHY_CTL6_t; //========================================================= 0x009C -+ -+typedef union { -+ u32 dwval; -+ struct { -+ u32 clk_greate3_340m : 10 ; // Default: 0x0; -+ u32 res0 : 2 ; // Default: 0x3FF; -+ u32 clk_low_340m : 10 ; // Default: 0x3FF; -+ u32 res1 : 10 ; // Default: 0x3FF; -+ } bits; -+} HDMI_PHY_CTL7_t; //========================================================= 0x00A0 -+ -+struct __aw_phy_reg_t { -+ u32 res[16]; /* 0x0 ~ 0x3c */ -+ HDMI_PHY_CTL0_t phy_ctl0; /* 0x0040 */ -+ HDMI_PHY_CTL1_t phy_ctl1; /* 0x0044 */ -+ HDMI_PHY_CTL2_t phy_ctl2; /* 0x0048 */ -+ HDMI_PHY_CTL3_t phy_ctl3; /* 0x004c */ -+ HDMI_PHY_CTL4_t phy_ctl4; /* 0x0050 */ -+ HDMI_PHY_CTL5_t phy_ctl5; /* 0x0054 */ -+ HDMI_PLL_CTL0_t pll_ctl0; /* 0x0058 */ -+ HDMI_PLL_CTL1_t pll_ctl1; /* 0x005c */ -+ HDMI_AFIFO_CFG_t afifo_cfg; /* 0x0060 */ -+ HDMI_MODULATOR_CFG0_t modulator_cfg0; /* 0x0064 */ -+ HDMI_MODULATOR_CFG1_t modulator_cfg1; /* 0x0068 */ -+ HDMI_PHY_INDBG_CTRL_t phy_indbg_ctrl; /* 0x006c */ -+ HDMI_PHY_INDBG_TXD0_t phy_indbg_txd0; /* 0x0070 */ -+ HDMI_PHY_INDBG_TXD1_t phy_indbg_txd1; /* 0x0074 */ -+ HDMI_PHY_INDBG_TXD2_t phy_indbg_txd2; /* 0x0078 */ -+ HDMI_PHY_INDBG_TXD3_t phy_indbg_txd3; /* 0x007c */ -+ HDMI_PHY_PLL_STS_t phy_pll_sts; /* 0x0080 */ -+ HDMI_PRBS_CTL_t prbs_ctl; /* 0x0084 */ -+ HDMI_PRBS_SEED_GEN_t prbs_seed_gen; /* 0x0088 */ -+ HDMI_PRBS_SEED_CHK_t prbs_seed_chk; /* 0x008c */ -+ HDMI_PRBS_SEED_NUM_t prbs_seed_num; /* 0x0090 */ -+ HDMI_PRBS_CYCLE_NUM_t prbs_cycle_num; /* 0x0094 */ -+ HDMI_PHY_PLL_ODLY_CFG_t phy_pll_odly_cfg; /* 0x0098 */ -+ HDMI_PHY_CTL6_t phy_ctl6; /* 0x009c */ -+ HDMI_PHY_CTL7_t phy_ctl7; /* 0x00A0 */ -+}; -+ -+#endif /* AW_PHY_H_ */ ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy { - struct clk *clk_pll1; - struct device *dev; - unsigned int rcal; -+ void __iomem *base; - struct regmap *regs; - struct reset_control *rst_phy; - const struct sun8i_hdmi_phy_variant *variant; ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -9,6 +9,8 @@ - - #include "sun8i_dw_hdmi.h" - -+#include "aw_phy.h" -+ - /* - * Address can be actually any value. Here is set to same value as - * it is set in BSP driver. -@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8 - .setup_hpd = dw_hdmi_phy_setup_hpd, - }; - -+static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base) -+{ -+ int i = 0, status = 0; -+ -+ pr_info("enter %s\n", __func__); -+ -+ //enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0] -+ phy_base->phy_ctl4.bits.reg_slv = 4; //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26] -+ phy_base->phy_ctl5.bits.enib = 1; -+ phy_base->phy_ctl0.bits.enldo = 1; -+ phy_base->phy_ctl0.bits.enldo_fs = 1; -+ phy_base->phy_ctl5.bits.enrcal = 1; -+ -+ phy_base->phy_ctl5.bits.encalog = 1; -+ -+ for (i = 0; i < AW_PHY_TIMEOUT; i++) { -+ udelay(5); -+ status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status; -+ if (status & 0x1) { -+ pr_info("[%s]:phy_rcalend2d_status\n", __func__); -+ break; -+ } -+ } -+ if ((i == AW_PHY_TIMEOUT) && !status) { -+ pr_err("phy_rcalend2d_status Timeout !\n"); -+ return -1; -+ } -+ -+ phy_base->phy_ctl0.bits.enbi = 0xF; -+ for (i = 0; i < AW_PHY_TIMEOUT; i++) { -+ udelay(5); -+ status = phy_base->phy_pll_sts.bits.pll_lock_status; -+ if (status & 0x1) { -+ pr_info("[%s]:pll_lock_status\n", __func__); -+ break; -+ } -+ } -+ if ((i == AW_PHY_TIMEOUT) && !status) { -+ pr_err("pll_lock_status Timeout! status = 0x%x\n", status); -+ return -1; -+ } -+ -+ phy_base->phy_ctl0.bits.enck = 1; -+ phy_base->phy_ctl5.bits.enp2s = 0xF; -+ phy_base->phy_ctl5.bits.enres = 1; -+ phy_base->phy_ctl5.bits.enresck = 1; -+ phy_base->phy_ctl0.bits.entx = 0xF; -+ -+ for (i = 0; i < AW_PHY_TIMEOUT; i++) { -+ udelay(5); -+ status = phy_base->phy_pll_sts.bits.tx_ready_dly_status; -+ if (status & 0x1) { -+ pr_info("[%s]:tx_ready_status\n", __func__); -+ break; -+ } -+ } -+ if ((i == AW_PHY_TIMEOUT) && !status) { -+ pr_err("tx_ready_status Timeout ! status = 0x%x\n", status); -+ return -1; -+ } -+ -+ return 0; -+} -+ - static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, - const struct drm_display_info *display, - const struct drm_display_mode *mode) - { - struct sun8i_hdmi_phy *phy = data; -+ volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base; -+ int ret; -+ -+ pr_info("enter %s\n", __func__); -+ -+ /* enable all channel */ -+ phy_base->phy_ctl5.bits.reg_p1opt = 0xF; -+ -+ // phy_reset -+ phy_base->phy_ctl0.bits.entx = 0; -+ phy_base->phy_ctl5.bits.enresck = 0; -+ phy_base->phy_ctl5.bits.enres = 0; -+ phy_base->phy_ctl5.bits.enp2s = 0; -+ phy_base->phy_ctl0.bits.enck = 0; -+ phy_base->phy_ctl0.bits.enbi = 0; -+ phy_base->phy_ctl5.bits.encalog = 0; -+ phy_base->phy_ctl5.bits.enrcal = 0; -+ phy_base->phy_ctl0.bits.enldo_fs = 0; -+ phy_base->phy_ctl0.bits.enldo = 0; -+ phy_base->phy_ctl5.bits.enib = 0; -+ phy_base->pll_ctl1.bits.reset = 1; -+ phy_base->pll_ctl1.bits.pwron = 0; -+ phy_base->pll_ctl0.bits.envbs = 0; -+ -+ // phy_set_mpll -+ phy_base->pll_ctl0.bits.cko_sel = 0x3; -+ phy_base->pll_ctl0.bits.bypass_ppll = 0x1; -+ phy_base->pll_ctl1.bits.drv_ana = 1; -+ phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video 1: MPLL -+ phy_base->pll_ctl1.bits.sdm_en = 0x0; //mpll sdm jitter is very large, not used for the time being -+ phy_base->pll_ctl1.bits.sckref = 0; //default value is 1 -+ phy_base->pll_ctl0.bits.slv = 4; -+ phy_base->pll_ctl0.bits.prop_cntrl = 7; //default value 7 -+ phy_base->pll_ctl0.bits.gmp_cntrl = 3; //default value 1 -+ phy_base->pll_ctl1.bits.ref_cntrl = 0; -+ phy_base->pll_ctl0.bits.vcorange = 1; -+ -+ // phy_set_div -+ phy_base->pll_ctl0.bits.div_pre = 0; //div7 = n+1 -+ phy_base->pll_ctl1.bits.pcnt_en = 0; -+ phy_base->pll_ctl1.bits.pcnt_n = 1; //div6 = 1 (pcnt_en=0) [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256 -+ phy_base->pll_ctl1.bits.pixel_rep = 0; //div5 = n+1 -+ phy_base->pll_ctl0.bits.bypass_clrdpth = 0; -+ phy_base->pll_ctl0.bits.clr_dpth = 0; //div4 = 1 (bypass_clrdpth = 0) -+ //00: 2 01: 2.5 10: 3 11: 4 -+ phy_base->pll_ctl0.bits.n_cntrl = 1; //div -+ phy_base->pll_ctl0.bits.div2_ckbit = 0; //div1 = n+1 -+ phy_base->pll_ctl0.bits.div2_cktmds = 0; //div2 = n+1 -+ phy_base->pll_ctl0.bits.bcr = 0; //div3 0: [1:10] 1: [1:40] -+ phy_base->pll_ctl1.bits.pwron = 1; -+ phy_base->pll_ctl1.bits.reset = 0; -+ -+ // configure phy -+ /* config values taken from table */ -+ phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0); -+ phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0); -+ phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF); -+ phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D); -+ //phy_base->pll_ctl0.dwval |= config->pll_ctl0; -+ //phy_base->pll_ctl1.dwval |= config->pll_ctl1; -+ -+ // phy_set_clk -+ phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0; -+ phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF; -+ phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF; -+ phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0; -+ phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0; -+ phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0; -+ phy_base->phy_ctl6.bits.en_ckdat = 1; //default value is 0 -+ -+ // phy_base->phy_ctl2.bits.reg_resdi = 0x18; -+ // phy_base->phy_ctl4.bits.reg_slv = 3; //low power voltage 1.08V, default value is 3 -+ -+ phy_base->phy_ctl1.bits.res_scktmds = 0; // -+ phy_base->phy_ctl0.bits.reg_csmps = 2; -+ phy_base->phy_ctl0.bits.reg_ck_test_sel = 0; //? -+ phy_base->phy_ctl0.bits.reg_ck_sel = 1; -+ phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0; -+ -+ // phy_enable -+ ret = sun20i_d1_hdmi_phy_enable(phy_base); -+ if (ret) -+ return ret; -+ -+ phy_base->phy_ctl0.bits.sda_en = 1; -+ phy_base->phy_ctl0.bits.scl_en = 1; -+ phy_base->phy_ctl0.bits.hpd_en = 1; -+ phy_base->phy_ctl0.bits.reg_den = 0xF; -+ phy_base->pll_ctl0.bits.envbs = 1; - - return 0; - } -@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p - return dev_err_probe(dev, PTR_ERR(regs), - "Couldn't map the HDMI PHY registers\n"); - -+ phy->base = regs; - phy->regs = devm_regmap_init_mmio(dev, regs, - &sun8i_hdmi_phy_regmap_config); - if (IS_ERR(phy->regs)) diff --git a/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch b/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch new file mode 100644 index 0000000000..345504d321 --- /dev/null +++ b/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch @@ -0,0 +1,274 @@ +From c8c3c516ca5c38e7858055ce0137efde17a07190 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:04 +0300 +Subject: [PATCH 10/14] ASoC: sunxi: Add new driver for Allwinner D1/T113s + codec's analog path controls + +The internal codec on D1/T113s is split into 2 parts like the previous +ones. But now analog path controls registers are mapped directly +on the bus, right after the registers of the digital part. + +Add an ASoC component driver for it. This should be tied to the codec +audio card as an auxiliary device. + +Signed-off-by: Maksim Kiselev +--- + sound/soc/sunxi/Kconfig | 11 ++ + sound/soc/sunxi/Makefile | 1 + + sound/soc/sunxi/sun20i-d1-codec-analog.c | 220 +++++++++++++++++++++++ + 3 files changed, 232 insertions(+) + create mode 100644 sound/soc/sunxi/sun20i-d1-codec-analog.c + +--- a/sound/soc/sunxi/Kconfig ++++ b/sound/soc/sunxi/Kconfig +@@ -38,6 +38,17 @@ config SND_SUN50I_CODEC_ANALOG + Say Y or M if you want to add support for the analog controls for + the codec embedded in Allwinner A64 SoC. + ++config SND_SUN20I_D1_CODEC_ANALOG ++ tristate "Allwinner D1 Codec Analog Controls Support" ++ depends on ARCH_SUNXI || COMPILE_TEST ++ select REGMAP_MMIO ++ help ++ This option enables the analog controls part of the internal audio ++ codec for Allwinner D1/T113s SoCs family. ++ ++ Say Y or M if you want to add support for the analog part of ++ the D1/T113s audio codec. ++ + config SND_SUN4I_I2S + tristate "Allwinner A10 I2S Support" + select SND_SOC_GENERIC_DMAENGINE_PCM +--- a/sound/soc/sunxi/Makefile ++++ b/sound/soc/sunxi/Makefile +@@ -4,6 +4,7 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s + obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o + obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o + obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o ++obj-$(CONFIG_SND_SUN20I_D1_CODEC_ANALOG) += sun20i-d1-codec-analog.o + obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o + obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o + obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o +--- /dev/null ++++ b/sound/soc/sunxi/sun20i-d1-codec-analog.c +@@ -0,0 +1,220 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * This driver supports the analog controls for the internal codec ++ * found in Allwinner's D1/T113s SoCs family. ++ * ++ * Based on sun50i-codec-analog.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* Codec analog control register offsets and bit fields */ ++#define SUN20I_D1_ADDA_ADC1 (0x00) ++#define SUN20I_D1_ADDA_ADC2 (0x04) ++#define SUN20I_D1_ADDA_ADC3 (0x08) ++#define SUN20I_D1_ADDA_ADC_EN (31) ++#define SUN20I_D1_ADDA_ADC_PGA_EN (30) ++#define SUN20I_D1_ADDA_ADC_MIC_SIN_EN (28) ++#define SUN20I_D1_ADDA_ADC_LINEINLEN (23) ++#define SUN20I_D1_ADDA_ADC_PGA_GAIN (8) ++ ++#define SUN20I_D1_ADDA_DAC (0x10) ++#define SUN20I_D1_ADDA_DAC_DACL_EN (15) ++#define SUN20I_D1_ADDA_DAC_DACR_EN (14) ++ ++#define SUN20I_D1_ADDA_MICBIAS (0x18) ++#define SUN20I_D1_ADDA_MICBIAS_MMICBIASEN (7) ++ ++#define SUN20I_D1_ADDA_RAMP (0x1C) ++#define SUN20I_D1_ADDA_RAMP_RD_EN (0) ++ ++#define SUN20I_D1_ADDA_HP2 (0x40) ++#define SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN (28) ++ ++#define SUN20I_D1_ADDA_ADC_CUR_REG (0x4C) ++ ++static const DECLARE_TLV_DB_RANGE(sun20i_d1_codec_adc_gain_scale, ++ 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), ++ 1, 3, TLV_DB_SCALE_ITEM(600, 0, 0), ++ 4, 4, TLV_DB_SCALE_ITEM(900, 0, 0), ++ 5, 31, TLV_DB_SCALE_ITEM(1000, 100, 0), ++); ++ ++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_hp_vol_scale, -4200, 600, 0); ++ ++/* volume controls */ ++static const struct snd_kcontrol_new sun20i_d1_codec_controls[] = { ++ SOC_SINGLE_TLV("Headphone Playback Volume", ++ SUN20I_D1_ADDA_HP2, ++ SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN, 0x7, 1, ++ sun20i_d1_codec_hp_vol_scale), ++ SOC_SINGLE_TLV("ADC1 Gain Capture Volume", ++ SUN20I_D1_ADDA_ADC1, ++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0, ++ sun20i_d1_codec_adc_gain_scale), ++ SOC_SINGLE_TLV("ADC2 Gain Capture Volume", ++ SUN20I_D1_ADDA_ADC2, ++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0, ++ sun20i_d1_codec_adc_gain_scale), ++ SOC_SINGLE_TLV("ADC3 Gain Capture Volume", ++ SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0, ++ sun20i_d1_codec_adc_gain_scale), ++}; ++ ++/* ADC mixer controls */ ++static const struct snd_kcontrol_new sun20i_d1_codec_mixer_controls[] = { ++ SOC_DAPM_DOUBLE_R("Line In Switch", ++ SUN20I_D1_ADDA_ADC1, ++ SUN20I_D1_ADDA_ADC2, ++ SUN20I_D1_ADDA_ADC_LINEINLEN, 1, 0), ++}; ++ ++static const char * const sun20i_d1_codec_mic3_src_enum_text[] = { ++ "Differential", "Single", ++}; ++ ++static SOC_ENUM_SINGLE_DECL(sun20i_d1_codec_mic3_src_enum, ++ SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_MIC_SIN_EN, ++ sun20i_d1_codec_mic3_src_enum_text); ++ ++static const struct snd_kcontrol_new sun20i_d1_codec_mic3_input_src[] = { ++ SOC_DAPM_ENUM("MIC3 Source Capture Route", ++ sun20i_d1_codec_mic3_src_enum), ++}; ++ ++static const struct snd_soc_dapm_widget sun20i_d1_codec_widgets[] = { ++ /* DAC */ ++ SND_SOC_DAPM_DAC("Left DAC", NULL, SUN20I_D1_ADDA_DAC, ++ SUN20I_D1_ADDA_DAC_DACL_EN, 0), ++ SND_SOC_DAPM_DAC("Right DAC", NULL, SUN20I_D1_ADDA_DAC, ++ SUN20I_D1_ADDA_DAC_DACR_EN, 0), ++ /* ADC */ ++ SND_SOC_DAPM_ADC("ADC1", NULL, SUN20I_D1_ADDA_ADC1, ++ SUN20I_D1_ADDA_ADC_EN, 0), ++ SND_SOC_DAPM_ADC("ADC2", NULL, SUN20I_D1_ADDA_ADC2, ++ SUN20I_D1_ADDA_ADC_EN, 0), ++ SND_SOC_DAPM_ADC("ADC3", NULL, SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_EN, 0), ++ ++ /* ADC Mixers */ ++ SND_SOC_DAPM_MIXER("ADC1 Mixer", SND_SOC_NOPM, 0, 0, ++ sun20i_d1_codec_mixer_controls, ++ ARRAY_SIZE(sun20i_d1_codec_mixer_controls)), ++ SND_SOC_DAPM_MIXER("ADC2 Mixer", SND_SOC_NOPM, 0, 0, ++ sun20i_d1_codec_mixer_controls, ++ ARRAY_SIZE(sun20i_d1_codec_mixer_controls)), ++ ++ /* Headphone */ ++ SND_SOC_DAPM_OUTPUT("HP"), ++ SND_SOC_DAPM_SUPPLY("RAMP Enable", SUN20I_D1_ADDA_RAMP, ++ SUN20I_D1_ADDA_RAMP_RD_EN, 0, NULL, 0), ++ ++ /* Line input */ ++ SND_SOC_DAPM_INPUT("LINEIN"), ++ ++ /* Microphone input */ ++ SND_SOC_DAPM_INPUT("MIC3"), ++ ++ /* Microphone input path */ ++ SND_SOC_DAPM_MUX("MIC3 Source Capture Route", SND_SOC_NOPM, 0, 0, ++ sun20i_d1_codec_mic3_input_src), ++ ++ SND_SOC_DAPM_PGA("Mic3 Amplifier", SUN20I_D1_ADDA_ADC3, ++ SUN20I_D1_ADDA_ADC_PGA_EN, 0, NULL, 0), ++ ++ /* Microphone Bias */ ++ SND_SOC_DAPM_SUPPLY("MBIAS", SUN20I_D1_ADDA_MICBIAS, ++ SUN20I_D1_ADDA_MICBIAS_MMICBIASEN, 0, NULL, 0), ++}; ++ ++static const struct snd_soc_dapm_route sun20i_d1_codec_routes[] = { ++ /* Headphone Routes */ ++ { "HP", NULL, "Left DAC" }, ++ { "HP", NULL, "Right DAC" }, ++ { "HP", NULL, "RAMP Enable" }, ++ ++ /* Line input Routes */ ++ { "ADC1", NULL, "ADC1 Mixer" }, ++ { "ADC2", NULL, "ADC2 Mixer" }, ++ { "ADC1 Mixer", "Line In Switch", "LINEIN" }, ++ { "ADC2 Mixer", "Line In Switch", "LINEIN" }, ++ ++ /* Microphone Routes */ ++ { "MIC3 Source Capture Route", "Differential", "MIC3" }, ++ { "MIC3 Source Capture Route", "Single", "MIC3" }, ++ { "Mic3 Amplifier", NULL, "MIC3 Source Capture Route" }, ++ { "ADC3", NULL, "Mic3 Amplifier" }, ++}; ++ ++static const struct snd_soc_component_driver sun20i_d1_codec_analog_cmpnt_drv = { ++ .controls = sun20i_d1_codec_controls, ++ .num_controls = ARRAY_SIZE(sun20i_d1_codec_controls), ++ .dapm_widgets = sun20i_d1_codec_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun20i_d1_codec_widgets), ++ .dapm_routes = sun20i_d1_codec_routes, ++ .num_dapm_routes = ARRAY_SIZE(sun20i_d1_codec_routes), ++}; ++ ++static const struct of_device_id sun20i_d1_codec_analog_of_match[] = { ++ { ++ .compatible = "allwinner,sun20i-d1-codec-analog", ++ }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sun20i_d1_codec_analog_of_match); ++ ++static const struct regmap_config sun20i_d1_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUN20I_D1_ADDA_ADC_CUR_REG, ++}; ++ ++static int sun20i_d1_codec_analog_probe(struct platform_device *pdev) ++{ ++ struct regmap *regmap; ++ void __iomem *base; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) { ++ dev_err(&pdev->dev, "Failed to map the registers\n"); ++ return PTR_ERR(base); ++ } ++ ++ regmap = devm_regmap_init_mmio(&pdev->dev, base, ++ &sun20i_d1_codec_regmap_config); ++ if (IS_ERR(regmap)) { ++ dev_err(&pdev->dev, "Failed to create regmap\n"); ++ return PTR_ERR(regmap); ++ } ++ ++ return devm_snd_soc_register_component(&pdev->dev, ++ &sun20i_d1_codec_analog_cmpnt_drv, ++ NULL, 0); ++} ++ ++static struct platform_driver sun20i_d1_codec_analog_driver = { ++ .driver = { ++ .name = "sun20i-d1-codec-analog", ++ .of_match_table = sun20i_d1_codec_analog_of_match, ++ }, ++ .probe = sun20i_d1_codec_analog_probe, ++}; ++module_platform_driver(sun20i_d1_codec_analog_driver); ++ ++MODULE_DESCRIPTION("Allwinner internal codec analog controls driver for D1"); ++MODULE_AUTHOR("Maksim Kiselev "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:sun20i-d1-codec-analog"); diff --git a/target/linux/d1/patches-6.6/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch b/target/linux/d1/patches-6.6/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch deleted file mode 100644 index 18dfa573e3..0000000000 --- a/target/linux/d1/patches-6.6/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Wed, 27 Apr 2022 18:47:53 -0500 -Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available - -Signed-off-by: Samuel Holland ---- - arch/riscv/mm/dma-noncoherent.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/riscv/mm/dma-noncoherent.c -+++ b/arch/riscv/mm/dma-noncoherent.c -@@ -7,6 +7,7 @@ - - #include - #include -+#include - #include - #include - -@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d - dev_driver_string(dev), dev_name(dev)); - - dev->dma_coherent = coherent; -+ -+ if (iommu) -+ iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); - } - - void riscv_noncoherent_supported(void) diff --git a/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch b/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch new file mode 100644 index 0000000000..06bd159998 --- /dev/null +++ b/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch @@ -0,0 +1,51 @@ +From 16728b748a44f1cea060a6ba57453c03e3745c1d Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Mon, 18 Dec 2023 00:06:22 +0300 +Subject: [PATCH 11/14] dt-bindings: thermal: sun8i: Add binding for D1/T113s + THS controller + +Add a binding for D1/T113s thermal sensor controller. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Conor Dooley +--- + .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml ++++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +@@ -16,6 +16,7 @@ properties: + - allwinner,sun8i-a83t-ths + - allwinner,sun8i-h3-ths + - allwinner,sun8i-r40-ths ++ - allwinner,sun20i-d1-ths + - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h5-ths +@@ -61,6 +62,7 @@ allOf: + compatible: + contains: + enum: ++ - allwinner,sun20i-d1-ths + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h6-ths + +@@ -84,7 +86,9 @@ allOf: + properties: + compatible: + contains: +- const: allwinner,sun8i-h3-ths ++ enum: ++ - allwinner,sun8i-h3-ths ++ - allwinner,sun20i-d1-ths + + then: + properties: +@@ -103,6 +107,7 @@ allOf: + enum: + - allwinner,sun8i-h3-ths + - allwinner,sun8i-r40-ths ++ - allwinner,sun20i-d1-ths + - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h5-ths diff --git a/target/linux/d1/patches-6.6/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch b/target/linux/d1/patches-6.6/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch deleted file mode 100644 index d8dd2878d1..0000000000 --- a/target/linux/d1/patches-6.6/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch +++ /dev/null @@ -1,124 +0,0 @@ -From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 7 May 2022 18:34:25 -0500 -Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs - -irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE | -IRQCHIP_EOI_THREADED to elide mask operations. - -Signed-off-by: Samuel Holland ---- - kernel/irq/chip.c | 36 +++++++++++++++++------------------- - kernel/irq/internals.h | 2 +- - kernel/irq/manage.c | 12 ++++++------ - 3 files changed, 24 insertions(+), 26 deletions(-) - ---- a/kernel/irq/chip.c -+++ b/kernel/irq/chip.c -@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc) - } - } - --void unmask_threaded_irq(struct irq_desc *desc) --{ -- struct irq_chip *chip = desc->irq_data.chip; -- -- if (chip->flags & IRQCHIP_EOI_THREADED) -- chip->irq_eoi(&desc->irq_data); -- -- unmask_irq(desc); --} -- - /* - * handle_nested_irq - Handle a nested irq from a irq thread - * @irq: the interrupt number -@@ -656,25 +646,33 @@ out_unlock: - } - EXPORT_SYMBOL_GPL(handle_level_irq); - --static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) -+void unmask_eoi_threaded_irq(struct irq_desc *desc) - { -- if (!(desc->istate & IRQS_ONESHOT)) { -+ struct irq_chip *chip = desc->irq_data.chip; -+ -+ if (desc->istate & IRQS_ONESHOT) -+ unmask_irq(desc); -+ -+ if (chip->flags & IRQCHIP_EOI_THREADED) - chip->irq_eoi(&desc->irq_data); -+} -+ -+static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) -+{ -+ /* Do not send EOI if the thread will do it for us. */ -+ if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot) - return; -- } -+ - /* - * We need to unmask in the following cases: - * - Oneshot irq which did not wake the thread (caused by a - * spurious interrupt or a primary handler handling it - * completely). - */ -- if (!irqd_irq_disabled(&desc->irq_data) && -- irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { -- chip->irq_eoi(&desc->irq_data); -+ if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot) - unmask_irq(desc); -- } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { -- chip->irq_eoi(&desc->irq_data); -- } -+ -+ chip->irq_eoi(&desc->irq_data); - } - - /** ---- a/kernel/irq/internals.h -+++ b/kernel/irq/internals.h -@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq - extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu); - extern void mask_irq(struct irq_desc *desc); - extern void unmask_irq(struct irq_desc *desc); --extern void unmask_threaded_irq(struct irq_desc *desc); -+extern void unmask_eoi_threaded_irq(struct irq_desc *desc); - - #ifdef CONFIG_SPARSE_IRQ - static inline void irq_mark_irq(unsigned int irq) { } ---- a/kernel/irq/manage.c -+++ b/kernel/irq/manage.c -@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct - static void irq_finalize_oneshot(struct irq_desc *desc, - struct irqaction *action) - { -- if (!(desc->istate & IRQS_ONESHOT) || -- action->handler == irq_forced_secondary_handler) -+ if (action->handler == irq_forced_secondary_handler) - return; -+ - again: - chip_bus_lock(desc); - raw_spin_lock_irq(&desc->lock); -@@ -1112,9 +1112,8 @@ again: - - desc->threads_oneshot &= ~action->thread_mask; - -- if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && -- irqd_irq_masked(&desc->irq_data)) -- unmask_threaded_irq(desc); -+ if (!desc->threads_oneshot) -+ unmask_eoi_threaded_irq(desc); - - out_unlock: - raw_spin_unlock_irq(&desc->lock); -@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq - * !ONESHOT irqs the thread mask is 0 so we can avoid a - * conditional in irq_wake_thread(). - */ -- if (new->flags & IRQF_ONESHOT) { -+ if ((new->flags & IRQF_ONESHOT) || -+ (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) { - /* - * Unlikely to have 32 resp 64 irqs sharing one line, - * but who knows. diff --git a/target/linux/d1/patches-6.6/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch b/target/linux/d1/patches-6.6/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch deleted file mode 100644 index 8cb949f186..0000000000 --- a/target/linux/d1/patches-6.6/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 7 May 2022 18:38:34 -0500 -Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded - EOIs - -Signed-off-by: Samuel Holland ---- - drivers/irqchip/irq-sifive-plic.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -207,7 +207,9 @@ static struct irq_chip plic_chip = { - .irq_set_affinity = plic_set_affinity, - #endif - .irq_set_type = plic_irq_set_type, -- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, -+ .flags = IRQCHIP_ONESHOT_SAFE | -+ IRQCHIP_EOI_THREADED | -+ IRQCHIP_AFFINITY_PRE_STARTUP, - }; - - static int plic_irq_set_type(struct irq_data *d, unsigned int type) diff --git a/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch new file mode 100644 index 0000000000..a7ded59868 --- /dev/null +++ b/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch @@ -0,0 +1,45 @@ +From eb7e78f9e4bb9133898875afb0e0b9f09663e802 Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Mon, 18 Dec 2023 00:06:23 +0300 +Subject: [PATCH 12/14] thermal: sun8i: Add D1/T113s THS controller support + +This patch adds a thermal sensor controller support for the D1/T113s, +which is similar to the one on H6, but with only one sensor and +different scale and offset values. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Andre Przywara +Acked-by: Jernej Skrabec +--- + drivers/thermal/sun8i_thermal.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/drivers/thermal/sun8i_thermal.c ++++ b/drivers/thermal/sun8i_thermal.c +@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun + .calc_temp = sun8i_ths_calc_temp, + }; + ++static const struct ths_thermal_chip sun20i_d1_ths = { ++ .sensor_num = 1, ++ .has_bus_clk_reset = true, ++ .offset = 188552, ++ .scale = 673, ++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, ++ .calibrate = sun50i_h6_ths_calibrate, ++ .init = sun50i_h6_thermal_init, ++ .irq_ack = sun50i_h6_irq_ack, ++ .calc_temp = sun8i_ths_calc_temp, ++}; ++ + static const struct of_device_id of_ths_match[] = { + { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, +@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_ + { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, + { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, + { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, ++ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/d1/patches-6.6/0013-irqchip-sifive-plic-Support-wake-IRQs.patch b/target/linux/d1/patches-6.6/0013-irqchip-sifive-plic-Support-wake-IRQs.patch deleted file mode 100644 index 209d97597c..0000000000 --- a/target/linux/d1/patches-6.6/0013-irqchip-sifive-plic-Support-wake-IRQs.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 28 May 2022 19:04:56 -0500 -Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs - -Signed-off-by: Samuel Holland ---- - drivers/irqchip/irq-sifive-plic.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -193,7 +193,8 @@ static struct irq_chip plic_edge_chip = - .irq_set_affinity = plic_set_affinity, - #endif - .irq_set_type = plic_irq_set_type, -- .flags = IRQCHIP_AFFINITY_PRE_STARTUP, -+ .flags = IRQCHIP_SKIP_SET_WAKE | -+ IRQCHIP_AFFINITY_PRE_STARTUP, - }; - - static struct irq_chip plic_chip = { -@@ -207,7 +208,8 @@ static struct irq_chip plic_chip = { - .irq_set_affinity = plic_set_affinity, - #endif - .irq_set_type = plic_irq_set_type, -- .flags = IRQCHIP_ONESHOT_SAFE | -+ .flags = IRQCHIP_SKIP_SET_WAKE | -+ IRQCHIP_ONESHOT_SAFE | - IRQCHIP_EOI_THREADED | - IRQCHIP_AFFINITY_PRE_STARTUP, - }; diff --git a/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch b/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch new file mode 100644 index 0000000000..f8318c8207 --- /dev/null +++ b/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch @@ -0,0 +1,47 @@ +From 196423a17b92ef241766691b42dac0136342bdb5 Mon Sep 17 00:00:00 2001 +From: Maxim Kiselev +Date: Mon, 18 Dec 2023 00:06:24 +0300 +Subject: [PATCH 13/14] riscv: dts: allwinner: d1: Add thermal sensor + +This patch adds a thermal sensor controller node for the D1/T113s. +Also it adds a THS calibration data cell to efuse node. + +Signed-off-by: Maxim Kiselev +Reviewed-by: Andre Przywara +--- + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -166,6 +166,19 @@ + #io-channel-cells = <1>; + }; + ++ ths: thermal-sensor@2009400 { ++ compatible = "allwinner,sun20i-d1-ths"; ++ reg = <0x02009400 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_THS>; ++ clock-names = "bus"; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ status = "disabled"; ++ #thermal-sensor-cells = <0>; ++ }; ++ + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; +@@ -415,6 +428,10 @@ + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@14 { ++ reg = <0x14 0x4>; ++ }; + }; + + crypto: crypto@3040000 { diff --git a/target/linux/d1/patches-6.6/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch b/target/linux/d1/patches-6.6/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch deleted file mode 100644 index 7e8098a2cf..0000000000 --- a/target/linux/d1/patches-6.6/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 13 Jun 2021 23:15:56 -0500 -Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size - -According to the DMA descriptor documentation, the lowest two bits of -the size field are ignored, so the size must be rounded up to a multiple -of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size -to 0 will cause that DMA descriptor to be ignored. - -Together, these restrictions limit the maximum DMA segment size to 4 -less than the power-of-two width of the size field. - -Series-to: Ulf Hansson -Series-to: linux-mmc@vger.kernel.org - -Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs") -Signed-off-by: Samuel Holland ---- - drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/sunxi-mmc.c -+++ b/drivers/mmc/host/sunxi-mmc.c -@@ -214,6 +214,9 @@ - #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ - #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ - -+/* Buffer size must be a multiple of 4 bytes. */ -+#define SDXC_IDMAC_SIZE_ALIGN 4 -+ - #define SDXC_CLK_400K 0 - #define SDXC_CLK_25M 1 - #define SDXC_CLK_50M 2 -@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru - { - struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; - dma_addr_t next_desc = host->sg_dma; -- int i, max_len = (1 << host->cfg->idma_des_size_bits); -+ int i; - - for (i = 0; i < data->sg_len; i++) { - pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | - SDXC_IDMAC_DES0_OWN | - SDXC_IDMAC_DES0_DIC); - -- if (data->sg[i].length == max_len) -- pdes[i].buf_size = 0; /* 0 == max_len */ -- else -- pdes[i].buf_size = cpu_to_le32(data->sg[i].length); -+ pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length, -+ SDXC_IDMAC_SIZE_ALIGN)); - - next_desc += sizeof(struct sunxi_idma_des); - pdes[i].buf_addr_ptr1 = -@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo - mmc->max_blk_count = 8192; - mmc->max_blk_size = 4096; - mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); -- mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); -+ mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits) - -+ SDXC_IDMAC_SIZE_ALIGN; - mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; - /* 400kHz ~ 52MHz */ - mmc->f_min = 400000; diff --git a/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch b/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch new file mode 100644 index 0000000000..14a4c3c131 --- /dev/null +++ b/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch @@ -0,0 +1,44 @@ +From edebcc9d47f0bfe9bd769a2c578dda16acbfbef2 Mon Sep 17 00:00:00 2001 +From: Maksim Kiselev +Date: Sat, 5 Aug 2023 21:05:05 +0300 +Subject: [PATCH 14/14] riscv: dts: allwinner: d1: Add device nodes for + internal audio codec + +Add DT nodes for the internal D1/T113s audio codec and its analog part. + +Signed-off-by: Maksim Kiselev +--- + .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi ++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +@@ -179,6 +179,28 @@ + #thermal-sensor-cells = <0>; + }; + ++ codec: codec@2030000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun20i-d1-codec"; ++ reg = <0x02030000 0x300>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_AUDIO>, ++ <&ccu CLK_AUDIO_ADC>, ++ <&ccu CLK_AUDIO_DAC>; ++ clock-names = "apb", "adc", "dac"; ++ resets = <&ccu RST_BUS_AUDIO>; ++ dmas = <&dma 7>, <&dma 7>; ++ dma-names = "rx", "tx"; ++ allwinner,codec-analog-controls = <&codec_analog>; ++ status = "disabled"; ++ }; ++ ++ codec_analog: codec-analog@2030300 { ++ compatible = "allwinner,sun20i-d1-codec-analog"; ++ reg = <0x02030300 0xd00>; ++ status = "disabled"; ++ }; ++ + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; diff --git a/target/linux/d1/patches-6.6/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch b/target/linux/d1/patches-6.6/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch deleted file mode 100644 index 665c55058c..0000000000 --- a/target/linux/d1/patches-6.6/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch +++ /dev/null @@ -1,82 +0,0 @@ -From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001 -From: Max Fierke -Date: Wed, 1 Jun 2022 00:17:47 -0500 -Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi - CWD686 - -The CWD686 is a 6.86" IPS LCD panel used as the primary -display in the ClockworkPi DevTerm portable (all cores) - -Signed-off-by: Max Fierke -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Samuel Holland ---- - .../display/panel/clockwork,cwd686.yaml | 62 +++++++++++++++++++ - 1 file changed, 62 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml -@@ -0,0 +1,62 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Clockwork CWD686 6.86" IPS LCD panel -+ -+maintainers: -+ - Max Fierke -+ -+description: | -+ The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the -+ Clockwork DevTerm series of portable devices. The panel has a 480x1280 -+ resolution and uses 24 bit RGB per pixel. -+ -+allOf: -+ - $ref: panel-common.yaml# -+ -+properties: -+ compatible: -+ const: clockwork,cwd686 -+ -+ reg: -+ description: DSI virtual channel used by that screen -+ maxItems: 1 -+ -+ reset-gpios: true -+ rotation: true -+ backlight: true -+ iovcc-supply: true -+ vci-supply: true -+ -+required: -+ - compatible -+ - reg -+ - backlight -+ - reset-gpios -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ backlight: backlight { -+ compatible = "gpio-backlight"; -+ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ dsi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ panel@0 { -+ compatible = "clockwork,cwd686"; -+ reg = <0>; -+ backlight = <&backlight>; -+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; -+ rotation = <90>; -+ }; -+ }; diff --git a/target/linux/d1/patches-6.6/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch b/target/linux/d1/patches-6.6/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch deleted file mode 100644 index 85d8421f62..0000000000 --- a/target/linux/d1/patches-6.6/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch +++ /dev/null @@ -1,47 +0,0 @@ -From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 12 Aug 2022 01:59:35 -0500 -Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel - binding - -Signed-off-by: Samuel Holland ---- - .../display/panel/sitronix,st7701s.yaml | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml -@@ -0,0 +1,32 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sitronix ST7701 based LCD panels -+ -+maintainers: -+ - Samuel Holland -+ -+description: | -+ Panel used on Lichee RV 86 Panel -+ -+allOf: -+ - $ref: panel-common.yaml# -+ - $ref: /schemas/spi/spi-peripheral-props.yaml# -+ -+properties: -+ compatible: -+ items: -+ - const: sitronix,st7701s -+ -+ backlight: true -+ -+ reset-gpios: true -+ -+required: -+ - compatible -+ - reset-gpios -+ -+unevaluatedProperties: false diff --git a/target/linux/d1/patches-6.6/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch b/target/linux/d1/patches-6.6/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch deleted file mode 100644 index 535478cf9e..0000000000 --- a/target/linux/d1/patches-6.6/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch +++ /dev/null @@ -1,487 +0,0 @@ -From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Tue, 29 Mar 2022 22:47:57 -0500 -Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel - -Signed-off-by: Samuel Holland ---- - drivers/gpu/drm/panel/Kconfig | 8 + - drivers/gpu/drm/panel/Makefile | 1 + - .../gpu/drm/panel/panel-sitronix-st7701s.c | 444 ++++++++++++++++++ - 3 files changed, 453 insertions(+) - create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c - ---- a/drivers/gpu/drm/panel/Kconfig -+++ b/drivers/gpu/drm/panel/Kconfig -@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701 - ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI - system interfaces. - -+config DRM_PANEL_SITRONIX_ST7701S -+ tristate "Sitronix ST7701s panel driver" -+ depends on OF -+ depends on BACKLIGHT_CLASS_DEVICE -+ help -+ Say Y here if you want to enable support for the Sitronix -+ ST7701s controller with a SPI interface. -+ - config DRM_PANEL_SITRONIX_ST7703 - tristate "Sitronix ST7703 based MIPI touchscreen panels" - depends on OF ---- a/drivers/gpu/drm/panel/Makefile -+++ b/drivers/gpu/drm/panel/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01 - obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o - obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o - obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o -+obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o - obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o - obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o - obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o ---- /dev/null -+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c -@@ -0,0 +1,444 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2017 Free Electrons -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include