From: Álvaro Fernández Rojas Date: Mon, 1 Mar 2021 07:21:59 +0000 (+0100) Subject: bmips: add experimental ethernet support X-Git-Tag: v22.03.0-rc1~3116 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=28dcb74de3a15fbdb0fd9afa16457b2de1181cd7;p=openwrt%2Fstaging%2Fpepe2k.git bmips: add experimental ethernet support This adds experimental ethernet support for BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268. BCM6358 needs a different driver, so there's no support for now. Working devices: - Comtrend AR-5315u - Comtrend AR-5387un - Comtrend VR-3025u - Comtrend VR-3032u Not working devices: - Netgear DGND3700 v2 (no idea on how the external switch is connected) - Huawei HG556a ver B (BCM6358 needs a separate driveer) Signed-off-by: Álvaro Fernández Rojas --- diff --git a/target/linux/bmips/Makefile b/target/linux/bmips/Makefile index 0adc8cd97e..14eff38bb6 100644 --- a/target/linux/bmips/Makefile +++ b/target/linux/bmips/Makefile @@ -18,6 +18,6 @@ endef include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES += kmod-gpio-button-hotplug +DEFAULT_PACKAGES += ethtool kmod-gpio-button-hotplug $(eval $(call BuildTarget)) diff --git a/target/linux/bmips/config-5.10 b/target/linux/bmips/config-5.10 index 749cc0eb69..96a7547593 100644 --- a/target/linux/bmips/config-5.10 +++ b/target/linux/bmips/config-5.10 @@ -3,8 +3,15 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_B53=y +# CONFIG_B53_MDIO_DRIVER is not set +CONFIG_B53_MMAP_DRIVER=y +# CONFIG_B53_SERDES is not set +CONFIG_B53_SPI_DRIVER=y +# CONFIG_B53_SRAB_DRIVER is not set CONFIG_BCM6345_EXT_IRQ=y CONFIG_BCM6345_L1_IRQ=y +CONFIG_BCM6368_ENETSW=y CONFIG_BCM63XX_POWER=y CONFIG_BCM7038_L1_IRQ=y CONFIG_BCM7038_WDT=y @@ -103,6 +110,7 @@ CONFIG_GPIOLIB=y # CONFIG_GPIO_BRCMSTB is not set CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GRO_CELLS=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y @@ -128,6 +136,8 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_BUS_MUX_BCM6368=y CONFIG_MDIO_DEVICE=y CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y @@ -163,7 +173,14 @@ CONFIG_MTD_CFI_STAA=y CONFIG_MTD_JEDECPROBE=y # CONFIG_MTD_PARSER_IMAGETAG is not set CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_BRCM=y +CONFIG_NET_DSA_TAG_BRCM_COMMON=y +CONFIG_NET_DSA_TAG_BRCM_LEGACY=y +CONFIG_NET_DSA_TAG_BRCM_PREPEND=y CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_SWITCHDEV=y CONFIG_NO_EXCEPT_FILL=y CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y CONFIG_NR_CPUS=2 @@ -181,6 +198,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y +CONFIG_PHYLINK=y CONFIG_PHYSICAL_START=0x80010000 CONFIG_PHY_BCM63XX_USBH=y # CONFIG_PHY_BRCM_SATA is not set diff --git a/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts b/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts index ed7f51890c..d82247d26c 100644 --- a/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts +++ b/target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts @@ -39,6 +39,12 @@ status = "okay"; }; +ðernet { + status = "okay"; + + mtd-mac-address = <&cferom 0x6a0>; +}; + &leds { status = "okay"; @@ -177,6 +183,38 @@ status = "okay"; }; +&switch0 { + ports { + port@0 { + reg = <0>; + label = "lan2"; + + phy-handle = <&phy1>; + }; + + port@1 { + reg = <1>; + label = "lan3"; + + phy-handle = <&phy2>; + }; + + port@2 { + reg = <2>; + label = "lan4"; + + phy-handle = <&phy3>; + }; + + port@3 { + reg = <3>; + label = "lan1"; + + phy-handle = <&phy4>; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts b/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts index 35c74fd3ac..a5ae435a3a 100644 --- a/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts +++ b/target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts @@ -37,6 +37,12 @@ status = "okay"; }; +ðernet { + status = "okay"; + + mtd-mac-address = <&cfe 0x6a0>; +}; + &hsspi { status = "okay"; @@ -168,6 +174,38 @@ }; }; +&switch0 { + ports { + port@0 { + reg = <0>; + label = "lan4"; + + phy-handle = <&phy1>; + }; + + port@1 { + reg = <1>; + label = "lan3"; + + phy-handle = <&phy2>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + + phy-handle = <&phy3>; + }; + + port@3 { + reg = <3>; + label = "lan1"; + + phy-handle = <&phy4>; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/target/linux/bmips/dts/bcm6318.dtsi b/target/linux/bmips/dts/bcm6318.dtsi index f5cfd77438..e7dc38e937 100644 --- a/target/linux/bmips/dts/bcm6318.dtsi +++ b/target/linux/bmips/dts/bcm6318.dtsi @@ -346,5 +346,103 @@ status = "disabled"; }; + + switch0: switch@10080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-switch"; + reg = <0x10080000 0x8000>; + big-endian; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + label = "cpu"; + + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@100800b0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6368-mdio-mux"; + reg = <0x100800b0 0x8>; + + mdio_int: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + mdio_ext: mdio@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + + ethernet: ethernet@10088000 { + compatible = "brcm,bcm6318-enetsw"; + reg = <0x10088000 0x80>, + <0x10088200 0x80>, + <0x10088400 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + + interrupt-parent = <&periph_intc>; + interrupts = , + ; + interrupt-names = "rx", + "tx"; + + clocks = <&periph_clk BCM6318_CLK_ROBOSW250>, + <&periph_clk BCM6318_CLK_ROBOSW025>, + <&ubus_clk BCM6318_UCLK_ROBOSW>; + + resets = <&periph_rst BCM6318_RST_ENETSW>, + <&periph_rst BCM6318_RST_EPHY>; + + power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_EPHY0>, + <&periph_pwr BCM6318_POWER_DOMAIN_EPHY1>, + <&periph_pwr BCM6318_POWER_DOMAIN_EPHY2>, + <&periph_pwr BCM6318_POWER_DOMAIN_EPHY3>; + + dma-rx = <0>; + dma-tx = <1>; + + status = "disabled"; + }; }; }; diff --git a/target/linux/bmips/dts/bcm63268.dtsi b/target/linux/bmips/dts/bcm63268.dtsi index bf9998a552..284d2c8ef0 100644 --- a/target/linux/bmips/dts/bcm63268.dtsi +++ b/target/linux/bmips/dts/bcm63268.dtsi @@ -432,5 +432,105 @@ status = "disabled"; }; + + ethernet: ethernet@1000d800 { + compatible = "brcm,bcm63268-enetsw"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + + interrupt-parent = <&periph_intc>; + interrupts = , + ; + interrupt-names = "rx", + "tx"; + + clocks = <&periph_clk BCM63268_CLK_GMAC>, + <&periph_clk BCM63268_CLK_ROBOSW>, + <&periph_clk BCM63268_CLK_ROBOSW250>, + <&timer_clk BCM63268_TCLK_EPHY1>, + <&timer_clk BCM63268_TCLK_EPHY2>, + <&timer_clk BCM63268_TCLK_EPHY3>, + <&timer_clk BCM63268_TCLK_GPHY1>; + + resets = <&periph_rst BCM63268_RST_ENETSW>, + <&periph_rst BCM63268_RST_EPHY>, + <&periph_rst BCM63268_RST_GPHY>; + + power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>; + + dma-rx = <0>; + dma-tx = <1>; + + status = "disabled"; + }; + + switch0: switch@10700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-switch"; + reg = <0x10700000 0x8000>; + big-endian; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + label = "cpu"; + + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@107000b0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6368-mdio-mux"; + reg = <0x107000b0 0x8>; + + mdio_int: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + mdio_ext: mdio@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; }; diff --git a/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts b/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts index a3192dffa4..9ebd6c5c4d 100644 --- a/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts +++ b/target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts @@ -30,6 +30,12 @@ status = "okay"; }; +ðernet { + status = "okay"; + + mtd-mac-address = <&cfe 0x6a0>; +}; + &hsspi { status = "okay"; @@ -113,6 +119,38 @@ }; }; +&switch0 { + ports { + port@0 { + reg = <0>; + label = "lan1"; + + phy-handle = <&phy1>; + }; + + port@1 { + reg = <1>; + label = "lan2"; + + phy-handle = <&phy2>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + + phy-handle = <&phy3>; + }; + + port@3 { + reg = <3>; + label = "lan4"; + + phy-handle = <&phy4>; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/target/linux/bmips/dts/bcm6328.dtsi b/target/linux/bmips/dts/bcm6328.dtsi index aa90cc2a9b..64fd04142c 100644 --- a/target/linux/bmips/dts/bcm6328.dtsi +++ b/target/linux/bmips/dts/bcm6328.dtsi @@ -368,5 +368,99 @@ status = "disabled"; }; + + ethernet: ethernet@1000d800 { + compatible = "brcm,bcm6328-enetsw"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + + interrupt-parent = <&periph_intc>; + interrupts = , + ; + interrupt-names = "rx", + "tx"; + + clocks = <&periph_clk BCM6328_CLK_ROBOSW>; + + resets = <&periph_rst BCM6328_RST_ENETSW>, + <&periph_rst BCM6328_RST_EPHY>; + + power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_ROBOSW>, + <&periph_pwr BCM6328_POWER_DOMAIN_EPHY>; + + dma-rx = <0>; + dma-tx = <1>; + + status = "disabled"; + }; + + switch0: switch@10e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-switch"; + reg = <0x10e00000 0x8000>; + big-endian; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + label = "cpu"; + + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@10e000b0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6368-mdio-mux"; + reg = <0x10e000b0 0x8>; + + mdio_int: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + mdio_ext: mdio@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; }; diff --git a/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts b/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts index 4da673cafa..fe26ebeed0 100644 --- a/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts +++ b/target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts @@ -62,6 +62,12 @@ status = "okay"; }; +ðernet { + status = "okay"; + + mtd-mac-address = <&cferom 0x6a0>; +}; + &leds { status = "okay"; diff --git a/target/linux/bmips/dts/bcm6362.dtsi b/target/linux/bmips/dts/bcm6362.dtsi index f46074045c..9a3d9c1f66 100644 --- a/target/linux/bmips/dts/bcm6362.dtsi +++ b/target/linux/bmips/dts/bcm6362.dtsi @@ -465,5 +465,99 @@ status = "disabled"; }; + + ethernet: ethernet@1000d800 { + compatible = "brcm,bcm6362-enetsw"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + + interrupt-parent = <&periph_intc>; + interrupts = ; + interrupt-names = "rx"; + + clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>, + <&periph_clk BCM6362_CLK_SWPKT_SAR>, + <&periph_clk BCM6362_CLK_ROBOSW>; + + resets = <&periph_rst BCM6362_RST_ENETSW>, + <&periph_rst BCM6362_RST_EPHY>; + + power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>, + <&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>; + + dma-rx = <0>; + dma-tx = <1>; + + status = "disabled"; + }; + + switch0: switch@10e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-switch"; + reg = <0x10e00000 0x8000>; + big-endian; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + label = "cpu"; + + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@10e000b0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6368-mdio-mux"; + reg = <0x10e000b0 0x8>; + + mdio_int: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + mdio_ext: mdio@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; }; diff --git a/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts b/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts index 683b01875e..b597a05f3a 100644 --- a/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts +++ b/target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts @@ -59,6 +59,12 @@ status = "okay"; }; +ðernet { + status = "okay"; + + mtd-mac-address = <&cfe 0x6a0>; +}; + &ohci { status = "okay"; }; @@ -96,6 +102,38 @@ &pinctrl_ephy2_led &pinctrl_ephy3_led>; }; +&switch0 { + ports { + port@0 { + reg = <0>; + label = "lan1"; + + phy-handle = <&phy1>; + }; + + port@1 { + reg = <1>; + label = "lan2"; + + phy-handle = <&phy2>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + + phy-handle = <&phy3>; + }; + + port@3 { + reg = <3>; + label = "lan4"; + + phy-handle = <&phy4>; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/target/linux/bmips/dts/bcm6368.dtsi b/target/linux/bmips/dts/bcm6368.dtsi index 5aa2b82221..5b5064b29e 100644 --- a/target/linux/bmips/dts/bcm6368.dtsi +++ b/target/linux/bmips/dts/bcm6368.dtsi @@ -467,6 +467,99 @@ resets = <&periph_rst BCM6368_RST_IPSEC>; }; + + ethernet: ethernet@10006800 { + compatible = "brcm,bcm6368-enetsw"; + reg = <0x10006800 0x80>, + <0x10006a00 0x80>, + <0x10006c00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + + interrupt-parent = <&periph_intc>; + interrupts = , + ; + interrupt-names = "rx", + "tx"; + + clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>, + <&periph_clk BCM6368_CLK_SWPKT_SAR>, + <&periph_clk BCM6368_CLK_ROBOSW>; + + resets = <&periph_rst BCM6368_RST_SWITCH>, + <&periph_rst BCM6368_RST_EPHY>; + + dma-rx = <0>; + dma-tx = <1>; + + status = "disabled"; + }; + + switch0: switch@10f00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-switch"; + reg = <0x10f00000 0x8000>; + big-endian; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + label = "cpu"; + + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@10f000b0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6368-mdio-mux"; + reg = <0x10f000b0 0x8>; + + mdio_int: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + + mdio_ext: mdio@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; pflash: nor@18000000 { diff --git a/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c b/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c new file mode 100644 index 0000000000..dc55e3ccb9 --- /dev/null +++ b/target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c @@ -0,0 +1,1116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * BCM6368 Ethernet Switch Controller Driver + * + * Copyright (C) 2021 Álvaro Fernández Rojas + * Copyright (C) 2015 Jonas Gorski + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MTU */ +#define ENETSW_TAG_SIZE 6 +#define ENETSW_MTU_OVERHEAD (VLAN_ETH_HLEN + VLAN_HLEN + \ + ENETSW_TAG_SIZE) + +/* default number of descriptor */ +#define ENETSW_DEF_RX_DESC 64 +#define ENETSW_DEF_TX_DESC 32 +#define ENETSW_DEF_CPY_BREAK 128 + +/* maximum burst len for dma (4 bytes unit) */ +#define ENETSW_DMA_MAXBURST 8 + +/* DMA channels */ +#define DMA_CHAN_WIDTH 0x10 + +/* Controller Configuration Register */ +#define DMA_CFG_REG (0x0) +#define DMA_CFG_EN_SHIFT 0 +#define DMA_CFG_EN_MASK (1 << DMA_CFG_EN_SHIFT) +#define DMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) + +/* Flow Control Descriptor Low Threshold register */ +#define DMA_FLOWCL_REG(x) (0x4 + (x) * 6) + +/* Flow Control Descriptor High Threshold register */ +#define DMA_FLOWCH_REG(x) (0x8 + (x) * 6) + +/* Flow Control Descriptor Buffer Alloca Threshold register */ +#define DMA_BUFALLOC_REG(x) (0xc + (x) * 6) +#define DMA_BUFALLOC_FORCE_SHIFT 31 +#define DMA_BUFALLOC_FORCE_MASK (1 << DMA_BUFALLOC_FORCE_SHIFT) + +/* Channel Configuration register */ +#define DMAC_CHANCFG_REG (0x0) +#define DMAC_CHANCFG_EN_SHIFT 0 +#define DMAC_CHANCFG_EN_MASK (1 << DMAC_CHANCFG_EN_SHIFT) +#define DMAC_CHANCFG_PKTHALT_SHIFT 1 +#define DMAC_CHANCFG_PKTHALT_MASK (1 << DMAC_CHANCFG_PKTHALT_SHIFT) +#define DMAC_CHANCFG_BUFHALT_SHIFT 2 +#define DMAC_CHANCFG_BUFHALT_MASK (1 << DMAC_CHANCFG_BUFHALT_SHIFT) +#define DMAC_CHANCFG_CHAINING_SHIFT 2 +#define DMAC_CHANCFG_CHAINING_MASK (1 << DMAC_CHANCFG_CHAINING_SHIFT) +#define DMAC_CHANCFG_WRAP_EN_SHIFT 3 +#define DMAC_CHANCFG_WRAP_EN_MASK (1 << DMAC_CHANCFG_WRAP_EN_SHIFT) +#define DMAC_CHANCFG_FLOWC_EN_SHIFT 4 +#define DMAC_CHANCFG_FLOWC_EN_MASK (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT) + +/* Interrupt Control/Status register */ +#define DMAC_IR_REG (0x4) +#define DMAC_IR_BUFDONE_MASK (1 << 0) +#define DMAC_IR_PKTDONE_MASK (1 << 1) +#define DMAC_IR_NOTOWNER_MASK (1 << 2) + +/* Interrupt Mask register */ +#define DMAC_IRMASK_REG (0x8) + +/* Maximum Burst Length */ +#define DMAC_MAXBURST_REG (0xc) + +/* Ring Start Address register */ +#define DMAS_RSTART_REG (0x0) + +/* State Ram Word 2 */ +#define DMAS_SRAM2_REG (0x4) + +/* State Ram Word 3 */ +#define DMAS_SRAM3_REG (0x8) + +/* State Ram Word 4 */ +#define DMAS_SRAM4_REG (0xc) + +struct bcm6368_enetsw_desc { + u32 len_stat; + u32 address; +}; + +/* control */ +#define DMADESC_LENGTH_SHIFT 16 +#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) +#define DMADESC_OWNER_MASK (1 << 15) +#define DMADESC_EOP_MASK (1 << 14) +#define DMADESC_SOP_MASK (1 << 13) +#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) +#define DMADESC_WRAP_MASK (1 << 12) +#define DMADESC_USB_NOZERO_MASK (1 << 1) +#define DMADESC_USB_ZERO_MASK (1 << 0) + +/* status */ +#define DMADESC_UNDER_MASK (1 << 9) +#define DMADESC_APPEND_CRC (1 << 8) +#define DMADESC_OVSIZE_MASK (1 << 4) +#define DMADESC_RXER_MASK (1 << 2) +#define DMADESC_CRC_MASK (1 << 1) +#define DMADESC_OV_MASK (1 << 0) +#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ + DMADESC_OVSIZE_MASK | \ + DMADESC_RXER_MASK | \ + DMADESC_CRC_MASK | \ + DMADESC_OV_MASK) + +struct bcm6368_enetsw { + void __iomem *dma_base; + void __iomem *dma_chan; + void __iomem *dma_sram; + + struct device **pm; + struct device_link **link_pm; + int num_pms; + + struct clk **clock; + unsigned int num_clocks; + + struct reset_control **reset; + unsigned int num_resets; + + int copybreak; + + int irq_rx; + int irq_tx; + + /* hw view of rx & tx dma ring */ + dma_addr_t rx_desc_dma; + dma_addr_t tx_desc_dma; + + /* allocated size (in bytes) for rx & tx dma ring */ + unsigned int rx_desc_alloc_size; + unsigned int tx_desc_alloc_size; + + struct napi_struct napi; + + /* dma channel id for rx */ + int rx_chan; + + /* number of dma desc in rx ring */ + int rx_ring_size; + + /* cpu view of rx dma ring */ + struct bcm6368_enetsw_desc *rx_desc_cpu; + + /* current number of armed descriptor given to hardware for rx */ + int rx_desc_count; + + /* next rx descriptor to fetch from hardware */ + int rx_curr_desc; + + /* next dirty rx descriptor to refill */ + int rx_dirty_desc; + + /* size of allocated rx skbs */ + unsigned int rx_skb_size; + + /* list of skb given to hw for rx */ + struct sk_buff **rx_skb; + + /* used when rx skb allocation failed, so we defer rx queue + * refill */ + struct timer_list rx_timeout; + + /* lock rx_timeout against rx normal operation */ + spinlock_t rx_lock; + + /* dma channel id for tx */ + int tx_chan; + + /* number of dma desc in tx ring */ + int tx_ring_size; + + /* maximum dma burst size */ + int dma_maxburst; + + /* cpu view of rx dma ring */ + struct bcm6368_enetsw_desc *tx_desc_cpu; + + /* number of available descriptor for tx */ + int tx_desc_count; + + /* next tx descriptor avaiable */ + int tx_curr_desc; + + /* next dirty tx descriptor to reclaim */ + int tx_dirty_desc; + + /* list of skb given to hw for tx */ + struct sk_buff **tx_skb; + + /* lock used by tx reclaim and xmit */ + spinlock_t tx_lock; + + /* network device reference */ + struct net_device *net_dev; + + /* platform device reference */ + struct platform_device *pdev; + + /* dma channel enable mask */ + u32 dma_chan_en_mask; + + /* dma channel interrupt mask */ + u32 dma_chan_int_mask; + + /* dma channel width */ + unsigned int dma_chan_width; + + /* dma descriptor shift value */ + unsigned int dma_desc_shift; +}; + +static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off) +{ + __raw_writel(val, priv->dma_base + off); +} + +static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan) +{ + return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width); +} + +static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val, + u32 off, int chan) +{ + __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width); +} + +static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val, + u32 off, int chan) +{ + __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width); +} + +/* + * refill rx queue + */ +static int bcm6368_enetsw_refill_rx(struct net_device *dev) +{ + struct bcm6368_enetsw *priv; + + priv = netdev_priv(dev); + + while (priv->rx_desc_count < priv->rx_ring_size) { + struct bcm6368_enetsw_desc *desc; + struct sk_buff *skb; + dma_addr_t p; + int desc_idx; + u32 len_stat; + + desc_idx = priv->rx_dirty_desc; + desc = &priv->rx_desc_cpu[desc_idx]; + + if (!priv->rx_skb[desc_idx]) { + skb = netdev_alloc_skb(dev, priv->rx_skb_size); + if (!skb) + break; + priv->rx_skb[desc_idx] = skb; + p = dma_map_single(&priv->pdev->dev, skb->data, + priv->rx_skb_size, + DMA_FROM_DEVICE); + desc->address = p; + } + + len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; + len_stat |= DMADESC_OWNER_MASK; + if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { + len_stat |= (DMADESC_WRAP_MASK >> + priv->dma_desc_shift); + priv->rx_dirty_desc = 0; + } else { + priv->rx_dirty_desc++; + } + wmb(); + desc->len_stat = len_stat; + + priv->rx_desc_count++; + + /* tell dma engine we allocated one buffer */ + dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan)); + } + + /* If rx ring is still empty, set a timer to try allocating + * again at a later time. */ + if (priv->rx_desc_count == 0 && netif_running(dev)) { + dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); + priv->rx_timeout.expires = jiffies + HZ; + add_timer(&priv->rx_timeout); + } + + return 0; +} + +/* + * timer callback to defer refill rx queue in case we're OOM + */ +static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t) +{ + struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout); + struct net_device *dev = priv->net_dev; + + spin_lock(&priv->rx_lock); + bcm6368_enetsw_refill_rx(dev); + spin_unlock(&priv->rx_lock); +} + +/* + * extract packet from rx queue + */ +static int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget) +{ + struct bcm6368_enetsw *priv; + struct device *kdev; + int processed; + + priv = netdev_priv(dev); + kdev = &priv->pdev->dev; + processed = 0; + + /* don't scan ring further than number of refilled + * descriptor */ + if (budget > priv->rx_desc_count) + budget = priv->rx_desc_count; + + do { + struct bcm6368_enetsw_desc *desc; + struct sk_buff *skb; + int desc_idx; + u32 len_stat; + unsigned int len; + + desc_idx = priv->rx_curr_desc; + desc = &priv->rx_desc_cpu[desc_idx]; + + /* make sure we actually read the descriptor status at + * each loop */ + rmb(); + + len_stat = desc->len_stat; + + /* break if dma ownership belongs to hw */ + if (len_stat & DMADESC_OWNER_MASK) + break; + + processed++; + priv->rx_curr_desc++; + if (priv->rx_curr_desc == priv->rx_ring_size) + priv->rx_curr_desc = 0; + priv->rx_desc_count--; + + /* if the packet does not have start of packet _and_ + * end of packet flag set, then just recycle it */ + if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) + != (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) { + dev->stats.rx_dropped++; + continue; + } + + /* valid packet */ + skb = priv->rx_skb[desc_idx]; + len = (len_stat & DMADESC_LENGTH_MASK) + >> DMADESC_LENGTH_SHIFT; + /* don't include FCS */ + len -= 4; + + if (len < priv->copybreak) { + struct sk_buff *nskb; + + nskb = napi_alloc_skb(&priv->napi, len); + if (!nskb) { + /* forget packet, just rearm desc */ + dev->stats.rx_dropped++; + continue; + } + + dma_sync_single_for_cpu(kdev, desc->address, + len, DMA_FROM_DEVICE); + memcpy(nskb->data, skb->data, len); + dma_sync_single_for_device(kdev, desc->address, + len, DMA_FROM_DEVICE); + skb = nskb; + } else { + dma_unmap_single(&priv->pdev->dev, desc->address, + priv->rx_skb_size, DMA_FROM_DEVICE); + priv->rx_skb[desc_idx] = NULL; + } + + skb_put(skb, len); + skb->protocol = eth_type_trans(skb, dev); + dev->stats.rx_packets++; + dev->stats.rx_bytes += len; + netif_receive_skb(skb); + } while (--budget > 0); + + if (processed || !priv->rx_desc_count) { + bcm6368_enetsw_refill_rx(dev); + + /* kick rx dma */ + dmac_writel(priv, priv->dma_chan_en_mask, + DMAC_CHANCFG_REG, priv->rx_chan); + } + + return processed; +} + +/* + * try to or force reclaim of transmitted buffers + */ +static int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force) +{ + struct bcm6368_enetsw *priv; + int released; + + priv = netdev_priv(dev); + released = 0; + + while (priv->tx_desc_count < priv->tx_ring_size) { + struct bcm6368_enetsw_desc *desc; + struct sk_buff *skb; + + /* We run in a bh and fight against start_xmit, which + * is called with bh disabled */ + spin_lock(&priv->tx_lock); + + desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; + + if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { + spin_unlock(&priv->tx_lock); + break; + } + + /* ensure other field of the descriptor were not read + * before we checked ownership */ + rmb(); + + skb = priv->tx_skb[priv->tx_dirty_desc]; + priv->tx_skb[priv->tx_dirty_desc] = NULL; + dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, + DMA_TO_DEVICE); + + priv->tx_dirty_desc++; + if (priv->tx_dirty_desc == priv->tx_ring_size) + priv->tx_dirty_desc = 0; + priv->tx_desc_count++; + + spin_unlock(&priv->tx_lock); + + if (desc->len_stat & DMADESC_UNDER_MASK) + dev->stats.tx_errors++; + + dev_kfree_skb(skb); + released++; + } + + if (netif_queue_stopped(dev) && released) + netif_wake_queue(dev); + + return released; +} + +/* + * poll func, called by network core + */ +static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget) +{ + struct bcm6368_enetsw *priv; + struct net_device *dev; + int rx_work_done; + + priv = container_of(napi, struct bcm6368_enetsw, napi); + dev = priv->net_dev; + + /* ack interrupts */ + dmac_writel(priv, priv->dma_chan_int_mask, + DMAC_IR_REG, priv->rx_chan); + dmac_writel(priv, priv->dma_chan_int_mask, + DMAC_IR_REG, priv->tx_chan); + + /* reclaim sent skb */ + bcm6368_enetsw_tx_reclaim(dev, 0); + + spin_lock(&priv->rx_lock); + rx_work_done = bcm6368_enetsw_receive_queue(dev, budget); + spin_unlock(&priv->rx_lock); + + if (rx_work_done >= budget) { + /* rx queue is not yet empty/clean */ + return rx_work_done; + } + + /* no more packet in rx/tx queue, remove device from poll + * queue */ + napi_complete_done(napi, rx_work_done); + + /* restore rx/tx interrupt */ + dmac_writel(priv, priv->dma_chan_int_mask, + DMAC_IRMASK_REG, priv->rx_chan); + dmac_writel(priv, priv->dma_chan_int_mask, + DMAC_IRMASK_REG, priv->tx_chan); + + return rx_work_done; +} + +/* + * rx/tx dma interrupt handler + */ +static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id) +{ + struct net_device *dev; + struct bcm6368_enetsw *priv; + + dev = dev_id; + priv = netdev_priv(dev); + + /* mask rx/tx interrupts */ + dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan); + dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan); + + napi_schedule(&priv->napi); + + return IRQ_HANDLED; +} + +/* + * tx request callback + */ +static netdev_tx_t +bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct bcm6368_enetsw *priv; + struct bcm6368_enetsw_desc *desc; + u32 len_stat; + netdev_tx_t ret; + + priv = netdev_priv(dev); + + /* lock against tx reclaim */ + spin_lock(&priv->tx_lock); + + /* make sure the tx hw queue is not full, should not happen + * since we stop queue before it's the case */ + if (unlikely(!priv->tx_desc_count)) { + netif_stop_queue(dev); + dev_err(&priv->pdev->dev, "xmit called with no tx desc " + "available?\n"); + ret = NETDEV_TX_BUSY; + goto out_unlock; + } + + /* pad small packets */ + if (skb->len < 64) { + int needed = 64 - skb->len; + char *data; + + if (unlikely(skb_tailroom(skb) < needed)) { + struct sk_buff *nskb; + + nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC); + if (!nskb) { + ret = NETDEV_TX_BUSY; + goto out_unlock; + } + dev_kfree_skb(skb); + skb = nskb; + } + data = skb_put_zero(skb, needed); + } + + /* point to the next available desc */ + desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; + priv->tx_skb[priv->tx_curr_desc] = skb; + + /* fill descriptor */ + desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; + len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) | + DMADESC_APPEND_CRC | DMADESC_OWNER_MASK; + + priv->tx_curr_desc++; + if (priv->tx_curr_desc == priv->tx_ring_size) { + priv->tx_curr_desc = 0; + len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift); + } + priv->tx_desc_count--; + + /* dma might be already polling, make sure we update desc + * fields in correct order */ + wmb(); + desc->len_stat = len_stat; + wmb(); + + /* kick tx dma */ + dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG, + priv->tx_chan); + + /* stop queue if no more desc available */ + if (!priv->tx_desc_count) + netif_stop_queue(dev); + + dev->stats.tx_bytes += skb->len; + dev->stats.tx_packets++; + ret = NETDEV_TX_OK; + +out_unlock: + spin_unlock(&priv->tx_lock); + return ret; +} + +/* + * disable dma in given channel + */ +static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan) +{ + int limit; + + dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan); + + limit = 1000; + do { + u32 val; + + val = dma_readl(priv, DMAC_CHANCFG_REG, chan); + if (!(val & DMAC_CHANCFG_EN_MASK)) + break; + udelay(1); + } while (limit--); +} + +static int bcm6368_enetsw_open(struct net_device *dev) +{ + struct bcm6368_enetsw *priv; + struct device *kdev; + int i, ret; + unsigned int size; + void *p; + u32 val; + + priv = netdev_priv(dev); + kdev = &priv->pdev->dev; + + /* mask all interrupts and request them */ + dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan); + dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan); + + ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma, + 0, dev->name, dev); + if (ret) + goto out_freeirq; + + if (priv->irq_tx != -1) { + ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma, + 0, dev->name, dev); + if (ret) + goto out_freeirq_rx; + } + + /* allocate rx dma ring */ + size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc); + p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); + if (!p) { + dev_err(kdev, "cannot allocate rx ring %u\n", size); + ret = -ENOMEM; + goto out_freeirq_tx; + } + + memset(p, 0, size); + priv->rx_desc_alloc_size = size; + priv->rx_desc_cpu = p; + + /* allocate tx dma ring */ + size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc); + p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); + if (!p) { + dev_err(kdev, "cannot allocate tx ring\n"); + ret = -ENOMEM; + goto out_free_rx_ring; + } + + memset(p, 0, size); + priv->tx_desc_alloc_size = size; + priv->tx_desc_cpu = p; + + priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size, + GFP_KERNEL); + if (!priv->tx_skb) { + dev_err(kdev, "cannot allocate rx skb queue\n"); + ret = -ENOMEM; + goto out_free_tx_ring; + } + + priv->tx_desc_count = priv->tx_ring_size; + priv->tx_dirty_desc = 0; + priv->tx_curr_desc = 0; + spin_lock_init(&priv->tx_lock); + + /* init & fill rx ring with skbs */ + priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size, + GFP_KERNEL); + if (!priv->rx_skb) { + dev_err(kdev, "cannot allocate rx skb queue\n"); + ret = -ENOMEM; + goto out_free_tx_skb; + } + + priv->rx_desc_count = 0; + priv->rx_dirty_desc = 0; + priv->rx_curr_desc = 0; + + /* initialize flow control buffer allocation */ + dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0, + DMA_BUFALLOC_REG(priv->rx_chan)); + + if (bcm6368_enetsw_refill_rx(dev)) { + dev_err(kdev, "cannot allocate rx skb queue\n"); + ret = -ENOMEM; + goto out; + } + + /* write rx & tx ring addresses */ + dmas_writel(priv, priv->rx_desc_dma, + DMAS_RSTART_REG, priv->rx_chan); + dmas_writel(priv, priv->tx_desc_dma, + DMAS_RSTART_REG, priv->tx_chan); + + /* clear remaining state ram for rx & tx channel */ + dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan); + dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan); + dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan); + dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan); + dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan); + dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan); + + /* set dma maximum burst len */ + dmac_writel(priv, priv->dma_maxburst, + DMAC_MAXBURST_REG, priv->rx_chan); + dmac_writel(priv, priv->dma_maxburst, + DMAC_MAXBURST_REG, priv->tx_chan); + + /* set flow control low/high threshold to 1/3 / 2/3 */ + val = priv->rx_ring_size / 3; + dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan)); + val = (priv->rx_ring_size * 2) / 3; + dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan)); + + /* all set, enable mac and interrupts, start dma engine and + * kick rx dma channel + */ + wmb(); + dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG); + dmac_writel(priv, DMAC_CHANCFG_EN_MASK, + DMAC_CHANCFG_REG, priv->rx_chan); + + /* watch "packet transferred" interrupt in rx and tx */ + dmac_writel(priv, DMAC_IR_PKTDONE_MASK, + DMAC_IR_REG, priv->rx_chan); + dmac_writel(priv, DMAC_IR_PKTDONE_MASK, + DMAC_IR_REG, priv->tx_chan); + + /* make sure we enable napi before rx interrupt */ + napi_enable(&priv->napi); + + dmac_writel(priv, DMAC_IR_PKTDONE_MASK, + DMAC_IRMASK_REG, priv->rx_chan); + dmac_writel(priv, DMAC_IR_PKTDONE_MASK, + DMAC_IRMASK_REG, priv->tx_chan); + + netif_carrier_on(dev); + netif_start_queue(dev); + + return 0; + +out: + for (i = 0; i < priv->rx_ring_size; i++) { + struct bcm6368_enetsw_desc *desc; + + if (!priv->rx_skb[i]) + continue; + + desc = &priv->rx_desc_cpu[i]; + dma_unmap_single(kdev, desc->address, priv->rx_skb_size, + DMA_FROM_DEVICE); + kfree_skb(priv->rx_skb[i]); + } + kfree(priv->rx_skb); + +out_free_tx_skb: + kfree(priv->tx_skb); + +out_free_tx_ring: + dma_free_coherent(kdev, priv->tx_desc_alloc_size, + priv->tx_desc_cpu, priv->tx_desc_dma); + +out_free_rx_ring: + dma_free_coherent(kdev, priv->rx_desc_alloc_size, + priv->rx_desc_cpu, priv->rx_desc_dma); + +out_freeirq_tx: + if (priv->irq_tx != -1) + free_irq(priv->irq_tx, dev); + +out_freeirq_rx: + free_irq(priv->irq_rx, dev); + +out_freeirq: + return ret; +} + +static int bcm6368_enetsw_stop(struct net_device *dev) +{ + struct bcm6368_enetsw *priv; + struct device *kdev; + int i; + + priv = netdev_priv(dev); + kdev = &priv->pdev->dev; + + netif_stop_queue(dev); + napi_disable(&priv->napi); + del_timer_sync(&priv->rx_timeout); + + /* mask all interrupts */ + dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan); + dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan); + + /* disable dma & mac */ + bcm6368_enetsw_disable_dma(priv, priv->tx_chan); + bcm6368_enetsw_disable_dma(priv, priv->rx_chan); + + /* force reclaim of all tx buffers */ + bcm6368_enetsw_tx_reclaim(dev, 1); + + /* free the rx skb ring */ + for (i = 0; i < priv->rx_ring_size; i++) { + struct bcm6368_enetsw_desc *desc; + + if (!priv->rx_skb[i]) + continue; + + desc = &priv->rx_desc_cpu[i]; + dma_unmap_single_attrs(kdev, desc->address, priv->rx_skb_size, + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + kfree_skb(priv->rx_skb[i]); + } + + /* free remaining allocated memory */ + kfree(priv->rx_skb); + kfree(priv->tx_skb); + dma_free_coherent(kdev, priv->rx_desc_alloc_size, + priv->rx_desc_cpu, priv->rx_desc_dma); + dma_free_coherent(kdev, priv->tx_desc_alloc_size, + priv->tx_desc_cpu, priv->tx_desc_dma); + if (priv->irq_tx != -1) + free_irq(priv->irq_tx, dev); + free_irq(priv->irq_rx, dev); + + return 0; +} + +static const struct net_device_ops bcm6368_enetsw_ops = { + .ndo_open = bcm6368_enetsw_open, + .ndo_stop = bcm6368_enetsw_stop, + .ndo_start_xmit = bcm6368_enetsw_start_xmit, +}; + +static int bcm6368_enetsw_probe(struct platform_device *pdev) +{ + struct bcm6368_enetsw *priv; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct net_device *ndev; + struct resource *res; + const void *mac; + unsigned i; + int ret; + + ndev = alloc_etherdev(sizeof(*priv)); + if (!ndev) + return -ENOMEM; + + priv = netdev_priv(ndev); + + priv->num_pms = of_count_phandle_with_args(node, "power-domains", + "#power-domain-cells"); + if (priv->num_pms > 1) { + priv->pm = devm_kcalloc(dev, priv->num_pms, + sizeof(struct device *), GFP_KERNEL); + if (!priv->pm) + return -ENOMEM; + + priv->link_pm = devm_kcalloc(dev, priv->num_pms, + sizeof(struct device_link *), + GFP_KERNEL); + if (!priv->link_pm) + return -ENOMEM; + + for (i = 0; i < priv->num_pms; i++) { + priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i); + if (IS_ERR(priv->pm[i])) { + dev_err(dev, "error getting pm %d\n", i); + return -EINVAL; + } + + priv->link_pm[i] = device_link_add(dev, priv->pm[i], + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + } + } + + pm_runtime_enable(dev); + pm_runtime_no_callbacks(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_disable(dev); + dev_info(dev, "PM prober defer: ret=%d\n", ret); + return -EPROBE_DEFER; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); + priv->dma_base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->dma_base)) + return PTR_ERR(priv->dma_base); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "dma-channels"); + priv->dma_chan = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->dma_chan)) + return PTR_ERR(priv->dma_chan); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram"); + priv->dma_sram = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->dma_sram)) + return PTR_ERR(priv->dma_sram); + + priv->irq_rx = platform_get_irq_byname(pdev, "rx"); + if (!priv->irq_rx) + return -ENODEV; + + priv->irq_tx = platform_get_irq_byname(pdev, "tx"); + if (!priv->irq_tx) + return -ENODEV; + else if (priv->irq_tx < 0) + priv->irq_tx = -1; + + if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan)) + return -ENODEV; + + if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan)) + return -ENODEV; + + priv->rx_ring_size = ENETSW_DEF_RX_DESC; + priv->tx_ring_size = ENETSW_DEF_TX_DESC; + + priv->dma_maxburst = ENETSW_DMA_MAXBURST; + + priv->copybreak = ENETSW_DEF_CPY_BREAK; + + priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK; + priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK; + priv->dma_chan_width = DMA_CHAN_WIDTH; + + mac = of_get_mac_address(node); + if (!IS_ERR_OR_NULL(mac)) { + memcpy(ndev->dev_addr, mac, ETH_ALEN); + dev_info(dev, "mtd mac %pM\n", ndev->dev_addr); + } else { + random_ether_addr(ndev->dev_addr); + dev_info(dev, "random mac %pM\n", ndev->dev_addr); + } + + priv->rx_skb_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD, + priv->dma_maxburst * 4); + + priv->num_clocks = of_clk_get_parent_count(node); + if (priv->num_clocks) { + priv->clock = devm_kcalloc(dev, priv->num_clocks, + sizeof(struct clk *), GFP_KERNEL); + if (!priv->clock) + return -ENOMEM; + } + for (i = 0; i < priv->num_clocks; i++) { + priv->clock[i] = of_clk_get(node, i); + if (IS_ERR(priv->clock[i])) { + dev_err(dev, "error getting clock %d\n", i); + return -EINVAL; + } + + ret = clk_prepare_enable(priv->clock[i]); + if (ret) { + dev_err(dev, "error enabling clock %d\n", i); + return ret; + } + } + + priv->num_resets = of_count_phandle_with_args(node, "resets", + "#reset-cells"); + if (priv->num_resets) { + priv->reset = devm_kcalloc(dev, priv->num_resets, + sizeof(struct reset_control *), + GFP_KERNEL); + if (!priv->reset) + return -ENOMEM; + } + for (i = 0; i < priv->num_resets; i++) { + priv->reset[i] = devm_reset_control_get_by_index(dev, i); + if (IS_ERR(priv->reset[i])) { + dev_err(dev, "error getting reset %d\n", i); + return -EINVAL; + } + + ret = reset_control_reset(priv->reset[i]); + if (ret) { + dev_err(dev, "error performing reset %d\n", i); + return ret; + } + } + + spin_lock_init(&priv->rx_lock); + + timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0); + + /* register netdevice */ + ndev->netdev_ops = &bcm6368_enetsw_ops; + ndev->min_mtu = ETH_ZLEN; + ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE; + ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE; + netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16); + SET_NETDEV_DEV(ndev, dev); + + ret = register_netdev(ndev); + if (ret) + goto out_disable_clk; + + netif_carrier_off(ndev); + platform_set_drvdata(pdev, ndev); + priv->pdev = pdev; + priv->net_dev = ndev; + + return 0; + +out_disable_clk: + for (i = 0; i < priv->num_resets; i++) + reset_control_assert(priv->reset[i]); + + for (i = 0; i < priv->num_clocks; i++) + clk_disable_unprepare(priv->clock[i]); + + return ret; +} + +static int bcm6368_enetsw_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct net_device *ndev = platform_get_drvdata(pdev); + struct bcm6368_enetsw *priv = netdev_priv(ndev); + unsigned int i; + + unregister_netdev(ndev); + + pm_runtime_put_sync(dev); + for (i = 0; priv->pm && i < priv->num_pms; i++) { + dev_pm_domain_detach(priv->pm[i], true); + device_link_del(priv->link_pm[i]); + } + + for (i = 0; i < priv->num_resets; i++) + reset_control_assert(priv->reset[i]); + + for (i = 0; i < priv->num_clocks; i++) + clk_disable_unprepare(priv->clock[i]); + + free_netdev(ndev); + + return 0; +} + +static const struct of_device_id bcm6368_enetsw_of_match[] = { + { .compatible = "brcm,bcm6318-enetsw", }, + { .compatible = "brcm,bcm6328-enetsw", }, + { .compatible = "brcm,bcm6362-enetsw", }, + { .compatible = "brcm,bcm6368-enetsw", }, + { .compatible = "brcm,bcm63268-enetsw", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, bcm6368_mdio_ids); + +static struct platform_driver bcm6368_enetsw_driver = { + .driver = { + .name = "bcm6368-enetsw", + .of_match_table = of_match_ptr(bcm6368_enetsw_of_match), + }, + .probe = bcm6368_enetsw_probe, + .remove = bcm6368_enetsw_remove, +}; +module_platform_driver(bcm6368_enetsw_driver); diff --git a/target/linux/bmips/generic/base-files/etc/board.d/02_network b/target/linux/bmips/generic/base-files/etc/board.d/02_network new file mode 100644 index 0000000000..3e60660331 --- /dev/null +++ b/target/linux/bmips/generic/base-files/etc/board.d/02_network @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +. /lib/functions/uci-defaults.sh + +board_config_update + +case "$(board_name)" in +comtrend,ar-5315u |\ +comtrend,ar-5387un |\ +comtrend,vr-3025u) + ucidef_set_interface_lan "lan1 lan2 lan3 lan4" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/bmips/nand/base-files/etc/board.d/02_network b/target/linux/bmips/nand/base-files/etc/board.d/02_network new file mode 100644 index 0000000000..db62e61287 --- /dev/null +++ b/target/linux/bmips/nand/base-files/etc/board.d/02_network @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +. /lib/functions/uci-defaults.sh + +board_config_update + +case "$(board_name)" in +comtrend,vr-3032u) + ucidef_set_interface_lan "lan1 lan2 lan3 lan4" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/bmips/patches-5.10/500-net-dsa-b53-relax-is63xx-condition.patch b/target/linux/bmips/patches-5.10/500-net-dsa-b53-relax-is63xx-condition.patch new file mode 100644 index 0000000000..f5dd4e2c59 --- /dev/null +++ b/target/linux/bmips/patches-5.10/500-net-dsa-b53-relax-is63xx-condition.patch @@ -0,0 +1,29 @@ +From cd6906754bbe3e0665ecaeca2cfb26d927fe9277 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Mon, 1 Mar 2021 07:29:29 +0100 +Subject: [PATCH 1/3] net: dsa: b53: relax is63xx() condition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM63xx switches are present on bcm63xx and bmips devices. + +Signed-off-by: Álvaro Fernández Rojas +--- + drivers/net/dsa/b53/b53_priv.h | 4 ---- + 1 file changed, 4 deletions(-) + +--- a/drivers/net/dsa/b53/b53_priv.h ++++ b/drivers/net/dsa/b53/b53_priv.h +@@ -185,11 +185,7 @@ static inline int is531x5(struct b53_dev + + static inline int is63xx(struct b53_device *dev) + { +-#ifdef CONFIG_BCM63XX + return dev->chip_id == BCM63XX_DEVICE_ID; +-#else +- return 0; +-#endif + } + + static inline int is5301x(struct b53_device *dev) diff --git a/target/linux/bmips/patches-5.10/501-net-dsa-b53-mmap-Add-device-tree-support.patch b/target/linux/bmips/patches-5.10/501-net-dsa-b53-mmap-Add-device-tree-support.patch new file mode 100644 index 0000000000..e9eb87cb5c --- /dev/null +++ b/target/linux/bmips/patches-5.10/501-net-dsa-b53-mmap-Add-device-tree-support.patch @@ -0,0 +1,82 @@ +From f5419e7f362ae1c462baf28a2da7360267f8e4f9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Mon, 1 Mar 2021 07:32:32 +0100 +Subject: [PATCH 2/3] net: dsa: b53: mmap: Add device tree support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add device tree support to b53_mmap.c while keeping platform devices support. + +Signed-off-by: Álvaro Fernández Rojas +--- + drivers/net/dsa/b53/b53_mmap.c | 36 ++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/net/dsa/b53/b53_mmap.c ++++ b/drivers/net/dsa/b53/b53_mmap.c +@@ -228,12 +228,64 @@ static const struct b53_io_ops b53_mmap_ + .write64 = b53_mmap_write64, + }; + ++static int b53_mmap_probe_of(struct platform_device *pdev, ++ struct b53_platform_data **ppdata) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *of_ports, *of_port; ++ struct b53_platform_data *pdata; ++ void __iomem *mem; ++ ++ mem = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(mem)) ++ return PTR_ERR(mem); ++ ++ pdata = devm_kzalloc(dev, sizeof(struct b53_platform_data), ++ GFP_KERNEL); ++ if (!pdata) ++ return -ENOMEM; ++ ++ pdata->regs = mem; ++ pdata->chip_id = BCM63XX_DEVICE_ID; ++ pdata->big_endian = of_property_read_bool(np, "big-endian"); ++ ++ of_ports = of_get_child_by_name(np, "ports"); ++ if (!of_ports) { ++ dev_err(dev, "no ports child node found\n"); ++ return -EINVAL; ++ } ++ ++ for_each_available_child_of_node(of_ports, of_port) { ++ u32 reg; ++ ++ if (of_property_read_u32(of_port, "reg", ®)) ++ continue; ++ ++ if (reg < B53_CPU_PORT) ++ pdata->enabled_ports |= BIT(reg); ++ } ++ ++ *ppdata = pdata; ++ ++ return 0; ++} ++ + static int b53_mmap_probe(struct platform_device *pdev) + { ++ struct device_node *np = pdev->dev.of_node; + struct b53_platform_data *pdata = pdev->dev.platform_data; + struct b53_mmap_priv *priv; + struct b53_device *dev; + ++ if (np) { ++ int ret = b53_mmap_probe_of(pdev, &pdata); ++ if (ret) { ++ dev_err(&pdev->dev, "OF probe error\n"); ++ return ret; ++ } ++ } ++ + if (!pdata) + return -EINVAL; + diff --git a/target/linux/bmips/patches-5.10/502-net-dsa-b53-support-tags-for-legacy-switches.patch b/target/linux/bmips/patches-5.10/502-net-dsa-b53-support-tags-for-legacy-switches.patch new file mode 100644 index 0000000000..b8aa8b844d --- /dev/null +++ b/target/linux/bmips/patches-5.10/502-net-dsa-b53-support-tags-for-legacy-switches.patch @@ -0,0 +1,209 @@ +From 3bc3d79efdff6e29b80bf35f7a56baaa36e4d8fe Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Fri, 12 Mar 2021 12:35:39 +0100 +Subject: [PATCH] net: dsa: b53: support tags for legacy switches +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Álvaro Fernández Rojas +--- + drivers/net/dsa/b53/Kconfig | 1 + + drivers/net/dsa/b53/b53_common.c | 6 +++ + include/net/dsa.h | 2 + + net/dsa/Kconfig | 7 +++ + net/dsa/tag_brcm.c | 93 ++++++++++++++++++++++++++++++++ + 5 files changed, 109 insertions(+) + +--- a/drivers/net/dsa/b53/Kconfig ++++ b/drivers/net/dsa/b53/Kconfig +@@ -3,6 +3,7 @@ menuconfig B53 + tristate "Broadcom BCM53xx managed switch support" + depends on NET_DSA + select NET_DSA_TAG_BRCM ++ select NET_DSA_TAG_BRCM_LEGACY + select NET_DSA_TAG_BRCM_PREPEND + help + This driver adds support for Broadcom managed switch chips. It supports +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1992,6 +1992,7 @@ static bool b53_can_enable_brcm_tags(str + + switch (tag_protocol) { + case DSA_TAG_PROTO_BRCM: ++ case DSA_TAG_PROTO_BRCM_LEGACY: + case DSA_TAG_PROTO_BRCM_PREPEND: + dev_warn(ds->dev, + "Port %d is stacked to Broadcom tag switch\n", port); +@@ -2013,12 +2014,16 @@ enum dsa_tag_protocol b53_get_tag_protoc + /* Older models (5325, 5365) support a different tag format that we do + * not support in net/dsa/tag_brcm.c yet. + */ +- if (is5325(dev) || is5365(dev) || +- !b53_can_enable_brcm_tags(ds, port, mprot)) { ++ if (!b53_can_enable_brcm_tags(ds, port, mprot)) { + dev->tag_protocol = DSA_TAG_PROTO_NONE; + goto out; + } + ++ if (is5325(dev) || is5365(dev) || is63xx(dev)) { ++ dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; ++ goto out; ++ } ++ + /* Broadcom BCM58xx chips have a flow accelerator on Port 8 + * which requires us to use the prepended Broadcom tag type + */ +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -45,10 +45,12 @@ struct phylink_link_state; + #define DSA_TAG_PROTO_OCELOT_VALUE 15 + #define DSA_TAG_PROTO_AR9331_VALUE 16 + #define DSA_TAG_PROTO_RTL4_A_VALUE 17 ++#define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22 + + enum dsa_tag_protocol { + DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, + DSA_TAG_PROTO_BRCM = DSA_TAG_PROTO_BRCM_VALUE, ++ DSA_TAG_PROTO_BRCM_LEGACY = DSA_TAG_PROTO_BRCM_LEGACY_VALUE, + DSA_TAG_PROTO_BRCM_PREPEND = DSA_TAG_PROTO_BRCM_PREPEND_VALUE, + DSA_TAG_PROTO_DSA = DSA_TAG_PROTO_DSA_VALUE, + DSA_TAG_PROTO_EDSA = DSA_TAG_PROTO_EDSA_VALUE, +--- a/net/dsa/Kconfig ++++ b/net/dsa/Kconfig +@@ -47,6 +47,13 @@ config NET_DSA_TAG_BRCM + Say Y if you want to enable support for tagging frames for the + Broadcom switches which place the tag after the MAC source address. + ++config NET_DSA_TAG_BRCM_LEGACY ++ tristate "Tag driver for Broadcom legacy switches using in-frame headers" ++ select NET_DSA_TAG_BRCM_COMMON ++ help ++ Say Y if you want to enable support for tagging frames for the ++ Broadcom legacy switches which place the tag after the MAC source ++ address. + + config NET_DSA_TAG_BRCM_PREPEND + tristate "Tag driver for Broadcom switches using prepended headers" +--- a/net/dsa/tag_brcm.c ++++ b/net/dsa/tag_brcm.c +@@ -8,9 +8,23 @@ + #include + #include + #include ++#include + + #include "dsa_priv.h" + ++struct bcm_legacy_tag { ++ uint16_t type; ++#define BRCM_LEG_TYPE 0x8874 ++ ++ uint32_t tag; ++#define BRCM_LEG_TAG_PORT_ID (0xf) ++#define BRCM_LEG_TAG_MULTICAST (1 << 29) ++#define BRCM_LEG_TAG_EGRESS (2 << 29) ++#define BRCM_LEG_TAG_INGRESS (3 << 29) ++} __attribute__((packed)); ++ ++#define BRCM_LEG_TAG_LEN sizeof(struct bcm_legacy_tag) ++ + /* This tag length is 4 bytes, older ones were 6 bytes, we do not + * handle them + */ +@@ -197,6 +211,85 @@ DSA_TAG_DRIVER(brcm_netdev_ops); + MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM); + #endif + ++#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_LEGACY) ++static struct sk_buff *brcm_leg_tag_xmit(struct sk_buff *skb, ++ struct net_device *dev) ++{ ++ struct dsa_port *dp = dsa_slave_to_port(dev); ++ struct bcm_legacy_tag *brcm_tag; ++ ++ if (skb_cow_head(skb, BRCM_LEG_TAG_LEN) < 0) ++ return NULL; ++ ++ /* The Ethernet switch we are interfaced with needs packets to be at ++ * least 64 bytes (including FCS) otherwise they will be discarded when ++ * they enter the switch port logic. When Broadcom tags are enabled, we ++ * need to make sure that packets are at least 70 bytes ++ * (including FCS and tag) because the length verification is done after ++ * the Broadcom tag is stripped off the ingress packet. ++ * ++ * Let dsa_slave_xmit() free the SKB ++ */ ++ if (__skb_put_padto(skb, ETH_ZLEN + BRCM_LEG_TAG_LEN, false)) ++ return NULL; ++ ++ skb_push(skb, BRCM_LEG_TAG_LEN); ++ ++ memmove(skb->data, skb->data + BRCM_LEG_TAG_LEN, 2 * ETH_ALEN); ++ ++ brcm_tag = (struct bcm_legacy_tag *) (skb->data + 2 * ETH_ALEN); ++ ++ brcm_tag->type = BRCM_LEG_TYPE; ++ brcm_tag->tag = BRCM_LEG_TAG_EGRESS; ++ brcm_tag->tag |= dp->index & BRCM_LEG_TAG_PORT_ID; ++ ++ return skb; ++} ++ ++ ++static struct sk_buff *brcm_leg_tag_rcv(struct sk_buff *skb, ++ struct net_device *dev, ++ struct packet_type *pt) ++{ ++ int source_port; ++ struct bcm_legacy_tag *brcm_tag; ++ ++ if (unlikely(!pskb_may_pull(skb, BRCM_LEG_TAG_LEN))) ++ return NULL; ++ ++ brcm_tag = (struct bcm_legacy_tag *) (skb->data - 2); ++ ++ source_port = brcm_tag->tag & BRCM_LEG_TAG_PORT_ID; ++ ++ skb->dev = dsa_master_find_slave(dev, 0, source_port); ++ if (!skb->dev) ++ return NULL; ++ ++ /* Remove Broadcom tag and update checksum */ ++ skb_pull_rcsum(skb, BRCM_LEG_TAG_LEN); ++ ++ skb->offload_fwd_mark = 1; ++ ++ /* Move the Ethernet DA and SA */ ++ memmove(skb->data - ETH_HLEN, ++ skb->data - ETH_HLEN - BRCM_LEG_TAG_LEN, ++ 2 * ETH_ALEN); ++ ++ return skb; ++} ++ ++static const struct dsa_device_ops brcm_legacy_netdev_ops = { ++ .name = "brcm-legacy", ++ .proto = DSA_TAG_PROTO_BRCM_LEGACY, ++ .xmit = brcm_leg_tag_xmit, ++ .rcv = brcm_leg_tag_rcv, ++ .overhead = BRCM_LEG_TAG_LEN, ++}; ++ ++DSA_TAG_DRIVER(brcm_legacy_netdev_ops); ++MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_LEGACY); ++#endif /* CONFIG_NET_DSA_TAG_BRCM_LEGACY */ ++ + #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) + static struct sk_buff *brcm_tag_xmit_prepend(struct sk_buff *skb, + struct net_device *dev) +@@ -229,6 +322,9 @@ static struct dsa_tag_driver *dsa_tag_dr + #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) + &DSA_TAG_DRIVER_NAME(brcm_netdev_ops), + #endif ++#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_LEGACY) ++ &DSA_TAG_DRIVER_NAME(brcm_legacy_netdev_ops), ++#endif + #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) + &DSA_TAG_DRIVER_NAME(brcm_prepend_netdev_ops), + #endif diff --git a/target/linux/bmips/patches-5.10/503-net-broadcom-add-BCM6368-enetsw-controller-driver.patch b/target/linux/bmips/patches-5.10/503-net-broadcom-add-BCM6368-enetsw-controller-driver.patch new file mode 100644 index 0000000000..c2c2e968e9 --- /dev/null +++ b/target/linux/bmips/patches-5.10/503-net-broadcom-add-BCM6368-enetsw-controller-driver.patch @@ -0,0 +1,46 @@ +From 590b60fb08cb1e70fe02d3f407c6b3dbe9ad06ff Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Mon, 1 Mar 2021 07:34:39 +0100 +Subject: [PATCH 3/4] net: broadcom: add BCM6368 enetsw controller driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268 +SoCs. + +Signed-off-by: Álvaro Fernández Rojas +--- + drivers/net/ethernet/broadcom/Kconfig | 8 + + drivers/net/ethernet/broadcom/Makefile | 1 + + .../net/ethernet/broadcom/bcm6368-enetsw.c | 1111 +++++++++++++++++ + 3 files changed, 1120 insertions(+) + create mode 100644 drivers/net/ethernet/broadcom/bcm6368-enetsw.c + +--- a/drivers/net/ethernet/broadcom/Kconfig ++++ b/drivers/net/ethernet/broadcom/Kconfig +@@ -60,6 +60,14 @@ config BCM63XX_ENET + This driver supports the ethernet MACs in the Broadcom 63xx + MIPS chipset family (BCM63XX). + ++config BCM6368_ENETSW ++ tristate "Broadcom BCM6368 internal mac support" ++ depends on BMIPS_GENERIC || COMPILE_TEST ++ default y ++ help ++ This driver supports Ethernet controller integrated into Broadcom ++ BCM6368 family SoCs. ++ + config BCMGENET + tristate "Broadcom GENET internal MAC support" + depends on HAS_IOMEM +--- a/drivers/net/ethernet/broadcom/Makefile ++++ b/drivers/net/ethernet/broadcom/Makefile +@@ -5,6 +5,7 @@ + + obj-$(CONFIG_B44) += b44.o + obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o ++obj-$(CONFIG_BCM6368_ENETSW) += bcm6368-enetsw.o + obj-$(CONFIG_BCMGENET) += genet/ + obj-$(CONFIG_BNX2) += bnx2.o + obj-$(CONFIG_CNIC) += cnic.o diff --git a/target/linux/bmips/patches-5.10/504-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch b/target/linux/bmips/patches-5.10/504-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch new file mode 100644 index 0000000000..a869681312 --- /dev/null +++ b/target/linux/bmips/patches-5.10/504-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch @@ -0,0 +1,231 @@ +From b6ecb2bca2b8ff80ae4b1b15f09dcf071f4ceaf4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= +Date: Mon, 1 Mar 2021 16:42:12 +0100 +Subject: [PATCH] net: mdio: Add BCM6368 MDIO mux bus controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268 +SoCs. + +Signed-off-by: Álvaro Fernández Rojas +--- + drivers/net/mdio/Kconfig | 11 ++ + drivers/net/mdio/Makefile | 1 + + drivers/net/mdio/mdio-mux-bcm6368.c | 179 ++++++++++++++++++++++++++++ + 3 files changed, 191 insertions(+) + create mode 100644 drivers/net/mdio/mdio-mux-bcm6368.c + +--- a/drivers/net/mdio/Kconfig ++++ b/drivers/net/mdio/Kconfig +@@ -200,6 +200,17 @@ config MDIO_BUS_MUX_MESON_G12A + the amlogic g12a SoC. The multiplexers connects either the external + or the internal MDIO bus to the parent bus. + ++config MDIO_BUS_MUX_BCM6368 ++ tristate "Broadcom BCM6368 MDIO bus multiplexers" ++ depends on OF && OF_MDIO && (BMIPS_GENERIC || COMPILE_TEST) ++ select MDIO_BUS_MUX ++ default BMIPS_GENERIC ++ help ++ This module provides a driver for MDIO bus multiplexers found in ++ BCM6368 based Broadcom SoCs. This multiplexer connects one of several ++ child MDIO bus to a parent bus. Buses could be internal as well as ++ external and selection logic lies inside the same multiplexer. ++ + config MDIO_BUS_MUX_BCM_IPROC + tristate "Broadcom iProc based MDIO bus multiplexers" + depends on OF && OF_MDIO && (ARCH_BCM_IPROC || COMPILE_TEST) +--- a/drivers/net/mdio/Makefile ++++ b/drivers/net/mdio/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_MDIO_THUNDER) += mdio-thun + obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o + + obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o ++obj-$(CONFIG_MDIO_BUS_MUX_BCM6368) += mdio-mux-bcm6368.o + obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o + obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o + obj-$(CONFIG_MDIO_BUS_MUX_MESON_G12A) += mdio-mux-meson-g12a.o +--- /dev/null ++++ b/drivers/net/mdio/mdio-mux-bcm6368.c +@@ -0,0 +1,179 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Broadcom BCM6368 mdiomux bus controller driver ++ * ++ * Copyright (C) 2021 Álvaro Fernández Rojas ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MDIOC_REG 0x0 ++#define MDIOC_EXT_MASK BIT(16) ++#define MDIOC_REG_SHIFT 20 ++#define MDIOC_PHYID_SHIFT 25 ++#define MDIOC_RD_MASK BIT(30) ++#define MDIOC_WR_MASK BIT(31) ++ ++#define MDIOD_REG 0x4 ++ ++struct bcm6368_mdiomux_desc { ++ void *mux_handle; ++ void __iomem *base; ++ struct device *dev; ++ struct mii_bus *mii_bus; ++ int ext_phy; ++}; ++ ++static int bcm6368_mdiomux_read(struct mii_bus *bus, int phy_id, int loc) ++{ ++ struct bcm6368_mdiomux_desc *md = bus->priv; ++ uint32_t reg; ++ int ret; ++ ++ __raw_writel(0, md->base + MDIOC_REG); ++ ++ reg = MDIOC_RD_MASK | ++ (phy_id << MDIOC_PHYID_SHIFT) | ++ (loc << MDIOC_REG_SHIFT); ++ if (md->ext_phy) ++ reg |= MDIOC_EXT_MASK; ++ ++ __raw_writel(reg, md->base + MDIOC_REG); ++ udelay(50); ++ ret = __raw_readw(md->base + MDIOD_REG); ++ ++ return ret; ++} ++ ++static int bcm6368_mdiomux_write(struct mii_bus *bus, int phy_id, int loc, ++ uint16_t val) ++{ ++ struct bcm6368_mdiomux_desc *md = bus->priv; ++ uint32_t reg; ++ ++ __raw_writel(0, md->base + MDIOC_REG); ++ ++ reg = MDIOC_WR_MASK | ++ (phy_id << MDIOC_PHYID_SHIFT) | ++ (loc << MDIOC_REG_SHIFT); ++ if (md->ext_phy) ++ reg |= MDIOC_EXT_MASK; ++ reg |= val; ++ ++ __raw_writel(reg, md->base + MDIOC_REG); ++ udelay(50); ++ ++ return 0; ++} ++ ++static int bcm6368_mdiomux_switch_fn(int current_child, int desired_child, ++ void *data) ++{ ++ struct bcm6368_mdiomux_desc *md = data; ++ ++ md->ext_phy = desired_child; ++ ++ return 0; ++} ++ ++static int bcm6368_mdiomux_probe(struct platform_device *pdev) ++{ ++ struct bcm6368_mdiomux_desc *md; ++ struct mii_bus *bus; ++ struct resource *res; ++ int rc; ++ ++ md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL); ++ if (!md) ++ return -ENOMEM; ++ md->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -EINVAL; ++ ++ /* Just ioremap, as this MDIO block is usually integrated into an ++ * Ethernet MAC controller register range ++ */ ++ md->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); ++ if (!md->base) { ++ dev_err(&pdev->dev, "failed to ioremap register\n"); ++ return -ENOMEM; ++ } ++ ++ md->mii_bus = devm_mdiobus_alloc(&pdev->dev); ++ if (!md->mii_bus) { ++ dev_err(&pdev->dev, "mdiomux bus alloc failed\n"); ++ return ENOMEM; ++ } ++ ++ bus = md->mii_bus; ++ bus->priv = md; ++ bus->name = "BCM6368 MDIO mux bus"; ++ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id); ++ bus->parent = &pdev->dev; ++ bus->read = bcm6368_mdiomux_read; ++ bus->write = bcm6368_mdiomux_write; ++ bus->phy_mask = 0x3f; ++ bus->dev.of_node = pdev->dev.of_node; ++ ++ rc = mdiobus_register(bus); ++ if (rc) { ++ dev_err(&pdev->dev, "mdiomux registration failed\n"); ++ return rc; ++ } ++ ++ platform_set_drvdata(pdev, md); ++ ++ rc = mdio_mux_init(md->dev, md->dev->of_node, ++ bcm6368_mdiomux_switch_fn, &md->mux_handle, md, ++ md->mii_bus); ++ if (rc) { ++ dev_info(md->dev, "mdiomux initialization failed\n"); ++ goto out_register; ++ } ++ ++ dev_info(&pdev->dev, "Broadcom BCM6368 MDIO mux bus\n"); ++ ++ return 0; ++ ++out_register: ++ mdiobus_unregister(bus); ++ return rc; ++} ++ ++static int bcm6368_mdiomux_remove(struct platform_device *pdev) ++{ ++ struct bcm6368_mdiomux_desc *md = platform_get_drvdata(pdev); ++ ++ mdio_mux_uninit(md->mux_handle); ++ mdiobus_unregister(md->mii_bus); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm6368_mdiomux_ids[] = { ++ { .compatible = "brcm,bcm6368-mdio-mux", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, bcm6368_mdiomux_ids); ++ ++static struct platform_driver bcm6368_mdiomux_driver = { ++ .driver = { ++ .name = "bcm6368-mdio-mux", ++ .of_match_table = bcm6368_mdiomux_ids, ++ }, ++ .probe = bcm6368_mdiomux_probe, ++ .remove = bcm6368_mdiomux_remove, ++}; ++module_platform_driver(bcm6368_mdiomux_driver);