From: Martin Blumenstingl Date: Mon, 10 Oct 2022 15:48:49 +0000 (+0200) Subject: lantiq: dts: vr9: Add missing properties to the CPU port on the switch X-Git-Tag: v23.05.0-rc1~2176 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=2683cca5927844594f7835aa983e2690d1e343c6;p=openwrt%2Fstaging%2Fhauke.git lantiq: dts: vr9: Add missing properties to the CPU port on the switch The CPU port should define the phy-mode and and a PHY phandle or fixed-link to indicate how the CPU port is connected to the SoC's Ethernet controller. On xRX200 this is all internal connection, so use phy-mode = "internal" along with a fixed-link that matches the definition inside ð0. Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports"). when these properties are missing. Adding the properties before OpenWrt is updated to Linux 6.0 is harmless. Suggested-by: Martin Schiller Signed-off-by: Martin Blumenstingl --- diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi index 1089cdc80c..7fa2fac1ef 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi @@ -448,7 +448,13 @@ port@6 { reg = <0x6>; label = "cpu"; + phy-mode = "internal"; ethernet = <ð0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; };