From: Antonio Nino Diaz Date: Fri, 11 Jan 2019 11:20:10 +0000 (+0000) Subject: xlat v2: Dynamically detect need for CnP bit X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=2559b2c8256f;p=project%2Fbcm63xx%2Fatf.git xlat v2: Dynamically detect need for CnP bit ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented in CPUs that don't implement all mandatory 8.2 features (and so have to claim to be a lower version). This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system ID registers to detect whether it is needed to set the bit or not. Change-Id: I7bcbf0c7c937590dfc2ca668cfd9267c50f7d52c Signed-off-by: Antonio Nino Diaz --- diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index cbe272c2..4af3e903 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -94,12 +94,16 @@ /* CSSELR definitions */ #define LEVEL_SHIFT U(1) -/* ID_PFR0 AMU definitions */ +/* ID_MMFR4 definitions */ +#define ID_MMFR4_CNP_SHIFT U(12) +#define ID_MMFR4_CNP_LENGTH U(4) +#define ID_MMFR4_CNP_MASK U(0xf) + +/* ID_PFR0 definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) #define ID_PFR0_AMU_MASK U(0xf) -/* ID_PFR0 DIT definitions */ #define ID_PFR0_DIT_SHIFT U(24) #define ID_PFR0_DIT_LENGTH U(4) #define ID_PFR0_DIT_MASK U(0xf) @@ -475,6 +479,7 @@ #define DCISW p15, 0, c7, c6, 2 #define CTR p15, 0, c0, c0, 1 #define CNTFRQ p15, 0, c14, c0, 0 +#define ID_MMFR4 p15, 0, c0, c2, 6 #define ID_PFR0 p15, 0, c0, c1, 0 #define ID_PFR1 p15, 0, c0, c1, 1 #define MAIR0 p15, 0, c10, c2, 0 diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h new file mode 100644 index 00000000..d9341026 --- /dev/null +++ b/include/arch/aarch32/arch_features.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARCH_FEATURES_H +#define ARCH_FEATURES_H + +#include + +#include + +static inline bool is_armv8_2_ttcnp_present(void) +{ + return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) & + ID_MMFR4_CNP_MASK) != 0U; +} + +#endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index c2773c13..64ddc86f 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -214,6 +214,7 @@ DEFINE_SYSREG_RW_FUNCS(cpsr) ******************************************************************************/ DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) DEFINE_COPROCR_READ_FUNC(midr, MIDR) +DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4) DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0) DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1) DEFINE_COPROCR_READ_FUNC(isr, ISR) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 8a44d83f..9e2bffac 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -156,10 +156,6 @@ #define ID_AA64PFR0_GIC_WIDTH U(4) #define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1)) -/* ID_AA64MMFR0_EL1 definitions */ -#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) -#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) - /* ID_AA64ISAR1_EL1 definitions */ #define ID_AA64ISAR1_GPI_SHIFT U(28) #define ID_AA64ISAR1_GPI_WIDTH U(4) @@ -179,6 +175,10 @@ #define ID_AA64ISAR1_APA_MASK \ (((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT) +/* ID_AA64MMFR0_EL1 definitions */ +#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) +#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) + #define PARANGE_0000 U(32) #define PARANGE_0001 U(36) #define PARANGE_0010 U(40) @@ -202,6 +202,11 @@ #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) +/* ID_AA64MMFR2_EL1 definitions */ +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) +#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) + /* ID_AA64PFR1_EL1 definitions */ #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h new file mode 100644 index 00000000..2b09ba07 --- /dev/null +++ b/include/arch/aarch64/arch_features.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARCH_FEATURES_H +#define ARCH_FEATURES_H + +#include + +#include + +static inline bool is_armv8_2_ttcnp_present(void) +{ + return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) & + ID_AA64MMFR2_EL1_CNP_MASK) != 0U; +} + +#endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index b912b422..d3f0df71 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -449,6 +449,9 @@ DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) +/* Armv8.2 Registers */ +DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) + /* Armv8.3 Pointer Authentication Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1) diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index 349b6c4d..913c86d3 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -219,13 +220,10 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags, /* Set TTBR0 bits as well */ ttbr0 = (uint64_t)(uintptr_t) base_table; -#if ARM_ARCH_AT_LEAST(8, 2) - /* - * Enable CnP bit so as to share page tables with all PEs. This - * is mandatory for ARMv8.2 implementations. - */ - ttbr0 |= TTBR_CNP_BIT; -#endif + if (is_armv8_2_ttcnp_present()) { + /* Enable CnP bit so as to share page tables with all PEs. */ + ttbr0 |= TTBR_CNP_BIT; + } /* Now populate MMU configuration */ params[MMU_CFG_MAIR] = mair; diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index a803d835..228f7514 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -266,13 +267,10 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags, /* Set TTBR bits as well */ ttbr0 = (uint64_t) base_table; -#if ARM_ARCH_AT_LEAST(8, 2) - /* - * Enable CnP bit so as to share page tables with all PEs. This - * is mandatory for ARMv8.2 implementations. - */ - ttbr0 |= TTBR_CNP_BIT; -#endif + if (is_armv8_2_ttcnp_present()) { + /* Enable CnP bit so as to share page tables with all PEs. */ + ttbr0 |= TTBR_CNP_BIT; + } params[MMU_CFG_MAIR] = mair; params[MMU_CFG_TCR] = tcr;